1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
10 * Distribute under GPL.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/types.h>
17 #include <linux/netdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/mii.h>
20 #include <linux/if_ether.h>
21 #include <linux/if_vlan.h>
22 #include <linux/etherdevice.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ssb/ssb.h>
29 #include <asm/uaccess.h>
36 #define DRV_MODULE_NAME "b44"
37 #define PFX DRV_MODULE_NAME ": "
38 #define DRV_MODULE_VERSION "2.0"
40 #define B44_DEF_MSG_ENABLE \
50 /* length of time before we decide the hardware is borked,
51 * and dev->tx_timeout() should be called to fix the problem
53 #define B44_TX_TIMEOUT (5 * HZ)
55 /* hardware minimum and maximum for a single frame's data payload */
56 #define B44_MIN_MTU 60
57 #define B44_MAX_MTU 1500
59 #define B44_RX_RING_SIZE 512
60 #define B44_DEF_RX_RING_PENDING 200
61 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
63 #define B44_TX_RING_SIZE 512
64 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
68 #define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70 #define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
76 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
77 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
79 /* minimum number of free TX descriptors required to wake up TX process */
80 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
82 /* b44 internal pattern match filter info */
83 #define B44_PATTERN_BASE 0x400
84 #define B44_PATTERN_SIZE 0x80
85 #define B44_PMASK_BASE 0x600
86 #define B44_PMASK_SIZE 0x10
87 #define B44_MAX_PATTERNS 16
88 #define B44_ETHIPV6UDP_HLEN 62
89 #define B44_ETHIPV4UDP_HLEN 42
91 static char version
[] __devinitdata
=
92 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
"\n";
94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
96 MODULE_LICENSE("GPL");
97 MODULE_VERSION(DRV_MODULE_VERSION
);
99 static int b44_debug
= -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
100 module_param(b44_debug
, int, 0);
101 MODULE_PARM_DESC(b44_debug
, "B44 bitmapped debugging message enable value");
104 #ifdef CONFIG_B44_PCI
105 static const struct pci_device_id b44_pci_tbl
[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401
) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B0
) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B1
) },
109 { 0 } /* terminate list with empty entry */
111 MODULE_DEVICE_TABLE(pci
, b44_pci_tbl
);
113 static struct pci_driver b44_pci_driver
= {
114 .name
= DRV_MODULE_NAME
,
115 .id_table
= b44_pci_tbl
,
117 #endif /* CONFIG_B44_PCI */
119 static const struct ssb_device_id b44_ssb_tbl
[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_ETHERNET
, SSB_ANY_REV
),
123 MODULE_DEVICE_TABLE(ssb
, b44_ssb_tbl
);
125 static void b44_halt(struct b44
*);
126 static void b44_init_rings(struct b44
*);
128 #define B44_FULL_RESET 1
129 #define B44_FULL_RESET_SKIP_PHY 2
130 #define B44_PARTIAL_RESET 3
131 #define B44_CHIP_RESET_FULL 4
132 #define B44_CHIP_RESET_PARTIAL 5
134 static void b44_init_hw(struct b44
*, int);
136 static int dma_desc_align_mask
;
137 static int dma_desc_sync_size
;
140 static const char b44_gstrings
[][ETH_GSTRING_LEN
] = {
141 #define _B44(x...) # x,
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device
*sdev
,
148 unsigned long offset
,
149 enum dma_data_direction dir
)
151 ssb_dma_sync_single_range_for_device(sdev
, dma_base
,
152 offset
& dma_desc_align_mask
,
153 dma_desc_sync_size
, dir
);
156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device
*sdev
,
158 unsigned long offset
,
159 enum dma_data_direction dir
)
161 ssb_dma_sync_single_range_for_cpu(sdev
, dma_base
,
162 offset
& dma_desc_align_mask
,
163 dma_desc_sync_size
, dir
);
166 static inline unsigned long br32(const struct b44
*bp
, unsigned long reg
)
168 return ssb_read32(bp
->sdev
, reg
);
171 static inline void bw32(const struct b44
*bp
,
172 unsigned long reg
, unsigned long val
)
174 ssb_write32(bp
->sdev
, reg
, val
);
177 static int b44_wait_bit(struct b44
*bp
, unsigned long reg
,
178 u32 bit
, unsigned long timeout
, const int clear
)
182 for (i
= 0; i
< timeout
; i
++) {
183 u32 val
= br32(bp
, reg
);
185 if (clear
&& !(val
& bit
))
187 if (!clear
&& (val
& bit
))
192 printk(KERN_ERR PFX
"%s: BUG! Timeout waiting for bit %08x of register "
196 (clear
? "clear" : "set"));
202 static inline void __b44_cam_read(struct b44
*bp
, unsigned char *data
, int index
)
206 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_READ
|
207 (index
<< CAM_CTRL_INDEX_SHIFT
)));
209 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
211 val
= br32(bp
, B44_CAM_DATA_LO
);
213 data
[2] = (val
>> 24) & 0xFF;
214 data
[3] = (val
>> 16) & 0xFF;
215 data
[4] = (val
>> 8) & 0xFF;
216 data
[5] = (val
>> 0) & 0xFF;
218 val
= br32(bp
, B44_CAM_DATA_HI
);
220 data
[0] = (val
>> 8) & 0xFF;
221 data
[1] = (val
>> 0) & 0xFF;
224 static inline void __b44_cam_write(struct b44
*bp
, unsigned char *data
, int index
)
228 val
= ((u32
) data
[2]) << 24;
229 val
|= ((u32
) data
[3]) << 16;
230 val
|= ((u32
) data
[4]) << 8;
231 val
|= ((u32
) data
[5]) << 0;
232 bw32(bp
, B44_CAM_DATA_LO
, val
);
233 val
= (CAM_DATA_HI_VALID
|
234 (((u32
) data
[0]) << 8) |
235 (((u32
) data
[1]) << 0));
236 bw32(bp
, B44_CAM_DATA_HI
, val
);
237 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_WRITE
|
238 (index
<< CAM_CTRL_INDEX_SHIFT
)));
239 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
242 static inline void __b44_disable_ints(struct b44
*bp
)
244 bw32(bp
, B44_IMASK
, 0);
247 static void b44_disable_ints(struct b44
*bp
)
249 __b44_disable_ints(bp
);
251 /* Flush posted writes. */
255 static void b44_enable_ints(struct b44
*bp
)
257 bw32(bp
, B44_IMASK
, bp
->imask
);
260 static int __b44_readphy(struct b44
*bp
, int phy_addr
, int reg
, u32
*val
)
264 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
265 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
266 (MDIO_OP_READ
<< MDIO_DATA_OP_SHIFT
) |
267 (phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
268 (reg
<< MDIO_DATA_RA_SHIFT
) |
269 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
)));
270 err
= b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
271 *val
= br32(bp
, B44_MDIO_DATA
) & MDIO_DATA_DATA
;
276 static int __b44_writephy(struct b44
*bp
, int phy_addr
, int reg
, u32 val
)
278 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
279 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
280 (MDIO_OP_WRITE
<< MDIO_DATA_OP_SHIFT
) |
281 (phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
282 (reg
<< MDIO_DATA_RA_SHIFT
) |
283 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
) |
284 (val
& MDIO_DATA_DATA
)));
285 return b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
288 static inline int b44_readphy(struct b44
*bp
, int reg
, u32
*val
)
290 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
293 return __b44_readphy(bp
, bp
->phy_addr
, reg
, val
);
296 static inline int b44_writephy(struct b44
*bp
, int reg
, u32 val
)
298 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
301 return __b44_writephy(bp
, bp
->phy_addr
, reg
, val
);
304 /* miilib interface */
305 static int b44_mii_read(struct net_device
*dev
, int phy_id
, int location
)
308 struct b44
*bp
= netdev_priv(dev
);
309 int rc
= __b44_readphy(bp
, phy_id
, location
, &val
);
315 static void b44_mii_write(struct net_device
*dev
, int phy_id
, int location
,
318 struct b44
*bp
= netdev_priv(dev
);
319 __b44_writephy(bp
, phy_id
, location
, val
);
322 static int b44_phy_reset(struct b44
*bp
)
327 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
329 err
= b44_writephy(bp
, MII_BMCR
, BMCR_RESET
);
333 err
= b44_readphy(bp
, MII_BMCR
, &val
);
335 if (val
& BMCR_RESET
) {
336 printk(KERN_ERR PFX
"%s: PHY Reset would not complete.\n",
345 static void __b44_set_flow_ctrl(struct b44
*bp
, u32 pause_flags
)
349 bp
->flags
&= ~(B44_FLAG_TX_PAUSE
| B44_FLAG_RX_PAUSE
);
350 bp
->flags
|= pause_flags
;
352 val
= br32(bp
, B44_RXCONFIG
);
353 if (pause_flags
& B44_FLAG_RX_PAUSE
)
354 val
|= RXCONFIG_FLOW
;
356 val
&= ~RXCONFIG_FLOW
;
357 bw32(bp
, B44_RXCONFIG
, val
);
359 val
= br32(bp
, B44_MAC_FLOW
);
360 if (pause_flags
& B44_FLAG_TX_PAUSE
)
361 val
|= (MAC_FLOW_PAUSE_ENAB
|
362 (0xc0 & MAC_FLOW_RX_HI_WATER
));
364 val
&= ~MAC_FLOW_PAUSE_ENAB
;
365 bw32(bp
, B44_MAC_FLOW
, val
);
368 static void b44_set_flow_ctrl(struct b44
*bp
, u32 local
, u32 remote
)
372 /* The driver supports only rx pause by default because
373 the b44 mac tx pause mechanism generates excessive
375 Use ethtool to turn on b44 tx pause if necessary.
377 if ((local
& ADVERTISE_PAUSE_CAP
) &&
378 (local
& ADVERTISE_PAUSE_ASYM
)){
379 if ((remote
& LPA_PAUSE_ASYM
) &&
380 !(remote
& LPA_PAUSE_CAP
))
381 pause_enab
|= B44_FLAG_RX_PAUSE
;
384 __b44_set_flow_ctrl(bp
, pause_enab
);
387 #ifdef SSB_DRIVER_MIPS
388 extern char *nvram_get(char *name
);
389 static void b44_wap54g10_workaround(struct b44
*bp
)
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
400 str
= nvram_get("boardnum");
403 if (simple_strtoul(str
, NULL
, 0) == 2) {
404 err
= __b44_readphy(bp
, 0, MII_BMCR
, &val
);
407 if (!(val
& BMCR_ISOLATE
))
409 val
&= ~BMCR_ISOLATE
;
410 err
= __b44_writephy(bp
, 0, MII_BMCR
, val
);
416 printk(KERN_WARNING PFX
"PHY: cannot reset MII transceiver isolate bit.\n");
419 static inline void b44_wap54g10_workaround(struct b44
*bp
)
424 static int b44_setup_phy(struct b44
*bp
)
429 b44_wap54g10_workaround(bp
);
431 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
)
433 if ((err
= b44_readphy(bp
, B44_MII_ALEDCTRL
, &val
)) != 0)
435 if ((err
= b44_writephy(bp
, B44_MII_ALEDCTRL
,
436 val
& MII_ALEDCTRL_ALLMSK
)) != 0)
438 if ((err
= b44_readphy(bp
, B44_MII_TLEDCTRL
, &val
)) != 0)
440 if ((err
= b44_writephy(bp
, B44_MII_TLEDCTRL
,
441 val
| MII_TLEDCTRL_ENABLE
)) != 0)
444 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
)) {
445 u32 adv
= ADVERTISE_CSMA
;
447 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
448 adv
|= ADVERTISE_10HALF
;
449 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
450 adv
|= ADVERTISE_10FULL
;
451 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
452 adv
|= ADVERTISE_100HALF
;
453 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
454 adv
|= ADVERTISE_100FULL
;
456 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
)
457 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
459 if ((err
= b44_writephy(bp
, MII_ADVERTISE
, adv
)) != 0)
461 if ((err
= b44_writephy(bp
, MII_BMCR
, (BMCR_ANENABLE
|
462 BMCR_ANRESTART
))) != 0)
467 if ((err
= b44_readphy(bp
, MII_BMCR
, &bmcr
)) != 0)
469 bmcr
&= ~(BMCR_FULLDPLX
| BMCR_ANENABLE
| BMCR_SPEED100
);
470 if (bp
->flags
& B44_FLAG_100_BASE_T
)
471 bmcr
|= BMCR_SPEED100
;
472 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
473 bmcr
|= BMCR_FULLDPLX
;
474 if ((err
= b44_writephy(bp
, MII_BMCR
, bmcr
)) != 0)
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
481 b44_set_flow_ctrl(bp
, 0, 0);
488 static void b44_stats_update(struct b44
*bp
)
493 val
= &bp
->hw_stats
.tx_good_octets
;
494 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL) {
495 *val
++ += br32(bp
, reg
);
501 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL) {
502 *val
++ += br32(bp
, reg
);
506 static void b44_link_report(struct b44
*bp
)
508 if (!netif_carrier_ok(bp
->dev
)) {
509 printk(KERN_INFO PFX
"%s: Link is down.\n", bp
->dev
->name
);
511 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
513 (bp
->flags
& B44_FLAG_100_BASE_T
) ? 100 : 10,
514 (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ? "full" : "half");
516 printk(KERN_INFO PFX
"%s: Flow control is %s for TX and "
519 (bp
->flags
& B44_FLAG_TX_PAUSE
) ? "on" : "off",
520 (bp
->flags
& B44_FLAG_RX_PAUSE
) ? "on" : "off");
524 static void b44_check_phy(struct b44
*bp
)
528 if (bp
->phy_addr
== B44_PHY_ADDR_NO_PHY
) {
529 bp
->flags
|= B44_FLAG_100_BASE_T
;
530 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
531 if (!netif_carrier_ok(bp
->dev
)) {
532 u32 val
= br32(bp
, B44_TX_CTRL
);
533 val
|= TX_CTRL_DUPLEX
;
534 bw32(bp
, B44_TX_CTRL
, val
);
535 netif_carrier_on(bp
->dev
);
541 if (!b44_readphy(bp
, MII_BMSR
, &bmsr
) &&
542 !b44_readphy(bp
, B44_MII_AUXCTRL
, &aux
) &&
544 if (aux
& MII_AUXCTRL_SPEED
)
545 bp
->flags
|= B44_FLAG_100_BASE_T
;
547 bp
->flags
&= ~B44_FLAG_100_BASE_T
;
548 if (aux
& MII_AUXCTRL_DUPLEX
)
549 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
551 bp
->flags
&= ~B44_FLAG_FULL_DUPLEX
;
553 if (!netif_carrier_ok(bp
->dev
) &&
554 (bmsr
& BMSR_LSTATUS
)) {
555 u32 val
= br32(bp
, B44_TX_CTRL
);
556 u32 local_adv
, remote_adv
;
558 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
559 val
|= TX_CTRL_DUPLEX
;
561 val
&= ~TX_CTRL_DUPLEX
;
562 bw32(bp
, B44_TX_CTRL
, val
);
564 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
) &&
565 !b44_readphy(bp
, MII_ADVERTISE
, &local_adv
) &&
566 !b44_readphy(bp
, MII_LPA
, &remote_adv
))
567 b44_set_flow_ctrl(bp
, local_adv
, remote_adv
);
570 netif_carrier_on(bp
->dev
);
572 } else if (netif_carrier_ok(bp
->dev
) && !(bmsr
& BMSR_LSTATUS
)) {
574 netif_carrier_off(bp
->dev
);
578 if (bmsr
& BMSR_RFAULT
)
579 printk(KERN_WARNING PFX
"%s: Remote fault detected in PHY\n",
582 printk(KERN_WARNING PFX
"%s: Jabber detected in PHY\n",
587 static void b44_timer(unsigned long __opaque
)
589 struct b44
*bp
= (struct b44
*) __opaque
;
591 spin_lock_irq(&bp
->lock
);
595 b44_stats_update(bp
);
597 spin_unlock_irq(&bp
->lock
);
599 mod_timer(&bp
->timer
, round_jiffies(jiffies
+ HZ
));
602 static void b44_tx(struct b44
*bp
)
606 cur
= br32(bp
, B44_DMATX_STAT
) & DMATX_STAT_CDMASK
;
607 cur
/= sizeof(struct dma_desc
);
609 /* XXX needs updating when NETIF_F_SG is supported */
610 for (cons
= bp
->tx_cons
; cons
!= cur
; cons
= NEXT_TX(cons
)) {
611 struct ring_info
*rp
= &bp
->tx_buffers
[cons
];
612 struct sk_buff
*skb
= rp
->skb
;
616 ssb_dma_unmap_single(bp
->sdev
,
621 dev_kfree_skb_irq(skb
);
625 if (netif_queue_stopped(bp
->dev
) &&
626 TX_BUFFS_AVAIL(bp
) > B44_TX_WAKEUP_THRESH
)
627 netif_wake_queue(bp
->dev
);
629 bw32(bp
, B44_GPTIMER
, 0);
632 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
633 * before the DMA address you give it. So we allocate 30 more bytes
634 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635 * point the chip at 30 bytes past where the rx_header will go.
637 static int b44_alloc_rx_skb(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
640 struct ring_info
*src_map
, *map
;
641 struct rx_header
*rh
;
649 src_map
= &bp
->rx_buffers
[src_idx
];
650 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
651 map
= &bp
->rx_buffers
[dest_idx
];
652 skb
= netdev_alloc_skb(bp
->dev
, RX_PKT_BUF_SZ
);
656 mapping
= ssb_dma_map_single(bp
->sdev
, skb
->data
,
660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */
662 if (ssb_dma_mapping_error(bp
->sdev
, mapping
) ||
663 mapping
+ RX_PKT_BUF_SZ
> DMA_BIT_MASK(30)) {
665 if (!ssb_dma_mapping_error(bp
->sdev
, mapping
))
666 ssb_dma_unmap_single(bp
->sdev
, mapping
,
667 RX_PKT_BUF_SZ
, DMA_FROM_DEVICE
);
668 dev_kfree_skb_any(skb
);
669 skb
= __netdev_alloc_skb(bp
->dev
, RX_PKT_BUF_SZ
, GFP_ATOMIC
|GFP_DMA
);
672 mapping
= ssb_dma_map_single(bp
->sdev
, skb
->data
,
675 if (ssb_dma_mapping_error(bp
->sdev
, mapping
) ||
676 mapping
+ RX_PKT_BUF_SZ
> DMA_BIT_MASK(30)) {
677 if (!ssb_dma_mapping_error(bp
->sdev
, mapping
))
678 ssb_dma_unmap_single(bp
->sdev
, mapping
, RX_PKT_BUF_SZ
,DMA_FROM_DEVICE
);
679 dev_kfree_skb_any(skb
);
682 bp
->force_copybreak
= 1;
685 rh
= (struct rx_header
*) skb
->data
;
691 map
->mapping
= mapping
;
696 ctrl
= (DESC_CTRL_LEN
& RX_PKT_BUF_SZ
);
697 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
698 ctrl
|= DESC_CTRL_EOT
;
700 dp
= &bp
->rx_ring
[dest_idx
];
701 dp
->ctrl
= cpu_to_le32(ctrl
);
702 dp
->addr
= cpu_to_le32((u32
) mapping
+ bp
->dma_offset
);
704 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
705 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->rx_ring_dma
,
706 dest_idx
* sizeof(*dp
),
709 return RX_PKT_BUF_SZ
;
712 static void b44_recycle_rx(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
714 struct dma_desc
*src_desc
, *dest_desc
;
715 struct ring_info
*src_map
, *dest_map
;
716 struct rx_header
*rh
;
720 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
721 dest_desc
= &bp
->rx_ring
[dest_idx
];
722 dest_map
= &bp
->rx_buffers
[dest_idx
];
723 src_desc
= &bp
->rx_ring
[src_idx
];
724 src_map
= &bp
->rx_buffers
[src_idx
];
726 dest_map
->skb
= src_map
->skb
;
727 rh
= (struct rx_header
*) src_map
->skb
->data
;
730 dest_map
->mapping
= src_map
->mapping
;
732 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
733 b44_sync_dma_desc_for_cpu(bp
->sdev
, bp
->rx_ring_dma
,
734 src_idx
* sizeof(*src_desc
),
737 ctrl
= src_desc
->ctrl
;
738 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
739 ctrl
|= cpu_to_le32(DESC_CTRL_EOT
);
741 ctrl
&= cpu_to_le32(~DESC_CTRL_EOT
);
743 dest_desc
->ctrl
= ctrl
;
744 dest_desc
->addr
= src_desc
->addr
;
748 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
749 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->rx_ring_dma
,
750 dest_idx
* sizeof(*dest_desc
),
753 ssb_dma_sync_single_for_device(bp
->sdev
, dest_map
->mapping
,
758 static int b44_rx(struct b44
*bp
, int budget
)
764 prod
= br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_CDMASK
;
765 prod
/= sizeof(struct dma_desc
);
768 while (cons
!= prod
&& budget
> 0) {
769 struct ring_info
*rp
= &bp
->rx_buffers
[cons
];
770 struct sk_buff
*skb
= rp
->skb
;
771 dma_addr_t map
= rp
->mapping
;
772 struct rx_header
*rh
;
775 ssb_dma_sync_single_for_cpu(bp
->sdev
, map
,
778 rh
= (struct rx_header
*) skb
->data
;
779 len
= le16_to_cpu(rh
->len
);
780 if ((len
> (RX_PKT_BUF_SZ
- RX_PKT_OFFSET
)) ||
781 (rh
->flags
& cpu_to_le16(RX_FLAG_ERRORS
))) {
783 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
785 bp
->dev
->stats
.rx_dropped
++;
795 len
= le16_to_cpu(rh
->len
);
796 } while (len
== 0 && i
++ < 5);
804 if (!bp
->force_copybreak
&& len
> RX_COPY_THRESHOLD
) {
806 skb_size
= b44_alloc_rx_skb(bp
, cons
, bp
->rx_prod
);
809 ssb_dma_unmap_single(bp
->sdev
, map
,
810 skb_size
, DMA_FROM_DEVICE
);
811 /* Leave out rx_header */
812 skb_put(skb
, len
+ RX_PKT_OFFSET
);
813 skb_pull(skb
, RX_PKT_OFFSET
);
815 struct sk_buff
*copy_skb
;
817 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
818 copy_skb
= dev_alloc_skb(len
+ 2);
819 if (copy_skb
== NULL
)
820 goto drop_it_no_recycle
;
822 skb_reserve(copy_skb
, 2);
823 skb_put(copy_skb
, len
);
824 /* DMA sync done above, copy just the actual packet */
825 skb_copy_from_linear_data_offset(skb
, RX_PKT_OFFSET
,
826 copy_skb
->data
, len
);
829 skb
->ip_summed
= CHECKSUM_NONE
;
830 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
831 netif_receive_skb(skb
);
835 bp
->rx_prod
= (bp
->rx_prod
+ 1) &
836 (B44_RX_RING_SIZE
- 1);
837 cons
= (cons
+ 1) & (B44_RX_RING_SIZE
- 1);
841 bw32(bp
, B44_DMARX_PTR
, cons
* sizeof(struct dma_desc
));
846 static int b44_poll(struct napi_struct
*napi
, int budget
)
848 struct b44
*bp
= container_of(napi
, struct b44
, napi
);
852 spin_lock_irqsave(&bp
->lock
, flags
);
854 if (bp
->istat
& (ISTAT_TX
| ISTAT_TO
)) {
855 /* spin_lock(&bp->tx_lock); */
857 /* spin_unlock(&bp->tx_lock); */
859 spin_unlock_irqrestore(&bp
->lock
, flags
);
862 if (bp
->istat
& ISTAT_RX
)
863 work_done
+= b44_rx(bp
, budget
);
865 if (bp
->istat
& ISTAT_ERRORS
) {
866 spin_lock_irqsave(&bp
->lock
, flags
);
869 b44_init_hw(bp
, B44_FULL_RESET_SKIP_PHY
);
870 netif_wake_queue(bp
->dev
);
871 spin_unlock_irqrestore(&bp
->lock
, flags
);
875 if (work_done
< budget
) {
883 static irqreturn_t
b44_interrupt(int irq
, void *dev_id
)
885 struct net_device
*dev
= dev_id
;
886 struct b44
*bp
= netdev_priv(dev
);
890 spin_lock(&bp
->lock
);
892 istat
= br32(bp
, B44_ISTAT
);
893 imask
= br32(bp
, B44_IMASK
);
895 /* The interrupt mask register controls which interrupt bits
896 * will actually raise an interrupt to the CPU when set by hw/firmware,
897 * but doesn't mask off the bits.
903 if (unlikely(!netif_running(dev
))) {
904 printk(KERN_INFO
"%s: late interrupt.\n", dev
->name
);
908 if (napi_schedule_prep(&bp
->napi
)) {
909 /* NOTE: These writes are posted by the readback of
910 * the ISTAT register below.
913 __b44_disable_ints(bp
);
914 __napi_schedule(&bp
->napi
);
918 bw32(bp
, B44_ISTAT
, istat
);
921 spin_unlock(&bp
->lock
);
922 return IRQ_RETVAL(handled
);
925 static void b44_tx_timeout(struct net_device
*dev
)
927 struct b44
*bp
= netdev_priv(dev
);
929 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
932 spin_lock_irq(&bp
->lock
);
936 b44_init_hw(bp
, B44_FULL_RESET
);
938 spin_unlock_irq(&bp
->lock
);
942 netif_wake_queue(dev
);
945 static netdev_tx_t
b44_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
947 struct b44
*bp
= netdev_priv(dev
);
948 int rc
= NETDEV_TX_OK
;
950 u32 len
, entry
, ctrl
;
954 spin_lock_irqsave(&bp
->lock
, flags
);
956 /* This is a hard error, log it. */
957 if (unlikely(TX_BUFFS_AVAIL(bp
) < 1)) {
958 netif_stop_queue(dev
);
959 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
964 mapping
= ssb_dma_map_single(bp
->sdev
, skb
->data
, len
, DMA_TO_DEVICE
);
965 if (ssb_dma_mapping_error(bp
->sdev
, mapping
) || mapping
+ len
> DMA_BIT_MASK(30)) {
966 struct sk_buff
*bounce_skb
;
968 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
969 if (!ssb_dma_mapping_error(bp
->sdev
, mapping
))
970 ssb_dma_unmap_single(bp
->sdev
, mapping
, len
,
973 bounce_skb
= __netdev_alloc_skb(dev
, len
, GFP_ATOMIC
| GFP_DMA
);
977 mapping
= ssb_dma_map_single(bp
->sdev
, bounce_skb
->data
,
979 if (ssb_dma_mapping_error(bp
->sdev
, mapping
) || mapping
+ len
> DMA_BIT_MASK(30)) {
980 if (!ssb_dma_mapping_error(bp
->sdev
, mapping
))
981 ssb_dma_unmap_single(bp
->sdev
, mapping
,
983 dev_kfree_skb_any(bounce_skb
);
987 skb_copy_from_linear_data(skb
, skb_put(bounce_skb
, len
), len
);
988 dev_kfree_skb_any(skb
);
993 bp
->tx_buffers
[entry
].skb
= skb
;
994 bp
->tx_buffers
[entry
].mapping
= mapping
;
996 ctrl
= (len
& DESC_CTRL_LEN
);
997 ctrl
|= DESC_CTRL_IOC
| DESC_CTRL_SOF
| DESC_CTRL_EOF
;
998 if (entry
== (B44_TX_RING_SIZE
- 1))
999 ctrl
|= DESC_CTRL_EOT
;
1001 bp
->tx_ring
[entry
].ctrl
= cpu_to_le32(ctrl
);
1002 bp
->tx_ring
[entry
].addr
= cpu_to_le32((u32
) mapping
+bp
->dma_offset
);
1004 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1005 b44_sync_dma_desc_for_device(bp
->sdev
, bp
->tx_ring_dma
,
1006 entry
* sizeof(bp
->tx_ring
[0]),
1009 entry
= NEXT_TX(entry
);
1011 bp
->tx_prod
= entry
;
1015 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1016 if (bp
->flags
& B44_FLAG_BUGGY_TXPTR
)
1017 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1018 if (bp
->flags
& B44_FLAG_REORDER_BUG
)
1019 br32(bp
, B44_DMATX_PTR
);
1021 if (TX_BUFFS_AVAIL(bp
) < 1)
1022 netif_stop_queue(dev
);
1024 dev
->trans_start
= jiffies
;
1027 spin_unlock_irqrestore(&bp
->lock
, flags
);
1032 rc
= NETDEV_TX_BUSY
;
1036 static int b44_change_mtu(struct net_device
*dev
, int new_mtu
)
1038 struct b44
*bp
= netdev_priv(dev
);
1040 if (new_mtu
< B44_MIN_MTU
|| new_mtu
> B44_MAX_MTU
)
1043 if (!netif_running(dev
)) {
1044 /* We'll just catch it later when the
1051 spin_lock_irq(&bp
->lock
);
1055 b44_init_hw(bp
, B44_FULL_RESET
);
1056 spin_unlock_irq(&bp
->lock
);
1058 b44_enable_ints(bp
);
1063 /* Free up pending packets in all rx/tx rings.
1065 * The chip has been shut down and the driver detached from
1066 * the networking, so no interrupts or new tx packets will
1067 * end up in the driver. bp->lock is not held and we are not
1068 * in an interrupt context and thus may sleep.
1070 static void b44_free_rings(struct b44
*bp
)
1072 struct ring_info
*rp
;
1075 for (i
= 0; i
< B44_RX_RING_SIZE
; i
++) {
1076 rp
= &bp
->rx_buffers
[i
];
1078 if (rp
->skb
== NULL
)
1080 ssb_dma_unmap_single(bp
->sdev
, rp
->mapping
, RX_PKT_BUF_SZ
,
1082 dev_kfree_skb_any(rp
->skb
);
1086 /* XXX needs changes once NETIF_F_SG is set... */
1087 for (i
= 0; i
< B44_TX_RING_SIZE
; i
++) {
1088 rp
= &bp
->tx_buffers
[i
];
1090 if (rp
->skb
== NULL
)
1092 ssb_dma_unmap_single(bp
->sdev
, rp
->mapping
, rp
->skb
->len
,
1094 dev_kfree_skb_any(rp
->skb
);
1099 /* Initialize tx/rx rings for packet processing.
1101 * The chip has been shut down and the driver detached from
1102 * the networking, so no interrupts or new tx packets will
1103 * end up in the driver.
1105 static void b44_init_rings(struct b44
*bp
)
1111 memset(bp
->rx_ring
, 0, B44_RX_RING_BYTES
);
1112 memset(bp
->tx_ring
, 0, B44_TX_RING_BYTES
);
1114 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
1115 ssb_dma_sync_single_for_device(bp
->sdev
, bp
->rx_ring_dma
,
1119 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1120 ssb_dma_sync_single_for_device(bp
->sdev
, bp
->tx_ring_dma
,
1124 for (i
= 0; i
< bp
->rx_pending
; i
++) {
1125 if (b44_alloc_rx_skb(bp
, -1, i
) < 0)
1131 * Must not be invoked with interrupt sources disabled and
1132 * the hardware shutdown down.
1134 static void b44_free_consistent(struct b44
*bp
)
1136 kfree(bp
->rx_buffers
);
1137 bp
->rx_buffers
= NULL
;
1138 kfree(bp
->tx_buffers
);
1139 bp
->tx_buffers
= NULL
;
1141 if (bp
->flags
& B44_FLAG_RX_RING_HACK
) {
1142 ssb_dma_unmap_single(bp
->sdev
, bp
->rx_ring_dma
,
1147 ssb_dma_free_consistent(bp
->sdev
, DMA_TABLE_BYTES
,
1148 bp
->rx_ring
, bp
->rx_ring_dma
,
1151 bp
->flags
&= ~B44_FLAG_RX_RING_HACK
;
1154 if (bp
->flags
& B44_FLAG_TX_RING_HACK
) {
1155 ssb_dma_unmap_single(bp
->sdev
, bp
->tx_ring_dma
,
1160 ssb_dma_free_consistent(bp
->sdev
, DMA_TABLE_BYTES
,
1161 bp
->tx_ring
, bp
->tx_ring_dma
,
1164 bp
->flags
&= ~B44_FLAG_TX_RING_HACK
;
1169 * Must not be invoked with interrupt sources disabled and
1170 * the hardware shutdown down. Can sleep.
1172 static int b44_alloc_consistent(struct b44
*bp
, gfp_t gfp
)
1176 size
= B44_RX_RING_SIZE
* sizeof(struct ring_info
);
1177 bp
->rx_buffers
= kzalloc(size
, gfp
);
1178 if (!bp
->rx_buffers
)
1181 size
= B44_TX_RING_SIZE
* sizeof(struct ring_info
);
1182 bp
->tx_buffers
= kzalloc(size
, gfp
);
1183 if (!bp
->tx_buffers
)
1186 size
= DMA_TABLE_BYTES
;
1187 bp
->rx_ring
= ssb_dma_alloc_consistent(bp
->sdev
, size
, &bp
->rx_ring_dma
, gfp
);
1189 /* Allocation may have failed due to pci_alloc_consistent
1190 insisting on use of GFP_DMA, which is more restrictive
1191 than necessary... */
1192 struct dma_desc
*rx_ring
;
1193 dma_addr_t rx_ring_dma
;
1195 rx_ring
= kzalloc(size
, gfp
);
1199 rx_ring_dma
= ssb_dma_map_single(bp
->sdev
, rx_ring
,
1203 if (ssb_dma_mapping_error(bp
->sdev
, rx_ring_dma
) ||
1204 rx_ring_dma
+ size
> DMA_BIT_MASK(30)) {
1209 bp
->rx_ring
= rx_ring
;
1210 bp
->rx_ring_dma
= rx_ring_dma
;
1211 bp
->flags
|= B44_FLAG_RX_RING_HACK
;
1214 bp
->tx_ring
= ssb_dma_alloc_consistent(bp
->sdev
, size
, &bp
->tx_ring_dma
, gfp
);
1216 /* Allocation may have failed due to ssb_dma_alloc_consistent
1217 insisting on use of GFP_DMA, which is more restrictive
1218 than necessary... */
1219 struct dma_desc
*tx_ring
;
1220 dma_addr_t tx_ring_dma
;
1222 tx_ring
= kzalloc(size
, gfp
);
1226 tx_ring_dma
= ssb_dma_map_single(bp
->sdev
, tx_ring
,
1230 if (ssb_dma_mapping_error(bp
->sdev
, tx_ring_dma
) ||
1231 tx_ring_dma
+ size
> DMA_BIT_MASK(30)) {
1236 bp
->tx_ring
= tx_ring
;
1237 bp
->tx_ring_dma
= tx_ring_dma
;
1238 bp
->flags
|= B44_FLAG_TX_RING_HACK
;
1244 b44_free_consistent(bp
);
1248 /* bp->lock is held. */
1249 static void b44_clear_stats(struct b44
*bp
)
1253 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1254 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL)
1256 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL)
1260 /* bp->lock is held. */
1261 static void b44_chip_reset(struct b44
*bp
, int reset_kind
)
1263 struct ssb_device
*sdev
= bp
->sdev
;
1266 was_enabled
= ssb_device_is_enabled(bp
->sdev
);
1268 ssb_device_enable(bp
->sdev
, 0);
1269 ssb_pcicore_dev_irqvecs_enable(&sdev
->bus
->pcicore
, sdev
);
1272 bw32(bp
, B44_RCV_LAZY
, 0);
1273 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
);
1274 b44_wait_bit(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
, 200, 1);
1275 bw32(bp
, B44_DMATX_CTRL
, 0);
1276 bp
->tx_prod
= bp
->tx_cons
= 0;
1277 if (br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_EMASK
) {
1278 b44_wait_bit(bp
, B44_DMARX_STAT
, DMARX_STAT_SIDLE
,
1281 bw32(bp
, B44_DMARX_CTRL
, 0);
1282 bp
->rx_prod
= bp
->rx_cons
= 0;
1285 b44_clear_stats(bp
);
1288 * Don't enable PHY if we are doing a partial reset
1289 * we are probably going to power down
1291 if (reset_kind
== B44_CHIP_RESET_PARTIAL
)
1294 switch (sdev
->bus
->bustype
) {
1295 case SSB_BUSTYPE_SSB
:
1296 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1297 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev
->bus
),
1299 & MDIO_CTRL_MAXF_MASK
)));
1301 case SSB_BUSTYPE_PCI
:
1302 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1303 (0x0d & MDIO_CTRL_MAXF_MASK
)));
1305 case SSB_BUSTYPE_PCMCIA
:
1306 case SSB_BUSTYPE_SDIO
:
1307 WARN_ON(1); /* A device with this bus does not exist. */
1311 br32(bp
, B44_MDIO_CTRL
);
1313 if (!(br32(bp
, B44_DEVCTRL
) & DEVCTRL_IPP
)) {
1314 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_EPSEL
);
1315 br32(bp
, B44_ENET_CTRL
);
1316 bp
->flags
&= ~B44_FLAG_INTERNAL_PHY
;
1318 u32 val
= br32(bp
, B44_DEVCTRL
);
1320 if (val
& DEVCTRL_EPR
) {
1321 bw32(bp
, B44_DEVCTRL
, (val
& ~DEVCTRL_EPR
));
1322 br32(bp
, B44_DEVCTRL
);
1325 bp
->flags
|= B44_FLAG_INTERNAL_PHY
;
1329 /* bp->lock is held. */
1330 static void b44_halt(struct b44
*bp
)
1332 b44_disable_ints(bp
);
1335 /* power down PHY */
1336 printk(KERN_INFO PFX
"%s: powering down PHY\n", bp
->dev
->name
);
1337 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_PHY_PDOWN
);
1338 /* now reset the chip, but without enabling the MAC&PHY
1339 * part of it. This has to be done _after_ we shut down the PHY */
1340 b44_chip_reset(bp
, B44_CHIP_RESET_PARTIAL
);
1343 /* bp->lock is held. */
1344 static void __b44_set_mac_addr(struct b44
*bp
)
1346 bw32(bp
, B44_CAM_CTRL
, 0);
1347 if (!(bp
->dev
->flags
& IFF_PROMISC
)) {
1350 __b44_cam_write(bp
, bp
->dev
->dev_addr
, 0);
1351 val
= br32(bp
, B44_CAM_CTRL
);
1352 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1356 static int b44_set_mac_addr(struct net_device
*dev
, void *p
)
1358 struct b44
*bp
= netdev_priv(dev
);
1359 struct sockaddr
*addr
= p
;
1362 if (netif_running(dev
))
1365 if (!is_valid_ether_addr(addr
->sa_data
))
1368 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1370 spin_lock_irq(&bp
->lock
);
1372 val
= br32(bp
, B44_RXCONFIG
);
1373 if (!(val
& RXCONFIG_CAM_ABSENT
))
1374 __b44_set_mac_addr(bp
);
1376 spin_unlock_irq(&bp
->lock
);
1381 /* Called at device open time to get the chip ready for
1382 * packet processing. Invoked with bp->lock held.
1384 static void __b44_set_rx_mode(struct net_device
*);
1385 static void b44_init_hw(struct b44
*bp
, int reset_kind
)
1389 b44_chip_reset(bp
, B44_CHIP_RESET_FULL
);
1390 if (reset_kind
== B44_FULL_RESET
) {
1395 /* Enable CRC32, set proper LED modes and power on PHY */
1396 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_CRC32_ENAB
| MAC_CTRL_PHY_LEDCTRL
);
1397 bw32(bp
, B44_RCV_LAZY
, (1 << RCV_LAZY_FC_SHIFT
));
1399 /* This sets the MAC address too. */
1400 __b44_set_rx_mode(bp
->dev
);
1402 /* MTU + eth header + possible VLAN tag + struct rx_header */
1403 bw32(bp
, B44_RXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1404 bw32(bp
, B44_TXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1406 bw32(bp
, B44_TX_WMARK
, 56); /* XXX magic */
1407 if (reset_kind
== B44_PARTIAL_RESET
) {
1408 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1409 (RX_PKT_OFFSET
<< DMARX_CTRL_ROSHIFT
)));
1411 bw32(bp
, B44_DMATX_CTRL
, DMATX_CTRL_ENABLE
);
1412 bw32(bp
, B44_DMATX_ADDR
, bp
->tx_ring_dma
+ bp
->dma_offset
);
1413 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1414 (RX_PKT_OFFSET
<< DMARX_CTRL_ROSHIFT
)));
1415 bw32(bp
, B44_DMARX_ADDR
, bp
->rx_ring_dma
+ bp
->dma_offset
);
1417 bw32(bp
, B44_DMARX_PTR
, bp
->rx_pending
);
1418 bp
->rx_prod
= bp
->rx_pending
;
1420 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1423 val
= br32(bp
, B44_ENET_CTRL
);
1424 bw32(bp
, B44_ENET_CTRL
, (val
| ENET_CTRL_ENABLE
));
1427 static int b44_open(struct net_device
*dev
)
1429 struct b44
*bp
= netdev_priv(dev
);
1432 err
= b44_alloc_consistent(bp
, GFP_KERNEL
);
1436 napi_enable(&bp
->napi
);
1439 b44_init_hw(bp
, B44_FULL_RESET
);
1443 err
= request_irq(dev
->irq
, b44_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
1444 if (unlikely(err
< 0)) {
1445 napi_disable(&bp
->napi
);
1446 b44_chip_reset(bp
, B44_CHIP_RESET_PARTIAL
);
1448 b44_free_consistent(bp
);
1452 init_timer(&bp
->timer
);
1453 bp
->timer
.expires
= jiffies
+ HZ
;
1454 bp
->timer
.data
= (unsigned long) bp
;
1455 bp
->timer
.function
= b44_timer
;
1456 add_timer(&bp
->timer
);
1458 b44_enable_ints(bp
);
1459 netif_start_queue(dev
);
1464 #ifdef CONFIG_NET_POLL_CONTROLLER
1466 * Polling receive - used by netconsole and other diagnostic tools
1467 * to allow network i/o with interrupts disabled.
1469 static void b44_poll_controller(struct net_device
*dev
)
1471 disable_irq(dev
->irq
);
1472 b44_interrupt(dev
->irq
, dev
);
1473 enable_irq(dev
->irq
);
1477 static void bwfilter_table(struct b44
*bp
, u8
*pp
, u32 bytes
, u32 table_offset
)
1480 u32
*pattern
= (u32
*) pp
;
1482 for (i
= 0; i
< bytes
; i
+= sizeof(u32
)) {
1483 bw32(bp
, B44_FILT_ADDR
, table_offset
+ i
);
1484 bw32(bp
, B44_FILT_DATA
, pattern
[i
/ sizeof(u32
)]);
1488 static int b44_magic_pattern(u8
*macaddr
, u8
*ppattern
, u8
*pmask
, int offset
)
1491 int k
, j
, len
= offset
;
1492 int ethaddr_bytes
= ETH_ALEN
;
1494 memset(ppattern
+ offset
, 0xff, magicsync
);
1495 for (j
= 0; j
< magicsync
; j
++)
1496 set_bit(len
++, (unsigned long *) pmask
);
1498 for (j
= 0; j
< B44_MAX_PATTERNS
; j
++) {
1499 if ((B44_PATTERN_SIZE
- len
) >= ETH_ALEN
)
1500 ethaddr_bytes
= ETH_ALEN
;
1502 ethaddr_bytes
= B44_PATTERN_SIZE
- len
;
1503 if (ethaddr_bytes
<=0)
1505 for (k
= 0; k
< ethaddr_bytes
; k
++) {
1506 ppattern
[offset
+ magicsync
+
1507 (j
* ETH_ALEN
) + k
] = macaddr
[k
];
1509 set_bit(len
, (unsigned long *) pmask
);
1515 /* Setup magic packet patterns in the b44 WOL
1516 * pattern matching filter.
1518 static void b44_setup_pseudo_magicp(struct b44
*bp
)
1522 int plen0
, plen1
, plen2
;
1524 u8 pwol_mask
[B44_PMASK_SIZE
];
1526 pwol_pattern
= kzalloc(B44_PATTERN_SIZE
, GFP_KERNEL
);
1527 if (!pwol_pattern
) {
1528 printk(KERN_ERR PFX
"Memory not available for WOL\n");
1532 /* Ipv4 magic packet pattern - pattern 0.*/
1533 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1534 plen0
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1535 B44_ETHIPV4UDP_HLEN
);
1537 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
, B44_PATTERN_BASE
);
1538 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
, B44_PMASK_BASE
);
1540 /* Raw ethernet II magic packet pattern - pattern 1 */
1541 memset(pwol_pattern
, 0, B44_PATTERN_SIZE
);
1542 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1543 plen1
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1546 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
,
1547 B44_PATTERN_BASE
+ B44_PATTERN_SIZE
);
1548 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
,
1549 B44_PMASK_BASE
+ B44_PMASK_SIZE
);
1551 /* Ipv6 magic packet pattern - pattern 2 */
1552 memset(pwol_pattern
, 0, B44_PATTERN_SIZE
);
1553 memset(pwol_mask
, 0, B44_PMASK_SIZE
);
1554 plen2
= b44_magic_pattern(bp
->dev
->dev_addr
, pwol_pattern
, pwol_mask
,
1555 B44_ETHIPV6UDP_HLEN
);
1557 bwfilter_table(bp
, pwol_pattern
, B44_PATTERN_SIZE
,
1558 B44_PATTERN_BASE
+ B44_PATTERN_SIZE
+ B44_PATTERN_SIZE
);
1559 bwfilter_table(bp
, pwol_mask
, B44_PMASK_SIZE
,
1560 B44_PMASK_BASE
+ B44_PMASK_SIZE
+ B44_PMASK_SIZE
);
1562 kfree(pwol_pattern
);
1564 /* set these pattern's lengths: one less than each real length */
1565 val
= plen0
| (plen1
<< 8) | (plen2
<< 16) | WKUP_LEN_ENABLE_THREE
;
1566 bw32(bp
, B44_WKUP_LEN
, val
);
1568 /* enable wakeup pattern matching */
1569 val
= br32(bp
, B44_DEVCTRL
);
1570 bw32(bp
, B44_DEVCTRL
, val
| DEVCTRL_PFE
);
1574 #ifdef CONFIG_B44_PCI
1575 static void b44_setup_wol_pci(struct b44
*bp
)
1579 if (bp
->sdev
->bus
->bustype
!= SSB_BUSTYPE_SSB
) {
1580 bw32(bp
, SSB_TMSLOW
, br32(bp
, SSB_TMSLOW
) | SSB_TMSLOW_PE
);
1581 pci_read_config_word(bp
->sdev
->bus
->host_pci
, SSB_PMCSR
, &val
);
1582 pci_write_config_word(bp
->sdev
->bus
->host_pci
, SSB_PMCSR
, val
| SSB_PE
);
1586 static inline void b44_setup_wol_pci(struct b44
*bp
) { }
1587 #endif /* CONFIG_B44_PCI */
1589 static void b44_setup_wol(struct b44
*bp
)
1593 bw32(bp
, B44_RXCONFIG
, RXCONFIG_ALLMULTI
);
1595 if (bp
->flags
& B44_FLAG_B0_ANDLATER
) {
1597 bw32(bp
, B44_WKUP_LEN
, WKUP_LEN_DISABLE
);
1599 val
= bp
->dev
->dev_addr
[2] << 24 |
1600 bp
->dev
->dev_addr
[3] << 16 |
1601 bp
->dev
->dev_addr
[4] << 8 |
1602 bp
->dev
->dev_addr
[5];
1603 bw32(bp
, B44_ADDR_LO
, val
);
1605 val
= bp
->dev
->dev_addr
[0] << 8 |
1606 bp
->dev
->dev_addr
[1];
1607 bw32(bp
, B44_ADDR_HI
, val
);
1609 val
= br32(bp
, B44_DEVCTRL
);
1610 bw32(bp
, B44_DEVCTRL
, val
| DEVCTRL_MPM
| DEVCTRL_PFE
);
1613 b44_setup_pseudo_magicp(bp
);
1615 b44_setup_wol_pci(bp
);
1618 static int b44_close(struct net_device
*dev
)
1620 struct b44
*bp
= netdev_priv(dev
);
1622 netif_stop_queue(dev
);
1624 napi_disable(&bp
->napi
);
1626 del_timer_sync(&bp
->timer
);
1628 spin_lock_irq(&bp
->lock
);
1632 netif_carrier_off(dev
);
1634 spin_unlock_irq(&bp
->lock
);
1636 free_irq(dev
->irq
, dev
);
1638 if (bp
->flags
& B44_FLAG_WOL_ENABLE
) {
1639 b44_init_hw(bp
, B44_PARTIAL_RESET
);
1643 b44_free_consistent(bp
);
1648 static struct net_device_stats
*b44_get_stats(struct net_device
*dev
)
1650 struct b44
*bp
= netdev_priv(dev
);
1651 struct net_device_stats
*nstat
= &dev
->stats
;
1652 struct b44_hw_stats
*hwstat
= &bp
->hw_stats
;
1654 /* Convert HW stats into netdevice stats. */
1655 nstat
->rx_packets
= hwstat
->rx_pkts
;
1656 nstat
->tx_packets
= hwstat
->tx_pkts
;
1657 nstat
->rx_bytes
= hwstat
->rx_octets
;
1658 nstat
->tx_bytes
= hwstat
->tx_octets
;
1659 nstat
->tx_errors
= (hwstat
->tx_jabber_pkts
+
1660 hwstat
->tx_oversize_pkts
+
1661 hwstat
->tx_underruns
+
1662 hwstat
->tx_excessive_cols
+
1663 hwstat
->tx_late_cols
);
1664 nstat
->multicast
= hwstat
->tx_multicast_pkts
;
1665 nstat
->collisions
= hwstat
->tx_total_cols
;
1667 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
1668 hwstat
->rx_undersize
);
1669 nstat
->rx_over_errors
= hwstat
->rx_missed_pkts
;
1670 nstat
->rx_frame_errors
= hwstat
->rx_align_errs
;
1671 nstat
->rx_crc_errors
= hwstat
->rx_crc_errs
;
1672 nstat
->rx_errors
= (hwstat
->rx_jabber_pkts
+
1673 hwstat
->rx_oversize_pkts
+
1674 hwstat
->rx_missed_pkts
+
1675 hwstat
->rx_crc_align_errs
+
1676 hwstat
->rx_undersize
+
1677 hwstat
->rx_crc_errs
+
1678 hwstat
->rx_align_errs
+
1679 hwstat
->rx_symbol_errs
);
1681 nstat
->tx_aborted_errors
= hwstat
->tx_underruns
;
1683 /* Carrier lost counter seems to be broken for some devices */
1684 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_lost
;
1690 static int __b44_load_mcast(struct b44
*bp
, struct net_device
*dev
)
1692 struct dev_mc_list
*mclist
;
1695 num_ents
= min_t(int, dev
->mc_count
, B44_MCAST_TABLE_SIZE
);
1696 mclist
= dev
->mc_list
;
1697 for (i
= 0; mclist
&& i
< num_ents
; i
++, mclist
= mclist
->next
) {
1698 __b44_cam_write(bp
, mclist
->dmi_addr
, i
+ 1);
1703 static void __b44_set_rx_mode(struct net_device
*dev
)
1705 struct b44
*bp
= netdev_priv(dev
);
1708 val
= br32(bp
, B44_RXCONFIG
);
1709 val
&= ~(RXCONFIG_PROMISC
| RXCONFIG_ALLMULTI
);
1710 if ((dev
->flags
& IFF_PROMISC
) || (val
& RXCONFIG_CAM_ABSENT
)) {
1711 val
|= RXCONFIG_PROMISC
;
1712 bw32(bp
, B44_RXCONFIG
, val
);
1714 unsigned char zero
[6] = {0, 0, 0, 0, 0, 0};
1717 __b44_set_mac_addr(bp
);
1719 if ((dev
->flags
& IFF_ALLMULTI
) ||
1720 (dev
->mc_count
> B44_MCAST_TABLE_SIZE
))
1721 val
|= RXCONFIG_ALLMULTI
;
1723 i
= __b44_load_mcast(bp
, dev
);
1726 __b44_cam_write(bp
, zero
, i
);
1728 bw32(bp
, B44_RXCONFIG
, val
);
1729 val
= br32(bp
, B44_CAM_CTRL
);
1730 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1734 static void b44_set_rx_mode(struct net_device
*dev
)
1736 struct b44
*bp
= netdev_priv(dev
);
1738 spin_lock_irq(&bp
->lock
);
1739 __b44_set_rx_mode(dev
);
1740 spin_unlock_irq(&bp
->lock
);
1743 static u32
b44_get_msglevel(struct net_device
*dev
)
1745 struct b44
*bp
= netdev_priv(dev
);
1746 return bp
->msg_enable
;
1749 static void b44_set_msglevel(struct net_device
*dev
, u32 value
)
1751 struct b44
*bp
= netdev_priv(dev
);
1752 bp
->msg_enable
= value
;
1755 static void b44_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1757 struct b44
*bp
= netdev_priv(dev
);
1758 struct ssb_bus
*bus
= bp
->sdev
->bus
;
1760 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
1761 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
1762 switch (bus
->bustype
) {
1763 case SSB_BUSTYPE_PCI
:
1764 strlcpy(info
->bus_info
, pci_name(bus
->host_pci
), sizeof(info
->bus_info
));
1766 case SSB_BUSTYPE_SSB
:
1767 strlcpy(info
->bus_info
, "SSB", sizeof(info
->bus_info
));
1769 case SSB_BUSTYPE_PCMCIA
:
1770 case SSB_BUSTYPE_SDIO
:
1771 WARN_ON(1); /* A device with this bus does not exist. */
1776 static int b44_nway_reset(struct net_device
*dev
)
1778 struct b44
*bp
= netdev_priv(dev
);
1782 spin_lock_irq(&bp
->lock
);
1783 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1784 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1786 if (bmcr
& BMCR_ANENABLE
) {
1787 b44_writephy(bp
, MII_BMCR
,
1788 bmcr
| BMCR_ANRESTART
);
1791 spin_unlock_irq(&bp
->lock
);
1796 static int b44_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1798 struct b44
*bp
= netdev_priv(dev
);
1800 cmd
->supported
= (SUPPORTED_Autoneg
);
1801 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
1802 SUPPORTED_100baseT_Full
|
1803 SUPPORTED_10baseT_Half
|
1804 SUPPORTED_10baseT_Full
|
1807 cmd
->advertising
= 0;
1808 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
1809 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
1810 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
1811 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
1812 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
1813 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
1814 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
1815 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
1816 cmd
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
1817 cmd
->speed
= (bp
->flags
& B44_FLAG_100_BASE_T
) ?
1818 SPEED_100
: SPEED_10
;
1819 cmd
->duplex
= (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ?
1820 DUPLEX_FULL
: DUPLEX_HALF
;
1822 cmd
->phy_address
= bp
->phy_addr
;
1823 cmd
->transceiver
= (bp
->flags
& B44_FLAG_INTERNAL_PHY
) ?
1824 XCVR_INTERNAL
: XCVR_EXTERNAL
;
1825 cmd
->autoneg
= (bp
->flags
& B44_FLAG_FORCE_LINK
) ?
1826 AUTONEG_DISABLE
: AUTONEG_ENABLE
;
1827 if (cmd
->autoneg
== AUTONEG_ENABLE
)
1828 cmd
->advertising
|= ADVERTISED_Autoneg
;
1829 if (!netif_running(dev
)){
1838 static int b44_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1840 struct b44
*bp
= netdev_priv(dev
);
1842 /* We do not support gigabit. */
1843 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1844 if (cmd
->advertising
&
1845 (ADVERTISED_1000baseT_Half
|
1846 ADVERTISED_1000baseT_Full
))
1848 } else if ((cmd
->speed
!= SPEED_100
&&
1849 cmd
->speed
!= SPEED_10
) ||
1850 (cmd
->duplex
!= DUPLEX_HALF
&&
1851 cmd
->duplex
!= DUPLEX_FULL
)) {
1855 spin_lock_irq(&bp
->lock
);
1857 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1858 bp
->flags
&= ~(B44_FLAG_FORCE_LINK
|
1859 B44_FLAG_100_BASE_T
|
1860 B44_FLAG_FULL_DUPLEX
|
1861 B44_FLAG_ADV_10HALF
|
1862 B44_FLAG_ADV_10FULL
|
1863 B44_FLAG_ADV_100HALF
|
1864 B44_FLAG_ADV_100FULL
);
1865 if (cmd
->advertising
== 0) {
1866 bp
->flags
|= (B44_FLAG_ADV_10HALF
|
1867 B44_FLAG_ADV_10FULL
|
1868 B44_FLAG_ADV_100HALF
|
1869 B44_FLAG_ADV_100FULL
);
1871 if (cmd
->advertising
& ADVERTISED_10baseT_Half
)
1872 bp
->flags
|= B44_FLAG_ADV_10HALF
;
1873 if (cmd
->advertising
& ADVERTISED_10baseT_Full
)
1874 bp
->flags
|= B44_FLAG_ADV_10FULL
;
1875 if (cmd
->advertising
& ADVERTISED_100baseT_Half
)
1876 bp
->flags
|= B44_FLAG_ADV_100HALF
;
1877 if (cmd
->advertising
& ADVERTISED_100baseT_Full
)
1878 bp
->flags
|= B44_FLAG_ADV_100FULL
;
1881 bp
->flags
|= B44_FLAG_FORCE_LINK
;
1882 bp
->flags
&= ~(B44_FLAG_100_BASE_T
| B44_FLAG_FULL_DUPLEX
);
1883 if (cmd
->speed
== SPEED_100
)
1884 bp
->flags
|= B44_FLAG_100_BASE_T
;
1885 if (cmd
->duplex
== DUPLEX_FULL
)
1886 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
1889 if (netif_running(dev
))
1892 spin_unlock_irq(&bp
->lock
);
1897 static void b44_get_ringparam(struct net_device
*dev
,
1898 struct ethtool_ringparam
*ering
)
1900 struct b44
*bp
= netdev_priv(dev
);
1902 ering
->rx_max_pending
= B44_RX_RING_SIZE
- 1;
1903 ering
->rx_pending
= bp
->rx_pending
;
1905 /* XXX ethtool lacks a tx_max_pending, oops... */
1908 static int b44_set_ringparam(struct net_device
*dev
,
1909 struct ethtool_ringparam
*ering
)
1911 struct b44
*bp
= netdev_priv(dev
);
1913 if ((ering
->rx_pending
> B44_RX_RING_SIZE
- 1) ||
1914 (ering
->rx_mini_pending
!= 0) ||
1915 (ering
->rx_jumbo_pending
!= 0) ||
1916 (ering
->tx_pending
> B44_TX_RING_SIZE
- 1))
1919 spin_lock_irq(&bp
->lock
);
1921 bp
->rx_pending
= ering
->rx_pending
;
1922 bp
->tx_pending
= ering
->tx_pending
;
1926 b44_init_hw(bp
, B44_FULL_RESET
);
1927 netif_wake_queue(bp
->dev
);
1928 spin_unlock_irq(&bp
->lock
);
1930 b44_enable_ints(bp
);
1935 static void b44_get_pauseparam(struct net_device
*dev
,
1936 struct ethtool_pauseparam
*epause
)
1938 struct b44
*bp
= netdev_priv(dev
);
1941 (bp
->flags
& B44_FLAG_PAUSE_AUTO
) != 0;
1943 (bp
->flags
& B44_FLAG_RX_PAUSE
) != 0;
1945 (bp
->flags
& B44_FLAG_TX_PAUSE
) != 0;
1948 static int b44_set_pauseparam(struct net_device
*dev
,
1949 struct ethtool_pauseparam
*epause
)
1951 struct b44
*bp
= netdev_priv(dev
);
1953 spin_lock_irq(&bp
->lock
);
1954 if (epause
->autoneg
)
1955 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
1957 bp
->flags
&= ~B44_FLAG_PAUSE_AUTO
;
1958 if (epause
->rx_pause
)
1959 bp
->flags
|= B44_FLAG_RX_PAUSE
;
1961 bp
->flags
&= ~B44_FLAG_RX_PAUSE
;
1962 if (epause
->tx_pause
)
1963 bp
->flags
|= B44_FLAG_TX_PAUSE
;
1965 bp
->flags
&= ~B44_FLAG_TX_PAUSE
;
1966 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
) {
1969 b44_init_hw(bp
, B44_FULL_RESET
);
1971 __b44_set_flow_ctrl(bp
, bp
->flags
);
1973 spin_unlock_irq(&bp
->lock
);
1975 b44_enable_ints(bp
);
1980 static void b44_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1984 memcpy(data
, *b44_gstrings
, sizeof(b44_gstrings
));
1989 static int b44_get_sset_count(struct net_device
*dev
, int sset
)
1993 return ARRAY_SIZE(b44_gstrings
);
1999 static void b44_get_ethtool_stats(struct net_device
*dev
,
2000 struct ethtool_stats
*stats
, u64
*data
)
2002 struct b44
*bp
= netdev_priv(dev
);
2003 u32
*val
= &bp
->hw_stats
.tx_good_octets
;
2006 spin_lock_irq(&bp
->lock
);
2008 b44_stats_update(bp
);
2010 for (i
= 0; i
< ARRAY_SIZE(b44_gstrings
); i
++)
2013 spin_unlock_irq(&bp
->lock
);
2016 static void b44_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2018 struct b44
*bp
= netdev_priv(dev
);
2020 wol
->supported
= WAKE_MAGIC
;
2021 if (bp
->flags
& B44_FLAG_WOL_ENABLE
)
2022 wol
->wolopts
= WAKE_MAGIC
;
2025 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
2028 static int b44_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2030 struct b44
*bp
= netdev_priv(dev
);
2032 spin_lock_irq(&bp
->lock
);
2033 if (wol
->wolopts
& WAKE_MAGIC
)
2034 bp
->flags
|= B44_FLAG_WOL_ENABLE
;
2036 bp
->flags
&= ~B44_FLAG_WOL_ENABLE
;
2037 spin_unlock_irq(&bp
->lock
);
2042 static const struct ethtool_ops b44_ethtool_ops
= {
2043 .get_drvinfo
= b44_get_drvinfo
,
2044 .get_settings
= b44_get_settings
,
2045 .set_settings
= b44_set_settings
,
2046 .nway_reset
= b44_nway_reset
,
2047 .get_link
= ethtool_op_get_link
,
2048 .get_wol
= b44_get_wol
,
2049 .set_wol
= b44_set_wol
,
2050 .get_ringparam
= b44_get_ringparam
,
2051 .set_ringparam
= b44_set_ringparam
,
2052 .get_pauseparam
= b44_get_pauseparam
,
2053 .set_pauseparam
= b44_set_pauseparam
,
2054 .get_msglevel
= b44_get_msglevel
,
2055 .set_msglevel
= b44_set_msglevel
,
2056 .get_strings
= b44_get_strings
,
2057 .get_sset_count
= b44_get_sset_count
,
2058 .get_ethtool_stats
= b44_get_ethtool_stats
,
2061 static int b44_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2063 struct mii_ioctl_data
*data
= if_mii(ifr
);
2064 struct b44
*bp
= netdev_priv(dev
);
2067 if (!netif_running(dev
))
2070 spin_lock_irq(&bp
->lock
);
2071 err
= generic_mii_ioctl(&bp
->mii_if
, data
, cmd
, NULL
);
2072 spin_unlock_irq(&bp
->lock
);
2077 static int __devinit
b44_get_invariants(struct b44
*bp
)
2079 struct ssb_device
*sdev
= bp
->sdev
;
2083 bp
->dma_offset
= ssb_dma_translation(sdev
);
2085 if (sdev
->bus
->bustype
== SSB_BUSTYPE_SSB
&&
2087 addr
= sdev
->bus
->sprom
.et1mac
;
2088 bp
->phy_addr
= sdev
->bus
->sprom
.et1phyaddr
;
2090 addr
= sdev
->bus
->sprom
.et0mac
;
2091 bp
->phy_addr
= sdev
->bus
->sprom
.et0phyaddr
;
2093 /* Some ROMs have buggy PHY addresses with the high
2094 * bits set (sign extension?). Truncate them to a
2095 * valid PHY address. */
2096 bp
->phy_addr
&= 0x1F;
2098 memcpy(bp
->dev
->dev_addr
, addr
, 6);
2100 if (!is_valid_ether_addr(&bp
->dev
->dev_addr
[0])){
2101 printk(KERN_ERR PFX
"Invalid MAC address found in EEPROM\n");
2105 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, bp
->dev
->addr_len
);
2107 bp
->imask
= IMASK_DEF
;
2109 /* XXX - really required?
2110 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2113 if (bp
->sdev
->id
.revision
>= 7)
2114 bp
->flags
|= B44_FLAG_B0_ANDLATER
;
2119 static const struct net_device_ops b44_netdev_ops
= {
2120 .ndo_open
= b44_open
,
2121 .ndo_stop
= b44_close
,
2122 .ndo_start_xmit
= b44_start_xmit
,
2123 .ndo_get_stats
= b44_get_stats
,
2124 .ndo_set_multicast_list
= b44_set_rx_mode
,
2125 .ndo_set_mac_address
= b44_set_mac_addr
,
2126 .ndo_validate_addr
= eth_validate_addr
,
2127 .ndo_do_ioctl
= b44_ioctl
,
2128 .ndo_tx_timeout
= b44_tx_timeout
,
2129 .ndo_change_mtu
= b44_change_mtu
,
2130 #ifdef CONFIG_NET_POLL_CONTROLLER
2131 .ndo_poll_controller
= b44_poll_controller
,
2135 static int __devinit
b44_init_one(struct ssb_device
*sdev
,
2136 const struct ssb_device_id
*ent
)
2138 static int b44_version_printed
= 0;
2139 struct net_device
*dev
;
2145 if (b44_version_printed
++ == 0)
2146 printk(KERN_INFO
"%s", version
);
2149 dev
= alloc_etherdev(sizeof(*bp
));
2151 dev_err(sdev
->dev
, "Etherdev alloc failed, aborting.\n");
2156 SET_NETDEV_DEV(dev
, sdev
->dev
);
2158 /* No interesting netdevice features in this card... */
2161 bp
= netdev_priv(dev
);
2164 bp
->force_copybreak
= 0;
2166 bp
->msg_enable
= netif_msg_init(b44_debug
, B44_DEF_MSG_ENABLE
);
2168 spin_lock_init(&bp
->lock
);
2170 bp
->rx_pending
= B44_DEF_RX_RING_PENDING
;
2171 bp
->tx_pending
= B44_DEF_TX_RING_PENDING
;
2173 dev
->netdev_ops
= &b44_netdev_ops
;
2174 netif_napi_add(dev
, &bp
->napi
, b44_poll
, 64);
2175 dev
->watchdog_timeo
= B44_TX_TIMEOUT
;
2176 dev
->irq
= sdev
->irq
;
2177 SET_ETHTOOL_OPS(dev
, &b44_ethtool_ops
);
2179 netif_carrier_off(dev
);
2181 err
= ssb_bus_powerup(sdev
->bus
, 0);
2184 "Failed to powerup the bus\n");
2185 goto err_out_free_dev
;
2187 err
= ssb_dma_set_mask(sdev
, DMA_BIT_MASK(30));
2190 "Required 30BIT DMA mask unsupported by the system.\n");
2191 goto err_out_powerdown
;
2193 err
= b44_get_invariants(bp
);
2196 "Problem fetching invariants of chip, aborting.\n");
2197 goto err_out_powerdown
;
2200 bp
->mii_if
.dev
= dev
;
2201 bp
->mii_if
.mdio_read
= b44_mii_read
;
2202 bp
->mii_if
.mdio_write
= b44_mii_write
;
2203 bp
->mii_if
.phy_id
= bp
->phy_addr
;
2204 bp
->mii_if
.phy_id_mask
= 0x1f;
2205 bp
->mii_if
.reg_num_mask
= 0x1f;
2207 /* By default, advertise all speed/duplex settings. */
2208 bp
->flags
|= (B44_FLAG_ADV_10HALF
| B44_FLAG_ADV_10FULL
|
2209 B44_FLAG_ADV_100HALF
| B44_FLAG_ADV_100FULL
);
2211 /* By default, auto-negotiate PAUSE. */
2212 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
2214 err
= register_netdev(dev
);
2216 dev_err(sdev
->dev
, "Cannot register net device, aborting.\n");
2217 goto err_out_powerdown
;
2220 ssb_set_drvdata(sdev
, dev
);
2222 /* Chip reset provides power to the b44 MAC & PCI cores, which
2223 * is necessary for MAC register access.
2225 b44_chip_reset(bp
, B44_CHIP_RESET_FULL
);
2227 printk(KERN_INFO
"%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2228 dev
->name
, dev
->dev_addr
);
2233 ssb_bus_may_powerdown(sdev
->bus
);
2242 static void __devexit
b44_remove_one(struct ssb_device
*sdev
)
2244 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2246 unregister_netdev(dev
);
2247 ssb_device_disable(sdev
, 0);
2248 ssb_bus_may_powerdown(sdev
->bus
);
2250 ssb_pcihost_set_power_state(sdev
, PCI_D3hot
);
2251 ssb_set_drvdata(sdev
, NULL
);
2254 static int b44_suspend(struct ssb_device
*sdev
, pm_message_t state
)
2256 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2257 struct b44
*bp
= netdev_priv(dev
);
2259 if (!netif_running(dev
))
2262 del_timer_sync(&bp
->timer
);
2264 spin_lock_irq(&bp
->lock
);
2267 netif_carrier_off(bp
->dev
);
2268 netif_device_detach(bp
->dev
);
2271 spin_unlock_irq(&bp
->lock
);
2273 free_irq(dev
->irq
, dev
);
2274 if (bp
->flags
& B44_FLAG_WOL_ENABLE
) {
2275 b44_init_hw(bp
, B44_PARTIAL_RESET
);
2279 ssb_pcihost_set_power_state(sdev
, PCI_D3hot
);
2283 static int b44_resume(struct ssb_device
*sdev
)
2285 struct net_device
*dev
= ssb_get_drvdata(sdev
);
2286 struct b44
*bp
= netdev_priv(dev
);
2289 rc
= ssb_bus_powerup(sdev
->bus
, 0);
2292 "Failed to powerup the bus\n");
2296 if (!netif_running(dev
))
2299 rc
= request_irq(dev
->irq
, b44_interrupt
, IRQF_SHARED
, dev
->name
, dev
);
2301 printk(KERN_ERR PFX
"%s: request_irq failed\n", dev
->name
);
2305 spin_lock_irq(&bp
->lock
);
2308 b44_init_hw(bp
, B44_FULL_RESET
);
2309 netif_device_attach(bp
->dev
);
2310 spin_unlock_irq(&bp
->lock
);
2312 b44_enable_ints(bp
);
2313 netif_wake_queue(dev
);
2315 mod_timer(&bp
->timer
, jiffies
+ 1);
2320 static struct ssb_driver b44_ssb_driver
= {
2321 .name
= DRV_MODULE_NAME
,
2322 .id_table
= b44_ssb_tbl
,
2323 .probe
= b44_init_one
,
2324 .remove
= __devexit_p(b44_remove_one
),
2325 .suspend
= b44_suspend
,
2326 .resume
= b44_resume
,
2329 static inline int b44_pci_init(void)
2332 #ifdef CONFIG_B44_PCI
2333 err
= ssb_pcihost_register(&b44_pci_driver
);
2338 static inline void b44_pci_exit(void)
2340 #ifdef CONFIG_B44_PCI
2341 ssb_pcihost_unregister(&b44_pci_driver
);
2345 static int __init
b44_init(void)
2347 unsigned int dma_desc_align_size
= dma_get_cache_alignment();
2350 /* Setup paramaters for syncing RX/TX DMA descriptors */
2351 dma_desc_align_mask
= ~(dma_desc_align_size
- 1);
2352 dma_desc_sync_size
= max_t(unsigned int, dma_desc_align_size
, sizeof(struct dma_desc
));
2354 err
= b44_pci_init();
2357 err
= ssb_driver_register(&b44_ssb_driver
);
2363 static void __exit
b44_cleanup(void)
2365 ssb_driver_unregister(&b44_ssb_driver
);
2369 module_init(b44_init
);
2370 module_exit(b44_cleanup
);