1 /* cpwatchdog.c - driver implementation for hardware watchdog
2 * timers found on Sun Microsystems CP1400 and CP1500 boards.
4 * This device supports both the generic Linux watchdog
5 * interface and Solaris-compatible ioctls as best it is
8 * NOTE: CP1400 systems appear to have a defective intr_mask
9 * register on the PLD, preventing the disabling of
10 * timer interrupts. We use a timer to periodically
11 * reset 'stopped' watchdogs on affected platforms.
13 * TODO: DevFS support (/dev/watchdogs/0 ... /dev/watchdogs/2)
15 * Copyright (c) 2000 Eric Brower (ebrower@usa.net)
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/errno.h>
22 #include <linux/major.h>
23 #include <linux/init.h>
24 #include <linux/miscdevice.h>
25 #include <linux/sched.h>
26 #include <linux/interrupt.h>
27 #include <linux/ioport.h>
28 #include <linux/timer.h>
29 #include <linux/smp_lock.h>
32 #include <asm/oplib.h>
33 #include <asm/uaccess.h>
35 #include <asm/watchdog.h>
37 #define WD_OBPNAME "watchdog"
38 #define WD_BADMODEL "SUNW,501-5336"
39 #define WD_BTIMEOUT (jiffies + (HZ * 1000))
40 #define WD_BLIMIT 0xFFFF
42 #define WD0_DEVNAME "watchdog0"
43 #define WD1_DEVNAME "watchdog1"
44 #define WD2_DEVNAME "watchdog2"
51 /* Internal driver definitions
53 #define WD0_ID 0 /* Watchdog0 */
54 #define WD1_ID 1 /* Watchdog1 */
55 #define WD2_ID 2 /* Watchdog2 */
56 #define WD_NUMDEVS 3 /* Device contains 3 timers */
58 #define WD_INTR_OFF 0 /* Interrupt disable value */
59 #define WD_INTR_ON 1 /* Interrupt enable value */
61 #define WD_STAT_INIT 0x01 /* Watchdog timer is initialized */
62 #define WD_STAT_BSTOP 0x02 /* Watchdog timer is brokenstopped */
63 #define WD_STAT_SVCD 0x04 /* Watchdog interrupt occurred */
65 /* Register value definitions
67 #define WD0_INTR_MASK 0x01 /* Watchdog device interrupt masks */
68 #define WD1_INTR_MASK 0x02
69 #define WD2_INTR_MASK 0x04
71 #define WD_S_RUNNING 0x01 /* Watchdog device status running */
72 #define WD_S_EXPIRED 0x02 /* Watchdog device status expired */
74 /* Sun uses Altera PLD EPF8820ATC144-4
75 * providing three hardware watchdogs:
77 * 1) RIC - sends an interrupt when triggered
78 * 2) XIR - asserts XIR_B_RESET when triggered, resets CPU
79 * 3) POR - asserts POR_B_RESET when triggered, resets CPU, backplane, board
81 *** Timer register block definition (struct wd_timer_regblk)
83 * dcntr and limit registers (halfword access):
89 * dcntr - Current 16-bit downcounter value.
90 * When downcounter reaches '0' watchdog expires.
91 * Reading this register resets downcounter with 'limit' value.
92 * limit - 16-bit countdown value in 1/10th second increments.
93 * Writing this register begins countdown with input value.
94 * Reading from this register does not affect counter.
95 * NOTES: After watchdog reset, dcntr and limit contain '1'
97 * status register (byte access):
98 * ---------------------------
99 * | 7 | ... | 2 | 1 | 0 |
100 * --------------+------------
101 * |- UNUSED -| EXP | RUN |
102 * ---------------------------
103 * status- Bit 0 - Watchdog is running
104 * Bit 1 - Watchdog has expired
106 *** PLD register block definition (struct wd_pld_regblk)
108 * intr_mask register (byte access):
109 * ---------------------------------
110 * | 7 | ... | 3 | 2 | 1 | 0 |
111 * +-------------+------------------
112 * |- UNUSED -| WD3 | WD2 | WD1 |
113 * ---------------------------------
114 * WD3 - 1 == Interrupt disabled for watchdog 3
115 * WD2 - 1 == Interrupt disabled for watchdog 2
116 * WD1 - 1 == Interrupt disabled for watchdog 1
118 * pld_status register (byte access):
119 * UNKNOWN, MAGICAL MYSTERY REGISTER
122 #define WD_TIMER_REGSZ 16
124 #define WD1_OFF (WD_TIMER_REGSZ * 1)
125 #define WD2_OFF (WD_TIMER_REGSZ * 2)
126 #define PLD_OFF (WD_TIMER_REGSZ * 3)
128 #define WD_DCNTR 0x00
129 #define WD_LIMIT 0x04
130 #define WD_STATUS 0x08
132 #define PLD_IMASK (PLD_OFF + 0x00)
133 #define PLD_STATUS (PLD_OFF + 0x04)
135 /* Individual timer structure
140 unsigned char runstatus
;
149 unsigned char isbaddoggie
; /* defective PLD */
150 unsigned char opt_enable
;
151 unsigned char opt_reboot
;
152 unsigned short opt_timeout
;
153 unsigned char initialized
;
154 struct wd_timer watchdog
[WD_NUMDEVS
];
158 static struct wd_device wd_dev
= {
159 0, SPIN_LOCK_UNLOCKED
, 0, 0, 0, 0,
162 static struct timer_list wd_timer
;
164 static int wd0_timeout
= 0;
165 static int wd1_timeout
= 0;
166 static int wd2_timeout
= 0;
169 module_param (wd0_timeout
, int, 0);
170 MODULE_PARM_DESC(wd0_timeout
, "Default watchdog0 timeout in 1/10secs");
171 module_param (wd1_timeout
, int, 0);
172 MODULE_PARM_DESC(wd1_timeout
, "Default watchdog1 timeout in 1/10secs");
173 module_param (wd2_timeout
, int, 0);
174 MODULE_PARM_DESC(wd2_timeout
, "Default watchdog2 timeout in 1/10secs");
177 ("Eric Brower <ebrower@usa.net>");
179 ("Hardware watchdog driver for Sun Microsystems CP1400/1500");
180 MODULE_LICENSE("GPL");
181 MODULE_SUPPORTED_DEVICE
183 #endif /* ifdef MODULE */
185 /* Forward declarations of internal methods
188 static void wd_dumpregs(void);
190 static irqreturn_t
wd_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
191 static void wd_toggleintr(struct wd_timer
* pTimer
, int enable
);
192 static void wd_pingtimer(struct wd_timer
* pTimer
);
193 static void wd_starttimer(struct wd_timer
* pTimer
);
194 static void wd_resetbrokentimer(struct wd_timer
* pTimer
);
195 static void wd_stoptimer(struct wd_timer
* pTimer
);
196 static void wd_brokentimer(unsigned long data
);
197 static int wd_getstatus(struct wd_timer
* pTimer
);
199 /* PLD expects words to be written in LSB format,
200 * so we must flip all words prior to writing them to regs
202 static inline unsigned short flip_word(unsigned short word
)
204 return ((word
& 0xff) << 8) | ((word
>> 8) & 0xff);
207 #define wd_writew(val, addr) (writew(flip_word(val), addr))
208 #define wd_readw(addr) (flip_word(readw(addr)))
209 #define wd_writeb(val, addr) (writeb(val, addr))
210 #define wd_readb(addr) (readb(addr))
213 /* CP1400s seem to have broken PLD implementations--
214 * the interrupt_mask register cannot be written, so
215 * no timer interrupts can be masked within the PLD.
217 static inline int wd_isbroken(void)
219 /* we could test this by read/write/read/restore
220 * on the interrupt mask register only if OBP
221 * 'watchdog-enable?' == FALSE, but it seems
222 * ubiquitous on CP1400s
225 prom_getproperty(prom_root_node
, "model", val
, sizeof(val
));
226 return((!strcmp(val
, WD_BADMODEL
)) ? 1 : 0);
229 /* Retrieve watchdog-enable? option from OBP
230 * Returns 0 if false, 1 if true
232 static inline int wd_opt_enable(void)
236 opt_node
= prom_getchild(prom_root_node
);
237 opt_node
= prom_searchsiblings(opt_node
, "options");
238 return((-1 == prom_getint(opt_node
, "watchdog-enable?")) ? 0 : 1);
241 /* Retrieve watchdog-reboot? option from OBP
242 * Returns 0 if false, 1 if true
244 static inline int wd_opt_reboot(void)
248 opt_node
= prom_getchild(prom_root_node
);
249 opt_node
= prom_searchsiblings(opt_node
, "options");
250 return((-1 == prom_getint(opt_node
, "watchdog-reboot?")) ? 0 : 1);
253 /* Retrieve watchdog-timeout option from OBP
254 * Returns OBP value, or 0 if not located
256 static inline int wd_opt_timeout(void)
262 opt_node
= prom_getchild(prom_root_node
);
263 opt_node
= prom_searchsiblings(opt_node
, "options");
264 opt_node
= prom_getproperty(opt_node
,
269 /* atoi implementation */
270 for(opt_node
= 0; /* nop */; p
++) {
271 if(*p
>= '0' && *p
<= '9') {
272 opt_node
= (10*opt_node
)+(*p
-'0');
279 return((-1 == opt_node
) ? (0) : (opt_node
));
282 static int wd_open(struct inode
*inode
, struct file
*f
)
284 switch(iminor(inode
))
287 f
->private_data
= &wd_dev
.watchdog
[WD0_ID
];
290 f
->private_data
= &wd_dev
.watchdog
[WD1_ID
];
293 f
->private_data
= &wd_dev
.watchdog
[WD2_ID
];
299 /* Register IRQ on first open of device */
300 if(0 == wd_dev
.initialized
)
302 if (request_irq(wd_dev
.irq
,
306 (void *)wd_dev
.regs
)) {
307 printk("%s: Cannot register IRQ %s\n",
308 WD_OBPNAME
, __irq_itoa(wd_dev
.irq
));
311 wd_dev
.initialized
= 1;
314 return(nonseekable_open(inode
, f
));
317 static int wd_release(struct inode
*inode
, struct file
*file
)
322 static int wd_ioctl(struct inode
*inode
, struct file
*file
,
323 unsigned int cmd
, unsigned long arg
)
326 struct wd_timer
* pTimer
= (struct wd_timer
*)file
->private_data
;
327 void __user
*argp
= (void __user
*)arg
;
328 struct watchdog_info info
= {
331 "Altera EPF8820ATC144-4"
340 /* Generic Linux IOCTLs */
341 case WDIOC_GETSUPPORT
:
342 if(copy_to_user(argp
, &info
, sizeof(struct watchdog_info
))) {
346 case WDIOC_GETSTATUS
:
347 case WDIOC_GETBOOTSTATUS
:
348 if (put_user(0, (int __user
*)argp
))
351 case WDIOC_KEEPALIVE
:
352 wd_pingtimer(pTimer
);
354 case WDIOC_SETOPTIONS
:
355 if(copy_from_user(&setopt
, argp
, sizeof(unsigned int))) {
358 if(setopt
& WDIOS_DISABLECARD
) {
359 if(wd_dev
.opt_enable
) {
361 "%s: cannot disable watchdog in ENABLED mode\n",
365 wd_stoptimer(pTimer
);
367 else if(setopt
& WDIOS_ENABLECARD
) {
368 wd_starttimer(pTimer
);
374 /* Solaris-compatible IOCTLs */
376 setopt
= wd_getstatus(pTimer
);
377 if(copy_to_user(argp
, &setopt
, sizeof(unsigned int))) {
382 wd_starttimer(pTimer
);
385 if(wd_dev
.opt_enable
) {
386 printk("%s: cannot disable watchdog in ENABLED mode\n",
390 wd_stoptimer(pTimer
);
398 static long wd_compat_ioctl(struct file
*file
, unsigned int cmd
,
401 int rval
= -ENOIOCTLCMD
;
404 /* solaris ioctls are specific to this driver */
409 rval
= wd_ioctl(file
->f_dentry
->d_inode
, file
, cmd
, arg
);
412 /* everything else is handled by the generic compat layer */
420 static ssize_t
wd_write(struct file
*file
,
421 const char __user
*buf
,
425 struct wd_timer
* pTimer
= (struct wd_timer
*)file
->private_data
;
432 wd_pingtimer(pTimer
);
438 static ssize_t
wd_read(struct file
* file
, char __user
*buffer
,
439 size_t count
, loff_t
*ppos
)
446 #endif /* ifdef WD_DEBUG */
449 static irqreturn_t
wd_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
451 /* Only WD0 will interrupt-- others are NMI and we won't
454 spin_lock_irq(&wd_dev
.lock
);
455 if((unsigned long)wd_dev
.regs
== (unsigned long)dev_id
)
457 wd_stoptimer(&wd_dev
.watchdog
[WD0_ID
]);
458 wd_dev
.watchdog
[WD0_ID
].runstatus
|= WD_STAT_SVCD
;
460 spin_unlock_irq(&wd_dev
.lock
);
464 static struct file_operations wd_fops
= {
465 .owner
= THIS_MODULE
,
467 .compat_ioctl
= wd_compat_ioctl
,
471 .release
= wd_release
,
474 static struct miscdevice wd0_miscdev
= { WD0_MINOR
, WD0_DEVNAME
, &wd_fops
};
475 static struct miscdevice wd1_miscdev
= { WD1_MINOR
, WD1_DEVNAME
, &wd_fops
};
476 static struct miscdevice wd2_miscdev
= { WD2_MINOR
, WD2_DEVNAME
, &wd_fops
};
479 static void wd_dumpregs(void)
481 /* Reading from downcounters initiates watchdog countdown--
482 * Example is included below for illustration purposes.
485 printk("%s: dumping register values\n", WD_OBPNAME
);
486 for(i
= WD0_ID
; i
< WD_NUMDEVS
; ++i
) {
487 /* printk("\t%s%i: dcntr at 0x%lx: 0x%x\n",
490 * (unsigned long)(&wd_dev.watchdog[i].regs->dcntr),
491 * readw(&wd_dev.watchdog[i].regs->dcntr));
493 printk("\t%s%i: limit at 0x%lx: 0x%x\n",
496 (unsigned long)(&wd_dev
.watchdog
[i
].regs
->limit
),
497 readw(&wd_dev
.watchdog
[i
].regs
->limit
));
498 printk("\t%s%i: status at 0x%lx: 0x%x\n",
501 (unsigned long)(&wd_dev
.watchdog
[i
].regs
->status
),
502 readb(&wd_dev
.watchdog
[i
].regs
->status
));
503 printk("\t%s%i: driver status: 0x%x\n",
506 wd_getstatus(&wd_dev
.watchdog
[i
]));
508 printk("\tintr_mask at %p: 0x%x\n",
509 wd_dev
.regs
+ PLD_IMASK
,
510 readb(wd_dev
.regs
+ PLD_IMASK
));
511 printk("\tpld_status at %p: 0x%x\n",
512 wd_dev
.regs
+ PLD_STATUS
,
513 readb(wd_dev
.regs
+ PLD_STATUS
));
517 /* Enable or disable watchdog interrupts
518 * Because of the CP1400 defect this should only be
519 * called during initialzation or by wd_[start|stop]timer()
521 * pTimer - pointer to timer device, or NULL to indicate all timers
522 * enable - non-zero to enable interrupts, zero to disable
524 static void wd_toggleintr(struct wd_timer
* pTimer
, int enable
)
526 unsigned char curregs
= wd_readb(wd_dev
.regs
+ PLD_IMASK
);
527 unsigned char setregs
=
529 (WD0_INTR_MASK
| WD1_INTR_MASK
| WD2_INTR_MASK
) :
532 (WD_INTR_ON
== enable
) ?
533 (curregs
&= ~setregs
):
534 (curregs
|= setregs
);
536 wd_writeb(curregs
, wd_dev
.regs
+ PLD_IMASK
);
540 /* Reset countdown timer with 'limit' value and continue countdown.
541 * This will not start a stopped timer.
543 * pTimer - pointer to timer device
545 static void wd_pingtimer(struct wd_timer
* pTimer
)
547 if (wd_readb(pTimer
->regs
+ WD_STATUS
) & WD_S_RUNNING
) {
548 wd_readw(pTimer
->regs
+ WD_DCNTR
);
552 /* Stop a running watchdog timer-- the timer actually keeps
553 * running, but the interrupt is masked so that no action is
554 * taken upon expiration.
556 * pTimer - pointer to timer device
558 static void wd_stoptimer(struct wd_timer
* pTimer
)
560 if(wd_readb(pTimer
->regs
+ WD_STATUS
) & WD_S_RUNNING
) {
561 wd_toggleintr(pTimer
, WD_INTR_OFF
);
563 if(wd_dev
.isbaddoggie
) {
564 pTimer
->runstatus
|= WD_STAT_BSTOP
;
565 wd_brokentimer((unsigned long)&wd_dev
);
570 /* Start a watchdog timer with the specified limit value
571 * If the watchdog is running, it will be restarted with
572 * the provided limit value.
574 * This function will enable interrupts on the specified
577 * pTimer - pointer to timer device
578 * limit - limit (countdown) value in 1/10th seconds
580 static void wd_starttimer(struct wd_timer
* pTimer
)
582 if(wd_dev
.isbaddoggie
) {
583 pTimer
->runstatus
&= ~WD_STAT_BSTOP
;
585 pTimer
->runstatus
&= ~WD_STAT_SVCD
;
587 wd_writew(pTimer
->timeout
, pTimer
->regs
+ WD_LIMIT
);
588 wd_toggleintr(pTimer
, WD_INTR_ON
);
591 /* Restarts timer with maximum limit value and
592 * does not unset 'brokenstop' value.
594 static void wd_resetbrokentimer(struct wd_timer
* pTimer
)
596 wd_toggleintr(pTimer
, WD_INTR_ON
);
597 wd_writew(WD_BLIMIT
, pTimer
->regs
+ WD_LIMIT
);
600 /* Timer device initialization helper.
601 * Returns 0 on success, other on failure
603 static int wd_inittimer(int whichdog
)
605 struct miscdevice
*whichmisc
;
606 void __iomem
*whichregs
;
614 whichmisc
= &wd0_miscdev
;
615 strcpy(whichident
, "RIC");
616 whichregs
= wd_dev
.regs
+ WD0_OFF
;
617 whichmask
= WD0_INTR_MASK
;
618 whichlimit
= (0 == wd0_timeout
) ?
619 (wd_dev
.opt_timeout
):
623 whichmisc
= &wd1_miscdev
;
624 strcpy(whichident
, "XIR");
625 whichregs
= wd_dev
.regs
+ WD1_OFF
;
626 whichmask
= WD1_INTR_MASK
;
627 whichlimit
= (0 == wd1_timeout
) ?
628 (wd_dev
.opt_timeout
):
632 whichmisc
= &wd2_miscdev
;
633 strcpy(whichident
, "POR");
634 whichregs
= wd_dev
.regs
+ WD2_OFF
;
635 whichmask
= WD2_INTR_MASK
;
636 whichlimit
= (0 == wd2_timeout
) ?
637 (wd_dev
.opt_timeout
):
641 printk("%s: %s: invalid watchdog id: %i\n",
642 WD_OBPNAME
, __FUNCTION__
, whichdog
);
645 if(0 != misc_register(whichmisc
))
649 wd_dev
.watchdog
[whichdog
].regs
= whichregs
;
650 wd_dev
.watchdog
[whichdog
].timeout
= whichlimit
;
651 wd_dev
.watchdog
[whichdog
].intr_mask
= whichmask
;
652 wd_dev
.watchdog
[whichdog
].runstatus
&= ~WD_STAT_BSTOP
;
653 wd_dev
.watchdog
[whichdog
].runstatus
|= WD_STAT_INIT
;
655 printk("%s%i: %s hardware watchdog [%01i.%i sec] %s\n",
659 wd_dev
.watchdog
[whichdog
].timeout
/ 10,
660 wd_dev
.watchdog
[whichdog
].timeout
% 10,
661 (0 != wd_dev
.opt_enable
) ? "in ENABLED mode" : "");
665 /* Timer method called to reset stopped watchdogs--
666 * because of the PLD bug on CP1400, we cannot mask
667 * interrupts within the PLD so me must continually
668 * reset the timers ad infinitum.
670 static void wd_brokentimer(unsigned long data
)
672 struct wd_device
* pDev
= (struct wd_device
*)data
;
675 /* kill a running timer instance, in case we
676 * were called directly instead of by kernel timer
678 if(timer_pending(&wd_timer
)) {
679 del_timer(&wd_timer
);
682 for(id
= WD0_ID
; id
< WD_NUMDEVS
; ++id
) {
683 if(pDev
->watchdog
[id
].runstatus
& WD_STAT_BSTOP
) {
685 wd_resetbrokentimer(&pDev
->watchdog
[id
]);
690 /* there is at least one timer brokenstopped-- reschedule */
691 init_timer(&wd_timer
);
692 wd_timer
.expires
= WD_BTIMEOUT
;
693 add_timer(&wd_timer
);
697 static int wd_getstatus(struct wd_timer
* pTimer
)
699 unsigned char stat
= wd_readb(pTimer
->regs
+ WD_STATUS
);
700 unsigned char intr
= wd_readb(wd_dev
.regs
+ PLD_IMASK
);
701 unsigned char ret
= WD_STOPPED
;
703 /* determine STOPPED */
707 /* determine EXPIRED vs FREERUN vs RUNNING */
708 else if(WD_S_EXPIRED
& stat
) {
711 else if(WD_S_RUNNING
& stat
) {
712 if(intr
& pTimer
->intr_mask
) {
716 /* Fudge WD_EXPIRED status for defective CP1400--
717 * IF timer is running
718 * AND brokenstop is set
719 * AND an interrupt has been serviced
722 * IF timer is running
723 * AND brokenstop is set
724 * AND no interrupt has been serviced
727 if(wd_dev
.isbaddoggie
&& (pTimer
->runstatus
& WD_STAT_BSTOP
)) {
728 if(pTimer
->runstatus
& WD_STAT_SVCD
) {
732 /* we could as well pretend we are expired */
742 /* determine SERVICED */
743 if(pTimer
->runstatus
& WD_STAT_SVCD
) {
750 static int __init
wd_init(void)
753 struct linux_ebus
*ebus
= NULL
;
754 struct linux_ebus_device
*edev
= NULL
;
756 for_each_ebus(ebus
) {
757 for_each_ebusdev(edev
, ebus
) {
758 if (!strcmp(edev
->prom_name
, WD_OBPNAME
))
765 printk("%s: unable to locate device\n", WD_OBPNAME
);
770 ioremap(edev
->resource
[0].start
, 4 * WD_TIMER_REGSZ
); /* ? */
772 if(NULL
== wd_dev
.regs
) {
773 printk("%s: unable to map registers\n", WD_OBPNAME
);
777 /* initialize device structure from OBP parameters */
778 wd_dev
.irq
= edev
->irqs
[0];
779 wd_dev
.opt_enable
= wd_opt_enable();
780 wd_dev
.opt_reboot
= wd_opt_reboot();
781 wd_dev
.opt_timeout
= wd_opt_timeout();
782 wd_dev
.isbaddoggie
= wd_isbroken();
784 /* disable all interrupts unless watchdog-enabled? == true */
785 if(! wd_dev
.opt_enable
) {
786 wd_toggleintr(NULL
, WD_INTR_OFF
);
789 /* register miscellaneous devices */
790 for(id
= WD0_ID
; id
< WD_NUMDEVS
; ++id
) {
791 if(0 != wd_inittimer(id
)) {
792 printk("%s%i: unable to initialize\n", WD_OBPNAME
, id
);
796 /* warn about possible defective PLD */
797 if(wd_dev
.isbaddoggie
) {
798 init_timer(&wd_timer
);
799 wd_timer
.function
= wd_brokentimer
;
800 wd_timer
.data
= (unsigned long)&wd_dev
;
801 wd_timer
.expires
= WD_BTIMEOUT
;
803 printk("%s: PLD defect workaround enabled for model %s\n",
804 WD_OBPNAME
, WD_BADMODEL
);
809 static void __exit
wd_cleanup(void)
813 /* if 'watchdog-enable?' == TRUE, timers are not stopped
814 * when module is unloaded. All brokenstopped timers will
815 * also now eventually trip.
817 for(id
= WD0_ID
; id
< WD_NUMDEVS
; ++id
) {
818 if(WD_S_RUNNING
== wd_readb(wd_dev
.watchdog
[id
].regs
+ WD_STATUS
)) {
819 if(wd_dev
.opt_enable
) {
820 printk(KERN_WARNING
"%s%i: timer not stopped at release\n",
824 wd_stoptimer(&wd_dev
.watchdog
[id
]);
825 if(wd_dev
.watchdog
[id
].runstatus
& WD_STAT_BSTOP
) {
826 wd_resetbrokentimer(&wd_dev
.watchdog
[id
]);
828 "%s%i: defect workaround disabled at release, "\
829 "timer expires in ~%01i sec\n",
831 wd_readw(wd_dev
.watchdog
[id
].regs
+ WD_LIMIT
) / 10);
837 if(wd_dev
.isbaddoggie
&& timer_pending(&wd_timer
)) {
838 del_timer(&wd_timer
);
840 if(0 != (wd_dev
.watchdog
[WD0_ID
].runstatus
& WD_STAT_INIT
)) {
841 misc_deregister(&wd0_miscdev
);
843 if(0 != (wd_dev
.watchdog
[WD1_ID
].runstatus
& WD_STAT_INIT
)) {
844 misc_deregister(&wd1_miscdev
);
846 if(0 != (wd_dev
.watchdog
[WD2_ID
].runstatus
& WD_STAT_INIT
)) {
847 misc_deregister(&wd2_miscdev
);
849 if(0 != wd_dev
.initialized
) {
850 free_irq(wd_dev
.irq
, (void *)wd_dev
.regs
);
852 iounmap(wd_dev
.regs
);
855 module_init(wd_init
);
856 module_exit(wd_cleanup
);