arch/x86/include/asm/i387.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  *
   4  * Pentium III FXSR, SSE support
   5  * General FPU state handling cleanups
   6  *      Gareth Hughes <gareth@valinux.com>, May 2000
   7  * x86-64 work by Andi Kleen 2002
   8  */
   9
  10 #ifndef _ASM_X86_I387_H
  11 #define _ASM_X86_I387_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/regset.h>
  16 #include <linux/hardirq.h>
  17 #include <asm/asm.h>
  18 #include <asm/processor.h>
  19 #include <asm/sigcontext.h>
  20 #include <asm/user.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/xsave.h>
  23
  24 extern unsigned int sig_xstate_size;
  25 extern void fpu_init(void);
  26 extern void mxcsr_feature_mask_init(void);
  27 extern int init_fpu(struct task_struct *child);
  28 extern asmlinkage void math_state_restore(void);
  29 extern void init_thread_xstate(void);
  30 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
  31
  32 extern user_regset_active_fn fpregs_active, xfpregs_active;
  33 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
  34 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
  35
  36 extern struct _fpx_sw_bytes fx_sw_reserved;
  37 #ifdef CONFIG_IA32_EMULATION
  38 extern unsigned int sig_xstate_ia32_size;
  39 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
  40 struct _fpstate_ia32;
  41 struct _xstate_ia32;
  42 extern int save_i387_xstate_ia32(void __user *buf);
  43 extern int restore_i387_xstate_ia32(void __user *buf);
  44 #endif
  45
  46 #define X87_FSW_ES (1 << 7)     /* Exception Summary */
  47
  48 #ifdef CONFIG_X86_64
  49
  50 /* Ignore delayed exceptions from user space */
  51 static inline void tolerant_fwait(void)
  52 {
  53         asm volatile("1: fwait\n"
  54                      "2:\n"
  55                      _ASM_EXTABLE(1b, 2b));
  56 }
  57
  58 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  59 {
  60         int err;
  61
  62         asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
  63                      "2:\n"
  64                      ".section .fixup,\"ax\"\n"
  65                      "3:  movl $-1,%[err]\n"
  66                      "    jmp  2b\n"
  67                      ".previous\n"
  68                      _ASM_EXTABLE(1b, 3b)
  69                      : [err] "=r" (err)
  70 #if 0 /* See comment in __save_init_fpu() below. */
  71                      : [fx] "r" (fx), "m" (*fx), "0" (0));
  72 #else
  73                      : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
  74 #endif
  75         return err;
  76 }
  77
  78 static inline int restore_fpu_checking(struct task_struct *tsk)
  79 {
  80         if (task_thread_info(tsk)->status & TS_XSAVE)
  81                 return xrstor_checking(&tsk->thread.xstate->xsave);
  82         else
  83                 return fxrstor_checking(&tsk->thread.xstate->fxsave);
  84 }
  85
  86 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
  87    is pending. Clear the x87 state here by setting it to fixed
  88    values. The kernel data segment can be sometimes 0 and sometimes
  89    new user value. Both should be ok.
  90    Use the PDA as safe address because it should be already in L1. */
  91 static inline void clear_fpu_state(struct task_struct *tsk)
  92 {
  93         struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
  94         struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
  95
  96         /*
  97          * xsave header may indicate the init state of the FP.
  98          */
  99         if ((task_thread_info(tsk)->status & TS_XSAVE) &&
 100             !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
 101                 return;
 102
 103         if (unlikely(fx->swd & X87_FSW_ES))
 104                 asm volatile("fnclex");
 105         alternative_input(ASM_NOP8 ASM_NOP2,
 106                           "    emms\n"          /* clear stack tags */
 107                           "    fildl %%gs:0",   /* load to clear state */
 108                           X86_FEATURE_FXSAVE_LEAK);
 109 }
 110
 111 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
 112 {
 113         int err;
 114
 115         asm volatile("1:  rex64/fxsave (%[fx])\n\t"
 116                      "2:\n"
 117                      ".section .fixup,\"ax\"\n"
 118                      "3:  movl $-1,%[err]\n"
 119                      "    jmp  2b\n"
 120                      ".previous\n"
 121                      _ASM_EXTABLE(1b, 3b)
 122                      : [err] "=r" (err), "=m" (*fx)
 123 #if 0 /* See comment in __fxsave_clear() below. */
 124                      : [fx] "r" (fx), "0" (0));
 125 #else
 126                      : [fx] "cdaSDb" (fx), "0" (0));
 127 #endif
 128         if (unlikely(err) &&
 129             __clear_user(fx, sizeof(struct i387_fxsave_struct)))
 130                 err = -EFAULT;
 131         /* No need to clear here because the caller clears USED_MATH */
 132         return err;
 133 }
 134
 135 static inline void fxsave(struct task_struct *tsk)
 136 {
 137         /* Using "rex64; fxsave %0" is broken because, if the memory operand
 138            uses any extended registers for addressing, a second REX prefix
 139            will be generated (to the assembler, rex64 followed by semicolon
 140            is a separate instruction), and hence the 64-bitness is lost. */
 141 #if 0
 142         /* Using "fxsaveq %0" would be the ideal choice, but is only supported
 143            starting with gas 2.16. */
 144         __asm__ __volatile__("fxsaveq %0"
 145                              : "=m" (tsk->thread.xstate->fxsave));
 146 #elif 0
 147         /* Using, as a workaround, the properly prefixed form below isn't
 148            accepted by any binutils version so far released, complaining that
 149            the same type of prefix is used twice if an extended register is
 150            needed for addressing (fix submitted to mainline 2005-11-21). */
 151         __asm__ __volatile__("rex64/fxsave %0"
 152                              : "=m" (tsk->thread.xstate->fxsave));
 153 #else
 154         /* This, however, we can work around by forcing the compiler to select
 155            an addressing mode that doesn't require extended registers. */
 156         __asm__ __volatile__("rex64/fxsave (%1)"
 157                              : "=m" (tsk->thread.xstate->fxsave)
 158                              : "cdaSDb" (&tsk->thread.xstate->fxsave));
 159 #endif
 160 }
 161
 162 static inline void __save_init_fpu(struct task_struct *tsk)
 163 {
 164         if (task_thread_info(tsk)->status & TS_XSAVE)
 165                 xsave(tsk);
 166         else
 167                 fxsave(tsk);
 168
 169         clear_fpu_state(tsk);
 170         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 171 }
 172
 173 #else  /* CONFIG_X86_32 */
 174
 175 extern void finit(void);
 176
 177 static inline void tolerant_fwait(void)
 178 {
 179         asm volatile("fnclex ; fwait");
 180 }
 181
 182 static inline void restore_fpu(struct task_struct *tsk)
 183 {
 184         if (task_thread_info(tsk)->status & TS_XSAVE) {
 185                 xrstor_checking(&tsk->thread.xstate->xsave);
 186                 return;
 187         }
 188         /*
 189          * The "nop" is needed to make the instructions the same
 190          * length.
 191          */
 192         alternative_input(
 193                 "nop ; frstor %1",
 194                 "fxrstor %1",
 195                 X86_FEATURE_FXSR,
 196                 "m" (tsk->thread.xstate->fxsave));
 197 }
 198
 199 /* We need a safe address that is cheap to find and that is already
 200    in L1 during context switch. The best choices are unfortunately
 201    different for UP and SMP */
 202 #ifdef CONFIG_SMP
 203 #define safe_address (__per_cpu_offset[0])
 204 #else
 205 #define safe_address (kstat_cpu(0).cpustat.user)
 206 #endif
 207
 208 /*
 209  * These must be called with preempt disabled
 210  */
 211 static inline void __save_init_fpu(struct task_struct *tsk)
 212 {
 213         if (task_thread_info(tsk)->status & TS_XSAVE) {
 214                 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
 215                 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
 216
 217                 xsave(tsk);
 218
 219                 /*
 220                  * xsave header may indicate the init state of the FP.
 221                  */
 222                 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
 223                         goto end;
 224
 225                 if (unlikely(fx->swd & X87_FSW_ES))
 226                         asm volatile("fnclex");
 227
 228                 /*
 229                  * we can do a simple return here or be paranoid :)
 230                  */
 231                 goto clear_state;
 232         }
 233
 234         /* Use more nops than strictly needed in case the compiler
 235            varies code */
 236         alternative_input(
 237                 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
 238                 "fxsave %[fx]\n"
 239                 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
 240                 X86_FEATURE_FXSR,
 241                 [fx] "m" (tsk->thread.xstate->fxsave),
 242                 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
 243 clear_state:
 244         /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
 245            is pending.  Clear the x87 state here by setting it to fixed
 246            values. safe_address is a random variable that should be in L1 */
 247         alternative_input(
 248                 GENERIC_NOP8 GENERIC_NOP2,
 249                 "emms\n\t"              /* clear stack tags */
 250                 "fildl %[addr]",        /* set F?P to defined value */
 251                 X86_FEATURE_FXSAVE_LEAK,
 252                 [addr] "m" (safe_address));
 253 end:
 254         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 255 }
 256
 257 #endif  /* CONFIG_X86_64 */
 258
 259 /*
 260  * Signal frame handlers...
 261  */
 262 extern int save_i387_xstate(void __user *buf);
 263 extern int restore_i387_xstate(void __user *buf);
 264
 265 static inline void __unlazy_fpu(struct task_struct *tsk)
 266 {
 267         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 268                 __save_init_fpu(tsk);
 269                 stts();
 270         } else
 271                 tsk->fpu_counter = 0;
 272 }
 273
 274 static inline void __clear_fpu(struct task_struct *tsk)
 275 {
 276         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 277                 tolerant_fwait();
 278                 task_thread_info(tsk)->status &= ~TS_USEDFPU;
 279                 stts();
 280         }
 281 }
 282
 283 static inline void kernel_fpu_begin(void)
 284 {
 285         struct thread_info *me = current_thread_info();
 286         preempt_disable();
 287         if (me->status & TS_USEDFPU)
 288                 __save_init_fpu(me->task);
 289         else
 290                 clts();
 291 }
 292
 293 static inline void kernel_fpu_end(void)
 294 {
 295         stts();
 296         preempt_enable();
 297 }
 298
 299 /*
 300  * Some instructions like VIA's padlock instructions generate a spurious
 301  * DNA fault but don't modify SSE registers. And these instructions
 302  * get used from interrupt context aswell. To prevent these kernel instructions
 303  * in interrupt context interact wrongly with other user/kernel fpu usage, we
 304  * should use them only in the context of irq_ts_save/restore()
 305  */
 306 static inline int irq_ts_save(void)
 307 {
 308         /*
 309          * If we are in process context, we are ok to take a spurious DNA fault.
 310          * Otherwise, doing clts() in process context require pre-emption to
 311          * be disabled or some heavy lifting like kernel_fpu_begin()
 312          */
 313         if (!in_interrupt())
 314                 return 0;
 315
 316         if (read_cr0() & X86_CR0_TS) {
 317                 clts();
 318                 return 1;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static inline void irq_ts_restore(int TS_state)
 325 {
 326         if (TS_state)
 327                 stts();
 328 }
 329
 330 #ifdef CONFIG_X86_64
 331
 332 static inline void save_init_fpu(struct task_struct *tsk)
 333 {
 334         __save_init_fpu(tsk);
 335         stts();
 336 }
 337
 338 #define unlazy_fpu      __unlazy_fpu
 339 #define clear_fpu       __clear_fpu
 340
 341 #else  /* CONFIG_X86_32 */
 342
 343 /*
 344  * These disable preemption on their own and are safe
 345  */
 346 static inline void save_init_fpu(struct task_struct *tsk)
 347 {
 348         preempt_disable();
 349         __save_init_fpu(tsk);
 350         stts();
 351         preempt_enable();
 352 }
 353
 354 static inline void unlazy_fpu(struct task_struct *tsk)
 355 {
 356         preempt_disable();
 357         __unlazy_fpu(tsk);
 358         preempt_enable();
 359 }
 360
 361 static inline void clear_fpu(struct task_struct *tsk)
 362 {
 363         preempt_disable();
 364         __clear_fpu(tsk);
 365         preempt_enable();
 366 }
 367
 368 #endif  /* CONFIG_X86_64 */
 369
 370 /*
 371  * i387 state interaction
 372  */
 373 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
 374 {
 375         if (cpu_has_fxsr) {
 376                 return tsk->thread.xstate->fxsave.cwd;
 377         } else {
 378                 return (unsigned short)tsk->thread.xstate->fsave.cwd;
 379         }
 380 }
 381
 382 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
 383 {
 384         if (cpu_has_fxsr) {
 385                 return tsk->thread.xstate->fxsave.swd;
 386         } else {
 387                 return (unsigned short)tsk->thread.xstate->fsave.swd;
 388         }
 389 }
 390
 391 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
 392 {
 393         if (cpu_has_xmm) {
 394                 return tsk->thread.xstate->fxsave.mxcsr;
 395         } else {
 396                 return MXCSR_DEFAULT;
 397         }
 398 }
 399
 400 #endif /* _ASM_X86_I387_H */