2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the
23 * file called COPYING.
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
89 #include <asm/hardware/pl080.h>
91 #define DRIVER_NAME "pl08xdmac"
94 * struct vendor_data - vendor-specific config parameters
95 * for PL08x derivatives
96 * @channels: the number of channels available in this variant
97 * @dualmaster: whether this version supports dual AHB masters
106 * PL08X private data structures
107 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
108 * start & end do not - their bus bit info is in cctl. Also note that these
109 * are fixed 32-bit quantities.
119 * struct pl08x_driver_data - the local state holder for the PL08x
120 * @slave: slave engine for this instance
121 * @memcpy: memcpy engine for this instance
122 * @base: virtual memory base (remapped) for the PL08x
123 * @adev: the corresponding AMBA (PrimeCell) bus entry
124 * @vd: vendor data for this PL08x variant
125 * @pd: platform data passed in from the platform/machine
126 * @phy_chans: array of data for the physical channels
127 * @pool: a pool for the LLI descriptors
128 * @pool_ctr: counter of LLIs in the pool
129 * @lock: a spinlock for this struct
131 struct pl08x_driver_data
{
132 struct dma_device slave
;
133 struct dma_device memcpy
;
135 struct amba_device
*adev
;
136 const struct vendor_data
*vd
;
137 struct pl08x_platform_data
*pd
;
138 struct pl08x_phy_chan
*phy_chans
;
139 struct dma_pool
*pool
;
145 * PL08X specific defines
149 * Memory boundaries: the manual for PL08x says that the controller
150 * cannot read past a 1KiB boundary, so these defines are used to
151 * create transfer LLIs that do not cross such boundaries.
153 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
154 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
156 /* Minimum period between work queue runs */
157 #define PL08X_WQ_PERIODMIN 20
159 /* Size (bytes) of each LLI buffer allocated for one transfer */
160 # define PL08X_LLI_TSFR_SIZE 0x2000
162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
163 #define PL08X_MAX_ALLOCS 0x40
164 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
165 #define PL08X_ALIGN 8
167 static inline struct pl08x_dma_chan
*to_pl08x_chan(struct dma_chan
*chan
)
169 return container_of(chan
, struct pl08x_dma_chan
, chan
);
173 * Physical channel handling
176 /* Whether a certain channel is busy or not */
177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan
*ch
)
181 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
182 return val
& PL080_CONFIG_ACTIVE
;
186 * Set the initial DMA register values i.e. those for the first LLI
187 * The next LLI pointer and the configuration interrupt bit have
188 * been set when the LLIs were constructed
190 static void pl08x_set_cregs(struct pl08x_driver_data
*pl08x
,
191 struct pl08x_phy_chan
*ch
)
193 /* Wait for channel inactive */
194 while (pl08x_phy_channel_busy(ch
))
197 dev_vdbg(&pl08x
->adev
->dev
,
198 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
199 "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
207 writel(ch
->csrc
, ch
->base
+ PL080_CH_SRC_ADDR
);
208 writel(ch
->cdst
, ch
->base
+ PL080_CH_DST_ADDR
);
209 writel(ch
->clli
, ch
->base
+ PL080_CH_LLI
);
210 writel(ch
->cctl
, ch
->base
+ PL080_CH_CONTROL
);
211 writel(ch
->ccfg
, ch
->base
+ PL080_CH_CONFIG
);
214 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan
*plchan
)
216 struct pl08x_channel_data
*cd
= plchan
->cd
;
217 struct pl08x_phy_chan
*phychan
= plchan
->phychan
;
218 struct pl08x_txd
*txd
= plchan
->at
;
220 /* Copy the basic control register calculated at transfer config */
221 phychan
->csrc
= txd
->csrc
;
222 phychan
->cdst
= txd
->cdst
;
223 phychan
->clli
= txd
->clli
;
224 phychan
->cctl
= txd
->cctl
;
226 /* Assign the signal to the proper control registers */
227 phychan
->ccfg
= cd
->ccfg
;
228 phychan
->ccfg
&= ~PL080_CONFIG_SRC_SEL_MASK
;
229 phychan
->ccfg
&= ~PL080_CONFIG_DST_SEL_MASK
;
230 /* If it wasn't set from AMBA, ignore it */
231 if (txd
->direction
== DMA_TO_DEVICE
)
232 /* Select signal as destination */
234 (phychan
->signal
<< PL080_CONFIG_DST_SEL_SHIFT
);
235 else if (txd
->direction
== DMA_FROM_DEVICE
)
236 /* Select signal as source */
238 (phychan
->signal
<< PL080_CONFIG_SRC_SEL_SHIFT
);
239 /* Always enable error interrupts */
240 phychan
->ccfg
|= PL080_CONFIG_ERR_IRQ_MASK
;
241 /* Always enable terminal interrupts */
242 phychan
->ccfg
|= PL080_CONFIG_TC_IRQ_MASK
;
246 * Enable the DMA channel
247 * Assumes all other configuration bits have been set
248 * as desired before this code is called
250 static void pl08x_enable_phy_chan(struct pl08x_driver_data
*pl08x
,
251 struct pl08x_phy_chan
*ch
)
256 * Do not access config register until channel shows as disabled
258 while (readl(pl08x
->base
+ PL080_EN_CHAN
) & (1 << ch
->id
))
262 * Do not access config register until channel shows as inactive
264 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
265 while ((val
& PL080_CONFIG_ACTIVE
) || (val
& PL080_CONFIG_ENABLE
))
266 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
268 writel(val
| PL080_CONFIG_ENABLE
, ch
->base
+ PL080_CH_CONFIG
);
272 * Overall DMAC remains enabled always.
274 * Disabling individual channels could lose data.
276 * Disable the peripheral DMA after disabling the DMAC
277 * in order to allow the DMAC FIFO to drain, and
278 * hence allow the channel to show inactive
281 static void pl08x_pause_phy_chan(struct pl08x_phy_chan
*ch
)
285 /* Set the HALT bit and wait for the FIFO to drain */
286 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
287 val
|= PL080_CONFIG_HALT
;
288 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
290 /* Wait for channel inactive */
291 while (pl08x_phy_channel_busy(ch
))
295 static void pl08x_resume_phy_chan(struct pl08x_phy_chan
*ch
)
299 /* Clear the HALT bit */
300 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
301 val
&= ~PL080_CONFIG_HALT
;
302 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
306 /* Stops the channel */
307 static void pl08x_stop_phy_chan(struct pl08x_phy_chan
*ch
)
311 pl08x_pause_phy_chan(ch
);
313 /* Disable channel */
314 val
= readl(ch
->base
+ PL080_CH_CONFIG
);
315 val
&= ~PL080_CONFIG_ENABLE
;
316 val
&= ~PL080_CONFIG_ERR_IRQ_MASK
;
317 val
&= ~PL080_CONFIG_TC_IRQ_MASK
;
318 writel(val
, ch
->base
+ PL080_CH_CONFIG
);
321 static inline u32
get_bytes_in_cctl(u32 cctl
)
323 /* The source width defines the number of bytes */
324 u32 bytes
= cctl
& PL080_CONTROL_TRANSFER_SIZE_MASK
;
326 switch (cctl
>> PL080_CONTROL_SWIDTH_SHIFT
) {
327 case PL080_WIDTH_8BIT
:
329 case PL080_WIDTH_16BIT
:
332 case PL080_WIDTH_32BIT
:
339 /* The channel should be paused when calling this */
340 static u32
pl08x_getbytes_chan(struct pl08x_dma_chan
*plchan
)
342 struct pl08x_phy_chan
*ch
;
343 struct pl08x_txd
*txdi
= NULL
;
344 struct pl08x_txd
*txd
;
348 spin_lock_irqsave(&plchan
->lock
, flags
);
350 ch
= plchan
->phychan
;
354 * Next follow the LLIs to get the number of pending bytes in the
355 * currently active transaction.
358 struct pl08x_lli
*llis_va
= txd
->llis_va
;
359 struct pl08x_lli
*llis_bus
= (struct pl08x_lli
*) txd
->llis_bus
;
360 u32 clli
= readl(ch
->base
+ PL080_CH_LLI
) & ~PL080_LLI_LM_AHB2
;
362 /* First get the bytes in the current active LLI */
363 bytes
= get_bytes_in_cctl(readl(ch
->base
+ PL080_CH_CONTROL
));
368 /* Forward to the LLI pointed to by clli */
369 while ((clli
!= (u32
) &(llis_bus
[i
])) &&
370 (i
< MAX_NUM_TSFR_LLIS
))
374 bytes
+= get_bytes_in_cctl(llis_va
[i
].cctl
);
376 * A LLI pointer of 0 terminates the LLI list
378 clli
= llis_va
[i
].next
;
384 /* Sum up all queued transactions */
385 if (!list_empty(&plchan
->desc_list
)) {
386 list_for_each_entry(txdi
, &plchan
->desc_list
, node
) {
392 spin_unlock_irqrestore(&plchan
->lock
, flags
);
398 * Allocate a physical channel for a virtual channel
400 static struct pl08x_phy_chan
*
401 pl08x_get_phy_channel(struct pl08x_driver_data
*pl08x
,
402 struct pl08x_dma_chan
*virt_chan
)
404 struct pl08x_phy_chan
*ch
= NULL
;
409 * Try to locate a physical channel to be used for
410 * this transfer. If all are taken return NULL and
411 * the requester will have to cope by using some fallback
412 * PIO mode or retrying later.
414 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
415 ch
= &pl08x
->phy_chans
[i
];
417 spin_lock_irqsave(&ch
->lock
, flags
);
420 ch
->serving
= virt_chan
;
422 spin_unlock_irqrestore(&ch
->lock
, flags
);
426 spin_unlock_irqrestore(&ch
->lock
, flags
);
429 if (i
== pl08x
->vd
->channels
) {
430 /* No physical channel available, cope with it */
437 static inline void pl08x_put_phy_channel(struct pl08x_driver_data
*pl08x
,
438 struct pl08x_phy_chan
*ch
)
442 /* Stop the channel and clear its interrupts */
443 pl08x_stop_phy_chan(ch
);
444 writel((1 << ch
->id
), pl08x
->base
+ PL080_ERR_CLEAR
);
445 writel((1 << ch
->id
), pl08x
->base
+ PL080_TC_CLEAR
);
447 /* Mark it as free */
448 spin_lock_irqsave(&ch
->lock
, flags
);
450 spin_unlock_irqrestore(&ch
->lock
, flags
);
457 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded
)
460 case PL080_WIDTH_8BIT
:
462 case PL080_WIDTH_16BIT
:
464 case PL080_WIDTH_32BIT
:
473 static inline u32
pl08x_cctl_bits(u32 cctl
, u8 srcwidth
, u8 dstwidth
,
478 /* Remove all src, dst and transfer size bits */
479 retbits
&= ~PL080_CONTROL_DWIDTH_MASK
;
480 retbits
&= ~PL080_CONTROL_SWIDTH_MASK
;
481 retbits
&= ~PL080_CONTROL_TRANSFER_SIZE_MASK
;
483 /* Then set the bits according to the parameters */
486 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
489 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
492 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
;
501 retbits
|= PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
504 retbits
|= PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
507 retbits
|= PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
;
514 retbits
|= tsize
<< PL080_CONTROL_TRANSFER_SIZE_SHIFT
;
519 * Autoselect a master bus to use for the transfer
520 * this prefers the destination bus if both available
521 * if fixed address on one bus the other will be chosen
523 static void pl08x_choose_master_bus(struct pl08x_bus_data
*src_bus
,
524 struct pl08x_bus_data
*dst_bus
, struct pl08x_bus_data
**mbus
,
525 struct pl08x_bus_data
**sbus
, u32 cctl
)
527 if (!(cctl
& PL080_CONTROL_DST_INCR
)) {
530 } else if (!(cctl
& PL080_CONTROL_SRC_INCR
)) {
534 if (dst_bus
->buswidth
== 4) {
537 } else if (src_bus
->buswidth
== 4) {
540 } else if (dst_bus
->buswidth
== 2) {
543 } else if (src_bus
->buswidth
== 2) {
547 /* src_bus->buswidth == 1 */
555 * Fills in one LLI for a certain transfer descriptor
556 * and advance the counter
558 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data
*pl08x
,
559 struct pl08x_txd
*txd
, int num_llis
, int len
,
560 u32 cctl
, u32
*remainder
)
562 struct pl08x_lli
*llis_va
= txd
->llis_va
;
563 dma_addr_t llis_bus
= txd
->llis_bus
;
565 BUG_ON(num_llis
>= MAX_NUM_TSFR_LLIS
);
567 llis_va
[num_llis
].cctl
= cctl
;
568 llis_va
[num_llis
].src
= txd
->srcbus
.addr
;
569 llis_va
[num_llis
].dst
= txd
->dstbus
.addr
;
572 * On versions with dual masters, you can optionally AND on
573 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
574 * in new LLIs with that controller, but we always try to
575 * choose AHB1 to point into memory. The idea is to have AHB2
576 * fixed on the peripheral and AHB1 messing around in the
577 * memory. So we don't manipulate this bit currently.
580 llis_va
[num_llis
].next
= llis_bus
+ (num_llis
+ 1) * sizeof(struct pl08x_lli
);
582 if (cctl
& PL080_CONTROL_SRC_INCR
)
583 txd
->srcbus
.addr
+= len
;
584 if (cctl
& PL080_CONTROL_DST_INCR
)
585 txd
->dstbus
.addr
+= len
;
587 BUG_ON(*remainder
< len
);
595 * Return number of bytes to fill to boundary, or len
597 static inline size_t pl08x_pre_boundary(u32 addr
, size_t len
)
601 boundary
= ((addr
>> PL08X_BOUNDARY_SHIFT
) + 1)
602 << PL08X_BOUNDARY_SHIFT
;
604 if (boundary
< addr
+ len
)
605 return boundary
- addr
;
611 * This fills in the table of LLIs for the transfer descriptor
612 * Note that we assume we never have to change the burst sizes
615 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data
*pl08x
,
616 struct pl08x_txd
*txd
)
618 struct pl08x_channel_data
*cd
= txd
->cd
;
619 struct pl08x_bus_data
*mbus
, *sbus
;
623 size_t max_bytes_per_lli
;
624 size_t total_bytes
= 0;
625 struct pl08x_lli
*llis_va
;
627 txd
->llis_va
= dma_pool_alloc(pl08x
->pool
, GFP_NOWAIT
,
630 dev_err(&pl08x
->adev
->dev
, "%s no memory for llis\n", __func__
);
637 * Initialize bus values for this transfer
638 * from the passed optimal values
641 dev_err(&pl08x
->adev
->dev
, "%s no channel data\n", __func__
);
645 /* Get the default CCTL from the platform data */
649 * On the PL080 we have two bus masters and we
650 * should select one for source and one for
651 * destination. We try to use AHB2 for the
652 * bus which does not increment (typically the
653 * peripheral) else we just choose something.
655 cctl
&= ~(PL080_CONTROL_DST_AHB2
| PL080_CONTROL_SRC_AHB2
);
656 if (pl08x
->vd
->dualmaster
) {
657 if (cctl
& PL080_CONTROL_SRC_INCR
)
658 /* Source increments, use AHB2 for destination */
659 cctl
|= PL080_CONTROL_DST_AHB2
;
660 else if (cctl
& PL080_CONTROL_DST_INCR
)
661 /* Destination increments, use AHB2 for source */
662 cctl
|= PL080_CONTROL_SRC_AHB2
;
664 /* Just pick something, source AHB1 dest AHB2 */
665 cctl
|= PL080_CONTROL_DST_AHB2
;
668 /* Find maximum width of the source bus */
669 txd
->srcbus
.maxwidth
=
670 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_SWIDTH_MASK
) >>
671 PL080_CONTROL_SWIDTH_SHIFT
);
673 /* Find maximum width of the destination bus */
674 txd
->dstbus
.maxwidth
=
675 pl08x_get_bytes_for_cctl((cctl
& PL080_CONTROL_DWIDTH_MASK
) >>
676 PL080_CONTROL_DWIDTH_SHIFT
);
678 /* Set up the bus widths to the maximum */
679 txd
->srcbus
.buswidth
= txd
->srcbus
.maxwidth
;
680 txd
->dstbus
.buswidth
= txd
->dstbus
.maxwidth
;
681 dev_vdbg(&pl08x
->adev
->dev
,
682 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
683 __func__
, txd
->srcbus
.buswidth
, txd
->dstbus
.buswidth
);
687 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
689 max_bytes_per_lli
= min(txd
->srcbus
.buswidth
, txd
->dstbus
.buswidth
) *
690 PL080_CONTROL_TRANSFER_SIZE_MASK
;
691 dev_vdbg(&pl08x
->adev
->dev
,
692 "%s max bytes per lli = %zu\n",
693 __func__
, max_bytes_per_lli
);
695 /* We need to count this down to zero */
696 remainder
= txd
->len
;
697 dev_vdbg(&pl08x
->adev
->dev
,
698 "%s remainder = %zu\n",
699 __func__
, remainder
);
702 * Choose bus to align to
703 * - prefers destination bus if both available
704 * - if fixed address on one bus chooses other
705 * - modifies cctl to choose an appropriate master
707 pl08x_choose_master_bus(&txd
->srcbus
, &txd
->dstbus
,
712 * The lowest bit of the LLI register
713 * is also used to indicate which master to
714 * use for reading the LLIs.
717 if (txd
->len
< mbus
->buswidth
) {
719 * Less than a bus width available
720 * - send as single bytes
723 dev_vdbg(&pl08x
->adev
->dev
,
724 "%s single byte LLIs for a transfer of "
725 "less than a bus width (remain 0x%08x)\n",
726 __func__
, remainder
);
727 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
729 pl08x_fill_lli_for_desc(pl08x
, txd
, num_llis
, 1,
735 * Make one byte LLIs until master bus is aligned
736 * - slave will then be aligned also
738 while ((mbus
->addr
) % (mbus
->buswidth
)) {
739 dev_vdbg(&pl08x
->adev
->dev
,
740 "%s adjustment lli for less than bus width "
742 __func__
, remainder
);
743 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
744 num_llis
= pl08x_fill_lli_for_desc
745 (pl08x
, txd
, num_llis
, 1, cctl
, &remainder
);
751 * - if slave is not then we must set its width down
753 if (sbus
->addr
% sbus
->buswidth
) {
754 dev_dbg(&pl08x
->adev
->dev
,
755 "%s set down bus width to one byte\n",
762 * Make largest possible LLIs until less than one bus
765 while (remainder
> (mbus
->buswidth
- 1)) {
766 size_t lli_len
, target_len
, tsize
, odd_bytes
;
769 * If enough left try to send max possible,
770 * otherwise try to send the remainder
772 target_len
= remainder
;
773 if (remainder
> max_bytes_per_lli
)
774 target_len
= max_bytes_per_lli
;
777 * Set bus lengths for incrementing buses
778 * to number of bytes which fill to next memory
781 if (cctl
& PL080_CONTROL_SRC_INCR
)
782 txd
->srcbus
.fill_bytes
=
787 txd
->srcbus
.fill_bytes
=
790 if (cctl
& PL080_CONTROL_DST_INCR
)
791 txd
->dstbus
.fill_bytes
=
796 txd
->dstbus
.fill_bytes
=
802 lli_len
= min(txd
->srcbus
.fill_bytes
,
803 txd
->dstbus
.fill_bytes
);
805 BUG_ON(lli_len
> remainder
);
808 dev_err(&pl08x
->adev
->dev
,
809 "%s lli_len is %zu, <= 0\n",
814 if (lli_len
== target_len
) {
816 * Can send what we wanted
821 lli_len
= (lli_len
/mbus
->buswidth
) *
826 * So now we know how many bytes to transfer
827 * to get to the nearest boundary
828 * The next LLI will past the boundary
829 * - however we may be working to a boundary
831 * We need to ensure the master stays aligned
833 odd_bytes
= lli_len
% mbus
->buswidth
;
835 * - and that we are working in multiples
838 lli_len
-= odd_bytes
;
844 * Check against minimum bus alignment:
845 * Calculate actual transfer size in relation
846 * to bus width an get a maximum remainder of
847 * the smallest bus width - 1
849 /* FIXME: use round_down()? */
850 tsize
= lli_len
/ min(mbus
->buswidth
,
852 lli_len
= tsize
* min(mbus
->buswidth
,
855 if (target_len
!= lli_len
) {
856 dev_vdbg(&pl08x
->adev
->dev
,
857 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
858 __func__
, target_len
, lli_len
, txd
->len
);
861 cctl
= pl08x_cctl_bits(cctl
,
862 txd
->srcbus
.buswidth
,
863 txd
->dstbus
.buswidth
,
866 dev_vdbg(&pl08x
->adev
->dev
,
867 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
868 __func__
, lli_len
, remainder
);
869 num_llis
= pl08x_fill_lli_for_desc(pl08x
, txd
,
870 num_llis
, lli_len
, cctl
,
872 total_bytes
+= lli_len
;
878 * Creep past the boundary,
879 * maintaining master alignment
882 for (j
= 0; (j
< mbus
->buswidth
)
883 && (remainder
); j
++) {
884 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
885 dev_vdbg(&pl08x
->adev
->dev
,
886 "%s align with boundary, single byte (remain 0x%08zx)\n",
887 __func__
, remainder
);
889 pl08x_fill_lli_for_desc(pl08x
,
901 cctl
= pl08x_cctl_bits(cctl
, 1, 1, 1);
902 dev_vdbg(&pl08x
->adev
->dev
,
903 "%s align with boundary, single odd byte (remain %zu)\n",
904 __func__
, remainder
);
905 num_llis
= pl08x_fill_lli_for_desc(pl08x
, txd
, num_llis
,
906 1, cctl
, &remainder
);
910 if (total_bytes
!= txd
->len
) {
911 dev_err(&pl08x
->adev
->dev
,
912 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
913 __func__
, total_bytes
, txd
->len
);
917 if (num_llis
>= MAX_NUM_TSFR_LLIS
) {
918 dev_err(&pl08x
->adev
->dev
,
919 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
920 __func__
, (u32
) MAX_NUM_TSFR_LLIS
);
924 llis_va
= txd
->llis_va
;
926 * The final LLI terminates the LLI.
928 llis_va
[num_llis
- 1].next
= 0;
930 * The final LLI element shall also fire an interrupt
932 llis_va
[num_llis
- 1].cctl
|= PL080_CONTROL_TC_IRQ_EN
;
934 /* Now store the channel register values */
935 txd
->csrc
= llis_va
[0].src
;
936 txd
->cdst
= llis_va
[0].dst
;
937 txd
->clli
= llis_va
[0].next
;
938 txd
->cctl
= llis_va
[0].cctl
;
939 /* ccfg will be set at physical channel allocation time */
945 for (i
= 0; i
< num_llis
; i
++) {
946 dev_vdbg(&pl08x
->adev
->dev
,
947 "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
962 /* You should call this with the struct pl08x lock held */
963 static void pl08x_free_txd(struct pl08x_driver_data
*pl08x
,
964 struct pl08x_txd
*txd
)
967 dma_pool_free(pl08x
->pool
, txd
->llis_va
, txd
->llis_bus
);
974 static void pl08x_free_txd_list(struct pl08x_driver_data
*pl08x
,
975 struct pl08x_dma_chan
*plchan
)
977 struct pl08x_txd
*txdi
= NULL
;
978 struct pl08x_txd
*next
;
980 if (!list_empty(&plchan
->desc_list
)) {
981 list_for_each_entry_safe(txdi
,
982 next
, &plchan
->desc_list
, node
) {
983 list_del(&txdi
->node
);
984 pl08x_free_txd(pl08x
, txdi
);
993 static int pl08x_alloc_chan_resources(struct dma_chan
*chan
)
998 static void pl08x_free_chan_resources(struct dma_chan
*chan
)
1003 * This should be called with the channel plchan->lock held
1005 static int prep_phy_channel(struct pl08x_dma_chan
*plchan
,
1006 struct pl08x_txd
*txd
)
1008 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1009 struct pl08x_phy_chan
*ch
;
1012 /* Check if we already have a channel */
1013 if (plchan
->phychan
)
1016 ch
= pl08x_get_phy_channel(pl08x
, plchan
);
1018 /* No physical channel available, cope with it */
1019 dev_dbg(&pl08x
->adev
->dev
, "no physical channel available for xfer on %s\n", plchan
->name
);
1024 * OK we have a physical channel: for memcpy() this is all we
1025 * need, but for slaves the physical signals may be muxed!
1026 * Can the platform allow us to use this channel?
1028 if (plchan
->slave
&&
1030 pl08x
->pd
->get_signal
) {
1031 ret
= pl08x
->pd
->get_signal(plchan
);
1033 dev_dbg(&pl08x
->adev
->dev
,
1034 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1035 ch
->id
, plchan
->name
);
1036 /* Release physical channel & return */
1037 pl08x_put_phy_channel(pl08x
, ch
);
1043 dev_dbg(&pl08x
->adev
->dev
, "allocated physical channel %d and signal %d for xfer on %s\n",
1048 plchan
->phychan
= ch
;
1053 static void release_phy_channel(struct pl08x_dma_chan
*plchan
)
1055 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1057 if ((plchan
->phychan
->signal
>= 0) && pl08x
->pd
->put_signal
) {
1058 pl08x
->pd
->put_signal(plchan
);
1059 plchan
->phychan
->signal
= -1;
1061 pl08x_put_phy_channel(pl08x
, plchan
->phychan
);
1062 plchan
->phychan
= NULL
;
1065 static dma_cookie_t
pl08x_tx_submit(struct dma_async_tx_descriptor
*tx
)
1067 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(tx
->chan
);
1069 plchan
->chan
.cookie
+= 1;
1070 if (plchan
->chan
.cookie
< 0)
1071 plchan
->chan
.cookie
= 1;
1072 tx
->cookie
= plchan
->chan
.cookie
;
1073 /* This unlock follows the lock in the prep() function */
1074 spin_unlock_irqrestore(&plchan
->lock
, plchan
->lockflags
);
1079 static struct dma_async_tx_descriptor
*pl08x_prep_dma_interrupt(
1080 struct dma_chan
*chan
, unsigned long flags
)
1082 struct dma_async_tx_descriptor
*retval
= NULL
;
1088 * Code accessing dma_async_is_complete() in a tight loop
1089 * may give problems - could schedule where indicated.
1090 * If slaves are relying on interrupts to signal completion this
1091 * function must not be called with interrupts disabled
1093 static enum dma_status
1094 pl08x_dma_tx_status(struct dma_chan
*chan
,
1095 dma_cookie_t cookie
,
1096 struct dma_tx_state
*txstate
)
1098 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1099 dma_cookie_t last_used
;
1100 dma_cookie_t last_complete
;
1101 enum dma_status ret
;
1104 last_used
= plchan
->chan
.cookie
;
1105 last_complete
= plchan
->lc
;
1107 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
1108 if (ret
== DMA_SUCCESS
) {
1109 dma_set_tx_state(txstate
, last_complete
, last_used
, 0);
1114 * schedule(); could be inserted here
1118 * This cookie not complete yet
1120 last_used
= plchan
->chan
.cookie
;
1121 last_complete
= plchan
->lc
;
1123 /* Get number of bytes left in the active transactions and queue */
1124 bytesleft
= pl08x_getbytes_chan(plchan
);
1126 dma_set_tx_state(txstate
, last_complete
, last_used
,
1129 if (plchan
->state
== PL08X_CHAN_PAUSED
)
1132 /* Whether waiting or running, we're in progress */
1133 return DMA_IN_PROGRESS
;
1136 /* PrimeCell DMA extension */
1137 struct burst_table
{
1142 static const struct burst_table burst_sizes
[] = {
1145 .reg
= (PL080_BSIZE_256
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1146 (PL080_BSIZE_256
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1150 .reg
= (PL080_BSIZE_128
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1151 (PL080_BSIZE_128
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1155 .reg
= (PL080_BSIZE_64
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1156 (PL080_BSIZE_64
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1160 .reg
= (PL080_BSIZE_32
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1161 (PL080_BSIZE_32
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1165 .reg
= (PL080_BSIZE_16
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1166 (PL080_BSIZE_16
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1170 .reg
= (PL080_BSIZE_8
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1171 (PL080_BSIZE_8
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1175 .reg
= (PL080_BSIZE_4
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1176 (PL080_BSIZE_4
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1180 .reg
= (PL080_BSIZE_1
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1181 (PL080_BSIZE_1
<< PL080_CONTROL_DB_SIZE_SHIFT
),
1185 static void dma_set_runtime_config(struct dma_chan
*chan
,
1186 struct dma_slave_config
*config
)
1188 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1189 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1190 struct pl08x_channel_data
*cd
= plchan
->cd
;
1191 enum dma_slave_buswidth addr_width
;
1194 /* Mask out all except src and dst channel */
1195 u32 ccfg
= cd
->ccfg
& 0x000003DEU
;
1198 /* Transfer direction */
1199 plchan
->runtime_direction
= config
->direction
;
1200 if (config
->direction
== DMA_TO_DEVICE
) {
1201 plchan
->runtime_addr
= config
->dst_addr
;
1202 cctl
|= PL080_CONTROL_SRC_INCR
;
1203 ccfg
|= PL080_FLOW_MEM2PER
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1204 addr_width
= config
->dst_addr_width
;
1205 maxburst
= config
->dst_maxburst
;
1206 } else if (config
->direction
== DMA_FROM_DEVICE
) {
1207 plchan
->runtime_addr
= config
->src_addr
;
1208 cctl
|= PL080_CONTROL_DST_INCR
;
1209 ccfg
|= PL080_FLOW_PER2MEM
<< PL080_CONFIG_FLOW_CONTROL_SHIFT
;
1210 addr_width
= config
->src_addr_width
;
1211 maxburst
= config
->src_maxburst
;
1213 dev_err(&pl08x
->adev
->dev
,
1214 "bad runtime_config: alien transfer direction\n");
1218 switch (addr_width
) {
1219 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
1220 cctl
|= (PL080_WIDTH_8BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1221 (PL080_WIDTH_8BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1223 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
1224 cctl
|= (PL080_WIDTH_16BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1225 (PL080_WIDTH_16BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1227 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
1228 cctl
|= (PL080_WIDTH_32BIT
<< PL080_CONTROL_SWIDTH_SHIFT
) |
1229 (PL080_WIDTH_32BIT
<< PL080_CONTROL_DWIDTH_SHIFT
);
1232 dev_err(&pl08x
->adev
->dev
,
1233 "bad runtime_config: alien address width\n");
1238 * Now decide on a maxburst:
1239 * If this channel will only request single transfers, set this
1240 * down to ONE element. Also select one element if no maxburst
1243 if (plchan
->cd
->single
|| maxburst
== 0) {
1244 cctl
|= (PL080_BSIZE_1
<< PL080_CONTROL_SB_SIZE_SHIFT
) |
1245 (PL080_BSIZE_1
<< PL080_CONTROL_DB_SIZE_SHIFT
);
1247 for (i
= 0; i
< ARRAY_SIZE(burst_sizes
); i
++)
1248 if (burst_sizes
[i
].burstwords
<= maxburst
)
1250 cctl
|= burst_sizes
[i
].reg
;
1253 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1254 cctl
&= ~PL080_CONTROL_PROT_MASK
;
1255 cctl
|= PL080_CONTROL_PROT_SYS
;
1257 /* Modify the default channel data to fit PrimeCell request */
1261 dev_dbg(&pl08x
->adev
->dev
,
1262 "configured channel %s (%s) for %s, data width %d, "
1263 "maxburst %d words, LE, CCTL=0x%08x, CCFG=0x%08x\n",
1264 dma_chan_name(chan
), plchan
->name
,
1265 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
1272 * Slave transactions callback to the slave device to allow
1273 * synchronization of slave DMA signals with the DMAC enable
1275 static void pl08x_issue_pending(struct dma_chan
*chan
)
1277 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1278 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1279 unsigned long flags
;
1281 spin_lock_irqsave(&plchan
->lock
, flags
);
1282 /* Something is already active, or we're waiting for a channel... */
1283 if (plchan
->at
|| plchan
->state
== PL08X_CHAN_WAITING
) {
1284 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1288 /* Take the first element in the queue and execute it */
1289 if (!list_empty(&plchan
->desc_list
)) {
1290 struct pl08x_txd
*next
;
1292 next
= list_first_entry(&plchan
->desc_list
,
1295 list_del(&next
->node
);
1297 plchan
->state
= PL08X_CHAN_RUNNING
;
1299 /* Configure the physical channel for the active txd */
1300 pl08x_config_phychan_for_txd(plchan
);
1301 pl08x_set_cregs(pl08x
, plchan
->phychan
);
1302 pl08x_enable_phy_chan(pl08x
, plchan
->phychan
);
1305 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1308 static int pl08x_prep_channel_resources(struct pl08x_dma_chan
*plchan
,
1309 struct pl08x_txd
*txd
)
1312 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1315 num_llis
= pl08x_fill_llis_for_desc(pl08x
, txd
);
1321 spin_lock_irqsave(&plchan
->lock
, plchan
->lockflags
);
1323 list_add_tail(&txd
->node
, &plchan
->desc_list
);
1326 * See if we already have a physical channel allocated,
1327 * else this is the time to try to get one.
1329 ret
= prep_phy_channel(plchan
, txd
);
1332 * No physical channel available, we will
1333 * stack up the memcpy channels until there is a channel
1334 * available to handle it whereas slave transfers may
1335 * have been denied due to platform channel muxing restrictions
1336 * and since there is no guarantee that this will ever be
1337 * resolved, and since the signal must be acquired AFTER
1338 * acquiring the physical channel, we will let them be NACK:ed
1339 * with -EBUSY here. The drivers can alway retry the prep()
1340 * call if they are eager on doing this using DMA.
1342 if (plchan
->slave
) {
1343 pl08x_free_txd_list(pl08x
, plchan
);
1344 spin_unlock_irqrestore(&plchan
->lock
, plchan
->lockflags
);
1347 /* Do this memcpy whenever there is a channel ready */
1348 plchan
->state
= PL08X_CHAN_WAITING
;
1349 plchan
->waiting
= txd
;
1352 * Else we're all set, paused and ready to roll,
1353 * status will switch to PL08X_CHAN_RUNNING when
1354 * we call issue_pending(). If there is something
1355 * running on the channel already we don't change
1358 if (plchan
->state
== PL08X_CHAN_IDLE
)
1359 plchan
->state
= PL08X_CHAN_PAUSED
;
1362 * Notice that we leave plchan->lock locked on purpose:
1363 * it will be unlocked in the subsequent tx_submit()
1364 * call. This is a consequence of the current API.
1370 static struct pl08x_txd
*pl08x_get_txd(struct pl08x_dma_chan
*plchan
)
1372 struct pl08x_txd
*txd
= kzalloc(sizeof(struct pl08x_txd
), GFP_NOWAIT
);
1375 dma_async_tx_descriptor_init(&txd
->tx
, &plchan
->chan
);
1376 txd
->tx
.tx_submit
= pl08x_tx_submit
;
1377 INIT_LIST_HEAD(&txd
->node
);
1383 * Initialize a descriptor to be used by memcpy submit
1385 static struct dma_async_tx_descriptor
*pl08x_prep_dma_memcpy(
1386 struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1387 size_t len
, unsigned long flags
)
1389 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1390 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1391 struct pl08x_txd
*txd
;
1394 txd
= pl08x_get_txd(plchan
);
1396 dev_err(&pl08x
->adev
->dev
,
1397 "%s no memory for descriptor\n", __func__
);
1401 txd
->direction
= DMA_NONE
;
1402 txd
->srcbus
.addr
= src
;
1403 txd
->dstbus
.addr
= dest
;
1405 /* Set platform data for m2m */
1406 txd
->cd
= &pl08x
->pd
->memcpy_channel
;
1407 /* Both to be incremented or the code will break */
1408 txd
->cd
->cctl
|= PL080_CONTROL_SRC_INCR
| PL080_CONTROL_DST_INCR
;
1411 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1415 * NB: the channel lock is held at this point so tx_submit()
1416 * must be called in direct succession.
1422 static struct dma_async_tx_descriptor
*pl08x_prep_slave_sg(
1423 struct dma_chan
*chan
, struct scatterlist
*sgl
,
1424 unsigned int sg_len
, enum dma_data_direction direction
,
1425 unsigned long flags
)
1427 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1428 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1429 struct pl08x_txd
*txd
;
1433 * Current implementation ASSUMES only one sg
1436 dev_err(&pl08x
->adev
->dev
, "%s prepared too long sglist\n",
1441 dev_dbg(&pl08x
->adev
->dev
, "%s prepare transaction of %d bytes from %s\n",
1442 __func__
, sgl
->length
, plchan
->name
);
1444 txd
= pl08x_get_txd(plchan
);
1446 dev_err(&pl08x
->adev
->dev
, "%s no txd\n", __func__
);
1450 if (direction
!= plchan
->runtime_direction
)
1451 dev_err(&pl08x
->adev
->dev
, "%s DMA setup does not match "
1452 "the direction configured for the PrimeCell\n",
1456 * Set up addresses, the PrimeCell configured address
1457 * will take precedence since this may configure the
1458 * channel target address dynamically at runtime.
1460 txd
->direction
= direction
;
1461 if (direction
== DMA_TO_DEVICE
) {
1462 txd
->srcbus
.addr
= sgl
->dma_address
;
1463 if (plchan
->runtime_addr
)
1464 txd
->dstbus
.addr
= plchan
->runtime_addr
;
1466 txd
->dstbus
.addr
= plchan
->cd
->addr
;
1467 } else if (direction
== DMA_FROM_DEVICE
) {
1468 if (plchan
->runtime_addr
)
1469 txd
->srcbus
.addr
= plchan
->runtime_addr
;
1471 txd
->srcbus
.addr
= plchan
->cd
->addr
;
1472 txd
->dstbus
.addr
= sgl
->dma_address
;
1474 dev_err(&pl08x
->adev
->dev
,
1475 "%s direction unsupported\n", __func__
);
1478 txd
->cd
= plchan
->cd
;
1479 txd
->len
= sgl
->length
;
1481 ret
= pl08x_prep_channel_resources(plchan
, txd
);
1485 * NB: the channel lock is held at this point so tx_submit()
1486 * must be called in direct succession.
1492 static int pl08x_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
1495 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1496 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1497 unsigned long flags
;
1500 /* Controls applicable to inactive channels */
1501 if (cmd
== DMA_SLAVE_CONFIG
) {
1502 dma_set_runtime_config(chan
,
1503 (struct dma_slave_config
*)
1509 * Anything succeeds on channels with no physical allocation and
1510 * no queued transfers.
1512 spin_lock_irqsave(&plchan
->lock
, flags
);
1513 if (!plchan
->phychan
&& !plchan
->at
) {
1514 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1519 case DMA_TERMINATE_ALL
:
1520 plchan
->state
= PL08X_CHAN_IDLE
;
1522 if (plchan
->phychan
) {
1523 pl08x_stop_phy_chan(plchan
->phychan
);
1526 * Mark physical channel as free and free any slave
1529 release_phy_channel(plchan
);
1531 /* Dequeue jobs and free LLIs */
1533 pl08x_free_txd(pl08x
, plchan
->at
);
1536 /* Dequeue jobs not yet fired as well */
1537 pl08x_free_txd_list(pl08x
, plchan
);
1540 pl08x_pause_phy_chan(plchan
->phychan
);
1541 plchan
->state
= PL08X_CHAN_PAUSED
;
1544 pl08x_resume_phy_chan(plchan
->phychan
);
1545 plchan
->state
= PL08X_CHAN_RUNNING
;
1548 /* Unknown command */
1553 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1558 bool pl08x_filter_id(struct dma_chan
*chan
, void *chan_id
)
1560 struct pl08x_dma_chan
*plchan
= to_pl08x_chan(chan
);
1561 char *name
= chan_id
;
1563 /* Check that the channel is not taken! */
1564 if (!strcmp(plchan
->name
, name
))
1571 * Just check that the device is there and active
1572 * TODO: turn this bit on/off depending on the number of
1573 * physical channels actually used, if it is zero... well
1574 * shut it off. That will save some power. Cut the clock
1577 static void pl08x_ensure_on(struct pl08x_driver_data
*pl08x
)
1581 val
= readl(pl08x
->base
+ PL080_CONFIG
);
1582 val
&= ~(PL080_CONFIG_M2_BE
| PL080_CONFIG_M1_BE
| PL080_CONFIG_ENABLE
);
1583 /* We implicitly clear bit 1 and that means little-endian mode */
1584 val
|= PL080_CONFIG_ENABLE
;
1585 writel(val
, pl08x
->base
+ PL080_CONFIG
);
1588 static void pl08x_tasklet(unsigned long data
)
1590 struct pl08x_dma_chan
*plchan
= (struct pl08x_dma_chan
*) data
;
1591 struct pl08x_driver_data
*pl08x
= plchan
->host
;
1592 unsigned long flags
;
1594 spin_lock_irqsave(&plchan
->lock
, flags
);
1597 dma_async_tx_callback callback
=
1598 plchan
->at
->tx
.callback
;
1599 void *callback_param
=
1600 plchan
->at
->tx
.callback_param
;
1603 * Update last completed
1605 plchan
->lc
= plchan
->at
->tx
.cookie
;
1608 * Callback to signal completion
1611 callback(callback_param
);
1614 * Free the descriptor
1616 pl08x_free_txd(pl08x
, plchan
->at
);
1620 * If a new descriptor is queued, set it up
1621 * plchan->at is NULL here
1623 if (!list_empty(&plchan
->desc_list
)) {
1624 struct pl08x_txd
*next
;
1626 next
= list_first_entry(&plchan
->desc_list
,
1629 list_del(&next
->node
);
1631 /* Configure the physical channel for the next txd */
1632 pl08x_config_phychan_for_txd(plchan
);
1633 pl08x_set_cregs(pl08x
, plchan
->phychan
);
1634 pl08x_enable_phy_chan(pl08x
, plchan
->phychan
);
1636 struct pl08x_dma_chan
*waiting
= NULL
;
1639 * No more jobs, so free up the physical channel
1640 * Free any allocated signal on slave transfers too
1642 release_phy_channel(plchan
);
1643 plchan
->state
= PL08X_CHAN_IDLE
;
1646 * And NOW before anyone else can grab that free:d
1647 * up physical channel, see if there is some memcpy
1648 * pending that seriously needs to start because of
1649 * being stacked up while we were choking the
1650 * physical channels with data.
1652 list_for_each_entry(waiting
, &pl08x
->memcpy
.channels
,
1654 if (waiting
->state
== PL08X_CHAN_WAITING
&&
1655 waiting
->waiting
!= NULL
) {
1658 /* This should REALLY not fail now */
1659 ret
= prep_phy_channel(waiting
,
1662 waiting
->state
= PL08X_CHAN_RUNNING
;
1663 waiting
->waiting
= NULL
;
1664 pl08x_issue_pending(&waiting
->chan
);
1670 spin_unlock_irqrestore(&plchan
->lock
, flags
);
1673 static irqreturn_t
pl08x_irq(int irq
, void *dev
)
1675 struct pl08x_driver_data
*pl08x
= dev
;
1680 val
= readl(pl08x
->base
+ PL080_ERR_STATUS
);
1683 * An error interrupt (on one or more channels)
1685 dev_err(&pl08x
->adev
->dev
,
1686 "%s error interrupt, register value 0x%08x\n",
1689 * Simply clear ALL PL08X error interrupts,
1690 * regardless of channel and cause
1691 * FIXME: should be 0x00000003 on PL081 really.
1693 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1695 val
= readl(pl08x
->base
+ PL080_INT_STATUS
);
1696 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1697 if ((1 << i
) & val
) {
1698 /* Locate physical channel */
1699 struct pl08x_phy_chan
*phychan
= &pl08x
->phy_chans
[i
];
1700 struct pl08x_dma_chan
*plchan
= phychan
->serving
;
1702 /* Schedule tasklet on this channel */
1703 tasklet_schedule(&plchan
->tasklet
);
1709 * Clear only the terminal interrupts on channels we processed
1711 writel(mask
, pl08x
->base
+ PL080_TC_CLEAR
);
1713 return mask
? IRQ_HANDLED
: IRQ_NONE
;
1717 * Initialise the DMAC memcpy/slave channels.
1718 * Make a local wrapper to hold required data
1720 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data
*pl08x
,
1721 struct dma_device
*dmadev
,
1722 unsigned int channels
,
1725 struct pl08x_dma_chan
*chan
;
1728 INIT_LIST_HEAD(&dmadev
->channels
);
1730 * Register as many many memcpy as we have physical channels,
1731 * we won't always be able to use all but the code will have
1732 * to cope with that situation.
1734 for (i
= 0; i
< channels
; i
++) {
1735 chan
= kzalloc(sizeof(struct pl08x_dma_chan
), GFP_KERNEL
);
1737 dev_err(&pl08x
->adev
->dev
,
1738 "%s no memory for channel\n", __func__
);
1743 chan
->state
= PL08X_CHAN_IDLE
;
1747 chan
->name
= pl08x
->pd
->slave_channels
[i
].bus_id
;
1748 chan
->cd
= &pl08x
->pd
->slave_channels
[i
];
1750 chan
->cd
= &pl08x
->pd
->memcpy_channel
;
1751 chan
->name
= kasprintf(GFP_KERNEL
, "memcpy%d", i
);
1757 if (chan
->cd
->circular_buffer
) {
1758 dev_err(&pl08x
->adev
->dev
,
1759 "channel %s: circular buffers not supported\n",
1764 dev_info(&pl08x
->adev
->dev
,
1765 "initialize virtual channel \"%s\"\n",
1768 chan
->chan
.device
= dmadev
;
1769 chan
->chan
.cookie
= 0;
1772 spin_lock_init(&chan
->lock
);
1773 INIT_LIST_HEAD(&chan
->desc_list
);
1774 tasklet_init(&chan
->tasklet
, pl08x_tasklet
,
1775 (unsigned long) chan
);
1777 list_add_tail(&chan
->chan
.device_node
, &dmadev
->channels
);
1779 dev_info(&pl08x
->adev
->dev
, "initialized %d virtual %s channels\n",
1780 i
, slave
? "slave" : "memcpy");
1784 static void pl08x_free_virtual_channels(struct dma_device
*dmadev
)
1786 struct pl08x_dma_chan
*chan
= NULL
;
1787 struct pl08x_dma_chan
*next
;
1789 list_for_each_entry_safe(chan
,
1790 next
, &dmadev
->channels
, chan
.device_node
) {
1791 list_del(&chan
->chan
.device_node
);
1796 #ifdef CONFIG_DEBUG_FS
1797 static const char *pl08x_state_str(enum pl08x_dma_chan_state state
)
1800 case PL08X_CHAN_IDLE
:
1802 case PL08X_CHAN_RUNNING
:
1804 case PL08X_CHAN_PAUSED
:
1806 case PL08X_CHAN_WAITING
:
1811 return "UNKNOWN STATE";
1814 static int pl08x_debugfs_show(struct seq_file
*s
, void *data
)
1816 struct pl08x_driver_data
*pl08x
= s
->private;
1817 struct pl08x_dma_chan
*chan
;
1818 struct pl08x_phy_chan
*ch
;
1819 unsigned long flags
;
1822 seq_printf(s
, "PL08x physical channels:\n");
1823 seq_printf(s
, "CHANNEL:\tUSER:\n");
1824 seq_printf(s
, "--------\t-----\n");
1825 for (i
= 0; i
< pl08x
->vd
->channels
; i
++) {
1826 struct pl08x_dma_chan
*virt_chan
;
1828 ch
= &pl08x
->phy_chans
[i
];
1830 spin_lock_irqsave(&ch
->lock
, flags
);
1831 virt_chan
= ch
->serving
;
1833 seq_printf(s
, "%d\t\t%s\n",
1834 ch
->id
, virt_chan
? virt_chan
->name
: "(none)");
1836 spin_unlock_irqrestore(&ch
->lock
, flags
);
1839 seq_printf(s
, "\nPL08x virtual memcpy channels:\n");
1840 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1841 seq_printf(s
, "--------\t------\n");
1842 list_for_each_entry(chan
, &pl08x
->memcpy
.channels
, chan
.device_node
) {
1843 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1844 pl08x_state_str(chan
->state
));
1847 seq_printf(s
, "\nPL08x virtual slave channels:\n");
1848 seq_printf(s
, "CHANNEL:\tSTATE:\n");
1849 seq_printf(s
, "--------\t------\n");
1850 list_for_each_entry(chan
, &pl08x
->slave
.channels
, chan
.device_node
) {
1851 seq_printf(s
, "%s\t\t%s\n", chan
->name
,
1852 pl08x_state_str(chan
->state
));
1858 static int pl08x_debugfs_open(struct inode
*inode
, struct file
*file
)
1860 return single_open(file
, pl08x_debugfs_show
, inode
->i_private
);
1863 static const struct file_operations pl08x_debugfs_operations
= {
1864 .open
= pl08x_debugfs_open
,
1866 .llseek
= seq_lseek
,
1867 .release
= single_release
,
1870 static void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1872 /* Expose a simple debugfs interface to view all clocks */
1873 (void) debugfs_create_file(dev_name(&pl08x
->adev
->dev
), S_IFREG
| S_IRUGO
,
1875 &pl08x_debugfs_operations
);
1879 static inline void init_pl08x_debugfs(struct pl08x_driver_data
*pl08x
)
1884 static int pl08x_probe(struct amba_device
*adev
, struct amba_id
*id
)
1886 struct pl08x_driver_data
*pl08x
;
1887 const struct vendor_data
*vd
= id
->data
;
1891 ret
= amba_request_regions(adev
, NULL
);
1895 /* Create the driver state holder */
1896 pl08x
= kzalloc(sizeof(struct pl08x_driver_data
), GFP_KERNEL
);
1902 /* Initialize memcpy engine */
1903 dma_cap_set(DMA_MEMCPY
, pl08x
->memcpy
.cap_mask
);
1904 pl08x
->memcpy
.dev
= &adev
->dev
;
1905 pl08x
->memcpy
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1906 pl08x
->memcpy
.device_free_chan_resources
= pl08x_free_chan_resources
;
1907 pl08x
->memcpy
.device_prep_dma_memcpy
= pl08x_prep_dma_memcpy
;
1908 pl08x
->memcpy
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1909 pl08x
->memcpy
.device_tx_status
= pl08x_dma_tx_status
;
1910 pl08x
->memcpy
.device_issue_pending
= pl08x_issue_pending
;
1911 pl08x
->memcpy
.device_control
= pl08x_control
;
1913 /* Initialize slave engine */
1914 dma_cap_set(DMA_SLAVE
, pl08x
->slave
.cap_mask
);
1915 pl08x
->slave
.dev
= &adev
->dev
;
1916 pl08x
->slave
.device_alloc_chan_resources
= pl08x_alloc_chan_resources
;
1917 pl08x
->slave
.device_free_chan_resources
= pl08x_free_chan_resources
;
1918 pl08x
->slave
.device_prep_dma_interrupt
= pl08x_prep_dma_interrupt
;
1919 pl08x
->slave
.device_tx_status
= pl08x_dma_tx_status
;
1920 pl08x
->slave
.device_issue_pending
= pl08x_issue_pending
;
1921 pl08x
->slave
.device_prep_slave_sg
= pl08x_prep_slave_sg
;
1922 pl08x
->slave
.device_control
= pl08x_control
;
1924 /* Get the platform data */
1925 pl08x
->pd
= dev_get_platdata(&adev
->dev
);
1927 dev_err(&adev
->dev
, "no platform data supplied\n");
1928 goto out_no_platdata
;
1931 /* Assign useful pointers to the driver state */
1935 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1936 pl08x
->pool
= dma_pool_create(DRIVER_NAME
, &pl08x
->adev
->dev
,
1937 PL08X_LLI_TSFR_SIZE
, PL08X_ALIGN
, 0);
1940 goto out_no_lli_pool
;
1943 spin_lock_init(&pl08x
->lock
);
1945 pl08x
->base
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
1948 goto out_no_ioremap
;
1951 /* Turn on the PL08x */
1952 pl08x_ensure_on(pl08x
);
1955 * Attach the interrupt handler
1957 writel(0x000000FF, pl08x
->base
+ PL080_ERR_CLEAR
);
1958 writel(0x000000FF, pl08x
->base
+ PL080_TC_CLEAR
);
1960 ret
= request_irq(adev
->irq
[0], pl08x_irq
, IRQF_DISABLED
,
1961 DRIVER_NAME
, pl08x
);
1963 dev_err(&adev
->dev
, "%s failed to request interrupt %d\n",
1964 __func__
, adev
->irq
[0]);
1968 /* Initialize physical channels */
1969 pl08x
->phy_chans
= kmalloc((vd
->channels
* sizeof(struct pl08x_phy_chan
)),
1971 if (!pl08x
->phy_chans
) {
1972 dev_err(&adev
->dev
, "%s failed to allocate "
1973 "physical channel holders\n",
1975 goto out_no_phychans
;
1978 for (i
= 0; i
< vd
->channels
; i
++) {
1979 struct pl08x_phy_chan
*ch
= &pl08x
->phy_chans
[i
];
1982 ch
->base
= pl08x
->base
+ PL080_Cx_BASE(i
);
1983 spin_lock_init(&ch
->lock
);
1986 dev_info(&adev
->dev
,
1987 "physical channel %d is %s\n", i
,
1988 pl08x_phy_channel_busy(ch
) ? "BUSY" : "FREE");
1991 /* Register as many memcpy channels as there are physical channels */
1992 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->memcpy
,
1993 pl08x
->vd
->channels
, false);
1995 dev_warn(&pl08x
->adev
->dev
,
1996 "%s failed to enumerate memcpy channels - %d\n",
2000 pl08x
->memcpy
.chancnt
= ret
;
2002 /* Register slave channels */
2003 ret
= pl08x_dma_init_virtual_channels(pl08x
, &pl08x
->slave
,
2004 pl08x
->pd
->num_slave_channels
,
2007 dev_warn(&pl08x
->adev
->dev
,
2008 "%s failed to enumerate slave channels - %d\n",
2012 pl08x
->slave
.chancnt
= ret
;
2014 ret
= dma_async_device_register(&pl08x
->memcpy
);
2016 dev_warn(&pl08x
->adev
->dev
,
2017 "%s failed to register memcpy as an async device - %d\n",
2019 goto out_no_memcpy_reg
;
2022 ret
= dma_async_device_register(&pl08x
->slave
);
2024 dev_warn(&pl08x
->adev
->dev
,
2025 "%s failed to register slave as an async device - %d\n",
2027 goto out_no_slave_reg
;
2030 amba_set_drvdata(adev
, pl08x
);
2031 init_pl08x_debugfs(pl08x
);
2032 dev_info(&pl08x
->adev
->dev
, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2033 amba_part(adev
), amba_rev(adev
),
2034 (unsigned long long)adev
->res
.start
, adev
->irq
[0]);
2038 dma_async_device_unregister(&pl08x
->memcpy
);
2040 pl08x_free_virtual_channels(&pl08x
->slave
);
2042 pl08x_free_virtual_channels(&pl08x
->memcpy
);
2044 kfree(pl08x
->phy_chans
);
2046 free_irq(adev
->irq
[0], pl08x
);
2048 iounmap(pl08x
->base
);
2050 dma_pool_destroy(pl08x
->pool
);
2055 amba_release_regions(adev
);
2059 /* PL080 has 8 channels and the PL080 have just 2 */
2060 static struct vendor_data vendor_pl080
= {
2065 static struct vendor_data vendor_pl081
= {
2067 .dualmaster
= false,
2070 static struct amba_id pl08x_ids
[] = {
2075 .data
= &vendor_pl080
,
2081 .data
= &vendor_pl081
,
2083 /* Nomadik 8815 PL080 variant */
2087 .data
= &vendor_pl080
,
2092 static struct amba_driver pl08x_amba_driver
= {
2093 .drv
.name
= DRIVER_NAME
,
2094 .id_table
= pl08x_ids
,
2095 .probe
= pl08x_probe
,
2098 static int __init
pl08x_init(void)
2101 retval
= amba_driver_register(&pl08x_amba_driver
);
2103 printk(KERN_WARNING DRIVER_NAME
2104 "failed to register as an AMBA device (%d)\n",
2108 subsys_initcall(pl08x_init
);