4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <linux/seq_file.h>
35 #include "intel_drv.h"
37 /* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41 #define IMAGE_MAX_WIDTH 2048
42 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43 /* on 830 and 845 these large limits result in the card hanging */
44 #define IMAGE_MAX_WIDTH_LEGACY 1024
45 #define IMAGE_MAX_HEIGHT_LEGACY 1088
47 /* overlay register definitions */
49 #define OCMD_TILED_SURFACE (0x1<<19)
50 #define OCMD_MIRROR_MASK (0x3<<17)
51 #define OCMD_MIRROR_MODE (0x3<<17)
52 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53 #define OCMD_MIRROR_VERTICAL (0x2<<17)
54 #define OCMD_MIRROR_BOTH (0x3<<17)
55 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63 #define OCMD_YUV_422_PACKED (0x8<<10)
64 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_420_PLANAR (0xc<<10)
66 #define OCMD_YUV_422_PLANAR (0xd<<10)
67 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
70 #define OCMD_BUF_TYPE_MASK (0x1<<5)
71 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
72 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
73 #define OCMD_TEST_MODE (0x1<<4)
74 #define OCMD_BUFFER_SELECT (0x3<<2)
75 #define OCMD_BUFFER0 (0x0<<2)
76 #define OCMD_BUFFER1 (0x1<<2)
77 #define OCMD_FIELD_SELECT (0x1<<2)
78 #define OCMD_FIELD0 (0x0<<1)
79 #define OCMD_FIELD1 (0x1<<1)
80 #define OCMD_ENABLE (0x1<<0)
82 /* OCONFIG register */
83 #define OCONF_PIPE_MASK (0x1<<18)
84 #define OCONF_PIPE_A (0x0<<18)
85 #define OCONF_PIPE_B (0x1<<18)
86 #define OCONF_GAMMA2_ENABLE (0x1<<16)
87 #define OCONF_CSC_MODE_BT601 (0x0<<5)
88 #define OCONF_CSC_MODE_BT709 (0x1<<5)
89 #define OCONF_CSC_BYPASS (0x1<<4)
90 #define OCONF_CC_OUT_8BIT (0x1<<3)
91 #define OCONF_TEST_MODE (0x1<<2)
92 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
93 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
95 /* DCLRKM (dst-key) register */
96 #define DST_KEY_ENABLE (0x1<<31)
97 #define CLK_RGB24_MASK 0x0
98 #define CLK_RGB16_MASK 0x070307
99 #define CLK_RGB15_MASK 0x070707
100 #define CLK_RGB8I_MASK 0xffffff
102 #define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104 #define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
107 /* overlay flip addr flag */
108 #define OFC_UPDATE 0x1
110 /* polyphase filter coefficients */
111 #define N_HORIZ_Y_TAPS 5
112 #define N_VERT_Y_TAPS 3
113 #define N_HORIZ_UV_TAPS 3
114 #define N_VERT_UV_TAPS 3
118 /* memory bufferd overlay registers */
119 struct overlay_registers
{
147 u32 RESERVED1
; /* 0x6C */
160 u32 FASTHSCALE
; /* 0xA0 */
161 u32 UVSCALEV
; /* 0xA4 */
162 u32 RESERVEDC
[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS
[N_VERT_Y_TAPS
* N_PHASES
]; /* 0x200 */
164 u16 RESERVEDD
[0x100 / 2 - N_VERT_Y_TAPS
* N_PHASES
];
165 u16 Y_HCOEFS
[N_HORIZ_Y_TAPS
* N_PHASES
]; /* 0x300 */
166 u16 RESERVEDE
[0x200 / 2 - N_HORIZ_Y_TAPS
* N_PHASES
];
167 u16 UV_VCOEFS
[N_VERT_UV_TAPS
* N_PHASES
]; /* 0x500 */
168 u16 RESERVEDF
[0x100 / 2 - N_VERT_UV_TAPS
* N_PHASES
];
169 u16 UV_HCOEFS
[N_HORIZ_UV_TAPS
* N_PHASES
]; /* 0x600 */
170 u16 RESERVEDG
[0x100 / 2 - N_HORIZ_UV_TAPS
* N_PHASES
];
173 struct intel_overlay
{
174 struct drm_device
*dev
;
175 struct intel_crtc
*crtc
;
176 struct drm_i915_gem_object
*vid_bo
;
177 struct drm_i915_gem_object
*old_vid_bo
;
180 u32 pfit_vscale_ratio
; /* shifted-point number, (1<<12) == 1.0 */
182 u32 brightness
, contrast
, saturation
;
183 u32 old_xscale
, old_yscale
;
184 /* register access */
186 struct drm_i915_gem_object
*reg_bo
;
188 uint32_t last_flip_req
;
189 void (*flip_tail
)(struct intel_overlay
*);
192 static struct overlay_registers
*
193 intel_overlay_map_regs(struct intel_overlay
*overlay
)
195 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
196 struct overlay_registers
*regs
;
198 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
199 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
201 regs
= io_mapping_map_wc(dev_priv
->mm
.gtt_mapping
,
202 overlay
->reg_bo
->gtt_offset
);
207 static void intel_overlay_unmap_regs(struct intel_overlay
*overlay
,
208 struct overlay_registers
*regs
)
210 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
211 io_mapping_unmap(regs
);
214 static int intel_overlay_do_wait_request(struct intel_overlay
*overlay
,
215 struct drm_i915_gem_request
*request
,
217 void (*tail
)(struct intel_overlay
*))
219 struct drm_device
*dev
= overlay
->dev
;
220 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
223 BUG_ON(overlay
->last_flip_req
);
224 overlay
->last_flip_req
=
225 i915_add_request(dev
, NULL
, request
, &dev_priv
->render_ring
);
226 if (overlay
->last_flip_req
== 0)
229 overlay
->flip_tail
= tail
;
230 ret
= i915_do_wait_request(dev
,
231 overlay
->last_flip_req
, true,
232 &dev_priv
->render_ring
);
236 overlay
->last_flip_req
= 0;
240 /* Workaround for i830 bug where pipe a must be enable to change control regs */
242 i830_activate_pipe_a(struct drm_device
*dev
)
244 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
245 struct intel_crtc
*crtc
;
246 struct drm_crtc_helper_funcs
*crtc_funcs
;
247 struct drm_display_mode vesa_640x480
= {
248 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
249 752, 800, 0, 480, 489, 492, 525, 0,
250 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
)
253 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[0]);
254 if (crtc
->dpms_mode
== DRM_MODE_DPMS_ON
)
257 /* most i8xx have pipe a forced on, so don't trust dpms mode */
258 if (I915_READ(PIPEACONF
) & PIPECONF_ENABLE
)
261 crtc_funcs
= crtc
->base
.helper_private
;
262 if (crtc_funcs
->dpms
== NULL
)
265 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
267 mode
= drm_mode_duplicate(dev
, &vesa_640x480
);
268 drm_mode_set_crtcinfo(mode
, CRTC_INTERLACE_HALVE_V
);
269 if(!drm_crtc_helper_set_mode(&crtc
->base
, mode
,
270 crtc
->base
.x
, crtc
->base
.y
,
274 crtc_funcs
->dpms(&crtc
->base
, DRM_MODE_DPMS_ON
);
279 i830_deactivate_pipe_a(struct drm_device
*dev
)
281 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
282 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[0];
283 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
285 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
288 /* overlay needs to be disable in OCMD reg */
289 static int intel_overlay_on(struct intel_overlay
*overlay
)
291 struct drm_device
*dev
= overlay
->dev
;
292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
293 struct drm_i915_gem_request
*request
;
294 int pipe_a_quirk
= 0;
297 BUG_ON(overlay
->active
);
301 pipe_a_quirk
= i830_activate_pipe_a(dev
);
302 if (pipe_a_quirk
< 0)
306 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
307 if (request
== NULL
) {
312 ret
= BEGIN_LP_RING(4);
318 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_ON
);
319 OUT_RING(overlay
->flip_addr
| OFC_UPDATE
);
320 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
324 ret
= intel_overlay_do_wait_request(overlay
, request
, true, NULL
);
327 i830_deactivate_pipe_a(dev
);
332 /* overlay needs to be enabled in OCMD reg */
333 static int intel_overlay_continue(struct intel_overlay
*overlay
,
334 bool load_polyphase_filter
)
336 struct drm_device
*dev
= overlay
->dev
;
337 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
338 struct drm_i915_gem_request
*request
;
339 u32 flip_addr
= overlay
->flip_addr
;
343 BUG_ON(!overlay
->active
);
345 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
349 if (load_polyphase_filter
)
350 flip_addr
|= OFC_UPDATE
;
352 /* check for underruns */
353 tmp
= I915_READ(DOVSTA
);
355 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp
);
357 ret
= BEGIN_LP_RING(2);
362 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
366 overlay
->last_flip_req
=
367 i915_add_request(dev
, NULL
, request
, &dev_priv
->render_ring
);
371 static void intel_overlay_release_old_vid_tail(struct intel_overlay
*overlay
)
373 struct drm_gem_object
*obj
= &overlay
->old_vid_bo
->base
;
375 i915_gem_object_unpin(obj
);
376 drm_gem_object_unreference(obj
);
378 overlay
->old_vid_bo
= NULL
;
381 static void intel_overlay_off_tail(struct intel_overlay
*overlay
)
383 struct drm_gem_object
*obj
;
385 /* never have the overlay hw on without showing a frame */
386 BUG_ON(!overlay
->vid_bo
);
387 obj
= &overlay
->vid_bo
->base
;
389 i915_gem_object_unpin(obj
);
390 drm_gem_object_unreference(obj
);
391 overlay
->vid_bo
= NULL
;
393 overlay
->crtc
->overlay
= NULL
;
394 overlay
->crtc
= NULL
;
398 /* overlay needs to be disabled in OCMD reg */
399 static int intel_overlay_off(struct intel_overlay
*overlay
,
402 struct drm_device
*dev
= overlay
->dev
;
403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
404 u32 flip_addr
= overlay
->flip_addr
;
405 struct drm_i915_gem_request
*request
;
408 BUG_ON(!overlay
->active
);
410 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
414 /* According to intel docs the overlay hw may hang (when switching
415 * off) without loading the filter coeffs. It is however unclear whether
416 * this applies to the disabling of the overlay or to the switching off
417 * of the hw. Do it in both cases */
418 flip_addr
|= OFC_UPDATE
;
420 ret
= BEGIN_LP_RING(6);
425 /* wait for overlay to go idle */
426 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_CONTINUE
);
428 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
429 /* turn overlay off */
430 OUT_RING(MI_OVERLAY_FLIP
| MI_OVERLAY_OFF
);
432 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
435 return intel_overlay_do_wait_request(overlay
, request
, interruptible
,
436 intel_overlay_off_tail
);
439 /* recover from an interruption due to a signal
440 * We have to be careful not to repeat work forever an make forward progess. */
441 static int intel_overlay_recover_from_interrupt(struct intel_overlay
*overlay
,
444 struct drm_device
*dev
= overlay
->dev
;
445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
448 if (overlay
->last_flip_req
== 0)
451 ret
= i915_do_wait_request(dev
, overlay
->last_flip_req
,
452 interruptible
, &dev_priv
->render_ring
);
456 if (overlay
->flip_tail
)
457 overlay
->flip_tail(overlay
);
459 overlay
->last_flip_req
= 0;
463 /* Wait for pending overlay flip and release old frame.
464 * Needs to be called before the overlay register are changed
465 * via intel_overlay_(un)map_regs
467 static int intel_overlay_release_old_vid(struct intel_overlay
*overlay
)
469 struct drm_device
*dev
= overlay
->dev
;
470 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
473 /* Only wait if there is actually an old frame to release to
474 * guarantee forward progress.
476 if (!overlay
->old_vid_bo
)
479 if (I915_READ(ISR
) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT
) {
480 struct drm_i915_gem_request
*request
;
482 /* synchronous slowpath */
483 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
487 ret
= BEGIN_LP_RING(2);
493 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_OVERLAY_FLIP
);
497 ret
= intel_overlay_do_wait_request(overlay
, request
, true,
498 intel_overlay_release_old_vid_tail
);
503 intel_overlay_release_old_vid_tail(overlay
);
507 struct put_image_params
{
524 static int packed_depth_bytes(u32 format
)
526 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
527 case I915_OVERLAY_YUV422
:
529 case I915_OVERLAY_YUV411
:
530 /* return 6; not implemented */
536 static int packed_width_bytes(u32 format
, short width
)
538 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
539 case I915_OVERLAY_YUV422
:
546 static int uv_hsubsampling(u32 format
)
548 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
549 case I915_OVERLAY_YUV422
:
550 case I915_OVERLAY_YUV420
:
552 case I915_OVERLAY_YUV411
:
553 case I915_OVERLAY_YUV410
:
560 static int uv_vsubsampling(u32 format
)
562 switch (format
& I915_OVERLAY_DEPTH_MASK
) {
563 case I915_OVERLAY_YUV420
:
564 case I915_OVERLAY_YUV410
:
566 case I915_OVERLAY_YUV422
:
567 case I915_OVERLAY_YUV411
:
574 static u32
calc_swidthsw(struct drm_device
*dev
, u32 offset
, u32 width
)
576 u32 mask
, shift
, ret
;
584 ret
= ((offset
+ width
+ mask
) >> shift
) - (offset
>> shift
);
591 static const u16 y_static_hcoeffs
[N_HORIZ_Y_TAPS
* N_PHASES
] = {
592 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
593 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
594 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
595 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
596 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
597 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
598 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
599 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
600 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
601 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
602 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
603 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
604 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
605 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
606 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
607 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
608 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
611 static const u16 uv_static_hcoeffs
[N_HORIZ_UV_TAPS
* N_PHASES
] = {
612 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
613 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
614 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
615 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
616 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
617 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
618 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
619 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
620 0x3000, 0x0800, 0x3000
623 static void update_polyphase_filter(struct overlay_registers
*regs
)
625 memcpy(regs
->Y_HCOEFS
, y_static_hcoeffs
, sizeof(y_static_hcoeffs
));
626 memcpy(regs
->UV_HCOEFS
, uv_static_hcoeffs
, sizeof(uv_static_hcoeffs
));
629 static bool update_scaling_factors(struct intel_overlay
*overlay
,
630 struct overlay_registers
*regs
,
631 struct put_image_params
*params
)
633 /* fixed point with a 12 bit shift */
634 u32 xscale
, yscale
, xscale_UV
, yscale_UV
;
636 #define FRACT_MASK 0xfff
637 bool scale_changed
= false;
638 int uv_hscale
= uv_hsubsampling(params
->format
);
639 int uv_vscale
= uv_vsubsampling(params
->format
);
641 if (params
->dst_w
> 1)
642 xscale
= ((params
->src_scan_w
- 1) << FP_SHIFT
)
645 xscale
= 1 << FP_SHIFT
;
647 if (params
->dst_h
> 1)
648 yscale
= ((params
->src_scan_h
- 1) << FP_SHIFT
)
651 yscale
= 1 << FP_SHIFT
;
653 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
654 xscale_UV
= xscale
/uv_hscale
;
655 yscale_UV
= yscale
/uv_vscale
;
656 /* make the Y scale to UV scale ratio an exact multiply */
657 xscale
= xscale_UV
* uv_hscale
;
658 yscale
= yscale_UV
* uv_vscale
;
664 if (xscale
!= overlay
->old_xscale
|| yscale
!= overlay
->old_yscale
)
665 scale_changed
= true;
666 overlay
->old_xscale
= xscale
;
667 overlay
->old_yscale
= yscale
;
669 regs
->YRGBSCALE
= (((yscale
& FRACT_MASK
) << 20) |
670 ((xscale
>> FP_SHIFT
) << 16) |
671 ((xscale
& FRACT_MASK
) << 3));
673 regs
->UVSCALE
= (((yscale_UV
& FRACT_MASK
) << 20) |
674 ((xscale_UV
>> FP_SHIFT
) << 16) |
675 ((xscale_UV
& FRACT_MASK
) << 3));
677 regs
->UVSCALEV
= ((((yscale
>> FP_SHIFT
) << 16) |
678 ((yscale_UV
>> FP_SHIFT
) << 0)));
681 update_polyphase_filter(regs
);
683 return scale_changed
;
686 static void update_colorkey(struct intel_overlay
*overlay
,
687 struct overlay_registers
*regs
)
689 u32 key
= overlay
->color_key
;
691 switch (overlay
->crtc
->base
.fb
->bits_per_pixel
) {
694 regs
->DCLRKM
= CLK_RGB8I_MASK
| DST_KEY_ENABLE
;
698 if (overlay
->crtc
->base
.fb
->depth
== 15) {
699 regs
->DCLRKV
= RGB15_TO_COLORKEY(key
);
700 regs
->DCLRKM
= CLK_RGB15_MASK
| DST_KEY_ENABLE
;
702 regs
->DCLRKV
= RGB16_TO_COLORKEY(key
);
703 regs
->DCLRKM
= CLK_RGB16_MASK
| DST_KEY_ENABLE
;
710 regs
->DCLRKM
= CLK_RGB24_MASK
| DST_KEY_ENABLE
;
715 static u32
overlay_cmd_reg(struct put_image_params
*params
)
717 u32 cmd
= OCMD_ENABLE
| OCMD_BUF_TYPE_FRAME
| OCMD_BUFFER0
;
719 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
720 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
721 case I915_OVERLAY_YUV422
:
722 cmd
|= OCMD_YUV_422_PLANAR
;
724 case I915_OVERLAY_YUV420
:
725 cmd
|= OCMD_YUV_420_PLANAR
;
727 case I915_OVERLAY_YUV411
:
728 case I915_OVERLAY_YUV410
:
729 cmd
|= OCMD_YUV_410_PLANAR
;
732 } else { /* YUV packed */
733 switch (params
->format
& I915_OVERLAY_DEPTH_MASK
) {
734 case I915_OVERLAY_YUV422
:
735 cmd
|= OCMD_YUV_422_PACKED
;
737 case I915_OVERLAY_YUV411
:
738 cmd
|= OCMD_YUV_411_PACKED
;
742 switch (params
->format
& I915_OVERLAY_SWAP_MASK
) {
743 case I915_OVERLAY_NO_SWAP
:
745 case I915_OVERLAY_UV_SWAP
:
748 case I915_OVERLAY_Y_SWAP
:
751 case I915_OVERLAY_Y_AND_UV_SWAP
:
752 cmd
|= OCMD_Y_AND_UV_SWAP
;
760 static int intel_overlay_do_put_image(struct intel_overlay
*overlay
,
761 struct drm_gem_object
*new_bo
,
762 struct put_image_params
*params
)
765 struct overlay_registers
*regs
;
766 bool scale_changed
= false;
767 struct drm_i915_gem_object
*bo_priv
= to_intel_bo(new_bo
);
768 struct drm_device
*dev
= overlay
->dev
;
770 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
771 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
774 ret
= intel_overlay_release_old_vid(overlay
);
778 ret
= i915_gem_object_pin(new_bo
, PAGE_SIZE
);
782 ret
= i915_gem_object_set_to_gtt_domain(new_bo
, 0);
786 if (!overlay
->active
) {
787 regs
= intel_overlay_map_regs(overlay
);
792 regs
->OCONFIG
= OCONF_CC_OUT_8BIT
;
793 if (IS_GEN4(overlay
->dev
))
794 regs
->OCONFIG
|= OCONF_CSC_MODE_BT709
;
795 regs
->OCONFIG
|= overlay
->crtc
->pipe
== 0 ?
796 OCONF_PIPE_A
: OCONF_PIPE_B
;
797 intel_overlay_unmap_regs(overlay
, regs
);
799 ret
= intel_overlay_on(overlay
);
804 regs
= intel_overlay_map_regs(overlay
);
810 regs
->DWINPOS
= (params
->dst_y
<< 16) | params
->dst_x
;
811 regs
->DWINSZ
= (params
->dst_h
<< 16) | params
->dst_w
;
813 if (params
->format
& I915_OVERLAY_YUV_PACKED
)
814 tmp_width
= packed_width_bytes(params
->format
, params
->src_w
);
816 tmp_width
= params
->src_w
;
818 regs
->SWIDTH
= params
->src_w
;
819 regs
->SWIDTHSW
= calc_swidthsw(overlay
->dev
,
820 params
->offset_Y
, tmp_width
);
821 regs
->SHEIGHT
= params
->src_h
;
822 regs
->OBUF_0Y
= bo_priv
->gtt_offset
+ params
-> offset_Y
;
823 regs
->OSTRIDE
= params
->stride_Y
;
825 if (params
->format
& I915_OVERLAY_YUV_PLANAR
) {
826 int uv_hscale
= uv_hsubsampling(params
->format
);
827 int uv_vscale
= uv_vsubsampling(params
->format
);
829 regs
->SWIDTH
|= (params
->src_w
/uv_hscale
) << 16;
830 tmp_U
= calc_swidthsw(overlay
->dev
, params
->offset_U
,
831 params
->src_w
/uv_hscale
);
832 tmp_V
= calc_swidthsw(overlay
->dev
, params
->offset_V
,
833 params
->src_w
/uv_hscale
);
834 regs
->SWIDTHSW
|= max_t(u32
, tmp_U
, tmp_V
) << 16;
835 regs
->SHEIGHT
|= (params
->src_h
/uv_vscale
) << 16;
836 regs
->OBUF_0U
= bo_priv
->gtt_offset
+ params
->offset_U
;
837 regs
->OBUF_0V
= bo_priv
->gtt_offset
+ params
->offset_V
;
838 regs
->OSTRIDE
|= params
->stride_UV
<< 16;
841 scale_changed
= update_scaling_factors(overlay
, regs
, params
);
843 update_colorkey(overlay
, regs
);
845 regs
->OCMD
= overlay_cmd_reg(params
);
847 intel_overlay_unmap_regs(overlay
, regs
);
849 ret
= intel_overlay_continue(overlay
, scale_changed
);
853 overlay
->old_vid_bo
= overlay
->vid_bo
;
854 overlay
->vid_bo
= to_intel_bo(new_bo
);
859 i915_gem_object_unpin(new_bo
);
863 int intel_overlay_switch_off(struct intel_overlay
*overlay
,
866 struct overlay_registers
*regs
;
867 struct drm_device
*dev
= overlay
->dev
;
870 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
871 BUG_ON(!mutex_is_locked(&dev
->mode_config
.mutex
));
873 ret
= intel_overlay_recover_from_interrupt(overlay
, interruptible
);
877 if (!overlay
->active
)
880 ret
= intel_overlay_release_old_vid(overlay
);
884 regs
= intel_overlay_map_regs(overlay
);
886 intel_overlay_unmap_regs(overlay
, regs
);
888 ret
= intel_overlay_off(overlay
, interruptible
);
892 intel_overlay_off_tail(overlay
);
896 static int check_overlay_possible_on_crtc(struct intel_overlay
*overlay
,
897 struct intel_crtc
*crtc
)
899 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
904 /* can't use the overlay with double wide pipe */
905 if (INTEL_INFO(overlay
->dev
)->gen
< 4 &&
906 (I915_READ(PIPECONF(crtc
->pipe
)) & (PIPECONF_DOUBLE_WIDE
| PIPECONF_ENABLE
)) != PIPECONF_ENABLE
)
912 static void update_pfit_vscale_ratio(struct intel_overlay
*overlay
)
914 struct drm_device
*dev
= overlay
->dev
;
915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
916 u32 pfit_control
= I915_READ(PFIT_CONTROL
);
919 /* XXX: This is not the same logic as in the xorg driver, but more in
920 * line with the intel documentation for the i965
922 if (INTEL_INFO(dev
)->gen
>= 4) {
923 /* on i965 use the PGM reg to read out the autoscaler values */
924 ratio
= I915_READ(PFIT_PGM_RATIOS
) >> PFIT_VERT_SCALE_SHIFT_965
;
926 if (pfit_control
& VERT_AUTO_SCALE
)
927 ratio
= I915_READ(PFIT_AUTO_RATIOS
);
929 ratio
= I915_READ(PFIT_PGM_RATIOS
);
930 ratio
>>= PFIT_VERT_SCALE_SHIFT
;
933 overlay
->pfit_vscale_ratio
= ratio
;
936 static int check_overlay_dst(struct intel_overlay
*overlay
,
937 struct drm_intel_overlay_put_image
*rec
)
939 struct drm_display_mode
*mode
= &overlay
->crtc
->base
.mode
;
941 if (rec
->dst_x
< mode
->crtc_hdisplay
&&
942 rec
->dst_x
+ rec
->dst_width
<= mode
->crtc_hdisplay
&&
943 rec
->dst_y
< mode
->crtc_vdisplay
&&
944 rec
->dst_y
+ rec
->dst_height
<= mode
->crtc_vdisplay
)
950 static int check_overlay_scaling(struct put_image_params
*rec
)
954 /* downscaling limit is 8.0 */
955 tmp
= ((rec
->src_scan_h
<< 16) / rec
->dst_h
) >> 16;
958 tmp
= ((rec
->src_scan_w
<< 16) / rec
->dst_w
) >> 16;
965 static int check_overlay_src(struct drm_device
*dev
,
966 struct drm_intel_overlay_put_image
*rec
,
967 struct drm_gem_object
*new_bo
)
969 int uv_hscale
= uv_hsubsampling(rec
->flags
);
970 int uv_vscale
= uv_vsubsampling(rec
->flags
);
971 u32 stride_mask
, depth
, tmp
;
973 /* check src dimensions */
974 if (IS_845G(dev
) || IS_I830(dev
)) {
975 if (rec
->src_height
> IMAGE_MAX_HEIGHT_LEGACY
||
976 rec
->src_width
> IMAGE_MAX_WIDTH_LEGACY
)
979 if (rec
->src_height
> IMAGE_MAX_HEIGHT
||
980 rec
->src_width
> IMAGE_MAX_WIDTH
)
984 /* better safe than sorry, use 4 as the maximal subsampling ratio */
985 if (rec
->src_height
< N_VERT_Y_TAPS
*4 ||
986 rec
->src_width
< N_HORIZ_Y_TAPS
*4)
989 /* check alignment constraints */
990 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
991 case I915_OVERLAY_RGB
:
992 /* not implemented */
995 case I915_OVERLAY_YUV_PACKED
:
999 depth
= packed_depth_bytes(rec
->flags
);
1003 /* ignore UV planes */
1007 /* check pixel alignment */
1008 if (rec
->offset_Y
% depth
)
1012 case I915_OVERLAY_YUV_PLANAR
:
1013 if (uv_vscale
< 0 || uv_hscale
< 0)
1015 /* no offset restrictions for planar formats */
1022 if (rec
->src_width
% uv_hscale
)
1025 /* stride checking */
1026 if (IS_I830(dev
) || IS_845G(dev
))
1031 if (rec
->stride_Y
& stride_mask
|| rec
->stride_UV
& stride_mask
)
1033 if (IS_GEN4(dev
) && rec
->stride_Y
< 512)
1036 tmp
= (rec
->flags
& I915_OVERLAY_TYPE_MASK
) == I915_OVERLAY_YUV_PLANAR
?
1038 if (rec
->stride_Y
> tmp
|| rec
->stride_UV
> 2*1024)
1041 /* check buffer dimensions */
1042 switch (rec
->flags
& I915_OVERLAY_TYPE_MASK
) {
1043 case I915_OVERLAY_RGB
:
1044 case I915_OVERLAY_YUV_PACKED
:
1045 /* always 4 Y values per depth pixels */
1046 if (packed_width_bytes(rec
->flags
, rec
->src_width
) > rec
->stride_Y
)
1049 tmp
= rec
->stride_Y
*rec
->src_height
;
1050 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1054 case I915_OVERLAY_YUV_PLANAR
:
1055 if (rec
->src_width
> rec
->stride_Y
)
1057 if (rec
->src_width
/uv_hscale
> rec
->stride_UV
)
1060 tmp
= rec
->stride_Y
* rec
->src_height
;
1061 if (rec
->offset_Y
+ tmp
> new_bo
->size
)
1064 tmp
= rec
->stride_UV
* (rec
->src_height
/ uv_vscale
);
1065 if (rec
->offset_U
+ tmp
> new_bo
->size
||
1066 rec
->offset_V
+ tmp
> new_bo
->size
)
1075 * Return the pipe currently connected to the panel fitter,
1076 * or -1 if the panel fitter is not present or not in use
1078 static int intel_panel_fitter_pipe(struct drm_device
*dev
)
1080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1083 /* i830 doesn't have a panel fitter */
1087 pfit_control
= I915_READ(PFIT_CONTROL
);
1089 /* See if the panel fitter is in use */
1090 if ((pfit_control
& PFIT_ENABLE
) == 0)
1093 /* 965 can place panel fitter on either pipe */
1095 return (pfit_control
>> 29) & 0x3;
1097 /* older chips can only use pipe 1 */
1101 int intel_overlay_put_image(struct drm_device
*dev
, void *data
,
1102 struct drm_file
*file_priv
)
1104 struct drm_intel_overlay_put_image
*put_image_rec
= data
;
1105 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1106 struct intel_overlay
*overlay
;
1107 struct drm_mode_object
*drmmode_obj
;
1108 struct intel_crtc
*crtc
;
1109 struct drm_gem_object
*new_bo
;
1110 struct put_image_params
*params
;
1114 DRM_ERROR("called with no initialization\n");
1118 overlay
= dev_priv
->overlay
;
1120 DRM_DEBUG("userspace bug: no overlay\n");
1124 if (!(put_image_rec
->flags
& I915_OVERLAY_ENABLE
)) {
1125 mutex_lock(&dev
->mode_config
.mutex
);
1126 mutex_lock(&dev
->struct_mutex
);
1128 ret
= intel_overlay_switch_off(overlay
, true);
1130 mutex_unlock(&dev
->struct_mutex
);
1131 mutex_unlock(&dev
->mode_config
.mutex
);
1136 params
= kmalloc(sizeof(struct put_image_params
), GFP_KERNEL
);
1140 drmmode_obj
= drm_mode_object_find(dev
, put_image_rec
->crtc_id
,
1141 DRM_MODE_OBJECT_CRTC
);
1146 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
1148 new_bo
= drm_gem_object_lookup(dev
, file_priv
,
1149 put_image_rec
->bo_handle
);
1155 mutex_lock(&dev
->mode_config
.mutex
);
1156 mutex_lock(&dev
->struct_mutex
);
1158 ret
= intel_overlay_recover_from_interrupt(overlay
, true);
1162 if (overlay
->crtc
!= crtc
) {
1163 struct drm_display_mode
*mode
= &crtc
->base
.mode
;
1164 ret
= intel_overlay_switch_off(overlay
, true);
1168 ret
= check_overlay_possible_on_crtc(overlay
, crtc
);
1172 overlay
->crtc
= crtc
;
1173 crtc
->overlay
= overlay
;
1175 /* line too wide, i.e. one-line-mode */
1176 if (mode
->hdisplay
> 1024 &&
1177 intel_panel_fitter_pipe(dev
) == crtc
->pipe
) {
1178 overlay
->pfit_active
= 1;
1179 update_pfit_vscale_ratio(overlay
);
1181 overlay
->pfit_active
= 0;
1184 ret
= check_overlay_dst(overlay
, put_image_rec
);
1188 if (overlay
->pfit_active
) {
1189 params
->dst_y
= ((((u32
)put_image_rec
->dst_y
) << 12) /
1190 overlay
->pfit_vscale_ratio
);
1191 /* shifting right rounds downwards, so add 1 */
1192 params
->dst_h
= ((((u32
)put_image_rec
->dst_height
) << 12) /
1193 overlay
->pfit_vscale_ratio
) + 1;
1195 params
->dst_y
= put_image_rec
->dst_y
;
1196 params
->dst_h
= put_image_rec
->dst_height
;
1198 params
->dst_x
= put_image_rec
->dst_x
;
1199 params
->dst_w
= put_image_rec
->dst_width
;
1201 params
->src_w
= put_image_rec
->src_width
;
1202 params
->src_h
= put_image_rec
->src_height
;
1203 params
->src_scan_w
= put_image_rec
->src_scan_width
;
1204 params
->src_scan_h
= put_image_rec
->src_scan_height
;
1205 if (params
->src_scan_h
> params
->src_h
||
1206 params
->src_scan_w
> params
->src_w
) {
1211 ret
= check_overlay_src(dev
, put_image_rec
, new_bo
);
1214 params
->format
= put_image_rec
->flags
& ~I915_OVERLAY_FLAGS_MASK
;
1215 params
->stride_Y
= put_image_rec
->stride_Y
;
1216 params
->stride_UV
= put_image_rec
->stride_UV
;
1217 params
->offset_Y
= put_image_rec
->offset_Y
;
1218 params
->offset_U
= put_image_rec
->offset_U
;
1219 params
->offset_V
= put_image_rec
->offset_V
;
1221 /* Check scaling after src size to prevent a divide-by-zero. */
1222 ret
= check_overlay_scaling(params
);
1226 ret
= intel_overlay_do_put_image(overlay
, new_bo
, params
);
1230 mutex_unlock(&dev
->struct_mutex
);
1231 mutex_unlock(&dev
->mode_config
.mutex
);
1238 mutex_unlock(&dev
->struct_mutex
);
1239 mutex_unlock(&dev
->mode_config
.mutex
);
1240 drm_gem_object_unreference_unlocked(new_bo
);
1247 static void update_reg_attrs(struct intel_overlay
*overlay
,
1248 struct overlay_registers
*regs
)
1250 regs
->OCLRC0
= (overlay
->contrast
<< 18) | (overlay
->brightness
& 0xff);
1251 regs
->OCLRC1
= overlay
->saturation
;
1254 static bool check_gamma_bounds(u32 gamma1
, u32 gamma2
)
1258 if (gamma1
& 0xff000000 || gamma2
& 0xff000000)
1261 for (i
= 0; i
< 3; i
++) {
1262 if (((gamma1
>> i
*8) & 0xff) >= ((gamma2
>> i
*8) & 0xff))
1269 static bool check_gamma5_errata(u32 gamma5
)
1273 for (i
= 0; i
< 3; i
++) {
1274 if (((gamma5
>> i
*8) & 0xff) == 0x80)
1281 static int check_gamma(struct drm_intel_overlay_attrs
*attrs
)
1283 if (!check_gamma_bounds(0, attrs
->gamma0
) ||
1284 !check_gamma_bounds(attrs
->gamma0
, attrs
->gamma1
) ||
1285 !check_gamma_bounds(attrs
->gamma1
, attrs
->gamma2
) ||
1286 !check_gamma_bounds(attrs
->gamma2
, attrs
->gamma3
) ||
1287 !check_gamma_bounds(attrs
->gamma3
, attrs
->gamma4
) ||
1288 !check_gamma_bounds(attrs
->gamma4
, attrs
->gamma5
) ||
1289 !check_gamma_bounds(attrs
->gamma5
, 0x00ffffff))
1292 if (!check_gamma5_errata(attrs
->gamma5
))
1298 int intel_overlay_attrs(struct drm_device
*dev
, void *data
,
1299 struct drm_file
*file_priv
)
1301 struct drm_intel_overlay_attrs
*attrs
= data
;
1302 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1303 struct intel_overlay
*overlay
;
1304 struct overlay_registers
*regs
;
1308 DRM_ERROR("called with no initialization\n");
1312 overlay
= dev_priv
->overlay
;
1314 DRM_DEBUG("userspace bug: no overlay\n");
1318 mutex_lock(&dev
->mode_config
.mutex
);
1319 mutex_lock(&dev
->struct_mutex
);
1322 if (!(attrs
->flags
& I915_OVERLAY_UPDATE_ATTRS
)) {
1323 attrs
->color_key
= overlay
->color_key
;
1324 attrs
->brightness
= overlay
->brightness
;
1325 attrs
->contrast
= overlay
->contrast
;
1326 attrs
->saturation
= overlay
->saturation
;
1328 if (!IS_GEN2(dev
)) {
1329 attrs
->gamma0
= I915_READ(OGAMC0
);
1330 attrs
->gamma1
= I915_READ(OGAMC1
);
1331 attrs
->gamma2
= I915_READ(OGAMC2
);
1332 attrs
->gamma3
= I915_READ(OGAMC3
);
1333 attrs
->gamma4
= I915_READ(OGAMC4
);
1334 attrs
->gamma5
= I915_READ(OGAMC5
);
1337 if (attrs
->brightness
< -128 || attrs
->brightness
> 127)
1339 if (attrs
->contrast
> 255)
1341 if (attrs
->saturation
> 1023)
1344 overlay
->color_key
= attrs
->color_key
;
1345 overlay
->brightness
= attrs
->brightness
;
1346 overlay
->contrast
= attrs
->contrast
;
1347 overlay
->saturation
= attrs
->saturation
;
1349 regs
= intel_overlay_map_regs(overlay
);
1355 update_reg_attrs(overlay
, regs
);
1357 intel_overlay_unmap_regs(overlay
, regs
);
1359 if (attrs
->flags
& I915_OVERLAY_UPDATE_GAMMA
) {
1363 if (overlay
->active
) {
1368 ret
= check_gamma(attrs
);
1372 I915_WRITE(OGAMC0
, attrs
->gamma0
);
1373 I915_WRITE(OGAMC1
, attrs
->gamma1
);
1374 I915_WRITE(OGAMC2
, attrs
->gamma2
);
1375 I915_WRITE(OGAMC3
, attrs
->gamma3
);
1376 I915_WRITE(OGAMC4
, attrs
->gamma4
);
1377 I915_WRITE(OGAMC5
, attrs
->gamma5
);
1383 mutex_unlock(&dev
->struct_mutex
);
1384 mutex_unlock(&dev
->mode_config
.mutex
);
1389 void intel_setup_overlay(struct drm_device
*dev
)
1391 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1392 struct intel_overlay
*overlay
;
1393 struct drm_gem_object
*reg_bo
;
1394 struct overlay_registers
*regs
;
1397 if (!HAS_OVERLAY(dev
))
1400 overlay
= kzalloc(sizeof(struct intel_overlay
), GFP_KERNEL
);
1405 reg_bo
= i915_gem_alloc_object(dev
, PAGE_SIZE
);
1408 overlay
->reg_bo
= to_intel_bo(reg_bo
);
1410 if (OVERLAY_NEEDS_PHYSICAL(dev
)) {
1411 ret
= i915_gem_attach_phys_object(dev
, reg_bo
,
1412 I915_GEM_PHYS_OVERLAY_REGS
,
1415 DRM_ERROR("failed to attach phys overlay regs\n");
1418 overlay
->flip_addr
= overlay
->reg_bo
->phys_obj
->handle
->busaddr
;
1420 ret
= i915_gem_object_pin(reg_bo
, PAGE_SIZE
);
1422 DRM_ERROR("failed to pin overlay register bo\n");
1425 overlay
->flip_addr
= overlay
->reg_bo
->gtt_offset
;
1427 ret
= i915_gem_object_set_to_gtt_domain(reg_bo
, true);
1429 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1434 /* init all values */
1435 overlay
->color_key
= 0x0101fe;
1436 overlay
->brightness
= -19;
1437 overlay
->contrast
= 75;
1438 overlay
->saturation
= 146;
1440 regs
= intel_overlay_map_regs(overlay
);
1444 memset(regs
, 0, sizeof(struct overlay_registers
));
1445 update_polyphase_filter(regs
);
1446 update_reg_attrs(overlay
, regs
);
1448 intel_overlay_unmap_regs(overlay
, regs
);
1450 dev_priv
->overlay
= overlay
;
1451 DRM_INFO("initialized overlay support\n");
1455 i915_gem_object_unpin(reg_bo
);
1457 drm_gem_object_unreference(reg_bo
);
1463 void intel_cleanup_overlay(struct drm_device
*dev
)
1465 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1467 if (!dev_priv
->overlay
)
1470 /* The bo's should be free'd by the generic code already.
1471 * Furthermore modesetting teardown happens beforehand so the
1472 * hardware should be off already */
1473 BUG_ON(dev_priv
->overlay
->active
);
1475 drm_gem_object_unreference_unlocked(&dev_priv
->overlay
->reg_bo
->base
);
1476 kfree(dev_priv
->overlay
);
1479 #ifdef CONFIG_DEBUG_FS
1480 #include <linux/seq_file.h>
1482 struct intel_overlay_error_state
{
1483 struct overlay_registers regs
;
1489 static struct overlay_registers
*
1490 intel_overlay_map_regs_atomic(struct intel_overlay
*overlay
)
1492 drm_i915_private_t
*dev_priv
= overlay
->dev
->dev_private
;
1493 struct overlay_registers
*regs
;
1495 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1496 regs
= overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1498 regs
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
1499 overlay
->reg_bo
->gtt_offset
);
1504 static void intel_overlay_unmap_regs_atomic(struct intel_overlay
*overlay
,
1505 struct overlay_registers
*regs
)
1507 if (!OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1508 io_mapping_unmap_atomic(regs
);
1512 struct intel_overlay_error_state
*
1513 intel_overlay_capture_error_state(struct drm_device
*dev
)
1515 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1516 struct intel_overlay
*overlay
= dev_priv
->overlay
;
1517 struct intel_overlay_error_state
*error
;
1518 struct overlay_registers __iomem
*regs
;
1520 if (!overlay
|| !overlay
->active
)
1523 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
1527 error
->dovsta
= I915_READ(DOVSTA
);
1528 error
->isr
= I915_READ(ISR
);
1529 if (OVERLAY_NEEDS_PHYSICAL(overlay
->dev
))
1530 error
->base
= (long) overlay
->reg_bo
->phys_obj
->handle
->vaddr
;
1532 error
->base
= (long) overlay
->reg_bo
->gtt_offset
;
1534 regs
= intel_overlay_map_regs_atomic(overlay
);
1538 memcpy_fromio(&error
->regs
, regs
, sizeof(struct overlay_registers
));
1539 intel_overlay_unmap_regs_atomic(overlay
, regs
);
1549 intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
)
1551 seq_printf(m
, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1552 error
->dovsta
, error
->isr
);
1553 seq_printf(m
, " Register file at 0x%08lx:\n",
1556 #define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)