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drm/i915: Propagate errors from writing to ringbuffer
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blobeb4c725e30696a30455e67bedaa75f77d9da341c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
646 {
647 struct drm_device *dev = crtc->dev;
648 struct drm_i915_private *dev_priv = dev->dev_private;
649 const intel_limit_t *limit;
650 int refclk = 120;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
654 refclk = 100;
655
656 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
657 LVDS_CLKB_POWER_UP) {
658 /* LVDS dual channel */
659 if (refclk == 100)
660 limit = &intel_limits_ironlake_dual_lvds_100m;
661 else
662 limit = &intel_limits_ironlake_dual_lvds;
663 } else {
664 if (refclk == 100)
665 limit = &intel_limits_ironlake_single_lvds_100m;
666 else
667 limit = &intel_limits_ironlake_single_lvds;
668 }
669 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
670 HAS_eDP)
671 limit = &intel_limits_ironlake_display_port;
672 else
673 limit = &intel_limits_ironlake_dac;
674
675 return limit;
676 }
677
678 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 const intel_limit_t *limit;
683
684 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
685 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
686 LVDS_CLKB_POWER_UP)
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_dual_channel_lvds;
689 else
690 /* LVDS with dual channel */
691 limit = &intel_limits_g4x_single_channel_lvds;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
693 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
694 limit = &intel_limits_g4x_hdmi;
695 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
696 limit = &intel_limits_g4x_sdvo;
697 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
698 limit = &intel_limits_g4x_display_port;
699 } else /* The option is for other outputs */
700 limit = &intel_limits_i9xx_sdvo;
701
702 return limit;
703 }
704
705 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
706 {
707 struct drm_device *dev = crtc->dev;
708 const intel_limit_t *limit;
709
710 if (HAS_PCH_SPLIT(dev))
711 limit = intel_ironlake_limit(crtc);
712 else if (IS_G4X(dev)) {
713 limit = intel_g4x_limit(crtc);
714 } else if (IS_PINEVIEW(dev)) {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_pineview_lvds;
717 else
718 limit = &intel_limits_pineview_sdvo;
719 } else if (!IS_GEN2(dev)) {
720 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
721 limit = &intel_limits_i9xx_lvds;
722 else
723 limit = &intel_limits_i9xx_sdvo;
724 } else {
725 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
726 limit = &intel_limits_i8xx_lvds;
727 else
728 limit = &intel_limits_i8xx_dvo;
729 }
730 return limit;
731 }
732
733 /* m1 is reserved as 0 in Pineview, n is a ring counter */
734 static void pineview_clock(int refclk, intel_clock_t *clock)
735 {
736 clock->m = clock->m2 + 2;
737 clock->p = clock->p1 * clock->p2;
738 clock->vco = refclk * clock->m / clock->n;
739 clock->dot = clock->vco / clock->p;
740 }
741
742 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
743 {
744 if (IS_PINEVIEW(dev)) {
745 pineview_clock(refclk, clock);
746 return;
747 }
748 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
749 clock->p = clock->p1 * clock->p2;
750 clock->vco = refclk * clock->m / (clock->n + 2);
751 clock->dot = clock->vco / clock->p;
752 }
753
754 /**
755 * Returns whether any output on the specified pipe is of the specified type
756 */
757 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
758 {
759 struct drm_device *dev = crtc->dev;
760 struct drm_mode_config *mode_config = &dev->mode_config;
761 struct intel_encoder *encoder;
762
763 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
764 if (encoder->base.crtc == crtc && encoder->type == type)
765 return true;
766
767 return false;
768 }
769
770 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
771 /**
772 * Returns whether the given set of divisors are valid for a given refclk with
773 * the given connectors.
774 */
775
776 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
777 {
778 const intel_limit_t *limit = intel_limit (crtc);
779 struct drm_device *dev = crtc->dev;
780
781 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
782 INTELPllInvalid ("p1 out of range\n");
783 if (clock->p < limit->p.min || limit->p.max < clock->p)
784 INTELPllInvalid ("p out of range\n");
785 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
786 INTELPllInvalid ("m2 out of range\n");
787 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
788 INTELPllInvalid ("m1 out of range\n");
789 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
790 INTELPllInvalid ("m1 <= m2\n");
791 if (clock->m < limit->m.min || limit->m.max < clock->m)
792 INTELPllInvalid ("m out of range\n");
793 if (clock->n < limit->n.min || limit->n.max < clock->n)
794 INTELPllInvalid ("n out of range\n");
795 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
796 INTELPllInvalid ("vco out of range\n");
797 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
798 * connector, etc., rather than just a single range.
799 */
800 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
801 INTELPllInvalid ("dot out of range\n");
802
803 return true;
804 }
805
806 static bool
807 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
808 int target, int refclk, intel_clock_t *best_clock)
809
810 {
811 struct drm_device *dev = crtc->dev;
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 intel_clock_t clock;
814 int err = target;
815
816 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
817 (I915_READ(LVDS)) != 0) {
818 /*
819 * For LVDS, if the panel is on, just rely on its current
820 * settings for dual-channel. We haven't figured out how to
821 * reliably set up different single/dual channel state, if we
822 * even can.
823 */
824 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
825 LVDS_CLKB_POWER_UP)
826 clock.p2 = limit->p2.p2_fast;
827 else
828 clock.p2 = limit->p2.p2_slow;
829 } else {
830 if (target < limit->p2.dot_limit)
831 clock.p2 = limit->p2.p2_slow;
832 else
833 clock.p2 = limit->p2.p2_fast;
834 }
835
836 memset (best_clock, 0, sizeof (*best_clock));
837
838 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
839 clock.m1++) {
840 for (clock.m2 = limit->m2.min;
841 clock.m2 <= limit->m2.max; clock.m2++) {
842 /* m1 is always 0 in Pineview */
843 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
844 break;
845 for (clock.n = limit->n.min;
846 clock.n <= limit->n.max; clock.n++) {
847 for (clock.p1 = limit->p1.min;
848 clock.p1 <= limit->p1.max; clock.p1++) {
849 int this_err;
850
851 intel_clock(dev, refclk, &clock);
852
853 if (!intel_PLL_is_valid(crtc, &clock))
854 continue;
855
856 this_err = abs(clock.dot - target);
857 if (this_err < err) {
858 *best_clock = clock;
859 err = this_err;
860 }
861 }
862 }
863 }
864 }
865
866 return (err != target);
867 }
868
869 static bool
870 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *best_clock)
872 {
873 struct drm_device *dev = crtc->dev;
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 intel_clock_t clock;
876 int max_n;
877 bool found;
878 /* approximately equals target * 0.00585 */
879 int err_most = (target >> 8) + (target >> 9);
880 found = false;
881
882 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
883 int lvds_reg;
884
885 if (HAS_PCH_SPLIT(dev))
886 lvds_reg = PCH_LVDS;
887 else
888 lvds_reg = LVDS;
889 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
890 LVDS_CLKB_POWER_UP)
891 clock.p2 = limit->p2.p2_fast;
892 else
893 clock.p2 = limit->p2.p2_slow;
894 } else {
895 if (target < limit->p2.dot_limit)
896 clock.p2 = limit->p2.p2_slow;
897 else
898 clock.p2 = limit->p2.p2_fast;
899 }
900
901 memset(best_clock, 0, sizeof(*best_clock));
902 max_n = limit->n.max;
903 /* based on hardware requirement, prefer smaller n to precision */
904 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
905 /* based on hardware requirement, prefere larger m1,m2 */
906 for (clock.m1 = limit->m1.max;
907 clock.m1 >= limit->m1.min; clock.m1--) {
908 for (clock.m2 = limit->m2.max;
909 clock.m2 >= limit->m2.min; clock.m2--) {
910 for (clock.p1 = limit->p1.max;
911 clock.p1 >= limit->p1.min; clock.p1--) {
912 int this_err;
913
914 intel_clock(dev, refclk, &clock);
915 if (!intel_PLL_is_valid(crtc, &clock))
916 continue;
917 this_err = abs(clock.dot - target) ;
918 if (this_err < err_most) {
919 *best_clock = clock;
920 err_most = this_err;
921 max_n = clock.n;
922 found = true;
923 }
924 }
925 }
926 }
927 }
928 return found;
929 }
930
931 static bool
932 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
933 int target, int refclk, intel_clock_t *best_clock)
934 {
935 struct drm_device *dev = crtc->dev;
936 intel_clock_t clock;
937
938 if (target < 200000) {
939 clock.n = 1;
940 clock.p1 = 2;
941 clock.p2 = 10;
942 clock.m1 = 12;
943 clock.m2 = 9;
944 } else {
945 clock.n = 2;
946 clock.p1 = 1;
947 clock.p2 = 10;
948 clock.m1 = 14;
949 clock.m2 = 8;
950 }
951 intel_clock(dev, refclk, &clock);
952 memcpy(best_clock, &clock, sizeof(intel_clock_t));
953 return true;
954 }
955
956 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
957 static bool
958 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
959 int target, int refclk, intel_clock_t *best_clock)
960 {
961 intel_clock_t clock;
962 if (target < 200000) {
963 clock.p1 = 2;
964 clock.p2 = 10;
965 clock.n = 2;
966 clock.m1 = 23;
967 clock.m2 = 8;
968 } else {
969 clock.p1 = 1;
970 clock.p2 = 10;
971 clock.n = 1;
972 clock.m1 = 14;
973 clock.m2 = 2;
974 }
975 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
976 clock.p = (clock.p1 * clock.p2);
977 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
978 clock.vco = 0;
979 memcpy(best_clock, &clock, sizeof(intel_clock_t));
980 return true;
981 }
982
983 /**
984 * intel_wait_for_vblank - wait for vblank on a given pipe
985 * @dev: drm device
986 * @pipe: pipe to wait for
987 *
988 * Wait for vblank to occur on a given pipe. Needed for various bits of
989 * mode setting code.
990 */
991 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
992 {
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
995
996 /* Clear existing vblank status. Note this will clear any other
997 * sticky status fields as well.
998 *
999 * This races with i915_driver_irq_handler() with the result
1000 * that either function could miss a vblank event. Here it is not
1001 * fatal, as we will either wait upon the next vblank interrupt or
1002 * timeout. Generally speaking intel_wait_for_vblank() is only
1003 * called during modeset at which time the GPU should be idle and
1004 * should *not* be performing page flips and thus not waiting on
1005 * vblanks...
1006 * Currently, the result of us stealing a vblank from the irq
1007 * handler is that a single frame will be skipped during swapbuffers.
1008 */
1009 I915_WRITE(pipestat_reg,
1010 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1011
1012 /* Wait for vblank interrupt bit to set */
1013 if (wait_for(I915_READ(pipestat_reg) &
1014 PIPE_VBLANK_INTERRUPT_STATUS,
1015 50))
1016 DRM_DEBUG_KMS("vblank wait timed out\n");
1017 }
1018
1019 /*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
1021 * @dev: drm device
1022 * @pipe: pipe to wait for
1023 *
1024 * After disabling a pipe, we can't wait for vblank in the usual way,
1025 * spinning on the vblank interrupt status bit, since we won't actually
1026 * see an interrupt when the pipe is disabled.
1027 *
1028 * On Gen4 and above:
1029 * wait for the pipe register state bit to turn off
1030 *
1031 * Otherwise:
1032 * wait for the display line value to settle (it usually
1033 * ends up stopping at the start of the next frame).
1034 *
1035 */
1036 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1037 {
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039
1040 if (INTEL_INFO(dev)->gen >= 4) {
1041 int reg = PIPECONF(pipe);
1042
1043 /* Wait for the Pipe State to go off */
1044 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1045 100))
1046 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1047 } else {
1048 u32 last_line;
1049 int reg = PIPEDSL(pipe);
1050 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1051
1052 /* Wait for the display line to settle */
1053 do {
1054 last_line = I915_READ(reg) & DSL_LINEMASK;
1055 mdelay(5);
1056 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1057 time_after(timeout, jiffies));
1058 if (time_after(jiffies, timeout))
1059 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1060 }
1061 }
1062
1063 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1064 {
1065 struct drm_device *dev = crtc->dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 struct drm_framebuffer *fb = crtc->fb;
1068 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1069 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1071 int plane, i;
1072 u32 fbc_ctl, fbc_ctl2;
1073
1074 if (fb->pitch == dev_priv->cfb_pitch &&
1075 obj_priv->fence_reg == dev_priv->cfb_fence &&
1076 intel_crtc->plane == dev_priv->cfb_plane &&
1077 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1078 return;
1079
1080 i8xx_disable_fbc(dev);
1081
1082 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1083
1084 if (fb->pitch < dev_priv->cfb_pitch)
1085 dev_priv->cfb_pitch = fb->pitch;
1086
1087 /* FBC_CTL wants 64B units */
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1092
1093 /* Clear old tags */
1094 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1095 I915_WRITE(FBC_TAG + (i * 4), 0);
1096
1097 /* Set it up... */
1098 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1099 if (obj_priv->tiling_mode != I915_TILING_NONE)
1100 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1101 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1102 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1103
1104 /* enable it... */
1105 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1106 if (IS_I945GM(dev))
1107 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1108 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1109 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1110 if (obj_priv->tiling_mode != I915_TILING_NONE)
1111 fbc_ctl |= dev_priv->cfb_fence;
1112 I915_WRITE(FBC_CONTROL, fbc_ctl);
1113
1114 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1115 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1116 }
1117
1118 void i8xx_disable_fbc(struct drm_device *dev)
1119 {
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1121 u32 fbc_ctl;
1122
1123 /* Disable compression */
1124 fbc_ctl = I915_READ(FBC_CONTROL);
1125 if ((fbc_ctl & FBC_CTL_EN) == 0)
1126 return;
1127
1128 fbc_ctl &= ~FBC_CTL_EN;
1129 I915_WRITE(FBC_CONTROL, fbc_ctl);
1130
1131 /* Wait for compressing bit to clear */
1132 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1133 DRM_DEBUG_KMS("FBC idle timed out\n");
1134 return;
1135 }
1136
1137 DRM_DEBUG_KMS("disabled FBC\n");
1138 }
1139
1140 static bool i8xx_fbc_enabled(struct drm_device *dev)
1141 {
1142 struct drm_i915_private *dev_priv = dev->dev_private;
1143
1144 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1145 }
1146
1147 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1148 {
1149 struct drm_device *dev = crtc->dev;
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 struct drm_framebuffer *fb = crtc->fb;
1152 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1153 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1155 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1156 unsigned long stall_watermark = 200;
1157 u32 dpfc_ctl;
1158
1159 dpfc_ctl = I915_READ(DPFC_CONTROL);
1160 if (dpfc_ctl & DPFC_CTL_EN) {
1161 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1162 dev_priv->cfb_fence == obj_priv->fence_reg &&
1163 dev_priv->cfb_plane == intel_crtc->plane &&
1164 dev_priv->cfb_y == crtc->y)
1165 return;
1166
1167 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1168 POSTING_READ(DPFC_CONTROL);
1169 intel_wait_for_vblank(dev, intel_crtc->pipe);
1170 }
1171
1172 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1173 dev_priv->cfb_fence = obj_priv->fence_reg;
1174 dev_priv->cfb_plane = intel_crtc->plane;
1175 dev_priv->cfb_y = crtc->y;
1176
1177 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1178 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1179 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1180 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1181 } else {
1182 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1183 }
1184
1185 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1186 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1187 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1188 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1189
1190 /* enable it... */
1191 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1192
1193 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1194 }
1195
1196 void g4x_disable_fbc(struct drm_device *dev)
1197 {
1198 struct drm_i915_private *dev_priv = dev->dev_private;
1199 u32 dpfc_ctl;
1200
1201 /* Disable compression */
1202 dpfc_ctl = I915_READ(DPFC_CONTROL);
1203 if (dpfc_ctl & DPFC_CTL_EN) {
1204 dpfc_ctl &= ~DPFC_CTL_EN;
1205 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1206
1207 DRM_DEBUG_KMS("disabled FBC\n");
1208 }
1209 }
1210
1211 static bool g4x_fbc_enabled(struct drm_device *dev)
1212 {
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1216 }
1217
1218 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1219 {
1220 struct drm_device *dev = crtc->dev;
1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 struct drm_framebuffer *fb = crtc->fb;
1223 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1224 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1226 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1227 unsigned long stall_watermark = 200;
1228 u32 dpfc_ctl;
1229
1230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1231 if (dpfc_ctl & DPFC_CTL_EN) {
1232 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1233 dev_priv->cfb_fence == obj_priv->fence_reg &&
1234 dev_priv->cfb_plane == intel_crtc->plane &&
1235 dev_priv->cfb_offset == obj_priv->gtt_offset &&
1236 dev_priv->cfb_y == crtc->y)
1237 return;
1238
1239 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1240 POSTING_READ(ILK_DPFC_CONTROL);
1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
1242 }
1243
1244 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1245 dev_priv->cfb_fence = obj_priv->fence_reg;
1246 dev_priv->cfb_plane = intel_crtc->plane;
1247 dev_priv->cfb_offset = obj_priv->gtt_offset;
1248 dev_priv->cfb_y = crtc->y;
1249
1250 dpfc_ctl &= DPFC_RESERVED;
1251 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1252 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1253 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1254 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1255 } else {
1256 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1257 }
1258
1259 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1260 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1261 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1262 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1263 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1264 /* enable it... */
1265 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1266
1267 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1268 }
1269
1270 void ironlake_disable_fbc(struct drm_device *dev)
1271 {
1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 u32 dpfc_ctl;
1274
1275 /* Disable compression */
1276 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1277 if (dpfc_ctl & DPFC_CTL_EN) {
1278 dpfc_ctl &= ~DPFC_CTL_EN;
1279 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1280
1281 DRM_DEBUG_KMS("disabled FBC\n");
1282 }
1283 }
1284
1285 static bool ironlake_fbc_enabled(struct drm_device *dev)
1286 {
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288
1289 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1290 }
1291
1292 bool intel_fbc_enabled(struct drm_device *dev)
1293 {
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295
1296 if (!dev_priv->display.fbc_enabled)
1297 return false;
1298
1299 return dev_priv->display.fbc_enabled(dev);
1300 }
1301
1302 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1303 {
1304 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1305
1306 if (!dev_priv->display.enable_fbc)
1307 return;
1308
1309 dev_priv->display.enable_fbc(crtc, interval);
1310 }
1311
1312 void intel_disable_fbc(struct drm_device *dev)
1313 {
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315
1316 if (!dev_priv->display.disable_fbc)
1317 return;
1318
1319 dev_priv->display.disable_fbc(dev);
1320 }
1321
1322 /**
1323 * intel_update_fbc - enable/disable FBC as needed
1324 * @dev: the drm_device
1325 *
1326 * Set up the framebuffer compression hardware at mode set time. We
1327 * enable it if possible:
1328 * - plane A only (on pre-965)
1329 * - no pixel mulitply/line duplication
1330 * - no alpha buffer discard
1331 * - no dual wide
1332 * - framebuffer <= 2048 in width, 1536 in height
1333 *
1334 * We can't assume that any compression will take place (worst case),
1335 * so the compressed buffer has to be the same size as the uncompressed
1336 * one. It also must reside (along with the line length buffer) in
1337 * stolen memory.
1338 *
1339 * We need to enable/disable FBC on a global basis.
1340 */
1341 static void intel_update_fbc(struct drm_device *dev)
1342 {
1343 struct drm_i915_private *dev_priv = dev->dev_private;
1344 struct drm_crtc *crtc = NULL, *tmp_crtc;
1345 struct intel_crtc *intel_crtc;
1346 struct drm_framebuffer *fb;
1347 struct intel_framebuffer *intel_fb;
1348 struct drm_i915_gem_object *obj_priv;
1349
1350 DRM_DEBUG_KMS("\n");
1351
1352 if (!i915_powersave)
1353 return;
1354
1355 if (!I915_HAS_FBC(dev))
1356 return;
1357
1358 /*
1359 * If FBC is already on, we just have to verify that we can
1360 * keep it that way...
1361 * Need to disable if:
1362 * - more than one pipe is active
1363 * - changing FBC params (stride, fence, mode)
1364 * - new fb is too large to fit in compressed buffer
1365 * - going to an unsupported config (interlace, pixel multiply, etc.)
1366 */
1367 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1368 if (tmp_crtc->enabled) {
1369 if (crtc) {
1370 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1371 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1372 goto out_disable;
1373 }
1374 crtc = tmp_crtc;
1375 }
1376 }
1377
1378 if (!crtc || crtc->fb == NULL) {
1379 DRM_DEBUG_KMS("no output, disabling\n");
1380 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1381 goto out_disable;
1382 }
1383
1384 intel_crtc = to_intel_crtc(crtc);
1385 fb = crtc->fb;
1386 intel_fb = to_intel_framebuffer(fb);
1387 obj_priv = to_intel_bo(intel_fb->obj);
1388
1389 if (intel_fb->obj->size > dev_priv->cfb_size) {
1390 DRM_DEBUG_KMS("framebuffer too large, disabling "
1391 "compression\n");
1392 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1393 goto out_disable;
1394 }
1395 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1396 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1397 DRM_DEBUG_KMS("mode incompatible with compression, "
1398 "disabling\n");
1399 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1400 goto out_disable;
1401 }
1402 if ((crtc->mode.hdisplay > 2048) ||
1403 (crtc->mode.vdisplay > 1536)) {
1404 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1405 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1406 goto out_disable;
1407 }
1408 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1409 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1410 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1411 goto out_disable;
1412 }
1413 if (obj_priv->tiling_mode != I915_TILING_X) {
1414 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1415 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1416 goto out_disable;
1417 }
1418
1419 /* If the kernel debugger is active, always disable compression */
1420 if (in_dbg_master())
1421 goto out_disable;
1422
1423 intel_enable_fbc(crtc, 500);
1424 return;
1425
1426 out_disable:
1427 /* Multiple disables should be harmless */
1428 if (intel_fbc_enabled(dev)) {
1429 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1430 intel_disable_fbc(dev);
1431 }
1432 }
1433
1434 int
1435 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1436 struct drm_gem_object *obj,
1437 bool pipelined)
1438 {
1439 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1440 u32 alignment;
1441 int ret;
1442
1443 switch (obj_priv->tiling_mode) {
1444 case I915_TILING_NONE:
1445 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1446 alignment = 128 * 1024;
1447 else if (INTEL_INFO(dev)->gen >= 4)
1448 alignment = 4 * 1024;
1449 else
1450 alignment = 64 * 1024;
1451 break;
1452 case I915_TILING_X:
1453 /* pin() will align the object as required by fence */
1454 alignment = 0;
1455 break;
1456 case I915_TILING_Y:
1457 /* FIXME: Is this true? */
1458 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1459 return -EINVAL;
1460 default:
1461 BUG();
1462 }
1463
1464 ret = i915_gem_object_pin(obj, alignment);
1465 if (ret)
1466 return ret;
1467
1468 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1469 if (ret)
1470 goto err_unpin;
1471
1472 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1473 * fence, whereas 965+ only requires a fence if using
1474 * framebuffer compression. For simplicity, we always install
1475 * a fence as the cost is not that onerous.
1476 */
1477 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1478 obj_priv->tiling_mode != I915_TILING_NONE) {
1479 ret = i915_gem_object_get_fence_reg(obj, false);
1480 if (ret)
1481 goto err_unpin;
1482 }
1483
1484 return 0;
1485
1486 err_unpin:
1487 i915_gem_object_unpin(obj);
1488 return ret;
1489 }
1490
1491 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1492 static int
1493 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1494 int x, int y, enum mode_set_atomic state)
1495 {
1496 struct drm_device *dev = crtc->dev;
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1499 struct intel_framebuffer *intel_fb;
1500 struct drm_i915_gem_object *obj_priv;
1501 struct drm_gem_object *obj;
1502 int plane = intel_crtc->plane;
1503 unsigned long Start, Offset;
1504 u32 dspcntr;
1505 u32 reg;
1506
1507 switch (plane) {
1508 case 0:
1509 case 1:
1510 break;
1511 default:
1512 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1513 return -EINVAL;
1514 }
1515
1516 intel_fb = to_intel_framebuffer(fb);
1517 obj = intel_fb->obj;
1518 obj_priv = to_intel_bo(obj);
1519
1520 reg = DSPCNTR(plane);
1521 dspcntr = I915_READ(reg);
1522 /* Mask out pixel format bits in case we change it */
1523 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1524 switch (fb->bits_per_pixel) {
1525 case 8:
1526 dspcntr |= DISPPLANE_8BPP;
1527 break;
1528 case 16:
1529 if (fb->depth == 15)
1530 dspcntr |= DISPPLANE_15_16BPP;
1531 else
1532 dspcntr |= DISPPLANE_16BPP;
1533 break;
1534 case 24:
1535 case 32:
1536 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1537 break;
1538 default:
1539 DRM_ERROR("Unknown color depth\n");
1540 return -EINVAL;
1541 }
1542 if (INTEL_INFO(dev)->gen >= 4) {
1543 if (obj_priv->tiling_mode != I915_TILING_NONE)
1544 dspcntr |= DISPPLANE_TILED;
1545 else
1546 dspcntr &= ~DISPPLANE_TILED;
1547 }
1548
1549 if (HAS_PCH_SPLIT(dev))
1550 /* must disable */
1551 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1552
1553 I915_WRITE(reg, dspcntr);
1554
1555 Start = obj_priv->gtt_offset;
1556 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1557
1558 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1559 Start, Offset, x, y, fb->pitch);
1560 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1561 if (INTEL_INFO(dev)->gen >= 4) {
1562 I915_WRITE(DSPSURF(plane), Start);
1563 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1564 I915_WRITE(DSPADDR(plane), Offset);
1565 } else
1566 I915_WRITE(DSPADDR(plane), Start + Offset);
1567 POSTING_READ(reg);
1568
1569 intel_update_fbc(dev);
1570 intel_increase_pllclock(crtc);
1571
1572 return 0;
1573 }
1574
1575 static int
1576 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1577 struct drm_framebuffer *old_fb)
1578 {
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_i915_master_private *master_priv;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 int ret;
1583
1584 /* no fb bound */
1585 if (!crtc->fb) {
1586 DRM_DEBUG_KMS("No FB bound\n");
1587 return 0;
1588 }
1589
1590 switch (intel_crtc->plane) {
1591 case 0:
1592 case 1:
1593 break;
1594 default:
1595 return -EINVAL;
1596 }
1597
1598 mutex_lock(&dev->struct_mutex);
1599 ret = intel_pin_and_fence_fb_obj(dev,
1600 to_intel_framebuffer(crtc->fb)->obj,
1601 false);
1602 if (ret != 0) {
1603 mutex_unlock(&dev->struct_mutex);
1604 return ret;
1605 }
1606
1607 if (old_fb) {
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 struct drm_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1610 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1611
1612 wait_event(dev_priv->pending_flip_queue,
1613 atomic_read(&obj_priv->pending_flip) == 0);
1614 }
1615
1616 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1617 LEAVE_ATOMIC_MODE_SET);
1618 if (ret) {
1619 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1620 mutex_unlock(&dev->struct_mutex);
1621 return ret;
1622 }
1623
1624 if (old_fb)
1625 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1626
1627 mutex_unlock(&dev->struct_mutex);
1628
1629 if (!dev->primary->master)
1630 return 0;
1631
1632 master_priv = dev->primary->master->driver_priv;
1633 if (!master_priv->sarea_priv)
1634 return 0;
1635
1636 if (intel_crtc->pipe) {
1637 master_priv->sarea_priv->pipeB_x = x;
1638 master_priv->sarea_priv->pipeB_y = y;
1639 } else {
1640 master_priv->sarea_priv->pipeA_x = x;
1641 master_priv->sarea_priv->pipeA_y = y;
1642 }
1643
1644 return 0;
1645 }
1646
1647 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1648 {
1649 struct drm_device *dev = crtc->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 u32 dpa_ctl;
1652
1653 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1654 dpa_ctl = I915_READ(DP_A);
1655 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1656
1657 if (clock < 200000) {
1658 u32 temp;
1659 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1660 /* workaround for 160Mhz:
1661 1) program 0x4600c bits 15:0 = 0x8124
1662 2) program 0x46010 bit 0 = 1
1663 3) program 0x46034 bit 24 = 1
1664 4) program 0x64000 bit 14 = 1
1665 */
1666 temp = I915_READ(0x4600c);
1667 temp &= 0xffff0000;
1668 I915_WRITE(0x4600c, temp | 0x8124);
1669
1670 temp = I915_READ(0x46010);
1671 I915_WRITE(0x46010, temp | 1);
1672
1673 temp = I915_READ(0x46034);
1674 I915_WRITE(0x46034, temp | (1 << 24));
1675 } else {
1676 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1677 }
1678 I915_WRITE(DP_A, dpa_ctl);
1679
1680 POSTING_READ(DP_A);
1681 udelay(500);
1682 }
1683
1684 /* The FDI link training functions for ILK/Ibexpeak. */
1685 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1686 {
1687 struct drm_device *dev = crtc->dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1690 int pipe = intel_crtc->pipe;
1691 u32 reg, temp, tries;
1692
1693 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1694 for train result */
1695 reg = FDI_RX_IMR(pipe);
1696 temp = I915_READ(reg);
1697 temp &= ~FDI_RX_SYMBOL_LOCK;
1698 temp &= ~FDI_RX_BIT_LOCK;
1699 I915_WRITE(reg, temp);
1700 I915_READ(reg);
1701 udelay(150);
1702
1703 /* enable CPU FDI TX and PCH FDI RX */
1704 reg = FDI_TX_CTL(pipe);
1705 temp = I915_READ(reg);
1706 temp &= ~(7 << 19);
1707 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1708 temp &= ~FDI_LINK_TRAIN_NONE;
1709 temp |= FDI_LINK_TRAIN_PATTERN_1;
1710 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1711
1712 reg = FDI_RX_CTL(pipe);
1713 temp = I915_READ(reg);
1714 temp &= ~FDI_LINK_TRAIN_NONE;
1715 temp |= FDI_LINK_TRAIN_PATTERN_1;
1716 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1717
1718 POSTING_READ(reg);
1719 udelay(150);
1720
1721 /* Ironlake workaround, enable clock pointer after FDI enable*/
1722 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1723
1724 reg = FDI_RX_IIR(pipe);
1725 for (tries = 0; tries < 5; tries++) {
1726 temp = I915_READ(reg);
1727 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1728
1729 if ((temp & FDI_RX_BIT_LOCK)) {
1730 DRM_DEBUG_KMS("FDI train 1 done.\n");
1731 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1732 break;
1733 }
1734 }
1735 if (tries == 5)
1736 DRM_ERROR("FDI train 1 fail!\n");
1737
1738 /* Train 2 */
1739 reg = FDI_TX_CTL(pipe);
1740 temp = I915_READ(reg);
1741 temp &= ~FDI_LINK_TRAIN_NONE;
1742 temp |= FDI_LINK_TRAIN_PATTERN_2;
1743 I915_WRITE(reg, temp);
1744
1745 reg = FDI_RX_CTL(pipe);
1746 temp = I915_READ(reg);
1747 temp &= ~FDI_LINK_TRAIN_NONE;
1748 temp |= FDI_LINK_TRAIN_PATTERN_2;
1749 I915_WRITE(reg, temp);
1750
1751 POSTING_READ(reg);
1752 udelay(150);
1753
1754 reg = FDI_RX_IIR(pipe);
1755 for (tries = 0; tries < 5; tries++) {
1756 temp = I915_READ(reg);
1757 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1758
1759 if (temp & FDI_RX_SYMBOL_LOCK) {
1760 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1761 DRM_DEBUG_KMS("FDI train 2 done.\n");
1762 break;
1763 }
1764 }
1765 if (tries == 5)
1766 DRM_ERROR("FDI train 2 fail!\n");
1767
1768 DRM_DEBUG_KMS("FDI train done\n");
1769
1770 /* enable normal train */
1771 reg = FDI_TX_CTL(pipe);
1772 temp = I915_READ(reg);
1773 temp &= ~FDI_LINK_TRAIN_NONE;
1774 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1775 I915_WRITE(reg, temp);
1776
1777 reg = FDI_RX_CTL(pipe);
1778 temp = I915_READ(reg);
1779 if (HAS_PCH_CPT(dev)) {
1780 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1781 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1782 } else {
1783 temp &= ~FDI_LINK_TRAIN_NONE;
1784 temp |= FDI_LINK_TRAIN_NONE;
1785 }
1786 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1787
1788 /* wait one idle pattern time */
1789 POSTING_READ(reg);
1790 udelay(1000);
1791 }
1792
1793 static const int const snb_b_fdi_train_param [] = {
1794 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1795 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1796 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1797 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1798 };
1799
1800 /* The FDI link training functions for SNB/Cougarpoint. */
1801 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1802 {
1803 struct drm_device *dev = crtc->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 int pipe = intel_crtc->pipe;
1807 u32 reg, temp, i;
1808
1809 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1810 for train result */
1811 reg = FDI_RX_IMR(pipe);
1812 temp = I915_READ(reg);
1813 temp &= ~FDI_RX_SYMBOL_LOCK;
1814 temp &= ~FDI_RX_BIT_LOCK;
1815 I915_WRITE(reg, temp);
1816
1817 POSTING_READ(reg);
1818 udelay(150);
1819
1820 /* enable CPU FDI TX and PCH FDI RX */
1821 reg = FDI_TX_CTL(pipe);
1822 temp = I915_READ(reg);
1823 temp &= ~(7 << 19);
1824 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1825 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_1;
1827 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1828 /* SNB-B */
1829 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1830 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1831
1832 reg = FDI_RX_CTL(pipe);
1833 temp = I915_READ(reg);
1834 if (HAS_PCH_CPT(dev)) {
1835 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1836 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1837 } else {
1838 temp &= ~FDI_LINK_TRAIN_NONE;
1839 temp |= FDI_LINK_TRAIN_PATTERN_1;
1840 }
1841 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1842
1843 POSTING_READ(reg);
1844 udelay(150);
1845
1846 for (i = 0; i < 4; i++ ) {
1847 reg = FDI_TX_CTL(pipe);
1848 temp = I915_READ(reg);
1849 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1850 temp |= snb_b_fdi_train_param[i];
1851 I915_WRITE(reg, temp);
1852
1853 POSTING_READ(reg);
1854 udelay(500);
1855
1856 reg = FDI_RX_IIR(pipe);
1857 temp = I915_READ(reg);
1858 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1859
1860 if (temp & FDI_RX_BIT_LOCK) {
1861 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1862 DRM_DEBUG_KMS("FDI train 1 done.\n");
1863 break;
1864 }
1865 }
1866 if (i == 4)
1867 DRM_ERROR("FDI train 1 fail!\n");
1868
1869 /* Train 2 */
1870 reg = FDI_TX_CTL(pipe);
1871 temp = I915_READ(reg);
1872 temp &= ~FDI_LINK_TRAIN_NONE;
1873 temp |= FDI_LINK_TRAIN_PATTERN_2;
1874 if (IS_GEN6(dev)) {
1875 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1876 /* SNB-B */
1877 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1878 }
1879 I915_WRITE(reg, temp);
1880
1881 reg = FDI_RX_CTL(pipe);
1882 temp = I915_READ(reg);
1883 if (HAS_PCH_CPT(dev)) {
1884 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1885 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1886 } else {
1887 temp &= ~FDI_LINK_TRAIN_NONE;
1888 temp |= FDI_LINK_TRAIN_PATTERN_2;
1889 }
1890 I915_WRITE(reg, temp);
1891
1892 POSTING_READ(reg);
1893 udelay(150);
1894
1895 for (i = 0; i < 4; i++ ) {
1896 reg = FDI_TX_CTL(pipe);
1897 temp = I915_READ(reg);
1898 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1899 temp |= snb_b_fdi_train_param[i];
1900 I915_WRITE(reg, temp);
1901
1902 POSTING_READ(reg);
1903 udelay(500);
1904
1905 reg = FDI_RX_IIR(pipe);
1906 temp = I915_READ(reg);
1907 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1908
1909 if (temp & FDI_RX_SYMBOL_LOCK) {
1910 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1911 DRM_DEBUG_KMS("FDI train 2 done.\n");
1912 break;
1913 }
1914 }
1915 if (i == 4)
1916 DRM_ERROR("FDI train 2 fail!\n");
1917
1918 DRM_DEBUG_KMS("FDI train done.\n");
1919 }
1920
1921 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1922 {
1923 struct drm_device *dev = crtc->dev;
1924 struct drm_i915_private *dev_priv = dev->dev_private;
1925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1926 int pipe = intel_crtc->pipe;
1927 u32 reg, temp;
1928
1929 /* Write the TU size bits so error detection works */
1930 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1931 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1932
1933 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1934 reg = FDI_RX_CTL(pipe);
1935 temp = I915_READ(reg);
1936 temp &= ~((0x7 << 19) | (0x7 << 16));
1937 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1938 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1939 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1940
1941 POSTING_READ(reg);
1942 udelay(200);
1943
1944 /* Switch from Rawclk to PCDclk */
1945 temp = I915_READ(reg);
1946 I915_WRITE(reg, temp | FDI_PCDCLK);
1947
1948 POSTING_READ(reg);
1949 udelay(200);
1950
1951 /* Enable CPU FDI TX PLL, always on for Ironlake */
1952 reg = FDI_TX_CTL(pipe);
1953 temp = I915_READ(reg);
1954 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1955 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1956
1957 POSTING_READ(reg);
1958 udelay(100);
1959 }
1960 }
1961
1962 static void intel_flush_display_plane(struct drm_device *dev,
1963 int plane)
1964 {
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 u32 reg = DSPADDR(plane);
1967 I915_WRITE(reg, I915_READ(reg));
1968 }
1969
1970 /*
1971 * When we disable a pipe, we need to clear any pending scanline wait events
1972 * to avoid hanging the ring, which we assume we are waiting on.
1973 */
1974 static void intel_clear_scanline_wait(struct drm_device *dev)
1975 {
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 u32 tmp;
1978
1979 if (IS_GEN2(dev))
1980 /* Can't break the hang on i8xx */
1981 return;
1982
1983 tmp = I915_READ(PRB0_CTL);
1984 if (tmp & RING_WAIT) {
1985 I915_WRITE(PRB0_CTL, tmp);
1986 POSTING_READ(PRB0_CTL);
1987 }
1988 }
1989
1990 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
1991 {
1992 struct drm_i915_gem_object *obj_priv;
1993 struct drm_i915_private *dev_priv;
1994
1995 if (crtc->fb == NULL)
1996 return;
1997
1998 obj_priv = to_intel_bo(to_intel_framebuffer(crtc->fb)->obj);
1999 dev_priv = crtc->dev->dev_private;
2000 wait_event(dev_priv->pending_flip_queue,
2001 atomic_read(&obj_priv->pending_flip) == 0);
2002 }
2003
2004 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2005 {
2006 struct drm_device *dev = crtc->dev;
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2009 int pipe = intel_crtc->pipe;
2010 int plane = intel_crtc->plane;
2011 u32 reg, temp;
2012
2013 if (intel_crtc->active)
2014 return;
2015
2016 intel_crtc->active = true;
2017 intel_update_watermarks(dev);
2018
2019 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2020 temp = I915_READ(PCH_LVDS);
2021 if ((temp & LVDS_PORT_EN) == 0)
2022 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2023 }
2024
2025 ironlake_fdi_enable(crtc);
2026
2027 /* Enable panel fitting for LVDS */
2028 if (dev_priv->pch_pf_size &&
2029 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2030 /* Force use of hard-coded filter coefficients
2031 * as some pre-programmed values are broken,
2032 * e.g. x201.
2033 */
2034 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2035 PF_ENABLE | PF_FILTER_MED_3x3);
2036 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2037 dev_priv->pch_pf_pos);
2038 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2039 dev_priv->pch_pf_size);
2040 }
2041
2042 /* Enable CPU pipe */
2043 reg = PIPECONF(pipe);
2044 temp = I915_READ(reg);
2045 if ((temp & PIPECONF_ENABLE) == 0) {
2046 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2047 POSTING_READ(reg);
2048 intel_wait_for_vblank(dev, intel_crtc->pipe);
2049 }
2050
2051 /* configure and enable CPU plane */
2052 reg = DSPCNTR(plane);
2053 temp = I915_READ(reg);
2054 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2055 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2056 intel_flush_display_plane(dev, plane);
2057 }
2058
2059 /* For PCH output, training FDI link */
2060 if (IS_GEN6(dev))
2061 gen6_fdi_link_train(crtc);
2062 else
2063 ironlake_fdi_link_train(crtc);
2064
2065 /* enable PCH DPLL */
2066 reg = PCH_DPLL(pipe);
2067 temp = I915_READ(reg);
2068 if ((temp & DPLL_VCO_ENABLE) == 0) {
2069 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2070 POSTING_READ(reg);
2071 udelay(200);
2072 }
2073
2074 if (HAS_PCH_CPT(dev)) {
2075 /* Be sure PCH DPLL SEL is set */
2076 temp = I915_READ(PCH_DPLL_SEL);
2077 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2078 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2079 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2080 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2081 I915_WRITE(PCH_DPLL_SEL, temp);
2082 }
2083
2084 /* set transcoder timing */
2085 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2086 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2087 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2088
2089 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2090 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2091 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2092
2093 /* For PCH DP, enable TRANS_DP_CTL */
2094 if (HAS_PCH_CPT(dev) &&
2095 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2096 reg = TRANS_DP_CTL(pipe);
2097 temp = I915_READ(reg);
2098 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2099 TRANS_DP_SYNC_MASK);
2100 temp |= (TRANS_DP_OUTPUT_ENABLE |
2101 TRANS_DP_ENH_FRAMING);
2102
2103 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2104 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2105 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2106 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2107
2108 switch (intel_trans_dp_port_sel(crtc)) {
2109 case PCH_DP_B:
2110 temp |= TRANS_DP_PORT_SEL_B;
2111 break;
2112 case PCH_DP_C:
2113 temp |= TRANS_DP_PORT_SEL_C;
2114 break;
2115 case PCH_DP_D:
2116 temp |= TRANS_DP_PORT_SEL_D;
2117 break;
2118 default:
2119 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2120 temp |= TRANS_DP_PORT_SEL_B;
2121 break;
2122 }
2123
2124 I915_WRITE(reg, temp);
2125 }
2126
2127 /* enable PCH transcoder */
2128 reg = TRANSCONF(pipe);
2129 temp = I915_READ(reg);
2130 /*
2131 * make the BPC in transcoder be consistent with
2132 * that in pipeconf reg.
2133 */
2134 temp &= ~PIPE_BPC_MASK;
2135 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2136 I915_WRITE(reg, temp | TRANS_ENABLE);
2137 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2138 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2139
2140 intel_crtc_load_lut(crtc);
2141 intel_update_fbc(dev);
2142 intel_crtc_update_cursor(crtc, true);
2143 }
2144
2145 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2146 {
2147 struct drm_device *dev = crtc->dev;
2148 struct drm_i915_private *dev_priv = dev->dev_private;
2149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150 int pipe = intel_crtc->pipe;
2151 int plane = intel_crtc->plane;
2152 u32 reg, temp;
2153
2154 if (!intel_crtc->active)
2155 return;
2156
2157 intel_crtc_wait_for_pending_flips(crtc);
2158 drm_vblank_off(dev, pipe);
2159 intel_crtc_update_cursor(crtc, false);
2160
2161 /* Disable display plane */
2162 reg = DSPCNTR(plane);
2163 temp = I915_READ(reg);
2164 if (temp & DISPLAY_PLANE_ENABLE) {
2165 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2166 intel_flush_display_plane(dev, plane);
2167 }
2168
2169 if (dev_priv->cfb_plane == plane &&
2170 dev_priv->display.disable_fbc)
2171 dev_priv->display.disable_fbc(dev);
2172
2173 /* disable cpu pipe, disable after all planes disabled */
2174 reg = PIPECONF(pipe);
2175 temp = I915_READ(reg);
2176 if (temp & PIPECONF_ENABLE) {
2177 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2178 POSTING_READ(reg);
2179 /* wait for cpu pipe off, pipe state */
2180 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2181 }
2182
2183 /* Disable PF */
2184 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2185 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2186
2187 /* disable CPU FDI tx and PCH FDI rx */
2188 reg = FDI_TX_CTL(pipe);
2189 temp = I915_READ(reg);
2190 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2191 POSTING_READ(reg);
2192
2193 reg = FDI_RX_CTL(pipe);
2194 temp = I915_READ(reg);
2195 temp &= ~(0x7 << 16);
2196 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2197 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2198
2199 POSTING_READ(reg);
2200 udelay(100);
2201
2202 /* Ironlake workaround, disable clock pointer after downing FDI */
2203 I915_WRITE(FDI_RX_CHICKEN(pipe),
2204 I915_READ(FDI_RX_CHICKEN(pipe) &
2205 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2206
2207 /* still set train pattern 1 */
2208 reg = FDI_TX_CTL(pipe);
2209 temp = I915_READ(reg);
2210 temp &= ~FDI_LINK_TRAIN_NONE;
2211 temp |= FDI_LINK_TRAIN_PATTERN_1;
2212 I915_WRITE(reg, temp);
2213
2214 reg = FDI_RX_CTL(pipe);
2215 temp = I915_READ(reg);
2216 if (HAS_PCH_CPT(dev)) {
2217 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2218 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2219 } else {
2220 temp &= ~FDI_LINK_TRAIN_NONE;
2221 temp |= FDI_LINK_TRAIN_PATTERN_1;
2222 }
2223 /* BPC in FDI rx is consistent with that in PIPECONF */
2224 temp &= ~(0x07 << 16);
2225 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2226 I915_WRITE(reg, temp);
2227
2228 POSTING_READ(reg);
2229 udelay(100);
2230
2231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2232 temp = I915_READ(PCH_LVDS);
2233 if (temp & LVDS_PORT_EN) {
2234 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2235 POSTING_READ(PCH_LVDS);
2236 udelay(100);
2237 }
2238 }
2239
2240 /* disable PCH transcoder */
2241 reg = TRANSCONF(plane);
2242 temp = I915_READ(reg);
2243 if (temp & TRANS_ENABLE) {
2244 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2245 /* wait for PCH transcoder off, transcoder state */
2246 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2247 DRM_ERROR("failed to disable transcoder\n");
2248 }
2249
2250 if (HAS_PCH_CPT(dev)) {
2251 /* disable TRANS_DP_CTL */
2252 reg = TRANS_DP_CTL(pipe);
2253 temp = I915_READ(reg);
2254 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2255 I915_WRITE(reg, temp);
2256
2257 /* disable DPLL_SEL */
2258 temp = I915_READ(PCH_DPLL_SEL);
2259 if (pipe == 0)
2260 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2261 else
2262 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2263 I915_WRITE(PCH_DPLL_SEL, temp);
2264 }
2265
2266 /* disable PCH DPLL */
2267 reg = PCH_DPLL(pipe);
2268 temp = I915_READ(reg);
2269 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2270
2271 /* Switch from PCDclk to Rawclk */
2272 reg = FDI_RX_CTL(pipe);
2273 temp = I915_READ(reg);
2274 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2275
2276 /* Disable CPU FDI TX PLL */
2277 reg = FDI_TX_CTL(pipe);
2278 temp = I915_READ(reg);
2279 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2280
2281 POSTING_READ(reg);
2282 udelay(100);
2283
2284 reg = FDI_RX_CTL(pipe);
2285 temp = I915_READ(reg);
2286 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2287
2288 /* Wait for the clocks to turn off. */
2289 POSTING_READ(reg);
2290 udelay(100);
2291
2292 intel_crtc->active = false;
2293 intel_update_watermarks(dev);
2294 intel_update_fbc(dev);
2295 intel_clear_scanline_wait(dev);
2296 }
2297
2298 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2299 {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 int pipe = intel_crtc->pipe;
2302 int plane = intel_crtc->plane;
2303
2304 /* XXX: When our outputs are all unaware of DPMS modes other than off
2305 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2306 */
2307 switch (mode) {
2308 case DRM_MODE_DPMS_ON:
2309 case DRM_MODE_DPMS_STANDBY:
2310 case DRM_MODE_DPMS_SUSPEND:
2311 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2312 ironlake_crtc_enable(crtc);
2313 break;
2314
2315 case DRM_MODE_DPMS_OFF:
2316 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2317 ironlake_crtc_disable(crtc);
2318 break;
2319 }
2320 }
2321
2322 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2323 {
2324 if (!enable && intel_crtc->overlay) {
2325 struct drm_device *dev = intel_crtc->base.dev;
2326
2327 mutex_lock(&dev->struct_mutex);
2328 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2329 mutex_unlock(&dev->struct_mutex);
2330 }
2331
2332 /* Let userspace switch the overlay on again. In most cases userspace
2333 * has to recompute where to put it anyway.
2334 */
2335 }
2336
2337 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2338 {
2339 struct drm_device *dev = crtc->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2342 int pipe = intel_crtc->pipe;
2343 int plane = intel_crtc->plane;
2344 u32 reg, temp;
2345
2346 if (intel_crtc->active)
2347 return;
2348
2349 intel_crtc->active = true;
2350 intel_update_watermarks(dev);
2351
2352 /* Enable the DPLL */
2353 reg = DPLL(pipe);
2354 temp = I915_READ(reg);
2355 if ((temp & DPLL_VCO_ENABLE) == 0) {
2356 I915_WRITE(reg, temp);
2357
2358 /* Wait for the clocks to stabilize. */
2359 POSTING_READ(reg);
2360 udelay(150);
2361
2362 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2363
2364 /* Wait for the clocks to stabilize. */
2365 POSTING_READ(reg);
2366 udelay(150);
2367
2368 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2369
2370 /* Wait for the clocks to stabilize. */
2371 POSTING_READ(reg);
2372 udelay(150);
2373 }
2374
2375 /* Enable the pipe */
2376 reg = PIPECONF(pipe);
2377 temp = I915_READ(reg);
2378 if ((temp & PIPECONF_ENABLE) == 0)
2379 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2380
2381 /* Enable the plane */
2382 reg = DSPCNTR(plane);
2383 temp = I915_READ(reg);
2384 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2385 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2386 intel_flush_display_plane(dev, plane);
2387 }
2388
2389 intel_crtc_load_lut(crtc);
2390 intel_update_fbc(dev);
2391
2392 /* Give the overlay scaler a chance to enable if it's on this pipe */
2393 intel_crtc_dpms_overlay(intel_crtc, true);
2394 intel_crtc_update_cursor(crtc, true);
2395 }
2396
2397 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2398 {
2399 struct drm_device *dev = crtc->dev;
2400 struct drm_i915_private *dev_priv = dev->dev_private;
2401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2402 int pipe = intel_crtc->pipe;
2403 int plane = intel_crtc->plane;
2404 u32 reg, temp;
2405
2406 if (!intel_crtc->active)
2407 return;
2408
2409 /* Give the overlay scaler a chance to disable if it's on this pipe */
2410 intel_crtc_wait_for_pending_flips(crtc);
2411 drm_vblank_off(dev, pipe);
2412 intel_crtc_dpms_overlay(intel_crtc, false);
2413 intel_crtc_update_cursor(crtc, false);
2414
2415 if (dev_priv->cfb_plane == plane &&
2416 dev_priv->display.disable_fbc)
2417 dev_priv->display.disable_fbc(dev);
2418
2419 /* Disable display plane */
2420 reg = DSPCNTR(plane);
2421 temp = I915_READ(reg);
2422 if (temp & DISPLAY_PLANE_ENABLE) {
2423 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2424 /* Flush the plane changes */
2425 intel_flush_display_plane(dev, plane);
2426
2427 /* Wait for vblank for the disable to take effect */
2428 if (IS_GEN2(dev))
2429 intel_wait_for_vblank(dev, pipe);
2430 }
2431
2432 /* Don't disable pipe A or pipe A PLLs if needed */
2433 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2434 goto done;
2435
2436 /* Next, disable display pipes */
2437 reg = PIPECONF(pipe);
2438 temp = I915_READ(reg);
2439 if (temp & PIPECONF_ENABLE) {
2440 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2441
2442 /* Wait for the pipe to turn off */
2443 POSTING_READ(reg);
2444 intel_wait_for_pipe_off(dev, pipe);
2445 }
2446
2447 reg = DPLL(pipe);
2448 temp = I915_READ(reg);
2449 if (temp & DPLL_VCO_ENABLE) {
2450 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2451
2452 /* Wait for the clocks to turn off. */
2453 POSTING_READ(reg);
2454 udelay(150);
2455 }
2456
2457 done:
2458 intel_crtc->active = false;
2459 intel_update_fbc(dev);
2460 intel_update_watermarks(dev);
2461 intel_clear_scanline_wait(dev);
2462 }
2463
2464 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2465 {
2466 /* XXX: When our outputs are all unaware of DPMS modes other than off
2467 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2468 */
2469 switch (mode) {
2470 case DRM_MODE_DPMS_ON:
2471 case DRM_MODE_DPMS_STANDBY:
2472 case DRM_MODE_DPMS_SUSPEND:
2473 i9xx_crtc_enable(crtc);
2474 break;
2475 case DRM_MODE_DPMS_OFF:
2476 i9xx_crtc_disable(crtc);
2477 break;
2478 }
2479 }
2480
2481 /**
2482 * Sets the power management mode of the pipe and plane.
2483 */
2484 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2485 {
2486 struct drm_device *dev = crtc->dev;
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 struct drm_i915_master_private *master_priv;
2489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490 int pipe = intel_crtc->pipe;
2491 bool enabled;
2492
2493 if (intel_crtc->dpms_mode == mode)
2494 return;
2495
2496 intel_crtc->dpms_mode = mode;
2497
2498 dev_priv->display.dpms(crtc, mode);
2499
2500 if (!dev->primary->master)
2501 return;
2502
2503 master_priv = dev->primary->master->driver_priv;
2504 if (!master_priv->sarea_priv)
2505 return;
2506
2507 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2508
2509 switch (pipe) {
2510 case 0:
2511 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2512 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2513 break;
2514 case 1:
2515 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2516 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2517 break;
2518 default:
2519 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2520 break;
2521 }
2522 }
2523
2524 static void intel_crtc_disable(struct drm_crtc *crtc)
2525 {
2526 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2527 struct drm_device *dev = crtc->dev;
2528
2529 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2530
2531 if (crtc->fb) {
2532 mutex_lock(&dev->struct_mutex);
2533 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2534 mutex_unlock(&dev->struct_mutex);
2535 }
2536 }
2537
2538 /* Prepare for a mode set.
2539 *
2540 * Note we could be a lot smarter here. We need to figure out which outputs
2541 * will be enabled, which disabled (in short, how the config will changes)
2542 * and perform the minimum necessary steps to accomplish that, e.g. updating
2543 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2544 * panel fitting is in the proper state, etc.
2545 */
2546 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2547 {
2548 i9xx_crtc_disable(crtc);
2549 }
2550
2551 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2552 {
2553 i9xx_crtc_enable(crtc);
2554 }
2555
2556 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2557 {
2558 ironlake_crtc_disable(crtc);
2559 }
2560
2561 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2562 {
2563 ironlake_crtc_enable(crtc);
2564 }
2565
2566 void intel_encoder_prepare (struct drm_encoder *encoder)
2567 {
2568 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2569 /* lvds has its own version of prepare see intel_lvds_prepare */
2570 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2571 }
2572
2573 void intel_encoder_commit (struct drm_encoder *encoder)
2574 {
2575 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2576 /* lvds has its own version of commit see intel_lvds_commit */
2577 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2578 }
2579
2580 void intel_encoder_destroy(struct drm_encoder *encoder)
2581 {
2582 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2583
2584 drm_encoder_cleanup(encoder);
2585 kfree(intel_encoder);
2586 }
2587
2588 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2589 struct drm_display_mode *mode,
2590 struct drm_display_mode *adjusted_mode)
2591 {
2592 struct drm_device *dev = crtc->dev;
2593
2594 if (HAS_PCH_SPLIT(dev)) {
2595 /* FDI link clock is fixed at 2.7G */
2596 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2597 return false;
2598 }
2599
2600 /* XXX some encoders set the crtcinfo, others don't.
2601 * Obviously we need some form of conflict resolution here...
2602 */
2603 if (adjusted_mode->crtc_htotal == 0)
2604 drm_mode_set_crtcinfo(adjusted_mode, 0);
2605
2606 return true;
2607 }
2608
2609 static int i945_get_display_clock_speed(struct drm_device *dev)
2610 {
2611 return 400000;
2612 }
2613
2614 static int i915_get_display_clock_speed(struct drm_device *dev)
2615 {
2616 return 333000;
2617 }
2618
2619 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2620 {
2621 return 200000;
2622 }
2623
2624 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2625 {
2626 u16 gcfgc = 0;
2627
2628 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2629
2630 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2631 return 133000;
2632 else {
2633 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2634 case GC_DISPLAY_CLOCK_333_MHZ:
2635 return 333000;
2636 default:
2637 case GC_DISPLAY_CLOCK_190_200_MHZ:
2638 return 190000;
2639 }
2640 }
2641 }
2642
2643 static int i865_get_display_clock_speed(struct drm_device *dev)
2644 {
2645 return 266000;
2646 }
2647
2648 static int i855_get_display_clock_speed(struct drm_device *dev)
2649 {
2650 u16 hpllcc = 0;
2651 /* Assume that the hardware is in the high speed state. This
2652 * should be the default.
2653 */
2654 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2655 case GC_CLOCK_133_200:
2656 case GC_CLOCK_100_200:
2657 return 200000;
2658 case GC_CLOCK_166_250:
2659 return 250000;
2660 case GC_CLOCK_100_133:
2661 return 133000;
2662 }
2663
2664 /* Shouldn't happen */
2665 return 0;
2666 }
2667
2668 static int i830_get_display_clock_speed(struct drm_device *dev)
2669 {
2670 return 133000;
2671 }
2672
2673 struct fdi_m_n {
2674 u32 tu;
2675 u32 gmch_m;
2676 u32 gmch_n;
2677 u32 link_m;
2678 u32 link_n;
2679 };
2680
2681 static void
2682 fdi_reduce_ratio(u32 *num, u32 *den)
2683 {
2684 while (*num > 0xffffff || *den > 0xffffff) {
2685 *num >>= 1;
2686 *den >>= 1;
2687 }
2688 }
2689
2690 #define DATA_N 0x800000
2691 #define LINK_N 0x80000
2692
2693 static void
2694 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2695 int link_clock, struct fdi_m_n *m_n)
2696 {
2697 u64 temp;
2698
2699 m_n->tu = 64; /* default size */
2700
2701 temp = (u64) DATA_N * pixel_clock;
2702 temp = div_u64(temp, link_clock);
2703 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2704 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2705 m_n->gmch_n = DATA_N;
2706 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2707
2708 temp = (u64) LINK_N * pixel_clock;
2709 m_n->link_m = div_u64(temp, link_clock);
2710 m_n->link_n = LINK_N;
2711 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2712 }
2713
2714
2715 struct intel_watermark_params {
2716 unsigned long fifo_size;
2717 unsigned long max_wm;
2718 unsigned long default_wm;
2719 unsigned long guard_size;
2720 unsigned long cacheline_size;
2721 };
2722
2723 /* Pineview has different values for various configs */
2724 static struct intel_watermark_params pineview_display_wm = {
2725 PINEVIEW_DISPLAY_FIFO,
2726 PINEVIEW_MAX_WM,
2727 PINEVIEW_DFT_WM,
2728 PINEVIEW_GUARD_WM,
2729 PINEVIEW_FIFO_LINE_SIZE
2730 };
2731 static struct intel_watermark_params pineview_display_hplloff_wm = {
2732 PINEVIEW_DISPLAY_FIFO,
2733 PINEVIEW_MAX_WM,
2734 PINEVIEW_DFT_HPLLOFF_WM,
2735 PINEVIEW_GUARD_WM,
2736 PINEVIEW_FIFO_LINE_SIZE
2737 };
2738 static struct intel_watermark_params pineview_cursor_wm = {
2739 PINEVIEW_CURSOR_FIFO,
2740 PINEVIEW_CURSOR_MAX_WM,
2741 PINEVIEW_CURSOR_DFT_WM,
2742 PINEVIEW_CURSOR_GUARD_WM,
2743 PINEVIEW_FIFO_LINE_SIZE,
2744 };
2745 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2746 PINEVIEW_CURSOR_FIFO,
2747 PINEVIEW_CURSOR_MAX_WM,
2748 PINEVIEW_CURSOR_DFT_WM,
2749 PINEVIEW_CURSOR_GUARD_WM,
2750 PINEVIEW_FIFO_LINE_SIZE
2751 };
2752 static struct intel_watermark_params g4x_wm_info = {
2753 G4X_FIFO_SIZE,
2754 G4X_MAX_WM,
2755 G4X_MAX_WM,
2756 2,
2757 G4X_FIFO_LINE_SIZE,
2758 };
2759 static struct intel_watermark_params g4x_cursor_wm_info = {
2760 I965_CURSOR_FIFO,
2761 I965_CURSOR_MAX_WM,
2762 I965_CURSOR_DFT_WM,
2763 2,
2764 G4X_FIFO_LINE_SIZE,
2765 };
2766 static struct intel_watermark_params i965_cursor_wm_info = {
2767 I965_CURSOR_FIFO,
2768 I965_CURSOR_MAX_WM,
2769 I965_CURSOR_DFT_WM,
2770 2,
2771 I915_FIFO_LINE_SIZE,
2772 };
2773 static struct intel_watermark_params i945_wm_info = {
2774 I945_FIFO_SIZE,
2775 I915_MAX_WM,
2776 1,
2777 2,
2778 I915_FIFO_LINE_SIZE
2779 };
2780 static struct intel_watermark_params i915_wm_info = {
2781 I915_FIFO_SIZE,
2782 I915_MAX_WM,
2783 1,
2784 2,
2785 I915_FIFO_LINE_SIZE
2786 };
2787 static struct intel_watermark_params i855_wm_info = {
2788 I855GM_FIFO_SIZE,
2789 I915_MAX_WM,
2790 1,
2791 2,
2792 I830_FIFO_LINE_SIZE
2793 };
2794 static struct intel_watermark_params i830_wm_info = {
2795 I830_FIFO_SIZE,
2796 I915_MAX_WM,
2797 1,
2798 2,
2799 I830_FIFO_LINE_SIZE
2800 };
2801
2802 static struct intel_watermark_params ironlake_display_wm_info = {
2803 ILK_DISPLAY_FIFO,
2804 ILK_DISPLAY_MAXWM,
2805 ILK_DISPLAY_DFTWM,
2806 2,
2807 ILK_FIFO_LINE_SIZE
2808 };
2809
2810 static struct intel_watermark_params ironlake_cursor_wm_info = {
2811 ILK_CURSOR_FIFO,
2812 ILK_CURSOR_MAXWM,
2813 ILK_CURSOR_DFTWM,
2814 2,
2815 ILK_FIFO_LINE_SIZE
2816 };
2817
2818 static struct intel_watermark_params ironlake_display_srwm_info = {
2819 ILK_DISPLAY_SR_FIFO,
2820 ILK_DISPLAY_MAX_SRWM,
2821 ILK_DISPLAY_DFT_SRWM,
2822 2,
2823 ILK_FIFO_LINE_SIZE
2824 };
2825
2826 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2827 ILK_CURSOR_SR_FIFO,
2828 ILK_CURSOR_MAX_SRWM,
2829 ILK_CURSOR_DFT_SRWM,
2830 2,
2831 ILK_FIFO_LINE_SIZE
2832 };
2833
2834 /**
2835 * intel_calculate_wm - calculate watermark level
2836 * @clock_in_khz: pixel clock
2837 * @wm: chip FIFO params
2838 * @pixel_size: display pixel size
2839 * @latency_ns: memory latency for the platform
2840 *
2841 * Calculate the watermark level (the level at which the display plane will
2842 * start fetching from memory again). Each chip has a different display
2843 * FIFO size and allocation, so the caller needs to figure that out and pass
2844 * in the correct intel_watermark_params structure.
2845 *
2846 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2847 * on the pixel size. When it reaches the watermark level, it'll start
2848 * fetching FIFO line sized based chunks from memory until the FIFO fills
2849 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2850 * will occur, and a display engine hang could result.
2851 */
2852 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2853 struct intel_watermark_params *wm,
2854 int pixel_size,
2855 unsigned long latency_ns)
2856 {
2857 long entries_required, wm_size;
2858
2859 /*
2860 * Note: we need to make sure we don't overflow for various clock &
2861 * latency values.
2862 * clocks go from a few thousand to several hundred thousand.
2863 * latency is usually a few thousand
2864 */
2865 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2866 1000;
2867 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2868
2869 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2870
2871 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2872
2873 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2874
2875 /* Don't promote wm_size to unsigned... */
2876 if (wm_size > (long)wm->max_wm)
2877 wm_size = wm->max_wm;
2878 if (wm_size <= 0)
2879 wm_size = wm->default_wm;
2880 return wm_size;
2881 }
2882
2883 struct cxsr_latency {
2884 int is_desktop;
2885 int is_ddr3;
2886 unsigned long fsb_freq;
2887 unsigned long mem_freq;
2888 unsigned long display_sr;
2889 unsigned long display_hpll_disable;
2890 unsigned long cursor_sr;
2891 unsigned long cursor_hpll_disable;
2892 };
2893
2894 static const struct cxsr_latency cxsr_latency_table[] = {
2895 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2896 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2897 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2898 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2899 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2900
2901 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2902 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2903 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2904 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2905 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2906
2907 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2908 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2909 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2910 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2911 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2912
2913 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2914 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2915 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2916 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2917 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2918
2919 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2920 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2921 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2922 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2923 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2924
2925 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2926 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2927 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2928 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2929 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2930 };
2931
2932 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2933 int is_ddr3,
2934 int fsb,
2935 int mem)
2936 {
2937 const struct cxsr_latency *latency;
2938 int i;
2939
2940 if (fsb == 0 || mem == 0)
2941 return NULL;
2942
2943 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2944 latency = &cxsr_latency_table[i];
2945 if (is_desktop == latency->is_desktop &&
2946 is_ddr3 == latency->is_ddr3 &&
2947 fsb == latency->fsb_freq && mem == latency->mem_freq)
2948 return latency;
2949 }
2950
2951 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2952
2953 return NULL;
2954 }
2955
2956 static void pineview_disable_cxsr(struct drm_device *dev)
2957 {
2958 struct drm_i915_private *dev_priv = dev->dev_private;
2959
2960 /* deactivate cxsr */
2961 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2962 }
2963
2964 /*
2965 * Latency for FIFO fetches is dependent on several factors:
2966 * - memory configuration (speed, channels)
2967 * - chipset
2968 * - current MCH state
2969 * It can be fairly high in some situations, so here we assume a fairly
2970 * pessimal value. It's a tradeoff between extra memory fetches (if we
2971 * set this value too high, the FIFO will fetch frequently to stay full)
2972 * and power consumption (set it too low to save power and we might see
2973 * FIFO underruns and display "flicker").
2974 *
2975 * A value of 5us seems to be a good balance; safe for very low end
2976 * platforms but not overly aggressive on lower latency configs.
2977 */
2978 static const int latency_ns = 5000;
2979
2980 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2981 {
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 uint32_t dsparb = I915_READ(DSPARB);
2984 int size;
2985
2986 size = dsparb & 0x7f;
2987 if (plane)
2988 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2989
2990 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2991 plane ? "B" : "A", size);
2992
2993 return size;
2994 }
2995
2996 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2997 {
2998 struct drm_i915_private *dev_priv = dev->dev_private;
2999 uint32_t dsparb = I915_READ(DSPARB);
3000 int size;
3001
3002 size = dsparb & 0x1ff;
3003 if (plane)
3004 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3005 size >>= 1; /* Convert to cachelines */
3006
3007 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3008 plane ? "B" : "A", size);
3009
3010 return size;
3011 }
3012
3013 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3014 {
3015 struct drm_i915_private *dev_priv = dev->dev_private;
3016 uint32_t dsparb = I915_READ(DSPARB);
3017 int size;
3018
3019 size = dsparb & 0x7f;
3020 size >>= 2; /* Convert to cachelines */
3021
3022 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3023 plane ? "B" : "A",
3024 size);
3025
3026 return size;
3027 }
3028
3029 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3030 {
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 uint32_t dsparb = I915_READ(DSPARB);
3033 int size;
3034
3035 size = dsparb & 0x7f;
3036 size >>= 1; /* Convert to cachelines */
3037
3038 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3039 plane ? "B" : "A", size);
3040
3041 return size;
3042 }
3043
3044 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3045 int planeb_clock, int sr_hdisplay, int unused,
3046 int pixel_size)
3047 {
3048 struct drm_i915_private *dev_priv = dev->dev_private;
3049 const struct cxsr_latency *latency;
3050 u32 reg;
3051 unsigned long wm;
3052 int sr_clock;
3053
3054 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3055 dev_priv->fsb_freq, dev_priv->mem_freq);
3056 if (!latency) {
3057 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3058 pineview_disable_cxsr(dev);
3059 return;
3060 }
3061
3062 if (!planea_clock || !planeb_clock) {
3063 sr_clock = planea_clock ? planea_clock : planeb_clock;
3064
3065 /* Display SR */
3066 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3067 pixel_size, latency->display_sr);
3068 reg = I915_READ(DSPFW1);
3069 reg &= ~DSPFW_SR_MASK;
3070 reg |= wm << DSPFW_SR_SHIFT;
3071 I915_WRITE(DSPFW1, reg);
3072 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3073
3074 /* cursor SR */
3075 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3076 pixel_size, latency->cursor_sr);
3077 reg = I915_READ(DSPFW3);
3078 reg &= ~DSPFW_CURSOR_SR_MASK;
3079 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3080 I915_WRITE(DSPFW3, reg);
3081
3082 /* Display HPLL off SR */
3083 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3084 pixel_size, latency->display_hpll_disable);
3085 reg = I915_READ(DSPFW3);
3086 reg &= ~DSPFW_HPLL_SR_MASK;
3087 reg |= wm & DSPFW_HPLL_SR_MASK;
3088 I915_WRITE(DSPFW3, reg);
3089
3090 /* cursor HPLL off SR */
3091 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3092 pixel_size, latency->cursor_hpll_disable);
3093 reg = I915_READ(DSPFW3);
3094 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3095 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3096 I915_WRITE(DSPFW3, reg);
3097 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3098
3099 /* activate cxsr */
3100 I915_WRITE(DSPFW3,
3101 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3102 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3103 } else {
3104 pineview_disable_cxsr(dev);
3105 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3106 }
3107 }
3108
3109 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3110 int planeb_clock, int sr_hdisplay, int sr_htotal,
3111 int pixel_size)
3112 {
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 int total_size, cacheline_size;
3115 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3116 struct intel_watermark_params planea_params, planeb_params;
3117 unsigned long line_time_us;
3118 int sr_clock, sr_entries = 0, entries_required;
3119
3120 /* Create copies of the base settings for each pipe */
3121 planea_params = planeb_params = g4x_wm_info;
3122
3123 /* Grab a couple of global values before we overwrite them */
3124 total_size = planea_params.fifo_size;
3125 cacheline_size = planea_params.cacheline_size;
3126
3127 /*
3128 * Note: we need to make sure we don't overflow for various clock &
3129 * latency values.
3130 * clocks go from a few thousand to several hundred thousand.
3131 * latency is usually a few thousand
3132 */
3133 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3134 1000;
3135 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3136 planea_wm = entries_required + planea_params.guard_size;
3137
3138 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3139 1000;
3140 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3141 planeb_wm = entries_required + planeb_params.guard_size;
3142
3143 cursora_wm = cursorb_wm = 16;
3144 cursor_sr = 32;
3145
3146 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3147
3148 /* Calc sr entries for one plane configs */
3149 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3150 /* self-refresh has much higher latency */
3151 static const int sr_latency_ns = 12000;
3152
3153 sr_clock = planea_clock ? planea_clock : planeb_clock;
3154 line_time_us = ((sr_htotal * 1000) / sr_clock);
3155
3156 /* Use ns/us then divide to preserve precision */
3157 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3158 pixel_size * sr_hdisplay;
3159 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3160
3161 entries_required = (((sr_latency_ns / line_time_us) +
3162 1000) / 1000) * pixel_size * 64;
3163 entries_required = DIV_ROUND_UP(entries_required,
3164 g4x_cursor_wm_info.cacheline_size);
3165 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3166
3167 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3168 cursor_sr = g4x_cursor_wm_info.max_wm;
3169 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3170 "cursor %d\n", sr_entries, cursor_sr);
3171
3172 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3173 } else {
3174 /* Turn off self refresh if both pipes are enabled */
3175 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3176 & ~FW_BLC_SELF_EN);
3177 }
3178
3179 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3180 planea_wm, planeb_wm, sr_entries);
3181
3182 planea_wm &= 0x3f;
3183 planeb_wm &= 0x3f;
3184
3185 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3186 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3187 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3188 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3189 (cursora_wm << DSPFW_CURSORA_SHIFT));
3190 /* HPLL off in SR has some issues on G4x... disable it */
3191 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3192 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3193 }
3194
3195 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3196 int planeb_clock, int sr_hdisplay, int sr_htotal,
3197 int pixel_size)
3198 {
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 unsigned long line_time_us;
3201 int sr_clock, sr_entries, srwm = 1;
3202 int cursor_sr = 16;
3203
3204 /* Calc sr entries for one plane configs */
3205 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3206 /* self-refresh has much higher latency */
3207 static const int sr_latency_ns = 12000;
3208
3209 sr_clock = planea_clock ? planea_clock : planeb_clock;
3210 line_time_us = ((sr_htotal * 1000) / sr_clock);
3211
3212 /* Use ns/us then divide to preserve precision */
3213 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3214 pixel_size * sr_hdisplay;
3215 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3216 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3217 srwm = I965_FIFO_SIZE - sr_entries;
3218 if (srwm < 0)
3219 srwm = 1;
3220 srwm &= 0x1ff;
3221
3222 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3223 pixel_size * 64;
3224 sr_entries = DIV_ROUND_UP(sr_entries,
3225 i965_cursor_wm_info.cacheline_size);
3226 cursor_sr = i965_cursor_wm_info.fifo_size -
3227 (sr_entries + i965_cursor_wm_info.guard_size);
3228
3229 if (cursor_sr > i965_cursor_wm_info.max_wm)
3230 cursor_sr = i965_cursor_wm_info.max_wm;
3231
3232 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3233 "cursor %d\n", srwm, cursor_sr);
3234
3235 if (IS_CRESTLINE(dev))
3236 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3237 } else {
3238 /* Turn off self refresh if both pipes are enabled */
3239 if (IS_CRESTLINE(dev))
3240 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3241 & ~FW_BLC_SELF_EN);
3242 }
3243
3244 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3245 srwm);
3246
3247 /* 965 has limitations... */
3248 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3249 (8 << 0));
3250 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3251 /* update cursor SR watermark */
3252 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3253 }
3254
3255 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3256 int planeb_clock, int sr_hdisplay, int sr_htotal,
3257 int pixel_size)
3258 {
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260 uint32_t fwater_lo;
3261 uint32_t fwater_hi;
3262 int total_size, cacheline_size, cwm, srwm = 1;
3263 int planea_wm, planeb_wm;
3264 struct intel_watermark_params planea_params, planeb_params;
3265 unsigned long line_time_us;
3266 int sr_clock, sr_entries = 0;
3267
3268 /* Create copies of the base settings for each pipe */
3269 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3270 planea_params = planeb_params = i945_wm_info;
3271 else if (!IS_GEN2(dev))
3272 planea_params = planeb_params = i915_wm_info;
3273 else
3274 planea_params = planeb_params = i855_wm_info;
3275
3276 /* Grab a couple of global values before we overwrite them */
3277 total_size = planea_params.fifo_size;
3278 cacheline_size = planea_params.cacheline_size;
3279
3280 /* Update per-plane FIFO sizes */
3281 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3282 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3283
3284 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3285 pixel_size, latency_ns);
3286 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3287 pixel_size, latency_ns);
3288 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3289
3290 /*
3291 * Overlay gets an aggressive default since video jitter is bad.
3292 */
3293 cwm = 2;
3294
3295 /* Calc sr entries for one plane configs */
3296 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3297 (!planea_clock || !planeb_clock)) {
3298 /* self-refresh has much higher latency */
3299 static const int sr_latency_ns = 6000;
3300
3301 sr_clock = planea_clock ? planea_clock : planeb_clock;
3302 line_time_us = ((sr_htotal * 1000) / sr_clock);
3303
3304 /* Use ns/us then divide to preserve precision */
3305 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3306 pixel_size * sr_hdisplay;
3307 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3308 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3309 srwm = total_size - sr_entries;
3310 if (srwm < 0)
3311 srwm = 1;
3312
3313 if (IS_I945G(dev) || IS_I945GM(dev))
3314 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3315 else if (IS_I915GM(dev)) {
3316 /* 915M has a smaller SRWM field */
3317 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3318 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3319 }
3320 } else {
3321 /* Turn off self refresh if both pipes are enabled */
3322 if (IS_I945G(dev) || IS_I945GM(dev)) {
3323 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3324 & ~FW_BLC_SELF_EN);
3325 } else if (IS_I915GM(dev)) {
3326 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3327 }
3328 }
3329
3330 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3331 planea_wm, planeb_wm, cwm, srwm);
3332
3333 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3334 fwater_hi = (cwm & 0x1f);
3335
3336 /* Set request length to 8 cachelines per fetch */
3337 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3338 fwater_hi = fwater_hi | (1 << 8);
3339
3340 I915_WRITE(FW_BLC, fwater_lo);
3341 I915_WRITE(FW_BLC2, fwater_hi);
3342 }
3343
3344 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3345 int unused2, int unused3, int pixel_size)
3346 {
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3349 int planea_wm;
3350
3351 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3352
3353 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3354 pixel_size, latency_ns);
3355 fwater_lo |= (3<<8) | planea_wm;
3356
3357 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3358
3359 I915_WRITE(FW_BLC, fwater_lo);
3360 }
3361
3362 #define ILK_LP0_PLANE_LATENCY 700
3363 #define ILK_LP0_CURSOR_LATENCY 1300
3364
3365 static bool ironlake_compute_wm0(struct drm_device *dev,
3366 int pipe,
3367 int *plane_wm,
3368 int *cursor_wm)
3369 {
3370 struct drm_crtc *crtc;
3371 int htotal, hdisplay, clock, pixel_size = 0;
3372 int line_time_us, line_count, entries;
3373
3374 crtc = intel_get_crtc_for_pipe(dev, pipe);
3375 if (crtc->fb == NULL || !crtc->enabled)
3376 return false;
3377
3378 htotal = crtc->mode.htotal;
3379 hdisplay = crtc->mode.hdisplay;
3380 clock = crtc->mode.clock;
3381 pixel_size = crtc->fb->bits_per_pixel / 8;
3382
3383 /* Use the small buffer method to calculate plane watermark */
3384 entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3385 entries = DIV_ROUND_UP(entries,
3386 ironlake_display_wm_info.cacheline_size);
3387 *plane_wm = entries + ironlake_display_wm_info.guard_size;
3388 if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3389 *plane_wm = ironlake_display_wm_info.max_wm;
3390
3391 /* Use the large buffer method to calculate cursor watermark */
3392 line_time_us = ((htotal * 1000) / clock);
3393 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3394 entries = line_count * 64 * pixel_size;
3395 entries = DIV_ROUND_UP(entries,
3396 ironlake_cursor_wm_info.cacheline_size);
3397 *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3398 if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3399 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3400
3401 return true;
3402 }
3403
3404 static void ironlake_update_wm(struct drm_device *dev,
3405 int planea_clock, int planeb_clock,
3406 int sr_hdisplay, int sr_htotal,
3407 int pixel_size)
3408 {
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 int plane_wm, cursor_wm, enabled;
3411 int tmp;
3412
3413 enabled = 0;
3414 if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3415 I915_WRITE(WM0_PIPEA_ILK,
3416 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3417 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3418 " plane %d, " "cursor: %d\n",
3419 plane_wm, cursor_wm);
3420 enabled++;
3421 }
3422
3423 if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3424 I915_WRITE(WM0_PIPEB_ILK,
3425 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3426 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3427 " plane %d, cursor: %d\n",
3428 plane_wm, cursor_wm);
3429 enabled++;
3430 }
3431
3432 /*
3433 * Calculate and update the self-refresh watermark only when one
3434 * display plane is used.
3435 */
3436 tmp = 0;
3437 if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3438 unsigned long line_time_us;
3439 int small, large, plane_fbc;
3440 int sr_clock, entries;
3441 int line_count, line_size;
3442 /* Read the self-refresh latency. The unit is 0.5us */
3443 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3444
3445 sr_clock = planea_clock ? planea_clock : planeb_clock;
3446 line_time_us = (sr_htotal * 1000) / sr_clock;
3447
3448 /* Use ns/us then divide to preserve precision */
3449 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3450 / 1000;
3451 line_size = sr_hdisplay * pixel_size;
3452
3453 /* Use the minimum of the small and large buffer method for primary */
3454 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3455 large = line_count * line_size;
3456
3457 entries = DIV_ROUND_UP(min(small, large),
3458 ironlake_display_srwm_info.cacheline_size);
3459
3460 plane_fbc = entries * 64;
3461 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3462
3463 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3464 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3465 plane_wm = ironlake_display_srwm_info.max_wm;
3466
3467 /* calculate the self-refresh watermark for display cursor */
3468 entries = line_count * pixel_size * 64;
3469 entries = DIV_ROUND_UP(entries,
3470 ironlake_cursor_srwm_info.cacheline_size);
3471
3472 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3473 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3474 cursor_wm = ironlake_cursor_srwm_info.max_wm;
3475
3476 /* configure watermark and enable self-refresh */
3477 tmp = (WM1_LP_SR_EN |
3478 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3479 (plane_fbc << WM1_LP_FBC_SHIFT) |
3480 (plane_wm << WM1_LP_SR_SHIFT) |
3481 cursor_wm);
3482 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3483 " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3484 }
3485 I915_WRITE(WM1_LP_ILK, tmp);
3486 /* XXX setup WM2 and WM3 */
3487 }
3488
3489 /**
3490 * intel_update_watermarks - update FIFO watermark values based on current modes
3491 *
3492 * Calculate watermark values for the various WM regs based on current mode
3493 * and plane configuration.
3494 *
3495 * There are several cases to deal with here:
3496 * - normal (i.e. non-self-refresh)
3497 * - self-refresh (SR) mode
3498 * - lines are large relative to FIFO size (buffer can hold up to 2)
3499 * - lines are small relative to FIFO size (buffer can hold more than 2
3500 * lines), so need to account for TLB latency
3501 *
3502 * The normal calculation is:
3503 * watermark = dotclock * bytes per pixel * latency
3504 * where latency is platform & configuration dependent (we assume pessimal
3505 * values here).
3506 *
3507 * The SR calculation is:
3508 * watermark = (trunc(latency/line time)+1) * surface width *
3509 * bytes per pixel
3510 * where
3511 * line time = htotal / dotclock
3512 * surface width = hdisplay for normal plane and 64 for cursor
3513 * and latency is assumed to be high, as above.
3514 *
3515 * The final value programmed to the register should always be rounded up,
3516 * and include an extra 2 entries to account for clock crossings.
3517 *
3518 * We don't use the sprite, so we can ignore that. And on Crestline we have
3519 * to set the non-SR watermarks to 8.
3520 */
3521 static void intel_update_watermarks(struct drm_device *dev)
3522 {
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct drm_crtc *crtc;
3525 int sr_hdisplay = 0;
3526 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3527 int enabled = 0, pixel_size = 0;
3528 int sr_htotal = 0;
3529
3530 if (!dev_priv->display.update_wm)
3531 return;
3532
3533 /* Get the clock config from both planes */
3534 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3536 if (intel_crtc->active) {
3537 enabled++;
3538 if (intel_crtc->plane == 0) {
3539 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3540 intel_crtc->pipe, crtc->mode.clock);
3541 planea_clock = crtc->mode.clock;
3542 } else {
3543 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3544 intel_crtc->pipe, crtc->mode.clock);
3545 planeb_clock = crtc->mode.clock;
3546 }
3547 sr_hdisplay = crtc->mode.hdisplay;
3548 sr_clock = crtc->mode.clock;
3549 sr_htotal = crtc->mode.htotal;
3550 if (crtc->fb)
3551 pixel_size = crtc->fb->bits_per_pixel / 8;
3552 else
3553 pixel_size = 4; /* by default */
3554 }
3555 }
3556
3557 if (enabled <= 0)
3558 return;
3559
3560 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3561 sr_hdisplay, sr_htotal, pixel_size);
3562 }
3563
3564 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3565 struct drm_display_mode *mode,
3566 struct drm_display_mode *adjusted_mode,
3567 int x, int y,
3568 struct drm_framebuffer *old_fb)
3569 {
3570 struct drm_device *dev = crtc->dev;
3571 struct drm_i915_private *dev_priv = dev->dev_private;
3572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3573 int pipe = intel_crtc->pipe;
3574 int plane = intel_crtc->plane;
3575 u32 fp_reg, dpll_reg;
3576 int refclk, num_connectors = 0;
3577 intel_clock_t clock, reduced_clock;
3578 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3579 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3580 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3581 struct intel_encoder *has_edp_encoder = NULL;
3582 struct drm_mode_config *mode_config = &dev->mode_config;
3583 struct intel_encoder *encoder;
3584 const intel_limit_t *limit;
3585 int ret;
3586 struct fdi_m_n m_n = {0};
3587 u32 reg, temp;
3588 int target_clock;
3589
3590 drm_vblank_pre_modeset(dev, pipe);
3591
3592 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3593 if (encoder->base.crtc != crtc)
3594 continue;
3595
3596 switch (encoder->type) {
3597 case INTEL_OUTPUT_LVDS:
3598 is_lvds = true;
3599 break;
3600 case INTEL_OUTPUT_SDVO:
3601 case INTEL_OUTPUT_HDMI:
3602 is_sdvo = true;
3603 if (encoder->needs_tv_clock)
3604 is_tv = true;
3605 break;
3606 case INTEL_OUTPUT_DVO:
3607 is_dvo = true;
3608 break;
3609 case INTEL_OUTPUT_TVOUT:
3610 is_tv = true;
3611 break;
3612 case INTEL_OUTPUT_ANALOG:
3613 is_crt = true;
3614 break;
3615 case INTEL_OUTPUT_DISPLAYPORT:
3616 is_dp = true;
3617 break;
3618 case INTEL_OUTPUT_EDP:
3619 has_edp_encoder = encoder;
3620 break;
3621 }
3622
3623 num_connectors++;
3624 }
3625
3626 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3627 refclk = dev_priv->lvds_ssc_freq * 1000;
3628 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3629 refclk / 1000);
3630 } else if (!IS_GEN2(dev)) {
3631 refclk = 96000;
3632 if (HAS_PCH_SPLIT(dev) &&
3633 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3634 refclk = 120000; /* 120Mhz refclk */
3635 } else {
3636 refclk = 48000;
3637 }
3638
3639 /*
3640 * Returns a set of divisors for the desired target clock with the given
3641 * refclk, or FALSE. The returned values represent the clock equation:
3642 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3643 */
3644 limit = intel_limit(crtc);
3645 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3646 if (!ok) {
3647 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3648 drm_vblank_post_modeset(dev, pipe);
3649 return -EINVAL;
3650 }
3651
3652 /* Ensure that the cursor is valid for the new mode before changing... */
3653 intel_crtc_update_cursor(crtc, true);
3654
3655 if (is_lvds && dev_priv->lvds_downclock_avail) {
3656 has_reduced_clock = limit->find_pll(limit, crtc,
3657 dev_priv->lvds_downclock,
3658 refclk,
3659 &reduced_clock);
3660 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3661 /*
3662 * If the different P is found, it means that we can't
3663 * switch the display clock by using the FP0/FP1.
3664 * In such case we will disable the LVDS downclock
3665 * feature.
3666 */
3667 DRM_DEBUG_KMS("Different P is found for "
3668 "LVDS clock/downclock\n");
3669 has_reduced_clock = 0;
3670 }
3671 }
3672 /* SDVO TV has fixed PLL values depend on its clock range,
3673 this mirrors vbios setting. */
3674 if (is_sdvo && is_tv) {
3675 if (adjusted_mode->clock >= 100000
3676 && adjusted_mode->clock < 140500) {
3677 clock.p1 = 2;
3678 clock.p2 = 10;
3679 clock.n = 3;
3680 clock.m1 = 16;
3681 clock.m2 = 8;
3682 } else if (adjusted_mode->clock >= 140500
3683 && adjusted_mode->clock <= 200000) {
3684 clock.p1 = 1;
3685 clock.p2 = 10;
3686 clock.n = 6;
3687 clock.m1 = 12;
3688 clock.m2 = 8;
3689 }
3690 }
3691
3692 /* FDI link */
3693 if (HAS_PCH_SPLIT(dev)) {
3694 int lane = 0, link_bw, bpp;
3695 /* CPU eDP doesn't require FDI link, so just set DP M/N
3696 according to current link config */
3697 if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) {
3698 target_clock = mode->clock;
3699 intel_edp_link_config(has_edp_encoder,
3700 &lane, &link_bw);
3701 } else {
3702 /* [e]DP over FDI requires target mode clock
3703 instead of link clock */
3704 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3705 target_clock = mode->clock;
3706 else
3707 target_clock = adjusted_mode->clock;
3708
3709 /* FDI is a binary signal running at ~2.7GHz, encoding
3710 * each output octet as 10 bits. The actual frequency
3711 * is stored as a divider into a 100MHz clock, and the
3712 * mode pixel clock is stored in units of 1KHz.
3713 * Hence the bw of each lane in terms of the mode signal
3714 * is:
3715 */
3716 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3717 }
3718
3719 /* determine panel color depth */
3720 temp = I915_READ(PIPECONF(pipe));
3721 temp &= ~PIPE_BPC_MASK;
3722 if (is_lvds) {
3723 /* the BPC will be 6 if it is 18-bit LVDS panel */
3724 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3725 temp |= PIPE_8BPC;
3726 else
3727 temp |= PIPE_6BPC;
3728 } else if (has_edp_encoder) {
3729 switch (dev_priv->edp.bpp/3) {
3730 case 8:
3731 temp |= PIPE_8BPC;
3732 break;
3733 case 10:
3734 temp |= PIPE_10BPC;
3735 break;
3736 case 6:
3737 temp |= PIPE_6BPC;
3738 break;
3739 case 12:
3740 temp |= PIPE_12BPC;
3741 break;
3742 }
3743 } else
3744 temp |= PIPE_8BPC;
3745 I915_WRITE(PIPECONF(pipe), temp);
3746
3747 switch (temp & PIPE_BPC_MASK) {
3748 case PIPE_8BPC:
3749 bpp = 24;
3750 break;
3751 case PIPE_10BPC:
3752 bpp = 30;
3753 break;
3754 case PIPE_6BPC:
3755 bpp = 18;
3756 break;
3757 case PIPE_12BPC:
3758 bpp = 36;
3759 break;
3760 default:
3761 DRM_ERROR("unknown pipe bpc value\n");
3762 bpp = 24;
3763 }
3764
3765 if (!lane) {
3766 /*
3767 * Account for spread spectrum to avoid
3768 * oversubscribing the link. Max center spread
3769 * is 2.5%; use 5% for safety's sake.
3770 */
3771 u32 bps = target_clock * bpp * 21 / 20;
3772 lane = bps / (link_bw * 8) + 1;
3773 }
3774
3775 intel_crtc->fdi_lanes = lane;
3776
3777 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3778 }
3779
3780 /* Ironlake: try to setup display ref clock before DPLL
3781 * enabling. This is only under driver's control after
3782 * PCH B stepping, previous chipset stepping should be
3783 * ignoring this setting.
3784 */
3785 if (HAS_PCH_SPLIT(dev)) {
3786 temp = I915_READ(PCH_DREF_CONTROL);
3787 /* Always enable nonspread source */
3788 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3789 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3790 temp &= ~DREF_SSC_SOURCE_MASK;
3791 temp |= DREF_SSC_SOURCE_ENABLE;
3792 I915_WRITE(PCH_DREF_CONTROL, temp);
3793
3794 POSTING_READ(PCH_DREF_CONTROL);
3795 udelay(200);
3796
3797 if (has_edp_encoder) {
3798 if (dev_priv->lvds_use_ssc) {
3799 temp |= DREF_SSC1_ENABLE;
3800 I915_WRITE(PCH_DREF_CONTROL, temp);
3801
3802 POSTING_READ(PCH_DREF_CONTROL);
3803 udelay(200);
3804 }
3805 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3806
3807 /* Enable CPU source on CPU attached eDP */
3808 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3809 if (dev_priv->lvds_use_ssc)
3810 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3811 else
3812 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3813 } else {
3814 /* Enable SSC on PCH eDP if needed */
3815 if (dev_priv->lvds_use_ssc) {
3816 DRM_ERROR("enabling SSC on PCH\n");
3817 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
3818 }
3819 }
3820 I915_WRITE(PCH_DREF_CONTROL, temp);
3821 POSTING_READ(PCH_DREF_CONTROL);
3822 udelay(200);
3823 }
3824 }
3825
3826 if (IS_PINEVIEW(dev)) {
3827 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3828 if (has_reduced_clock)
3829 fp2 = (1 << reduced_clock.n) << 16 |
3830 reduced_clock.m1 << 8 | reduced_clock.m2;
3831 } else {
3832 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3833 if (has_reduced_clock)
3834 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3835 reduced_clock.m2;
3836 }
3837
3838 dpll = 0;
3839 if (!HAS_PCH_SPLIT(dev))
3840 dpll = DPLL_VGA_MODE_DIS;
3841
3842 if (!IS_GEN2(dev)) {
3843 if (is_lvds)
3844 dpll |= DPLLB_MODE_LVDS;
3845 else
3846 dpll |= DPLLB_MODE_DAC_SERIAL;
3847 if (is_sdvo) {
3848 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3849 if (pixel_multiplier > 1) {
3850 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3851 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3852 else if (HAS_PCH_SPLIT(dev))
3853 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3854 }
3855 dpll |= DPLL_DVO_HIGH_SPEED;
3856 }
3857 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3858 dpll |= DPLL_DVO_HIGH_SPEED;
3859
3860 /* compute bitmask from p1 value */
3861 if (IS_PINEVIEW(dev))
3862 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3863 else {
3864 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3865 /* also FPA1 */
3866 if (HAS_PCH_SPLIT(dev))
3867 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3868 if (IS_G4X(dev) && has_reduced_clock)
3869 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3870 }
3871 switch (clock.p2) {
3872 case 5:
3873 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3874 break;
3875 case 7:
3876 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3877 break;
3878 case 10:
3879 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3880 break;
3881 case 14:
3882 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3883 break;
3884 }
3885 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
3886 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3887 } else {
3888 if (is_lvds) {
3889 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3890 } else {
3891 if (clock.p1 == 2)
3892 dpll |= PLL_P1_DIVIDE_BY_TWO;
3893 else
3894 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3895 if (clock.p2 == 4)
3896 dpll |= PLL_P2_DIVIDE_BY_4;
3897 }
3898 }
3899
3900 if (is_sdvo && is_tv)
3901 dpll |= PLL_REF_INPUT_TVCLKINBC;
3902 else if (is_tv)
3903 /* XXX: just matching BIOS for now */
3904 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3905 dpll |= 3;
3906 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3907 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3908 else
3909 dpll |= PLL_REF_INPUT_DREFCLK;
3910
3911 /* setup pipeconf */
3912 pipeconf = I915_READ(PIPECONF(pipe));
3913
3914 /* Set up the display plane register */
3915 dspcntr = DISPPLANE_GAMMA_ENABLE;
3916
3917 /* Ironlake's plane is forced to pipe, bit 24 is to
3918 enable color space conversion */
3919 if (!HAS_PCH_SPLIT(dev)) {
3920 if (pipe == 0)
3921 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3922 else
3923 dspcntr |= DISPPLANE_SEL_PIPE_B;
3924 }
3925
3926 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3927 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3928 * core speed.
3929 *
3930 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3931 * pipe == 0 check?
3932 */
3933 if (mode->clock >
3934 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3935 pipeconf |= PIPECONF_DOUBLE_WIDE;
3936 else
3937 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3938 }
3939
3940 dspcntr |= DISPLAY_PLANE_ENABLE;
3941 pipeconf |= PIPECONF_ENABLE;
3942 dpll |= DPLL_VCO_ENABLE;
3943
3944 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3945 drm_mode_debug_printmodeline(mode);
3946
3947 /* assign to Ironlake registers */
3948 if (HAS_PCH_SPLIT(dev)) {
3949 fp_reg = PCH_FP0(pipe);
3950 dpll_reg = PCH_DPLL(pipe);
3951 } else {
3952 fp_reg = FP0(pipe);
3953 dpll_reg = DPLL(pipe);
3954 }
3955
3956 /* PCH eDP needs FDI, but CPU eDP does not */
3957 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3958 I915_WRITE(fp_reg, fp);
3959 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3960
3961 POSTING_READ(dpll_reg);
3962 udelay(150);
3963 }
3964
3965 /* enable transcoder DPLL */
3966 if (HAS_PCH_CPT(dev)) {
3967 temp = I915_READ(PCH_DPLL_SEL);
3968 if (pipe == 0)
3969 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3970 else
3971 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3972 I915_WRITE(PCH_DPLL_SEL, temp);
3973
3974 POSTING_READ(PCH_DPLL_SEL);
3975 udelay(150);
3976 }
3977
3978 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3979 * This is an exception to the general rule that mode_set doesn't turn
3980 * things on.
3981 */
3982 if (is_lvds) {
3983 reg = LVDS;
3984 if (HAS_PCH_SPLIT(dev))
3985 reg = PCH_LVDS;
3986
3987 temp = I915_READ(reg);
3988 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3989 if (pipe == 1) {
3990 if (HAS_PCH_CPT(dev))
3991 temp |= PORT_TRANS_B_SEL_CPT;
3992 else
3993 temp |= LVDS_PIPEB_SELECT;
3994 } else {
3995 if (HAS_PCH_CPT(dev))
3996 temp &= ~PORT_TRANS_SEL_MASK;
3997 else
3998 temp &= ~LVDS_PIPEB_SELECT;
3999 }
4000 /* set the corresponsding LVDS_BORDER bit */
4001 temp |= dev_priv->lvds_border_bits;
4002 /* Set the B0-B3 data pairs corresponding to whether we're going to
4003 * set the DPLLs for dual-channel mode or not.
4004 */
4005 if (clock.p2 == 7)
4006 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4007 else
4008 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4009
4010 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4011 * appropriately here, but we need to look more thoroughly into how
4012 * panels behave in the two modes.
4013 */
4014 /* set the dithering flag on non-PCH LVDS as needed */
4015 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4016 if (dev_priv->lvds_dither)
4017 temp |= LVDS_ENABLE_DITHER;
4018 else
4019 temp &= ~LVDS_ENABLE_DITHER;
4020 }
4021 I915_WRITE(reg, temp);
4022 }
4023
4024 /* set the dithering flag and clear for anything other than a panel. */
4025 if (HAS_PCH_SPLIT(dev)) {
4026 pipeconf &= ~PIPECONF_DITHER_EN;
4027 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4028 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4029 pipeconf |= PIPECONF_DITHER_EN;
4030 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4031 }
4032 }
4033
4034 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4035 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4036 } else if (HAS_PCH_SPLIT(dev)) {
4037 /* For non-DP output, clear any trans DP clock recovery setting.*/
4038 if (pipe == 0) {
4039 I915_WRITE(TRANSA_DATA_M1, 0);
4040 I915_WRITE(TRANSA_DATA_N1, 0);
4041 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4042 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4043 } else {
4044 I915_WRITE(TRANSB_DATA_M1, 0);
4045 I915_WRITE(TRANSB_DATA_N1, 0);
4046 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4047 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4048 }
4049 }
4050
4051 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4052 I915_WRITE(fp_reg, fp);
4053 I915_WRITE(dpll_reg, dpll);
4054
4055 /* Wait for the clocks to stabilize. */
4056 POSTING_READ(dpll_reg);
4057 udelay(150);
4058
4059 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4060 temp = 0;
4061 if (is_sdvo) {
4062 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4063 if (temp > 1)
4064 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4065 else
4066 temp = 0;
4067 }
4068 I915_WRITE(DPLL_MD(pipe), temp);
4069 } else {
4070 /* write it again -- the BIOS does, after all */
4071 I915_WRITE(dpll_reg, dpll);
4072 }
4073
4074 /* Wait for the clocks to stabilize. */
4075 POSTING_READ(dpll_reg);
4076 udelay(150);
4077 }
4078
4079 intel_crtc->lowfreq_avail = false;
4080 if (is_lvds && has_reduced_clock && i915_powersave) {
4081 I915_WRITE(fp_reg + 4, fp2);
4082 intel_crtc->lowfreq_avail = true;
4083 if (HAS_PIPE_CXSR(dev)) {
4084 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4085 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4086 }
4087 } else {
4088 I915_WRITE(fp_reg + 4, fp);
4089 if (HAS_PIPE_CXSR(dev)) {
4090 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4091 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4092 }
4093 }
4094
4095 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4096 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4097 /* the chip adds 2 halflines automatically */
4098 adjusted_mode->crtc_vdisplay -= 1;
4099 adjusted_mode->crtc_vtotal -= 1;
4100 adjusted_mode->crtc_vblank_start -= 1;
4101 adjusted_mode->crtc_vblank_end -= 1;
4102 adjusted_mode->crtc_vsync_end -= 1;
4103 adjusted_mode->crtc_vsync_start -= 1;
4104 } else
4105 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4106
4107 I915_WRITE(HTOTAL(pipe),
4108 (adjusted_mode->crtc_hdisplay - 1) |
4109 ((adjusted_mode->crtc_htotal - 1) << 16));
4110 I915_WRITE(HBLANK(pipe),
4111 (adjusted_mode->crtc_hblank_start - 1) |
4112 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4113 I915_WRITE(HSYNC(pipe),
4114 (adjusted_mode->crtc_hsync_start - 1) |
4115 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4116
4117 I915_WRITE(VTOTAL(pipe),
4118 (adjusted_mode->crtc_vdisplay - 1) |
4119 ((adjusted_mode->crtc_vtotal - 1) << 16));
4120 I915_WRITE(VBLANK(pipe),
4121 (adjusted_mode->crtc_vblank_start - 1) |
4122 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4123 I915_WRITE(VSYNC(pipe),
4124 (adjusted_mode->crtc_vsync_start - 1) |
4125 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4126
4127 /* pipesrc and dspsize control the size that is scaled from,
4128 * which should always be the user's requested size.
4129 */
4130 if (!HAS_PCH_SPLIT(dev)) {
4131 I915_WRITE(DSPSIZE(plane),
4132 ((mode->vdisplay - 1) << 16) |
4133 (mode->hdisplay - 1));
4134 I915_WRITE(DSPPOS(plane), 0);
4135 }
4136 I915_WRITE(PIPESRC(pipe),
4137 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4138
4139 if (HAS_PCH_SPLIT(dev)) {
4140 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4141 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4142 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4143 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4144
4145 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4146 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4147 }
4148 }
4149
4150 I915_WRITE(PIPECONF(pipe), pipeconf);
4151 POSTING_READ(PIPECONF(pipe));
4152
4153 intel_wait_for_vblank(dev, pipe);
4154
4155 if (IS_GEN5(dev)) {
4156 /* enable address swizzle for tiling buffer */
4157 temp = I915_READ(DISP_ARB_CTL);
4158 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4159 }
4160
4161 I915_WRITE(DSPCNTR(plane), dspcntr);
4162
4163 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4164
4165 intel_update_watermarks(dev);
4166
4167 drm_vblank_post_modeset(dev, pipe);
4168
4169 return ret;
4170 }
4171
4172 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4173 void intel_crtc_load_lut(struct drm_crtc *crtc)
4174 {
4175 struct drm_device *dev = crtc->dev;
4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4178 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4179 int i;
4180
4181 /* The clocks have to be on to load the palette. */
4182 if (!crtc->enabled)
4183 return;
4184
4185 /* use legacy palette for Ironlake */
4186 if (HAS_PCH_SPLIT(dev))
4187 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4188 LGC_PALETTE_B;
4189
4190 for (i = 0; i < 256; i++) {
4191 I915_WRITE(palreg + 4 * i,
4192 (intel_crtc->lut_r[i] << 16) |
4193 (intel_crtc->lut_g[i] << 8) |
4194 intel_crtc->lut_b[i]);
4195 }
4196 }
4197
4198 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4199 {
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203 bool visible = base != 0;
4204 u32 cntl;
4205
4206 if (intel_crtc->cursor_visible == visible)
4207 return;
4208
4209 cntl = I915_READ(CURACNTR);
4210 if (visible) {
4211 /* On these chipsets we can only modify the base whilst
4212 * the cursor is disabled.
4213 */
4214 I915_WRITE(CURABASE, base);
4215
4216 cntl &= ~(CURSOR_FORMAT_MASK);
4217 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4218 cntl |= CURSOR_ENABLE |
4219 CURSOR_GAMMA_ENABLE |
4220 CURSOR_FORMAT_ARGB;
4221 } else
4222 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4223 I915_WRITE(CURACNTR, cntl);
4224
4225 intel_crtc->cursor_visible = visible;
4226 }
4227
4228 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4229 {
4230 struct drm_device *dev = crtc->dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233 int pipe = intel_crtc->pipe;
4234 bool visible = base != 0;
4235
4236 if (intel_crtc->cursor_visible != visible) {
4237 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4238 if (base) {
4239 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4240 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4241 cntl |= pipe << 28; /* Connect to correct pipe */
4242 } else {
4243 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4244 cntl |= CURSOR_MODE_DISABLE;
4245 }
4246 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4247
4248 intel_crtc->cursor_visible = visible;
4249 }
4250 /* and commit changes on next vblank */
4251 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4252 }
4253
4254 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4255 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4256 bool on)
4257 {
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4261 int pipe = intel_crtc->pipe;
4262 int x = intel_crtc->cursor_x;
4263 int y = intel_crtc->cursor_y;
4264 u32 base, pos;
4265 bool visible;
4266
4267 pos = 0;
4268
4269 if (on && crtc->enabled && crtc->fb) {
4270 base = intel_crtc->cursor_addr;
4271 if (x > (int) crtc->fb->width)
4272 base = 0;
4273
4274 if (y > (int) crtc->fb->height)
4275 base = 0;
4276 } else
4277 base = 0;
4278
4279 if (x < 0) {
4280 if (x + intel_crtc->cursor_width < 0)
4281 base = 0;
4282
4283 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4284 x = -x;
4285 }
4286 pos |= x << CURSOR_X_SHIFT;
4287
4288 if (y < 0) {
4289 if (y + intel_crtc->cursor_height < 0)
4290 base = 0;
4291
4292 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4293 y = -y;
4294 }
4295 pos |= y << CURSOR_Y_SHIFT;
4296
4297 visible = base != 0;
4298 if (!visible && !intel_crtc->cursor_visible)
4299 return;
4300
4301 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4302 if (IS_845G(dev) || IS_I865G(dev))
4303 i845_update_cursor(crtc, base);
4304 else
4305 i9xx_update_cursor(crtc, base);
4306
4307 if (visible)
4308 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4309 }
4310
4311 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4312 struct drm_file *file_priv,
4313 uint32_t handle,
4314 uint32_t width, uint32_t height)
4315 {
4316 struct drm_device *dev = crtc->dev;
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4319 struct drm_gem_object *bo;
4320 struct drm_i915_gem_object *obj_priv;
4321 uint32_t addr;
4322 int ret;
4323
4324 DRM_DEBUG_KMS("\n");
4325
4326 /* if we want to turn off the cursor ignore width and height */
4327 if (!handle) {
4328 DRM_DEBUG_KMS("cursor off\n");
4329 addr = 0;
4330 bo = NULL;
4331 mutex_lock(&dev->struct_mutex);
4332 goto finish;
4333 }
4334
4335 /* Currently we only support 64x64 cursors */
4336 if (width != 64 || height != 64) {
4337 DRM_ERROR("we currently only support 64x64 cursors\n");
4338 return -EINVAL;
4339 }
4340
4341 bo = drm_gem_object_lookup(dev, file_priv, handle);
4342 if (!bo)
4343 return -ENOENT;
4344
4345 obj_priv = to_intel_bo(bo);
4346
4347 if (bo->size < width * height * 4) {
4348 DRM_ERROR("buffer is to small\n");
4349 ret = -ENOMEM;
4350 goto fail;
4351 }
4352
4353 /* we only need to pin inside GTT if cursor is non-phy */
4354 mutex_lock(&dev->struct_mutex);
4355 if (!dev_priv->info->cursor_needs_physical) {
4356 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4357 if (ret) {
4358 DRM_ERROR("failed to pin cursor bo\n");
4359 goto fail_locked;
4360 }
4361
4362 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4363 if (ret) {
4364 DRM_ERROR("failed to move cursor bo into the GTT\n");
4365 goto fail_unpin;
4366 }
4367
4368 addr = obj_priv->gtt_offset;
4369 } else {
4370 int align = IS_I830(dev) ? 16 * 1024 : 256;
4371 ret = i915_gem_attach_phys_object(dev, bo,
4372 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4373 align);
4374 if (ret) {
4375 DRM_ERROR("failed to attach phys object\n");
4376 goto fail_locked;
4377 }
4378 addr = obj_priv->phys_obj->handle->busaddr;
4379 }
4380
4381 if (IS_GEN2(dev))
4382 I915_WRITE(CURSIZE, (height << 12) | width);
4383
4384 finish:
4385 if (intel_crtc->cursor_bo) {
4386 if (dev_priv->info->cursor_needs_physical) {
4387 if (intel_crtc->cursor_bo != bo)
4388 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4389 } else
4390 i915_gem_object_unpin(intel_crtc->cursor_bo);
4391 drm_gem_object_unreference(intel_crtc->cursor_bo);
4392 }
4393
4394 mutex_unlock(&dev->struct_mutex);
4395
4396 intel_crtc->cursor_addr = addr;
4397 intel_crtc->cursor_bo = bo;
4398 intel_crtc->cursor_width = width;
4399 intel_crtc->cursor_height = height;
4400
4401 intel_crtc_update_cursor(crtc, true);
4402
4403 return 0;
4404 fail_unpin:
4405 i915_gem_object_unpin(bo);
4406 fail_locked:
4407 mutex_unlock(&dev->struct_mutex);
4408 fail:
4409 drm_gem_object_unreference_unlocked(bo);
4410 return ret;
4411 }
4412
4413 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4414 {
4415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4416
4417 intel_crtc->cursor_x = x;
4418 intel_crtc->cursor_y = y;
4419
4420 intel_crtc_update_cursor(crtc, true);
4421
4422 return 0;
4423 }
4424
4425 /** Sets the color ramps on behalf of RandR */
4426 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4427 u16 blue, int regno)
4428 {
4429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4430
4431 intel_crtc->lut_r[regno] = red >> 8;
4432 intel_crtc->lut_g[regno] = green >> 8;
4433 intel_crtc->lut_b[regno] = blue >> 8;
4434 }
4435
4436 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4437 u16 *blue, int regno)
4438 {
4439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4440
4441 *red = intel_crtc->lut_r[regno] << 8;
4442 *green = intel_crtc->lut_g[regno] << 8;
4443 *blue = intel_crtc->lut_b[regno] << 8;
4444 }
4445
4446 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4447 u16 *blue, uint32_t start, uint32_t size)
4448 {
4449 int end = (start + size > 256) ? 256 : start + size, i;
4450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4451
4452 for (i = start; i < end; i++) {
4453 intel_crtc->lut_r[i] = red[i] >> 8;
4454 intel_crtc->lut_g[i] = green[i] >> 8;
4455 intel_crtc->lut_b[i] = blue[i] >> 8;
4456 }
4457
4458 intel_crtc_load_lut(crtc);
4459 }
4460
4461 /**
4462 * Get a pipe with a simple mode set on it for doing load-based monitor
4463 * detection.
4464 *
4465 * It will be up to the load-detect code to adjust the pipe as appropriate for
4466 * its requirements. The pipe will be connected to no other encoders.
4467 *
4468 * Currently this code will only succeed if there is a pipe with no encoders
4469 * configured for it. In the future, it could choose to temporarily disable
4470 * some outputs to free up a pipe for its use.
4471 *
4472 * \return crtc, or NULL if no pipes are available.
4473 */
4474
4475 /* VESA 640x480x72Hz mode to set on the pipe */
4476 static struct drm_display_mode load_detect_mode = {
4477 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4478 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4479 };
4480
4481 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4482 struct drm_connector *connector,
4483 struct drm_display_mode *mode,
4484 int *dpms_mode)
4485 {
4486 struct intel_crtc *intel_crtc;
4487 struct drm_crtc *possible_crtc;
4488 struct drm_crtc *supported_crtc =NULL;
4489 struct drm_encoder *encoder = &intel_encoder->base;
4490 struct drm_crtc *crtc = NULL;
4491 struct drm_device *dev = encoder->dev;
4492 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4493 struct drm_crtc_helper_funcs *crtc_funcs;
4494 int i = -1;
4495
4496 /*
4497 * Algorithm gets a little messy:
4498 * - if the connector already has an assigned crtc, use it (but make
4499 * sure it's on first)
4500 * - try to find the first unused crtc that can drive this connector,
4501 * and use that if we find one
4502 * - if there are no unused crtcs available, try to use the first
4503 * one we found that supports the connector
4504 */
4505
4506 /* See if we already have a CRTC for this connector */
4507 if (encoder->crtc) {
4508 crtc = encoder->crtc;
4509 /* Make sure the crtc and connector are running */
4510 intel_crtc = to_intel_crtc(crtc);
4511 *dpms_mode = intel_crtc->dpms_mode;
4512 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4513 crtc_funcs = crtc->helper_private;
4514 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4515 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4516 }
4517 return crtc;
4518 }
4519
4520 /* Find an unused one (if possible) */
4521 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4522 i++;
4523 if (!(encoder->possible_crtcs & (1 << i)))
4524 continue;
4525 if (!possible_crtc->enabled) {
4526 crtc = possible_crtc;
4527 break;
4528 }
4529 if (!supported_crtc)
4530 supported_crtc = possible_crtc;
4531 }
4532
4533 /*
4534 * If we didn't find an unused CRTC, don't use any.
4535 */
4536 if (!crtc) {
4537 return NULL;
4538 }
4539
4540 encoder->crtc = crtc;
4541 connector->encoder = encoder;
4542 intel_encoder->load_detect_temp = true;
4543
4544 intel_crtc = to_intel_crtc(crtc);
4545 *dpms_mode = intel_crtc->dpms_mode;
4546
4547 if (!crtc->enabled) {
4548 if (!mode)
4549 mode = &load_detect_mode;
4550 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4551 } else {
4552 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4553 crtc_funcs = crtc->helper_private;
4554 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4555 }
4556
4557 /* Add this connector to the crtc */
4558 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4559 encoder_funcs->commit(encoder);
4560 }
4561 /* let the connector get through one full cycle before testing */
4562 intel_wait_for_vblank(dev, intel_crtc->pipe);
4563
4564 return crtc;
4565 }
4566
4567 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4568 struct drm_connector *connector, int dpms_mode)
4569 {
4570 struct drm_encoder *encoder = &intel_encoder->base;
4571 struct drm_device *dev = encoder->dev;
4572 struct drm_crtc *crtc = encoder->crtc;
4573 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4574 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4575
4576 if (intel_encoder->load_detect_temp) {
4577 encoder->crtc = NULL;
4578 connector->encoder = NULL;
4579 intel_encoder->load_detect_temp = false;
4580 crtc->enabled = drm_helper_crtc_in_use(crtc);
4581 drm_helper_disable_unused_functions(dev);
4582 }
4583
4584 /* Switch crtc and encoder back off if necessary */
4585 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4586 if (encoder->crtc == crtc)
4587 encoder_funcs->dpms(encoder, dpms_mode);
4588 crtc_funcs->dpms(crtc, dpms_mode);
4589 }
4590 }
4591
4592 /* Returns the clock of the currently programmed mode of the given pipe. */
4593 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4594 {
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 int pipe = intel_crtc->pipe;
4598 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4599 u32 fp;
4600 intel_clock_t clock;
4601
4602 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4603 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4604 else
4605 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4606
4607 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4608 if (IS_PINEVIEW(dev)) {
4609 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4610 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4611 } else {
4612 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4613 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4614 }
4615
4616 if (!IS_GEN2(dev)) {
4617 if (IS_PINEVIEW(dev))
4618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4619 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4620 else
4621 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4622 DPLL_FPA01_P1_POST_DIV_SHIFT);
4623
4624 switch (dpll & DPLL_MODE_MASK) {
4625 case DPLLB_MODE_DAC_SERIAL:
4626 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4627 5 : 10;
4628 break;
4629 case DPLLB_MODE_LVDS:
4630 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4631 7 : 14;
4632 break;
4633 default:
4634 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4635 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4636 return 0;
4637 }
4638
4639 /* XXX: Handle the 100Mhz refclk */
4640 intel_clock(dev, 96000, &clock);
4641 } else {
4642 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4643
4644 if (is_lvds) {
4645 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4646 DPLL_FPA01_P1_POST_DIV_SHIFT);
4647 clock.p2 = 14;
4648
4649 if ((dpll & PLL_REF_INPUT_MASK) ==
4650 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4651 /* XXX: might not be 66MHz */
4652 intel_clock(dev, 66000, &clock);
4653 } else
4654 intel_clock(dev, 48000, &clock);
4655 } else {
4656 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4657 clock.p1 = 2;
4658 else {
4659 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4660 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4661 }
4662 if (dpll & PLL_P2_DIVIDE_BY_4)
4663 clock.p2 = 4;
4664 else
4665 clock.p2 = 2;
4666
4667 intel_clock(dev, 48000, &clock);
4668 }
4669 }
4670
4671 /* XXX: It would be nice to validate the clocks, but we can't reuse
4672 * i830PllIsValid() because it relies on the xf86_config connector
4673 * configuration being accurate, which it isn't necessarily.
4674 */
4675
4676 return clock.dot;
4677 }
4678
4679 /** Returns the currently programmed mode of the given pipe. */
4680 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4681 struct drm_crtc *crtc)
4682 {
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4685 int pipe = intel_crtc->pipe;
4686 struct drm_display_mode *mode;
4687 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4688 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4689 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4690 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4691
4692 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4693 if (!mode)
4694 return NULL;
4695
4696 mode->clock = intel_crtc_clock_get(dev, crtc);
4697 mode->hdisplay = (htot & 0xffff) + 1;
4698 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4699 mode->hsync_start = (hsync & 0xffff) + 1;
4700 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4701 mode->vdisplay = (vtot & 0xffff) + 1;
4702 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4703 mode->vsync_start = (vsync & 0xffff) + 1;
4704 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4705
4706 drm_mode_set_name(mode);
4707 drm_mode_set_crtcinfo(mode, 0);
4708
4709 return mode;
4710 }
4711
4712 #define GPU_IDLE_TIMEOUT 500 /* ms */
4713
4714 /* When this timer fires, we've been idle for awhile */
4715 static void intel_gpu_idle_timer(unsigned long arg)
4716 {
4717 struct drm_device *dev = (struct drm_device *)arg;
4718 drm_i915_private_t *dev_priv = dev->dev_private;
4719
4720 dev_priv->busy = false;
4721
4722 queue_work(dev_priv->wq, &dev_priv->idle_work);
4723 }
4724
4725 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4726
4727 static void intel_crtc_idle_timer(unsigned long arg)
4728 {
4729 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4730 struct drm_crtc *crtc = &intel_crtc->base;
4731 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4732
4733 intel_crtc->busy = false;
4734
4735 queue_work(dev_priv->wq, &dev_priv->idle_work);
4736 }
4737
4738 static void intel_increase_pllclock(struct drm_crtc *crtc)
4739 {
4740 struct drm_device *dev = crtc->dev;
4741 drm_i915_private_t *dev_priv = dev->dev_private;
4742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4743 int pipe = intel_crtc->pipe;
4744 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4745 int dpll = I915_READ(dpll_reg);
4746
4747 if (HAS_PCH_SPLIT(dev))
4748 return;
4749
4750 if (!dev_priv->lvds_downclock_avail)
4751 return;
4752
4753 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4754 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4755
4756 /* Unlock panel regs */
4757 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4758 PANEL_UNLOCK_REGS);
4759
4760 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4761 I915_WRITE(dpll_reg, dpll);
4762 dpll = I915_READ(dpll_reg);
4763 intel_wait_for_vblank(dev, pipe);
4764 dpll = I915_READ(dpll_reg);
4765 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4766 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4767
4768 /* ...and lock them again */
4769 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4770 }
4771
4772 /* Schedule downclock */
4773 mod_timer(&intel_crtc->idle_timer, jiffies +
4774 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4775 }
4776
4777 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4778 {
4779 struct drm_device *dev = crtc->dev;
4780 drm_i915_private_t *dev_priv = dev->dev_private;
4781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782 int pipe = intel_crtc->pipe;
4783 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4784 int dpll = I915_READ(dpll_reg);
4785
4786 if (HAS_PCH_SPLIT(dev))
4787 return;
4788
4789 if (!dev_priv->lvds_downclock_avail)
4790 return;
4791
4792 /*
4793 * Since this is called by a timer, we should never get here in
4794 * the manual case.
4795 */
4796 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4797 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4798
4799 /* Unlock panel regs */
4800 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4801 PANEL_UNLOCK_REGS);
4802
4803 dpll |= DISPLAY_RATE_SELECT_FPA1;
4804 I915_WRITE(dpll_reg, dpll);
4805 dpll = I915_READ(dpll_reg);
4806 intel_wait_for_vblank(dev, pipe);
4807 dpll = I915_READ(dpll_reg);
4808 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4809 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4810
4811 /* ...and lock them again */
4812 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4813 }
4814
4815 }
4816
4817 /**
4818 * intel_idle_update - adjust clocks for idleness
4819 * @work: work struct
4820 *
4821 * Either the GPU or display (or both) went idle. Check the busy status
4822 * here and adjust the CRTC and GPU clocks as necessary.
4823 */
4824 static void intel_idle_update(struct work_struct *work)
4825 {
4826 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4827 idle_work);
4828 struct drm_device *dev = dev_priv->dev;
4829 struct drm_crtc *crtc;
4830 struct intel_crtc *intel_crtc;
4831 int enabled = 0;
4832
4833 if (!i915_powersave)
4834 return;
4835
4836 mutex_lock(&dev->struct_mutex);
4837
4838 i915_update_gfx_val(dev_priv);
4839
4840 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4841 /* Skip inactive CRTCs */
4842 if (!crtc->fb)
4843 continue;
4844
4845 enabled++;
4846 intel_crtc = to_intel_crtc(crtc);
4847 if (!intel_crtc->busy)
4848 intel_decrease_pllclock(crtc);
4849 }
4850
4851 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4852 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4853 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4854 }
4855
4856 mutex_unlock(&dev->struct_mutex);
4857 }
4858
4859 /**
4860 * intel_mark_busy - mark the GPU and possibly the display busy
4861 * @dev: drm device
4862 * @obj: object we're operating on
4863 *
4864 * Callers can use this function to indicate that the GPU is busy processing
4865 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4866 * buffer), we'll also mark the display as busy, so we know to increase its
4867 * clock frequency.
4868 */
4869 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4870 {
4871 drm_i915_private_t *dev_priv = dev->dev_private;
4872 struct drm_crtc *crtc = NULL;
4873 struct intel_framebuffer *intel_fb;
4874 struct intel_crtc *intel_crtc;
4875
4876 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4877 return;
4878
4879 if (!dev_priv->busy) {
4880 if (IS_I945G(dev) || IS_I945GM(dev)) {
4881 u32 fw_blc_self;
4882
4883 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4884 fw_blc_self = I915_READ(FW_BLC_SELF);
4885 fw_blc_self &= ~FW_BLC_SELF_EN;
4886 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4887 }
4888 dev_priv->busy = true;
4889 } else
4890 mod_timer(&dev_priv->idle_timer, jiffies +
4891 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4892
4893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4894 if (!crtc->fb)
4895 continue;
4896
4897 intel_crtc = to_intel_crtc(crtc);
4898 intel_fb = to_intel_framebuffer(crtc->fb);
4899 if (intel_fb->obj == obj) {
4900 if (!intel_crtc->busy) {
4901 if (IS_I945G(dev) || IS_I945GM(dev)) {
4902 u32 fw_blc_self;
4903
4904 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4905 fw_blc_self = I915_READ(FW_BLC_SELF);
4906 fw_blc_self &= ~FW_BLC_SELF_EN;
4907 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4908 }
4909 /* Non-busy -> busy, upclock */
4910 intel_increase_pllclock(crtc);
4911 intel_crtc->busy = true;
4912 } else {
4913 /* Busy -> busy, put off timer */
4914 mod_timer(&intel_crtc->idle_timer, jiffies +
4915 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4916 }
4917 }
4918 }
4919 }
4920
4921 static void intel_crtc_destroy(struct drm_crtc *crtc)
4922 {
4923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4924 struct drm_device *dev = crtc->dev;
4925 struct intel_unpin_work *work;
4926 unsigned long flags;
4927
4928 spin_lock_irqsave(&dev->event_lock, flags);
4929 work = intel_crtc->unpin_work;
4930 intel_crtc->unpin_work = NULL;
4931 spin_unlock_irqrestore(&dev->event_lock, flags);
4932
4933 if (work) {
4934 cancel_work_sync(&work->work);
4935 kfree(work);
4936 }
4937
4938 drm_crtc_cleanup(crtc);
4939
4940 kfree(intel_crtc);
4941 }
4942
4943 static void intel_unpin_work_fn(struct work_struct *__work)
4944 {
4945 struct intel_unpin_work *work =
4946 container_of(__work, struct intel_unpin_work, work);
4947
4948 mutex_lock(&work->dev->struct_mutex);
4949 i915_gem_object_unpin(work->old_fb_obj);
4950 drm_gem_object_unreference(work->pending_flip_obj);
4951 drm_gem_object_unreference(work->old_fb_obj);
4952 mutex_unlock(&work->dev->struct_mutex);
4953 kfree(work);
4954 }
4955
4956 static void do_intel_finish_page_flip(struct drm_device *dev,
4957 struct drm_crtc *crtc)
4958 {
4959 drm_i915_private_t *dev_priv = dev->dev_private;
4960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4961 struct intel_unpin_work *work;
4962 struct drm_i915_gem_object *obj_priv;
4963 struct drm_pending_vblank_event *e;
4964 struct timeval now;
4965 unsigned long flags;
4966
4967 /* Ignore early vblank irqs */
4968 if (intel_crtc == NULL)
4969 return;
4970
4971 spin_lock_irqsave(&dev->event_lock, flags);
4972 work = intel_crtc->unpin_work;
4973 if (work == NULL || !work->pending) {
4974 spin_unlock_irqrestore(&dev->event_lock, flags);
4975 return;
4976 }
4977
4978 intel_crtc->unpin_work = NULL;
4979 drm_vblank_put(dev, intel_crtc->pipe);
4980
4981 if (work->event) {
4982 e = work->event;
4983 do_gettimeofday(&now);
4984 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4985 e->event.tv_sec = now.tv_sec;
4986 e->event.tv_usec = now.tv_usec;
4987 list_add_tail(&e->base.link,
4988 &e->base.file_priv->event_list);
4989 wake_up_interruptible(&e->base.file_priv->event_wait);
4990 }
4991
4992 spin_unlock_irqrestore(&dev->event_lock, flags);
4993
4994 obj_priv = to_intel_bo(work->old_fb_obj);
4995 atomic_clear_mask(1 << intel_crtc->plane,
4996 &obj_priv->pending_flip.counter);
4997 if (atomic_read(&obj_priv->pending_flip) == 0)
4998 wake_up(&dev_priv->pending_flip_queue);
4999 schedule_work(&work->work);
5000
5001 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5002 }
5003
5004 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5005 {
5006 drm_i915_private_t *dev_priv = dev->dev_private;
5007 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5008
5009 do_intel_finish_page_flip(dev, crtc);
5010 }
5011
5012 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5013 {
5014 drm_i915_private_t *dev_priv = dev->dev_private;
5015 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5016
5017 do_intel_finish_page_flip(dev, crtc);
5018 }
5019
5020 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5021 {
5022 drm_i915_private_t *dev_priv = dev->dev_private;
5023 struct intel_crtc *intel_crtc =
5024 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5025 unsigned long flags;
5026
5027 spin_lock_irqsave(&dev->event_lock, flags);
5028 if (intel_crtc->unpin_work) {
5029 if ((++intel_crtc->unpin_work->pending) > 1)
5030 DRM_ERROR("Prepared flip multiple times\n");
5031 } else {
5032 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5033 }
5034 spin_unlock_irqrestore(&dev->event_lock, flags);
5035 }
5036
5037 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5038 struct drm_framebuffer *fb,
5039 struct drm_pending_vblank_event *event)
5040 {
5041 struct drm_device *dev = crtc->dev;
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043 struct intel_framebuffer *intel_fb;
5044 struct drm_i915_gem_object *obj_priv;
5045 struct drm_gem_object *obj;
5046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047 struct intel_unpin_work *work;
5048 unsigned long flags, offset;
5049 int pipe = intel_crtc->pipe;
5050 u32 pf, pipesrc;
5051 int ret;
5052
5053 work = kzalloc(sizeof *work, GFP_KERNEL);
5054 if (work == NULL)
5055 return -ENOMEM;
5056
5057 work->event = event;
5058 work->dev = crtc->dev;
5059 intel_fb = to_intel_framebuffer(crtc->fb);
5060 work->old_fb_obj = intel_fb->obj;
5061 INIT_WORK(&work->work, intel_unpin_work_fn);
5062
5063 /* We borrow the event spin lock for protecting unpin_work */
5064 spin_lock_irqsave(&dev->event_lock, flags);
5065 if (intel_crtc->unpin_work) {
5066 spin_unlock_irqrestore(&dev->event_lock, flags);
5067 kfree(work);
5068
5069 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5070 return -EBUSY;
5071 }
5072 intel_crtc->unpin_work = work;
5073 spin_unlock_irqrestore(&dev->event_lock, flags);
5074
5075 intel_fb = to_intel_framebuffer(fb);
5076 obj = intel_fb->obj;
5077
5078 mutex_lock(&dev->struct_mutex);
5079 ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5080 if (ret)
5081 goto cleanup_work;
5082
5083 /* Reference the objects for the scheduled work. */
5084 drm_gem_object_reference(work->old_fb_obj);
5085 drm_gem_object_reference(obj);
5086
5087 crtc->fb = fb;
5088
5089 ret = drm_vblank_get(dev, intel_crtc->pipe);
5090 if (ret)
5091 goto cleanup_objs;
5092
5093 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5094 u32 flip_mask;
5095
5096 /* Can't queue multiple flips, so wait for the previous
5097 * one to finish before executing the next.
5098 */
5099 ret = BEGIN_LP_RING(2);
5100 if (ret)
5101 goto cleanup_objs;
5102
5103 if (intel_crtc->plane)
5104 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5105 else
5106 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5107 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5108 OUT_RING(MI_NOOP);
5109 ADVANCE_LP_RING();
5110 }
5111
5112 work->pending_flip_obj = obj;
5113 obj_priv = to_intel_bo(obj);
5114
5115 work->enable_stall_check = true;
5116
5117 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5118 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5119
5120 ret = BEGIN_LP_RING(4);
5121 if (ret)
5122 goto cleanup_objs;
5123
5124 /* Block clients from rendering to the new back buffer until
5125 * the flip occurs and the object is no longer visible.
5126 */
5127 atomic_add(1 << intel_crtc->plane,
5128 &to_intel_bo(work->old_fb_obj)->pending_flip);
5129
5130 switch (INTEL_INFO(dev)->gen) {
5131 case 2:
5132 OUT_RING(MI_DISPLAY_FLIP |
5133 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5134 OUT_RING(fb->pitch);
5135 OUT_RING(obj_priv->gtt_offset + offset);
5136 OUT_RING(MI_NOOP);
5137 break;
5138
5139 case 3:
5140 OUT_RING(MI_DISPLAY_FLIP_I915 |
5141 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5142 OUT_RING(fb->pitch);
5143 OUT_RING(obj_priv->gtt_offset + offset);
5144 OUT_RING(MI_NOOP);
5145 break;
5146
5147 case 4:
5148 case 5:
5149 /* i965+ uses the linear or tiled offsets from the
5150 * Display Registers (which do not change across a page-flip)
5151 * so we need only reprogram the base address.
5152 */
5153 OUT_RING(MI_DISPLAY_FLIP |
5154 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5155 OUT_RING(fb->pitch);
5156 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5157
5158 /* XXX Enabling the panel-fitter across page-flip is so far
5159 * untested on non-native modes, so ignore it for now.
5160 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5161 */
5162 pf = 0;
5163 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5164 OUT_RING(pf | pipesrc);
5165 break;
5166
5167 case 6:
5168 OUT_RING(MI_DISPLAY_FLIP |
5169 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5170 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5171 OUT_RING(obj_priv->gtt_offset);
5172
5173 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5174 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5175 OUT_RING(pf | pipesrc);
5176 break;
5177 }
5178 ADVANCE_LP_RING();
5179
5180 mutex_unlock(&dev->struct_mutex);
5181
5182 trace_i915_flip_request(intel_crtc->plane, obj);
5183
5184 return 0;
5185
5186 cleanup_objs:
5187 drm_gem_object_unreference(work->old_fb_obj);
5188 drm_gem_object_unreference(obj);
5189 cleanup_work:
5190 mutex_unlock(&dev->struct_mutex);
5191
5192 spin_lock_irqsave(&dev->event_lock, flags);
5193 intel_crtc->unpin_work = NULL;
5194 spin_unlock_irqrestore(&dev->event_lock, flags);
5195
5196 kfree(work);
5197
5198 return ret;
5199 }
5200
5201 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5202 .dpms = intel_crtc_dpms,
5203 .mode_fixup = intel_crtc_mode_fixup,
5204 .mode_set = intel_crtc_mode_set,
5205 .mode_set_base = intel_pipe_set_base,
5206 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5207 .load_lut = intel_crtc_load_lut,
5208 .disable = intel_crtc_disable,
5209 };
5210
5211 static const struct drm_crtc_funcs intel_crtc_funcs = {
5212 .cursor_set = intel_crtc_cursor_set,
5213 .cursor_move = intel_crtc_cursor_move,
5214 .gamma_set = intel_crtc_gamma_set,
5215 .set_config = drm_crtc_helper_set_config,
5216 .destroy = intel_crtc_destroy,
5217 .page_flip = intel_crtc_page_flip,
5218 };
5219
5220
5221 static void intel_crtc_init(struct drm_device *dev, int pipe)
5222 {
5223 drm_i915_private_t *dev_priv = dev->dev_private;
5224 struct intel_crtc *intel_crtc;
5225 int i;
5226
5227 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5228 if (intel_crtc == NULL)
5229 return;
5230
5231 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5232
5233 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5234 for (i = 0; i < 256; i++) {
5235 intel_crtc->lut_r[i] = i;
5236 intel_crtc->lut_g[i] = i;
5237 intel_crtc->lut_b[i] = i;
5238 }
5239
5240 /* Swap pipes & planes for FBC on pre-965 */
5241 intel_crtc->pipe = pipe;
5242 intel_crtc->plane = pipe;
5243 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5244 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5245 intel_crtc->plane = !pipe;
5246 }
5247
5248 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5249 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5250 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5251 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5252
5253 intel_crtc->cursor_addr = 0;
5254 intel_crtc->dpms_mode = -1;
5255 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5256
5257 if (HAS_PCH_SPLIT(dev)) {
5258 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5259 intel_helper_funcs.commit = ironlake_crtc_commit;
5260 } else {
5261 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5262 intel_helper_funcs.commit = i9xx_crtc_commit;
5263 }
5264
5265 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5266
5267 intel_crtc->busy = false;
5268
5269 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5270 (unsigned long)intel_crtc);
5271 }
5272
5273 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5274 struct drm_file *file_priv)
5275 {
5276 drm_i915_private_t *dev_priv = dev->dev_private;
5277 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5278 struct drm_mode_object *drmmode_obj;
5279 struct intel_crtc *crtc;
5280
5281 if (!dev_priv) {
5282 DRM_ERROR("called with no initialization\n");
5283 return -EINVAL;
5284 }
5285
5286 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5287 DRM_MODE_OBJECT_CRTC);
5288
5289 if (!drmmode_obj) {
5290 DRM_ERROR("no such CRTC id\n");
5291 return -EINVAL;
5292 }
5293
5294 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5295 pipe_from_crtc_id->pipe = crtc->pipe;
5296
5297 return 0;
5298 }
5299
5300 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5301 {
5302 struct intel_encoder *encoder;
5303 int index_mask = 0;
5304 int entry = 0;
5305
5306 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5307 if (type_mask & encoder->clone_mask)
5308 index_mask |= (1 << entry);
5309 entry++;
5310 }
5311
5312 return index_mask;
5313 }
5314
5315 static void intel_setup_outputs(struct drm_device *dev)
5316 {
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318 struct intel_encoder *encoder;
5319 bool dpd_is_edp = false;
5320
5321 if (IS_MOBILE(dev) && !IS_I830(dev))
5322 intel_lvds_init(dev);
5323
5324 if (HAS_PCH_SPLIT(dev)) {
5325 dpd_is_edp = intel_dpd_is_edp(dev);
5326
5327 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5328 intel_dp_init(dev, DP_A);
5329
5330 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5331 intel_dp_init(dev, PCH_DP_D);
5332 }
5333
5334 intel_crt_init(dev);
5335
5336 if (HAS_PCH_SPLIT(dev)) {
5337 int found;
5338
5339 if (I915_READ(HDMIB) & PORT_DETECTED) {
5340 /* PCH SDVOB multiplex with HDMIB */
5341 found = intel_sdvo_init(dev, PCH_SDVOB);
5342 if (!found)
5343 intel_hdmi_init(dev, HDMIB);
5344 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5345 intel_dp_init(dev, PCH_DP_B);
5346 }
5347
5348 if (I915_READ(HDMIC) & PORT_DETECTED)
5349 intel_hdmi_init(dev, HDMIC);
5350
5351 if (I915_READ(HDMID) & PORT_DETECTED)
5352 intel_hdmi_init(dev, HDMID);
5353
5354 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5355 intel_dp_init(dev, PCH_DP_C);
5356
5357 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5358 intel_dp_init(dev, PCH_DP_D);
5359
5360 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5361 bool found = false;
5362
5363 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5364 DRM_DEBUG_KMS("probing SDVOB\n");
5365 found = intel_sdvo_init(dev, SDVOB);
5366 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5367 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5368 intel_hdmi_init(dev, SDVOB);
5369 }
5370
5371 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5372 DRM_DEBUG_KMS("probing DP_B\n");
5373 intel_dp_init(dev, DP_B);
5374 }
5375 }
5376
5377 /* Before G4X SDVOC doesn't have its own detect register */
5378
5379 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5380 DRM_DEBUG_KMS("probing SDVOC\n");
5381 found = intel_sdvo_init(dev, SDVOC);
5382 }
5383
5384 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5385
5386 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5387 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5388 intel_hdmi_init(dev, SDVOC);
5389 }
5390 if (SUPPORTS_INTEGRATED_DP(dev)) {
5391 DRM_DEBUG_KMS("probing DP_C\n");
5392 intel_dp_init(dev, DP_C);
5393 }
5394 }
5395
5396 if (SUPPORTS_INTEGRATED_DP(dev) &&
5397 (I915_READ(DP_D) & DP_DETECTED)) {
5398 DRM_DEBUG_KMS("probing DP_D\n");
5399 intel_dp_init(dev, DP_D);
5400 }
5401 } else if (IS_GEN2(dev))
5402 intel_dvo_init(dev);
5403
5404 if (SUPPORTS_TV(dev))
5405 intel_tv_init(dev);
5406
5407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5408 encoder->base.possible_crtcs = encoder->crtc_mask;
5409 encoder->base.possible_clones =
5410 intel_encoder_clones(dev, encoder->clone_mask);
5411 }
5412 }
5413
5414 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5415 {
5416 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5417
5418 drm_framebuffer_cleanup(fb);
5419 drm_gem_object_unreference_unlocked(intel_fb->obj);
5420
5421 kfree(intel_fb);
5422 }
5423
5424 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5425 struct drm_file *file_priv,
5426 unsigned int *handle)
5427 {
5428 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5429 struct drm_gem_object *object = intel_fb->obj;
5430
5431 return drm_gem_handle_create(file_priv, object, handle);
5432 }
5433
5434 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5435 .destroy = intel_user_framebuffer_destroy,
5436 .create_handle = intel_user_framebuffer_create_handle,
5437 };
5438
5439 int intel_framebuffer_init(struct drm_device *dev,
5440 struct intel_framebuffer *intel_fb,
5441 struct drm_mode_fb_cmd *mode_cmd,
5442 struct drm_gem_object *obj)
5443 {
5444 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5445 int ret;
5446
5447 if (obj_priv->tiling_mode == I915_TILING_Y)
5448 return -EINVAL;
5449
5450 if (mode_cmd->pitch & 63)
5451 return -EINVAL;
5452
5453 switch (mode_cmd->bpp) {
5454 case 8:
5455 case 16:
5456 case 24:
5457 case 32:
5458 break;
5459 default:
5460 return -EINVAL;
5461 }
5462
5463 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5464 if (ret) {
5465 DRM_ERROR("framebuffer init failed %d\n", ret);
5466 return ret;
5467 }
5468
5469 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5470 intel_fb->obj = obj;
5471 return 0;
5472 }
5473
5474 static struct drm_framebuffer *
5475 intel_user_framebuffer_create(struct drm_device *dev,
5476 struct drm_file *filp,
5477 struct drm_mode_fb_cmd *mode_cmd)
5478 {
5479 struct drm_gem_object *obj;
5480 struct intel_framebuffer *intel_fb;
5481 int ret;
5482
5483 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5484 if (!obj)
5485 return ERR_PTR(-ENOENT);
5486
5487 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5488 if (!intel_fb)
5489 return ERR_PTR(-ENOMEM);
5490
5491 ret = intel_framebuffer_init(dev, intel_fb,
5492 mode_cmd, obj);
5493 if (ret) {
5494 drm_gem_object_unreference_unlocked(obj);
5495 kfree(intel_fb);
5496 return ERR_PTR(ret);
5497 }
5498
5499 return &intel_fb->base;
5500 }
5501
5502 static const struct drm_mode_config_funcs intel_mode_funcs = {
5503 .fb_create = intel_user_framebuffer_create,
5504 .output_poll_changed = intel_fb_output_poll_changed,
5505 };
5506
5507 static struct drm_gem_object *
5508 intel_alloc_context_page(struct drm_device *dev)
5509 {
5510 struct drm_gem_object *ctx;
5511 int ret;
5512
5513 ctx = i915_gem_alloc_object(dev, 4096);
5514 if (!ctx) {
5515 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5516 return NULL;
5517 }
5518
5519 mutex_lock(&dev->struct_mutex);
5520 ret = i915_gem_object_pin(ctx, 4096);
5521 if (ret) {
5522 DRM_ERROR("failed to pin power context: %d\n", ret);
5523 goto err_unref;
5524 }
5525
5526 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5527 if (ret) {
5528 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5529 goto err_unpin;
5530 }
5531 mutex_unlock(&dev->struct_mutex);
5532
5533 return ctx;
5534
5535 err_unpin:
5536 i915_gem_object_unpin(ctx);
5537 err_unref:
5538 drm_gem_object_unreference(ctx);
5539 mutex_unlock(&dev->struct_mutex);
5540 return NULL;
5541 }
5542
5543 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5544 {
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 u16 rgvswctl;
5547
5548 rgvswctl = I915_READ16(MEMSWCTL);
5549 if (rgvswctl & MEMCTL_CMD_STS) {
5550 DRM_DEBUG("gpu busy, RCS change rejected\n");
5551 return false; /* still busy with another command */
5552 }
5553
5554 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5555 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5556 I915_WRITE16(MEMSWCTL, rgvswctl);
5557 POSTING_READ16(MEMSWCTL);
5558
5559 rgvswctl |= MEMCTL_CMD_STS;
5560 I915_WRITE16(MEMSWCTL, rgvswctl);
5561
5562 return true;
5563 }
5564
5565 void ironlake_enable_drps(struct drm_device *dev)
5566 {
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 u32 rgvmodectl = I915_READ(MEMMODECTL);
5569 u8 fmax, fmin, fstart, vstart;
5570
5571 /* Enable temp reporting */
5572 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5573 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5574
5575 /* 100ms RC evaluation intervals */
5576 I915_WRITE(RCUPEI, 100000);
5577 I915_WRITE(RCDNEI, 100000);
5578
5579 /* Set max/min thresholds to 90ms and 80ms respectively */
5580 I915_WRITE(RCBMAXAVG, 90000);
5581 I915_WRITE(RCBMINAVG, 80000);
5582
5583 I915_WRITE(MEMIHYST, 1);
5584
5585 /* Set up min, max, and cur for interrupt handling */
5586 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5587 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5588 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5589 MEMMODE_FSTART_SHIFT;
5590 fstart = fmax;
5591
5592 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5593 PXVFREQ_PX_SHIFT;
5594
5595 dev_priv->fmax = fstart; /* IPS callback will increase this */
5596 dev_priv->fstart = fstart;
5597
5598 dev_priv->max_delay = fmax;
5599 dev_priv->min_delay = fmin;
5600 dev_priv->cur_delay = fstart;
5601
5602 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5603 fstart);
5604
5605 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5606
5607 /*
5608 * Interrupts will be enabled in ironlake_irq_postinstall
5609 */
5610
5611 I915_WRITE(VIDSTART, vstart);
5612 POSTING_READ(VIDSTART);
5613
5614 rgvmodectl |= MEMMODE_SWMODE_EN;
5615 I915_WRITE(MEMMODECTL, rgvmodectl);
5616
5617 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5618 DRM_ERROR("stuck trying to change perf mode\n");
5619 msleep(1);
5620
5621 ironlake_set_drps(dev, fstart);
5622
5623 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5624 I915_READ(0x112e0);
5625 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5626 dev_priv->last_count2 = I915_READ(0x112f4);
5627 getrawmonotonic(&dev_priv->last_time2);
5628 }
5629
5630 void ironlake_disable_drps(struct drm_device *dev)
5631 {
5632 struct drm_i915_private *dev_priv = dev->dev_private;
5633 u16 rgvswctl = I915_READ16(MEMSWCTL);
5634
5635 /* Ack interrupts, disable EFC interrupt */
5636 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5637 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5638 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5639 I915_WRITE(DEIIR, DE_PCU_EVENT);
5640 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5641
5642 /* Go back to the starting frequency */
5643 ironlake_set_drps(dev, dev_priv->fstart);
5644 msleep(1);
5645 rgvswctl |= MEMCTL_CMD_STS;
5646 I915_WRITE(MEMSWCTL, rgvswctl);
5647 msleep(1);
5648
5649 }
5650
5651 static unsigned long intel_pxfreq(u32 vidfreq)
5652 {
5653 unsigned long freq;
5654 int div = (vidfreq & 0x3f0000) >> 16;
5655 int post = (vidfreq & 0x3000) >> 12;
5656 int pre = (vidfreq & 0x7);
5657
5658 if (!pre)
5659 return 0;
5660
5661 freq = ((div * 133333) / ((1<<post) * pre));
5662
5663 return freq;
5664 }
5665
5666 void intel_init_emon(struct drm_device *dev)
5667 {
5668 struct drm_i915_private *dev_priv = dev->dev_private;
5669 u32 lcfuse;
5670 u8 pxw[16];
5671 int i;
5672
5673 /* Disable to program */
5674 I915_WRITE(ECR, 0);
5675 POSTING_READ(ECR);
5676
5677 /* Program energy weights for various events */
5678 I915_WRITE(SDEW, 0x15040d00);
5679 I915_WRITE(CSIEW0, 0x007f0000);
5680 I915_WRITE(CSIEW1, 0x1e220004);
5681 I915_WRITE(CSIEW2, 0x04000004);
5682
5683 for (i = 0; i < 5; i++)
5684 I915_WRITE(PEW + (i * 4), 0);
5685 for (i = 0; i < 3; i++)
5686 I915_WRITE(DEW + (i * 4), 0);
5687
5688 /* Program P-state weights to account for frequency power adjustment */
5689 for (i = 0; i < 16; i++) {
5690 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5691 unsigned long freq = intel_pxfreq(pxvidfreq);
5692 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5693 PXVFREQ_PX_SHIFT;
5694 unsigned long val;
5695
5696 val = vid * vid;
5697 val *= (freq / 1000);
5698 val *= 255;
5699 val /= (127*127*900);
5700 if (val > 0xff)
5701 DRM_ERROR("bad pxval: %ld\n", val);
5702 pxw[i] = val;
5703 }
5704 /* Render standby states get 0 weight */
5705 pxw[14] = 0;
5706 pxw[15] = 0;
5707
5708 for (i = 0; i < 4; i++) {
5709 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5710 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5711 I915_WRITE(PXW + (i * 4), val);
5712 }
5713
5714 /* Adjust magic regs to magic values (more experimental results) */
5715 I915_WRITE(OGW0, 0);
5716 I915_WRITE(OGW1, 0);
5717 I915_WRITE(EG0, 0x00007f00);
5718 I915_WRITE(EG1, 0x0000000e);
5719 I915_WRITE(EG2, 0x000e0000);
5720 I915_WRITE(EG3, 0x68000300);
5721 I915_WRITE(EG4, 0x42000000);
5722 I915_WRITE(EG5, 0x00140031);
5723 I915_WRITE(EG6, 0);
5724 I915_WRITE(EG7, 0);
5725
5726 for (i = 0; i < 8; i++)
5727 I915_WRITE(PXWL + (i * 4), 0);
5728
5729 /* Enable PMON + select events */
5730 I915_WRITE(ECR, 0x80000019);
5731
5732 lcfuse = I915_READ(LCFUSE02);
5733
5734 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5735 }
5736
5737 void intel_init_clock_gating(struct drm_device *dev)
5738 {
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740
5741 /*
5742 * Disable clock gating reported to work incorrectly according to the
5743 * specs, but enable as much else as we can.
5744 */
5745 if (HAS_PCH_SPLIT(dev)) {
5746 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5747
5748 if (IS_GEN5(dev)) {
5749 /* Required for FBC */
5750 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5751 /* Required for CxSR */
5752 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5753
5754 I915_WRITE(PCH_3DCGDIS0,
5755 MARIUNIT_CLOCK_GATE_DISABLE |
5756 SVSMUNIT_CLOCK_GATE_DISABLE);
5757 }
5758
5759 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5760
5761 /*
5762 * On Ibex Peak and Cougar Point, we need to disable clock
5763 * gating for the panel power sequencer or it will fail to
5764 * start up when no ports are active.
5765 */
5766 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5767
5768 /*
5769 * According to the spec the following bits should be set in
5770 * order to enable memory self-refresh
5771 * The bit 22/21 of 0x42004
5772 * The bit 5 of 0x42020
5773 * The bit 15 of 0x45000
5774 */
5775 if (IS_GEN5(dev)) {
5776 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5777 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5778 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5779 I915_WRITE(ILK_DSPCLK_GATE,
5780 (I915_READ(ILK_DSPCLK_GATE) |
5781 ILK_DPARB_CLK_GATE));
5782 I915_WRITE(DISP_ARB_CTL,
5783 (I915_READ(DISP_ARB_CTL) |
5784 DISP_FBC_WM_DIS));
5785 I915_WRITE(WM3_LP_ILK, 0);
5786 I915_WRITE(WM2_LP_ILK, 0);
5787 I915_WRITE(WM1_LP_ILK, 0);
5788 }
5789 /*
5790 * Based on the document from hardware guys the following bits
5791 * should be set unconditionally in order to enable FBC.
5792 * The bit 22 of 0x42000
5793 * The bit 22 of 0x42004
5794 * The bit 7,8,9 of 0x42020.
5795 */
5796 if (IS_IRONLAKE_M(dev)) {
5797 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5798 I915_READ(ILK_DISPLAY_CHICKEN1) |
5799 ILK_FBCQ_DIS);
5800 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5801 I915_READ(ILK_DISPLAY_CHICKEN2) |
5802 ILK_DPARB_GATE);
5803 I915_WRITE(ILK_DSPCLK_GATE,
5804 I915_READ(ILK_DSPCLK_GATE) |
5805 ILK_DPFC_DIS1 |
5806 ILK_DPFC_DIS2 |
5807 ILK_CLK_FBC);
5808 }
5809 return;
5810 } else if (IS_G4X(dev)) {
5811 uint32_t dspclk_gate;
5812 I915_WRITE(RENCLK_GATE_D1, 0);
5813 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5814 GS_UNIT_CLOCK_GATE_DISABLE |
5815 CL_UNIT_CLOCK_GATE_DISABLE);
5816 I915_WRITE(RAMCLK_GATE_D, 0);
5817 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5818 OVRUNIT_CLOCK_GATE_DISABLE |
5819 OVCUNIT_CLOCK_GATE_DISABLE;
5820 if (IS_GM45(dev))
5821 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5822 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5823 } else if (IS_CRESTLINE(dev)) {
5824 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5825 I915_WRITE(RENCLK_GATE_D2, 0);
5826 I915_WRITE(DSPCLK_GATE_D, 0);
5827 I915_WRITE(RAMCLK_GATE_D, 0);
5828 I915_WRITE16(DEUC, 0);
5829 } else if (IS_BROADWATER(dev)) {
5830 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5831 I965_RCC_CLOCK_GATE_DISABLE |
5832 I965_RCPB_CLOCK_GATE_DISABLE |
5833 I965_ISC_CLOCK_GATE_DISABLE |
5834 I965_FBC_CLOCK_GATE_DISABLE);
5835 I915_WRITE(RENCLK_GATE_D2, 0);
5836 } else if (IS_GEN3(dev)) {
5837 u32 dstate = I915_READ(D_STATE);
5838
5839 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5840 DSTATE_DOT_CLOCK_GATING;
5841 I915_WRITE(D_STATE, dstate);
5842 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5843 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5844 } else if (IS_I830(dev)) {
5845 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5846 }
5847
5848 /*
5849 * GPU can automatically power down the render unit if given a page
5850 * to save state.
5851 */
5852 if (IS_IRONLAKE_M(dev)) {
5853 if (dev_priv->renderctx == NULL)
5854 dev_priv->renderctx = intel_alloc_context_page(dev);
5855 if (dev_priv->renderctx) {
5856 struct drm_i915_gem_object *obj_priv;
5857 obj_priv = to_intel_bo(dev_priv->renderctx);
5858 if (obj_priv) {
5859 if (BEGIN_LP_RING(4) == 0) {
5860 OUT_RING(MI_SET_CONTEXT);
5861 OUT_RING(obj_priv->gtt_offset |
5862 MI_MM_SPACE_GTT |
5863 MI_SAVE_EXT_STATE_EN |
5864 MI_RESTORE_EXT_STATE_EN |
5865 MI_RESTORE_INHIBIT);
5866 OUT_RING(MI_NOOP);
5867 OUT_RING(MI_FLUSH);
5868 ADVANCE_LP_RING();
5869 }
5870 }
5871 } else
5872 DRM_DEBUG_KMS("Failed to allocate render context."
5873 "Disable RC6\n");
5874 }
5875
5876 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5877 struct drm_i915_gem_object *obj_priv = NULL;
5878
5879 if (dev_priv->pwrctx) {
5880 obj_priv = to_intel_bo(dev_priv->pwrctx);
5881 } else {
5882 struct drm_gem_object *pwrctx;
5883
5884 pwrctx = intel_alloc_context_page(dev);
5885 if (pwrctx) {
5886 dev_priv->pwrctx = pwrctx;
5887 obj_priv = to_intel_bo(pwrctx);
5888 }
5889 }
5890
5891 if (obj_priv) {
5892 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5893 I915_WRITE(MCHBAR_RENDER_STANDBY,
5894 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5895 }
5896 }
5897 }
5898
5899 /* Set up chip specific display functions */
5900 static void intel_init_display(struct drm_device *dev)
5901 {
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903
5904 /* We always want a DPMS function */
5905 if (HAS_PCH_SPLIT(dev))
5906 dev_priv->display.dpms = ironlake_crtc_dpms;
5907 else
5908 dev_priv->display.dpms = i9xx_crtc_dpms;
5909
5910 if (I915_HAS_FBC(dev)) {
5911 if (IS_IRONLAKE_M(dev)) {
5912 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5913 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5914 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5915 } else if (IS_GM45(dev)) {
5916 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5917 dev_priv->display.enable_fbc = g4x_enable_fbc;
5918 dev_priv->display.disable_fbc = g4x_disable_fbc;
5919 } else if (IS_CRESTLINE(dev)) {
5920 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5921 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5922 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5923 }
5924 /* 855GM needs testing */
5925 }
5926
5927 /* Returns the core display clock speed */
5928 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5929 dev_priv->display.get_display_clock_speed =
5930 i945_get_display_clock_speed;
5931 else if (IS_I915G(dev))
5932 dev_priv->display.get_display_clock_speed =
5933 i915_get_display_clock_speed;
5934 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5935 dev_priv->display.get_display_clock_speed =
5936 i9xx_misc_get_display_clock_speed;
5937 else if (IS_I915GM(dev))
5938 dev_priv->display.get_display_clock_speed =
5939 i915gm_get_display_clock_speed;
5940 else if (IS_I865G(dev))
5941 dev_priv->display.get_display_clock_speed =
5942 i865_get_display_clock_speed;
5943 else if (IS_I85X(dev))
5944 dev_priv->display.get_display_clock_speed =
5945 i855_get_display_clock_speed;
5946 else /* 852, 830 */
5947 dev_priv->display.get_display_clock_speed =
5948 i830_get_display_clock_speed;
5949
5950 /* For FIFO watermark updates */
5951 if (HAS_PCH_SPLIT(dev)) {
5952 if (IS_GEN5(dev)) {
5953 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5954 dev_priv->display.update_wm = ironlake_update_wm;
5955 else {
5956 DRM_DEBUG_KMS("Failed to get proper latency. "
5957 "Disable CxSR\n");
5958 dev_priv->display.update_wm = NULL;
5959 }
5960 } else
5961 dev_priv->display.update_wm = NULL;
5962 } else if (IS_PINEVIEW(dev)) {
5963 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5964 dev_priv->is_ddr3,
5965 dev_priv->fsb_freq,
5966 dev_priv->mem_freq)) {
5967 DRM_INFO("failed to find known CxSR latency "
5968 "(found ddr%s fsb freq %d, mem freq %d), "
5969 "disabling CxSR\n",
5970 (dev_priv->is_ddr3 == 1) ? "3": "2",
5971 dev_priv->fsb_freq, dev_priv->mem_freq);
5972 /* Disable CxSR and never update its watermark again */
5973 pineview_disable_cxsr(dev);
5974 dev_priv->display.update_wm = NULL;
5975 } else
5976 dev_priv->display.update_wm = pineview_update_wm;
5977 } else if (IS_G4X(dev))
5978 dev_priv->display.update_wm = g4x_update_wm;
5979 else if (IS_GEN4(dev))
5980 dev_priv->display.update_wm = i965_update_wm;
5981 else if (IS_GEN3(dev)) {
5982 dev_priv->display.update_wm = i9xx_update_wm;
5983 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5984 } else if (IS_I85X(dev)) {
5985 dev_priv->display.update_wm = i9xx_update_wm;
5986 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5987 } else {
5988 dev_priv->display.update_wm = i830_update_wm;
5989 if (IS_845G(dev))
5990 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5991 else
5992 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5993 }
5994 }
5995
5996 /*
5997 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5998 * resume, or other times. This quirk makes sure that's the case for
5999 * affected systems.
6000 */
6001 static void quirk_pipea_force (struct drm_device *dev)
6002 {
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004
6005 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6006 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6007 }
6008
6009 struct intel_quirk {
6010 int device;
6011 int subsystem_vendor;
6012 int subsystem_device;
6013 void (*hook)(struct drm_device *dev);
6014 };
6015
6016 struct intel_quirk intel_quirks[] = {
6017 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6018 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6019 /* HP Mini needs pipe A force quirk (LP: #322104) */
6020 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6021
6022 /* Thinkpad R31 needs pipe A force quirk */
6023 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6024 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6025 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6026
6027 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6028 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6029 /* ThinkPad X40 needs pipe A force quirk */
6030
6031 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6032 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6033
6034 /* 855 & before need to leave pipe A & dpll A up */
6035 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6036 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6037 };
6038
6039 static void intel_init_quirks(struct drm_device *dev)
6040 {
6041 struct pci_dev *d = dev->pdev;
6042 int i;
6043
6044 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6045 struct intel_quirk *q = &intel_quirks[i];
6046
6047 if (d->device == q->device &&
6048 (d->subsystem_vendor == q->subsystem_vendor ||
6049 q->subsystem_vendor == PCI_ANY_ID) &&
6050 (d->subsystem_device == q->subsystem_device ||
6051 q->subsystem_device == PCI_ANY_ID))
6052 q->hook(dev);
6053 }
6054 }
6055
6056 /* Disable the VGA plane that we never use */
6057 static void i915_disable_vga(struct drm_device *dev)
6058 {
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 u8 sr1;
6061 u32 vga_reg;
6062
6063 if (HAS_PCH_SPLIT(dev))
6064 vga_reg = CPU_VGACNTRL;
6065 else
6066 vga_reg = VGACNTRL;
6067
6068 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6069 outb(1, VGA_SR_INDEX);
6070 sr1 = inb(VGA_SR_DATA);
6071 outb(sr1 | 1<<5, VGA_SR_DATA);
6072 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6073 udelay(300);
6074
6075 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6076 POSTING_READ(vga_reg);
6077 }
6078
6079 void intel_modeset_init(struct drm_device *dev)
6080 {
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6082 int i;
6083
6084 drm_mode_config_init(dev);
6085
6086 dev->mode_config.min_width = 0;
6087 dev->mode_config.min_height = 0;
6088
6089 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6090
6091 intel_init_quirks(dev);
6092
6093 intel_init_display(dev);
6094
6095 if (IS_GEN2(dev)) {
6096 dev->mode_config.max_width = 2048;
6097 dev->mode_config.max_height = 2048;
6098 } else if (IS_GEN3(dev)) {
6099 dev->mode_config.max_width = 4096;
6100 dev->mode_config.max_height = 4096;
6101 } else {
6102 dev->mode_config.max_width = 8192;
6103 dev->mode_config.max_height = 8192;
6104 }
6105
6106 /* set memory base */
6107 if (IS_GEN2(dev))
6108 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6109 else
6110 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6111
6112 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6113 dev_priv->num_pipe = 2;
6114 else
6115 dev_priv->num_pipe = 1;
6116 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6117 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6118
6119 for (i = 0; i < dev_priv->num_pipe; i++) {
6120 intel_crtc_init(dev, i);
6121 }
6122
6123 intel_setup_outputs(dev);
6124
6125 intel_init_clock_gating(dev);
6126
6127 /* Just disable it once at startup */
6128 i915_disable_vga(dev);
6129
6130 if (IS_IRONLAKE_M(dev)) {
6131 ironlake_enable_drps(dev);
6132 intel_init_emon(dev);
6133 }
6134
6135 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6136 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6137 (unsigned long)dev);
6138
6139 intel_setup_overlay(dev);
6140 }
6141
6142 void intel_modeset_cleanup(struct drm_device *dev)
6143 {
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145 struct drm_crtc *crtc;
6146 struct intel_crtc *intel_crtc;
6147
6148 drm_kms_helper_poll_fini(dev);
6149 mutex_lock(&dev->struct_mutex);
6150
6151 intel_unregister_dsm_handler();
6152
6153
6154 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6155 /* Skip inactive CRTCs */
6156 if (!crtc->fb)
6157 continue;
6158
6159 intel_crtc = to_intel_crtc(crtc);
6160 intel_increase_pllclock(crtc);
6161 }
6162
6163 if (dev_priv->display.disable_fbc)
6164 dev_priv->display.disable_fbc(dev);
6165
6166 if (dev_priv->renderctx) {
6167 struct drm_i915_gem_object *obj_priv;
6168
6169 obj_priv = to_intel_bo(dev_priv->renderctx);
6170 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6171 I915_READ(CCID);
6172 i915_gem_object_unpin(dev_priv->renderctx);
6173 drm_gem_object_unreference(dev_priv->renderctx);
6174 }
6175
6176 if (dev_priv->pwrctx) {
6177 struct drm_i915_gem_object *obj_priv;
6178
6179 obj_priv = to_intel_bo(dev_priv->pwrctx);
6180 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6181 I915_READ(PWRCTXA);
6182 i915_gem_object_unpin(dev_priv->pwrctx);
6183 drm_gem_object_unreference(dev_priv->pwrctx);
6184 }
6185
6186 if (IS_IRONLAKE_M(dev))
6187 ironlake_disable_drps(dev);
6188
6189 mutex_unlock(&dev->struct_mutex);
6190
6191 /* Disable the irq before mode object teardown, for the irq might
6192 * enqueue unpin/hotplug work. */
6193 drm_irq_uninstall(dev);
6194 cancel_work_sync(&dev_priv->hotplug_work);
6195
6196 /* Shut off idle work before the crtcs get freed. */
6197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6198 intel_crtc = to_intel_crtc(crtc);
6199 del_timer_sync(&intel_crtc->idle_timer);
6200 }
6201 del_timer_sync(&dev_priv->idle_timer);
6202 cancel_work_sync(&dev_priv->idle_work);
6203
6204 drm_mode_config_cleanup(dev);
6205 }
6206
6207 /*
6208 * Return which encoder is currently attached for connector.
6209 */
6210 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6211 {
6212 return &intel_attached_encoder(connector)->base;
6213 }
6214
6215 void intel_connector_attach_encoder(struct intel_connector *connector,
6216 struct intel_encoder *encoder)
6217 {
6218 connector->encoder = encoder;
6219 drm_mode_connector_attach_encoder(&connector->base,
6220 &encoder->base);
6221 }
6222
6223 /*
6224 * set vga decode state - true == enable VGA decode
6225 */
6226 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6227 {
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 u16 gmch_ctrl;
6230
6231 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6232 if (state)
6233 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6234 else
6235 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6236 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6237 return 0;
6238 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree