2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
181 (start
& (PAGE_SIZE
- 1)) != 0 ||
182 (end
& (PAGE_SIZE
- 1)) != 0) {
186 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
189 dev_priv
->mm
.gtt_total
= end
- start
;
195 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
196 struct drm_file
*file_priv
)
198 struct drm_i915_gem_init
*args
= data
;
201 mutex_lock(&dev
->struct_mutex
);
202 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
203 mutex_unlock(&dev
->struct_mutex
);
209 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*file_priv
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct drm_i915_gem_get_aperture
*args
= data
;
215 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
218 mutex_lock(&dev
->struct_mutex
);
219 args
->aper_size
= dev_priv
->mm
.gtt_total
;
220 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
221 mutex_unlock(&dev
->struct_mutex
);
228 * Creates a new mm object and returns a handle to it.
231 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_gem_create
*args
= data
;
235 struct drm_gem_object
*obj
;
239 args
->size
= roundup(args
->size
, PAGE_SIZE
);
241 /* Allocate the new object */
242 obj
= i915_gem_alloc_object(dev
, args
->size
);
246 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
248 drm_gem_object_release(obj
);
249 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
254 /* drop reference from allocate - handle holds it now */
255 drm_gem_object_unreference(obj
);
256 trace_i915_gem_object_create(obj
);
258 args
->handle
= handle
;
263 fast_shmem_read(struct page
**pages
,
264 loff_t page_base
, int page_offset
,
271 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
]);
272 ret
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
273 kunmap_atomic(vaddr
);
278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
280 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
283 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
284 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
288 slow_shmem_copy(struct page
*dst_page
,
290 struct page
*src_page
,
294 char *dst_vaddr
, *src_vaddr
;
296 dst_vaddr
= kmap(dst_page
);
297 src_vaddr
= kmap(src_page
);
299 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
306 slow_shmem_bit17_copy(struct page
*gpu_page
,
308 struct page
*cpu_page
,
313 char *gpu_vaddr
, *cpu_vaddr
;
315 /* Use the unswizzled path if this page isn't affected. */
316 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
318 return slow_shmem_copy(cpu_page
, cpu_offset
,
319 gpu_page
, gpu_offset
, length
);
321 return slow_shmem_copy(gpu_page
, gpu_offset
,
322 cpu_page
, cpu_offset
, length
);
325 gpu_vaddr
= kmap(gpu_page
);
326 cpu_vaddr
= kmap(cpu_page
);
328 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
329 * XORing with the other bits (A9 for Y, A9 and A10 for X)
332 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
333 int this_length
= min(cacheline_end
- gpu_offset
, length
);
334 int swizzled_gpu_offset
= gpu_offset
^ 64;
337 memcpy(cpu_vaddr
+ cpu_offset
,
338 gpu_vaddr
+ swizzled_gpu_offset
,
341 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
342 cpu_vaddr
+ cpu_offset
,
345 cpu_offset
+= this_length
;
346 gpu_offset
+= this_length
;
347 length
-= this_length
;
355 * This is the fast shmem pread path, which attempts to copy_from_user directly
356 * from the backing pages of the object to the user's address space. On a
357 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
360 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
361 struct drm_i915_gem_pread
*args
,
362 struct drm_file
*file_priv
)
364 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
366 loff_t offset
, page_base
;
367 char __user
*user_data
;
368 int page_offset
, page_length
;
370 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
373 obj_priv
= to_intel_bo(obj
);
374 offset
= args
->offset
;
377 /* Operation in this page
379 * page_base = page offset within aperture
380 * page_offset = offset within page
381 * page_length = bytes to copy for this page
383 page_base
= (offset
& ~(PAGE_SIZE
-1));
384 page_offset
= offset
& (PAGE_SIZE
-1);
385 page_length
= remain
;
386 if ((page_offset
+ remain
) > PAGE_SIZE
)
387 page_length
= PAGE_SIZE
- page_offset
;
389 if (fast_shmem_read(obj_priv
->pages
,
390 page_base
, page_offset
,
391 user_data
, page_length
))
394 remain
-= page_length
;
395 user_data
+= page_length
;
396 offset
+= page_length
;
403 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
407 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
409 /* If we've insufficient memory to map in the pages, attempt
410 * to make some space by throwing out some old buffers.
412 if (ret
== -ENOMEM
) {
413 struct drm_device
*dev
= obj
->dev
;
415 ret
= i915_gem_evict_something(dev
, obj
->size
,
416 i915_gem_get_gtt_alignment(obj
));
420 ret
= i915_gem_object_get_pages(obj
, 0);
427 * This is the fallback shmem pread path, which allocates temporary storage
428 * in kernel space to copy_to_user into outside of the struct_mutex, so we
429 * can copy out of the object's backing pages while holding the struct mutex
430 * and not take page faults.
433 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
434 struct drm_i915_gem_pread
*args
,
435 struct drm_file
*file_priv
)
437 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
438 struct mm_struct
*mm
= current
->mm
;
439 struct page
**user_pages
;
441 loff_t offset
, pinned_pages
, i
;
442 loff_t first_data_page
, last_data_page
, num_pages
;
443 int shmem_page_index
, shmem_page_offset
;
444 int data_page_index
, data_page_offset
;
447 uint64_t data_ptr
= args
->data_ptr
;
448 int do_bit17_swizzling
;
452 /* Pin the user pages containing the data. We can't fault while
453 * holding the struct mutex, yet we want to hold it while
454 * dereferencing the user data.
456 first_data_page
= data_ptr
/ PAGE_SIZE
;
457 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
458 num_pages
= last_data_page
- first_data_page
+ 1;
460 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
461 if (user_pages
== NULL
)
464 mutex_unlock(&dev
->struct_mutex
);
465 down_read(&mm
->mmap_sem
);
466 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
467 num_pages
, 1, 0, user_pages
, NULL
);
468 up_read(&mm
->mmap_sem
);
469 mutex_lock(&dev
->struct_mutex
);
470 if (pinned_pages
< num_pages
) {
475 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
481 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
483 obj_priv
= to_intel_bo(obj
);
484 offset
= args
->offset
;
487 /* Operation in this page
489 * shmem_page_index = page number within shmem file
490 * shmem_page_offset = offset within page in shmem file
491 * data_page_index = page number in get_user_pages return
492 * data_page_offset = offset with data_page_index page.
493 * page_length = bytes to copy for this page
495 shmem_page_index
= offset
/ PAGE_SIZE
;
496 shmem_page_offset
= offset
& ~PAGE_MASK
;
497 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
498 data_page_offset
= data_ptr
& ~PAGE_MASK
;
500 page_length
= remain
;
501 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
502 page_length
= PAGE_SIZE
- shmem_page_offset
;
503 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
504 page_length
= PAGE_SIZE
- data_page_offset
;
506 if (do_bit17_swizzling
) {
507 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
509 user_pages
[data_page_index
],
514 slow_shmem_copy(user_pages
[data_page_index
],
516 obj_priv
->pages
[shmem_page_index
],
521 remain
-= page_length
;
522 data_ptr
+= page_length
;
523 offset
+= page_length
;
527 for (i
= 0; i
< pinned_pages
; i
++) {
528 SetPageDirty(user_pages
[i
]);
529 page_cache_release(user_pages
[i
]);
531 drm_free_large(user_pages
);
537 * Reads data from the object referenced by handle.
539 * On error, the contents of *data are undefined.
542 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
543 struct drm_file
*file_priv
)
545 struct drm_i915_gem_pread
*args
= data
;
546 struct drm_gem_object
*obj
;
547 struct drm_i915_gem_object
*obj_priv
;
550 ret
= i915_mutex_lock_interruptible(dev
);
554 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
559 obj_priv
= to_intel_bo(obj
);
561 /* Bounds check source. */
562 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
570 if (!access_ok(VERIFY_WRITE
,
571 (char __user
*)(uintptr_t)args
->data_ptr
,
577 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
584 ret
= i915_gem_object_get_pages_or_evict(obj
);
588 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
595 if (!i915_gem_object_needs_bit17_swizzle(obj
))
596 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
598 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
601 i915_gem_object_put_pages(obj
);
603 drm_gem_object_unreference(obj
);
605 mutex_unlock(&dev
->struct_mutex
);
609 /* This is the fast write path which cannot handle
610 * page faults in the source data
614 fast_user_write(struct io_mapping
*mapping
,
615 loff_t page_base
, int page_offset
,
616 char __user
*user_data
,
620 unsigned long unwritten
;
622 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
623 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
625 io_mapping_unmap_atomic(vaddr_atomic
);
629 /* Here's the write path which can sleep for
634 slow_kernel_write(struct io_mapping
*mapping
,
635 loff_t gtt_base
, int gtt_offset
,
636 struct page
*user_page
, int user_offset
,
639 char __iomem
*dst_vaddr
;
642 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
643 src_vaddr
= kmap(user_page
);
645 memcpy_toio(dst_vaddr
+ gtt_offset
,
646 src_vaddr
+ user_offset
,
650 io_mapping_unmap(dst_vaddr
);
654 fast_shmem_write(struct page
**pages
,
655 loff_t page_base
, int page_offset
,
662 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
]);
663 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
664 kunmap_atomic(vaddr
);
670 * This is the fast pwrite path, where we copy the data directly from the
671 * user into the GTT, uncached.
674 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
675 struct drm_i915_gem_pwrite
*args
,
676 struct drm_file
*file_priv
)
678 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
681 loff_t offset
, page_base
;
682 char __user
*user_data
;
683 int page_offset
, page_length
;
685 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
688 obj_priv
= to_intel_bo(obj
);
689 offset
= obj_priv
->gtt_offset
+ args
->offset
;
692 /* Operation in this page
694 * page_base = page offset within aperture
695 * page_offset = offset within page
696 * page_length = bytes to copy for this page
698 page_base
= (offset
& ~(PAGE_SIZE
-1));
699 page_offset
= offset
& (PAGE_SIZE
-1);
700 page_length
= remain
;
701 if ((page_offset
+ remain
) > PAGE_SIZE
)
702 page_length
= PAGE_SIZE
- page_offset
;
704 /* If we get a fault while copying data, then (presumably) our
705 * source page isn't available. Return the error and we'll
706 * retry in the slow path.
708 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
709 page_offset
, user_data
, page_length
))
713 remain
-= page_length
;
714 user_data
+= page_length
;
715 offset
+= page_length
;
722 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
723 * the memory and maps it using kmap_atomic for copying.
725 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
726 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
729 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
730 struct drm_i915_gem_pwrite
*args
,
731 struct drm_file
*file_priv
)
733 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
734 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
736 loff_t gtt_page_base
, offset
;
737 loff_t first_data_page
, last_data_page
, num_pages
;
738 loff_t pinned_pages
, i
;
739 struct page
**user_pages
;
740 struct mm_struct
*mm
= current
->mm
;
741 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
743 uint64_t data_ptr
= args
->data_ptr
;
747 /* Pin the user pages containing the data. We can't fault while
748 * holding the struct mutex, and all of the pwrite implementations
749 * want to hold it while dereferencing the user data.
751 first_data_page
= data_ptr
/ PAGE_SIZE
;
752 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
753 num_pages
= last_data_page
- first_data_page
+ 1;
755 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
756 if (user_pages
== NULL
)
759 mutex_unlock(&dev
->struct_mutex
);
760 down_read(&mm
->mmap_sem
);
761 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
762 num_pages
, 0, 0, user_pages
, NULL
);
763 up_read(&mm
->mmap_sem
);
764 mutex_lock(&dev
->struct_mutex
);
765 if (pinned_pages
< num_pages
) {
767 goto out_unpin_pages
;
770 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
772 goto out_unpin_pages
;
774 obj_priv
= to_intel_bo(obj
);
775 offset
= obj_priv
->gtt_offset
+ args
->offset
;
778 /* Operation in this page
780 * gtt_page_base = page offset within aperture
781 * gtt_page_offset = offset within page in aperture
782 * data_page_index = page number in get_user_pages return
783 * data_page_offset = offset with data_page_index page.
784 * page_length = bytes to copy for this page
786 gtt_page_base
= offset
& PAGE_MASK
;
787 gtt_page_offset
= offset
& ~PAGE_MASK
;
788 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
789 data_page_offset
= data_ptr
& ~PAGE_MASK
;
791 page_length
= remain
;
792 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
793 page_length
= PAGE_SIZE
- gtt_page_offset
;
794 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
795 page_length
= PAGE_SIZE
- data_page_offset
;
797 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
798 gtt_page_base
, gtt_page_offset
,
799 user_pages
[data_page_index
],
803 remain
-= page_length
;
804 offset
+= page_length
;
805 data_ptr
+= page_length
;
809 for (i
= 0; i
< pinned_pages
; i
++)
810 page_cache_release(user_pages
[i
]);
811 drm_free_large(user_pages
);
817 * This is the fast shmem pwrite path, which attempts to directly
818 * copy_from_user into the kmapped pages backing the object.
821 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
822 struct drm_i915_gem_pwrite
*args
,
823 struct drm_file
*file_priv
)
825 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
827 loff_t offset
, page_base
;
828 char __user
*user_data
;
829 int page_offset
, page_length
;
831 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
834 obj_priv
= to_intel_bo(obj
);
835 offset
= args
->offset
;
839 /* Operation in this page
841 * page_base = page offset within aperture
842 * page_offset = offset within page
843 * page_length = bytes to copy for this page
845 page_base
= (offset
& ~(PAGE_SIZE
-1));
846 page_offset
= offset
& (PAGE_SIZE
-1);
847 page_length
= remain
;
848 if ((page_offset
+ remain
) > PAGE_SIZE
)
849 page_length
= PAGE_SIZE
- page_offset
;
851 if (fast_shmem_write(obj_priv
->pages
,
852 page_base
, page_offset
,
853 user_data
, page_length
))
856 remain
-= page_length
;
857 user_data
+= page_length
;
858 offset
+= page_length
;
865 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
866 * the memory and maps it using kmap_atomic for copying.
868 * This avoids taking mmap_sem for faulting on the user's address while the
869 * struct_mutex is held.
872 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
873 struct drm_i915_gem_pwrite
*args
,
874 struct drm_file
*file_priv
)
876 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
877 struct mm_struct
*mm
= current
->mm
;
878 struct page
**user_pages
;
880 loff_t offset
, pinned_pages
, i
;
881 loff_t first_data_page
, last_data_page
, num_pages
;
882 int shmem_page_index
, shmem_page_offset
;
883 int data_page_index
, data_page_offset
;
886 uint64_t data_ptr
= args
->data_ptr
;
887 int do_bit17_swizzling
;
891 /* Pin the user pages containing the data. We can't fault while
892 * holding the struct mutex, and all of the pwrite implementations
893 * want to hold it while dereferencing the user data.
895 first_data_page
= data_ptr
/ PAGE_SIZE
;
896 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
897 num_pages
= last_data_page
- first_data_page
+ 1;
899 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
900 if (user_pages
== NULL
)
903 mutex_unlock(&dev
->struct_mutex
);
904 down_read(&mm
->mmap_sem
);
905 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
906 num_pages
, 0, 0, user_pages
, NULL
);
907 up_read(&mm
->mmap_sem
);
908 mutex_lock(&dev
->struct_mutex
);
909 if (pinned_pages
< num_pages
) {
914 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
918 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
920 obj_priv
= to_intel_bo(obj
);
921 offset
= args
->offset
;
925 /* Operation in this page
927 * shmem_page_index = page number within shmem file
928 * shmem_page_offset = offset within page in shmem file
929 * data_page_index = page number in get_user_pages return
930 * data_page_offset = offset with data_page_index page.
931 * page_length = bytes to copy for this page
933 shmem_page_index
= offset
/ PAGE_SIZE
;
934 shmem_page_offset
= offset
& ~PAGE_MASK
;
935 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
936 data_page_offset
= data_ptr
& ~PAGE_MASK
;
938 page_length
= remain
;
939 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
940 page_length
= PAGE_SIZE
- shmem_page_offset
;
941 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
942 page_length
= PAGE_SIZE
- data_page_offset
;
944 if (do_bit17_swizzling
) {
945 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
947 user_pages
[data_page_index
],
952 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
954 user_pages
[data_page_index
],
959 remain
-= page_length
;
960 data_ptr
+= page_length
;
961 offset
+= page_length
;
965 for (i
= 0; i
< pinned_pages
; i
++)
966 page_cache_release(user_pages
[i
]);
967 drm_free_large(user_pages
);
973 * Writes data to the object referenced by handle.
975 * On error, the contents of the buffer that were to be modified are undefined.
978 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
979 struct drm_file
*file
)
981 struct drm_i915_gem_pwrite
*args
= data
;
982 struct drm_gem_object
*obj
;
983 struct drm_i915_gem_object
*obj_priv
;
986 ret
= i915_mutex_lock_interruptible(dev
);
990 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
995 obj_priv
= to_intel_bo(obj
);
998 /* Bounds check destination. */
999 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1004 if (args
->size
== 0)
1007 if (!access_ok(VERIFY_READ
,
1008 (char __user
*)(uintptr_t)args
->data_ptr
,
1014 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1021 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1022 * it would end up going through the fenced access, and we'll get
1023 * different detiling behavior between reading and writing.
1024 * pread/pwrite currently are reading and writing from the CPU
1025 * perspective, requiring manual detiling by the client.
1027 if (obj_priv
->phys_obj
)
1028 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1029 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1030 obj_priv
->gtt_space
&&
1031 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1032 ret
= i915_gem_object_pin(obj
, 0);
1036 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1040 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1042 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1045 i915_gem_object_unpin(obj
);
1047 ret
= i915_gem_object_get_pages_or_evict(obj
);
1051 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1056 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1057 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1059 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1062 i915_gem_object_put_pages(obj
);
1066 drm_gem_object_unreference(obj
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space prepares to use an object with the CPU, either
1074 * through the mmap ioctl's mapping or a GTT mapping.
1077 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1078 struct drm_file
*file_priv
)
1080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1081 struct drm_i915_gem_set_domain
*args
= data
;
1082 struct drm_gem_object
*obj
;
1083 struct drm_i915_gem_object
*obj_priv
;
1084 uint32_t read_domains
= args
->read_domains
;
1085 uint32_t write_domain
= args
->write_domain
;
1088 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1091 /* Only handle setting domains to types used by the CPU. */
1092 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1095 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1098 /* Having something in the write domain implies it's in the read
1099 * domain, and only that read domain. Enforce that in the request.
1101 if (write_domain
!= 0 && read_domains
!= write_domain
)
1104 ret
= i915_mutex_lock_interruptible(dev
);
1108 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1113 obj_priv
= to_intel_bo(obj
);
1115 intel_mark_busy(dev
, obj
);
1117 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1118 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1120 /* Update the LRU on the fence for the CPU access that's
1123 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1124 struct drm_i915_fence_reg
*reg
=
1125 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1126 list_move_tail(®
->lru_list
,
1127 &dev_priv
->mm
.fence_list
);
1130 /* Silently promote "you're not bound, there was nothing to do"
1131 * to success, since the client was just asking us to
1132 * make sure everything was done.
1137 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1140 /* Maintain LRU order of "inactive" objects */
1141 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1142 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1144 drm_gem_object_unreference(obj
);
1146 mutex_unlock(&dev
->struct_mutex
);
1151 * Called when user space has done writes to this buffer
1154 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1155 struct drm_file
*file_priv
)
1157 struct drm_i915_gem_sw_finish
*args
= data
;
1158 struct drm_gem_object
*obj
;
1161 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1164 ret
= i915_mutex_lock_interruptible(dev
);
1168 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1174 /* Pinned buffers may be scanout, so flush the cache */
1175 if (to_intel_bo(obj
)->pin_count
)
1176 i915_gem_object_flush_cpu_write_domain(obj
);
1178 drm_gem_object_unreference(obj
);
1180 mutex_unlock(&dev
->struct_mutex
);
1185 * Maps the contents of an object, returning the address it is mapped
1188 * While the mapping holds a reference on the contents of the object, it doesn't
1189 * imply a ref on the object itself.
1192 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1193 struct drm_file
*file_priv
)
1195 struct drm_i915_gem_mmap
*args
= data
;
1196 struct drm_gem_object
*obj
;
1200 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1203 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1207 offset
= args
->offset
;
1209 down_write(¤t
->mm
->mmap_sem
);
1210 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1211 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1213 up_write(¤t
->mm
->mmap_sem
);
1214 drm_gem_object_unreference_unlocked(obj
);
1215 if (IS_ERR((void *)addr
))
1218 args
->addr_ptr
= (uint64_t) addr
;
1224 * i915_gem_fault - fault a page into the GTT
1225 * vma: VMA in question
1228 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1229 * from userspace. The fault handler takes care of binding the object to
1230 * the GTT (if needed), allocating and programming a fence register (again,
1231 * only if needed based on whether the old reg is still valid or the object
1232 * is tiled) and inserting a new PTE into the faulting process.
1234 * Note that the faulting process may involve evicting existing objects
1235 * from the GTT and/or fence registers to make room. So performance may
1236 * suffer if the GTT working set is large or there are few fence registers
1239 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1241 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1242 struct drm_device
*dev
= obj
->dev
;
1243 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1244 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1245 pgoff_t page_offset
;
1248 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1250 /* We don't use vmf->pgoff since that has the fake offset */
1251 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1254 /* Now bind it into the GTT if needed */
1255 mutex_lock(&dev
->struct_mutex
);
1256 if (!obj_priv
->gtt_space
) {
1257 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1261 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1266 /* Need a new fence register? */
1267 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1268 ret
= i915_gem_object_get_fence_reg(obj
, true);
1273 if (i915_gem_object_is_inactive(obj_priv
))
1274 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1276 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1279 /* Finally, remap it using the new GTT offset */
1280 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1282 mutex_unlock(&dev
->struct_mutex
);
1287 return VM_FAULT_NOPAGE
;
1290 return VM_FAULT_OOM
;
1292 return VM_FAULT_SIGBUS
;
1297 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1298 * @obj: obj in question
1300 * GEM memory mapping works by handing back to userspace a fake mmap offset
1301 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1302 * up the object based on the offset and sets up the various memory mapping
1305 * This routine allocates and attaches a fake offset for @obj.
1308 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1310 struct drm_device
*dev
= obj
->dev
;
1311 struct drm_gem_mm
*mm
= dev
->mm_private
;
1312 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1313 struct drm_map_list
*list
;
1314 struct drm_local_map
*map
;
1317 /* Set the object up for mmap'ing */
1318 list
= &obj
->map_list
;
1319 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1324 map
->type
= _DRM_GEM
;
1325 map
->size
= obj
->size
;
1328 /* Get a DRM GEM mmap offset allocated... */
1329 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1330 obj
->size
/ PAGE_SIZE
, 0, 0);
1331 if (!list
->file_offset_node
) {
1332 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1337 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1338 obj
->size
/ PAGE_SIZE
, 0);
1339 if (!list
->file_offset_node
) {
1344 list
->hash
.key
= list
->file_offset_node
->start
;
1345 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1347 DRM_ERROR("failed to add to map hash\n");
1351 /* By now we should be all set, any drm_mmap request on the offset
1352 * below will get to our mmap & fault handler */
1353 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1358 drm_mm_put_block(list
->file_offset_node
);
1366 * i915_gem_release_mmap - remove physical page mappings
1367 * @obj: obj in question
1369 * Preserve the reservation of the mmapping with the DRM core code, but
1370 * relinquish ownership of the pages back to the system.
1372 * It is vital that we remove the page mapping if we have mapped a tiled
1373 * object through the GTT and then lose the fence register due to
1374 * resource pressure. Similarly if the object has been moved out of the
1375 * aperture, than pages mapped into userspace must be revoked. Removing the
1376 * mapping will then trigger a page fault on the next user access, allowing
1377 * fixup by i915_gem_fault().
1380 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1382 struct drm_device
*dev
= obj
->dev
;
1383 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1385 if (dev
->dev_mapping
)
1386 unmap_mapping_range(dev
->dev_mapping
,
1387 obj_priv
->mmap_offset
, obj
->size
, 1);
1391 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1393 struct drm_device
*dev
= obj
->dev
;
1394 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1395 struct drm_gem_mm
*mm
= dev
->mm_private
;
1396 struct drm_map_list
*list
;
1398 list
= &obj
->map_list
;
1399 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1401 if (list
->file_offset_node
) {
1402 drm_mm_put_block(list
->file_offset_node
);
1403 list
->file_offset_node
= NULL
;
1411 obj_priv
->mmap_offset
= 0;
1415 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1416 * @obj: object to check
1418 * Return the required GTT alignment for an object, taking into account
1419 * potential fence register mapping if needed.
1422 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1424 struct drm_device
*dev
= obj
->dev
;
1425 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1429 * Minimum alignment is 4k (GTT page size), but might be greater
1430 * if a fence register is needed for the object.
1432 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1436 * Previous chips need to be aligned to the size of the smallest
1437 * fence register that can contain the object.
1439 if (INTEL_INFO(dev
)->gen
== 3)
1444 for (i
= start
; i
< obj
->size
; i
<<= 1)
1451 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1453 * @data: GTT mapping ioctl data
1454 * @file_priv: GEM object info
1456 * Simply returns the fake offset to userspace so it can mmap it.
1457 * The mmap call will end up in drm_gem_mmap(), which will set things
1458 * up so we can get faults in the handler above.
1460 * The fault handler will take care of binding the object into the GTT
1461 * (since it may have been evicted to make room for something), allocating
1462 * a fence register, and mapping the appropriate aperture address into
1466 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1467 struct drm_file
*file_priv
)
1469 struct drm_i915_gem_mmap_gtt
*args
= data
;
1470 struct drm_gem_object
*obj
;
1471 struct drm_i915_gem_object
*obj_priv
;
1474 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1477 ret
= i915_mutex_lock_interruptible(dev
);
1481 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1486 obj_priv
= to_intel_bo(obj
);
1488 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1489 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1494 if (!obj_priv
->mmap_offset
) {
1495 ret
= i915_gem_create_mmap_offset(obj
);
1500 args
->offset
= obj_priv
->mmap_offset
;
1503 * Pull it into the GTT so that we have a page list (makes the
1504 * initial fault faster and any subsequent flushing possible).
1506 if (!obj_priv
->agp_mem
) {
1507 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1513 drm_gem_object_unreference(obj
);
1515 mutex_unlock(&dev
->struct_mutex
);
1520 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1523 int page_count
= obj
->size
/ PAGE_SIZE
;
1526 BUG_ON(obj_priv
->pages_refcount
== 0);
1527 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1529 if (--obj_priv
->pages_refcount
!= 0)
1532 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1533 i915_gem_object_save_bit_17_swizzle(obj
);
1535 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1536 obj_priv
->dirty
= 0;
1538 for (i
= 0; i
< page_count
; i
++) {
1539 if (obj_priv
->dirty
)
1540 set_page_dirty(obj_priv
->pages
[i
]);
1542 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1543 mark_page_accessed(obj_priv
->pages
[i
]);
1545 page_cache_release(obj_priv
->pages
[i
]);
1547 obj_priv
->dirty
= 0;
1549 drm_free_large(obj_priv
->pages
);
1550 obj_priv
->pages
= NULL
;
1554 i915_gem_next_request_seqno(struct drm_device
*dev
,
1555 struct intel_ring_buffer
*ring
)
1557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1559 ring
->outstanding_lazy_request
= true;
1560 return dev_priv
->next_seqno
;
1564 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1565 struct intel_ring_buffer
*ring
)
1567 struct drm_device
*dev
= obj
->dev
;
1568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1569 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1570 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1572 BUG_ON(ring
== NULL
);
1573 obj_priv
->ring
= ring
;
1575 /* Add a reference if we're newly entering the active list. */
1576 if (!obj_priv
->active
) {
1577 drm_gem_object_reference(obj
);
1578 obj_priv
->active
= 1;
1581 /* Move from whatever list we were on to the tail of execution. */
1582 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1583 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1584 obj_priv
->last_rendering_seqno
= seqno
;
1588 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1590 struct drm_device
*dev
= obj
->dev
;
1591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1592 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1594 BUG_ON(!obj_priv
->active
);
1595 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1596 list_del_init(&obj_priv
->ring_list
);
1597 obj_priv
->last_rendering_seqno
= 0;
1600 /* Immediately discard the backing storage */
1602 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1604 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1605 struct inode
*inode
;
1607 /* Our goal here is to return as much of the memory as
1608 * is possible back to the system as we are called from OOM.
1609 * To do this we must instruct the shmfs to drop all of its
1610 * backing pages, *now*. Here we mirror the actions taken
1611 * when by shmem_delete_inode() to release the backing store.
1613 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1614 truncate_inode_pages(inode
->i_mapping
, 0);
1615 if (inode
->i_op
->truncate_range
)
1616 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1618 obj_priv
->madv
= __I915_MADV_PURGED
;
1622 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1624 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1628 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1630 struct drm_device
*dev
= obj
->dev
;
1631 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1632 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1634 if (obj_priv
->pin_count
!= 0)
1635 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1637 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1638 list_del_init(&obj_priv
->ring_list
);
1640 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1642 obj_priv
->last_rendering_seqno
= 0;
1643 obj_priv
->ring
= NULL
;
1644 if (obj_priv
->active
) {
1645 obj_priv
->active
= 0;
1646 drm_gem_object_unreference(obj
);
1648 WARN_ON(i915_verify_lists(dev
));
1652 i915_gem_process_flushing_list(struct drm_device
*dev
,
1653 uint32_t flush_domains
,
1654 struct intel_ring_buffer
*ring
)
1656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1657 struct drm_i915_gem_object
*obj_priv
, *next
;
1659 list_for_each_entry_safe(obj_priv
, next
,
1660 &ring
->gpu_write_list
,
1662 struct drm_gem_object
*obj
= &obj_priv
->base
;
1664 if (obj
->write_domain
& flush_domains
) {
1665 uint32_t old_write_domain
= obj
->write_domain
;
1667 obj
->write_domain
= 0;
1668 list_del_init(&obj_priv
->gpu_write_list
);
1669 i915_gem_object_move_to_active(obj
, ring
);
1671 /* update the fence lru list */
1672 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1673 struct drm_i915_fence_reg
*reg
=
1674 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1675 list_move_tail(®
->lru_list
,
1676 &dev_priv
->mm
.fence_list
);
1679 trace_i915_gem_object_change_domain(obj
,
1687 i915_add_request(struct drm_device
*dev
,
1688 struct drm_file
*file
,
1689 struct drm_i915_gem_request
*request
,
1690 struct intel_ring_buffer
*ring
)
1692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1693 struct drm_i915_file_private
*file_priv
= NULL
;
1698 file_priv
= file
->driver_priv
;
1700 if (request
== NULL
) {
1701 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1702 if (request
== NULL
)
1706 seqno
= ring
->add_request(ring
, 0);
1707 ring
->outstanding_lazy_request
= false;
1709 request
->seqno
= seqno
;
1710 request
->ring
= ring
;
1711 request
->emitted_jiffies
= jiffies
;
1712 was_empty
= list_empty(&ring
->request_list
);
1713 list_add_tail(&request
->list
, &ring
->request_list
);
1716 spin_lock(&file_priv
->mm
.lock
);
1717 request
->file_priv
= file_priv
;
1718 list_add_tail(&request
->client_list
,
1719 &file_priv
->mm
.request_list
);
1720 spin_unlock(&file_priv
->mm
.lock
);
1723 if (!dev_priv
->mm
.suspended
) {
1724 mod_timer(&dev_priv
->hangcheck_timer
,
1725 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1727 queue_delayed_work(dev_priv
->wq
,
1728 &dev_priv
->mm
.retire_work
, HZ
);
1734 * Command execution barrier
1736 * Ensures that all commands in the ring are finished
1737 * before signalling the CPU
1740 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1742 uint32_t flush_domains
= 0;
1744 /* The sampler always gets flushed on i965 (sigh) */
1745 if (INTEL_INFO(dev
)->gen
>= 4)
1746 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1748 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1752 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1754 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1759 spin_lock(&file_priv
->mm
.lock
);
1760 list_del(&request
->client_list
);
1761 request
->file_priv
= NULL
;
1762 spin_unlock(&file_priv
->mm
.lock
);
1765 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1766 struct intel_ring_buffer
*ring
)
1768 while (!list_empty(&ring
->request_list
)) {
1769 struct drm_i915_gem_request
*request
;
1771 request
= list_first_entry(&ring
->request_list
,
1772 struct drm_i915_gem_request
,
1775 list_del(&request
->list
);
1776 i915_gem_request_remove_from_client(request
);
1780 while (!list_empty(&ring
->active_list
)) {
1781 struct drm_i915_gem_object
*obj_priv
;
1783 obj_priv
= list_first_entry(&ring
->active_list
,
1784 struct drm_i915_gem_object
,
1787 obj_priv
->base
.write_domain
= 0;
1788 list_del_init(&obj_priv
->gpu_write_list
);
1789 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1793 void i915_gem_reset(struct drm_device
*dev
)
1795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1796 struct drm_i915_gem_object
*obj_priv
;
1799 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1800 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1801 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1803 /* Remove anything from the flushing lists. The GPU cache is likely
1804 * to be lost on reset along with the data, so simply move the
1805 * lost bo to the inactive list.
1807 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1808 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1809 struct drm_i915_gem_object
,
1812 obj_priv
->base
.write_domain
= 0;
1813 list_del_init(&obj_priv
->gpu_write_list
);
1814 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1817 /* Move everything out of the GPU domains to ensure we do any
1818 * necessary invalidation upon reuse.
1820 list_for_each_entry(obj_priv
,
1821 &dev_priv
->mm
.inactive_list
,
1824 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1827 /* The fence registers are invalidated so clear them out */
1828 for (i
= 0; i
< 16; i
++) {
1829 struct drm_i915_fence_reg
*reg
;
1831 reg
= &dev_priv
->fence_regs
[i
];
1835 i915_gem_clear_fence_reg(reg
->obj
);
1840 * This function clears the request list as sequence numbers are passed.
1843 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1844 struct intel_ring_buffer
*ring
)
1846 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1849 if (!ring
->status_page
.page_addr
||
1850 list_empty(&ring
->request_list
))
1853 WARN_ON(i915_verify_lists(dev
));
1855 seqno
= ring
->get_seqno(ring
);
1856 while (!list_empty(&ring
->request_list
)) {
1857 struct drm_i915_gem_request
*request
;
1859 request
= list_first_entry(&ring
->request_list
,
1860 struct drm_i915_gem_request
,
1863 if (!i915_seqno_passed(seqno
, request
->seqno
))
1866 trace_i915_gem_request_retire(dev
, request
->seqno
);
1868 list_del(&request
->list
);
1869 i915_gem_request_remove_from_client(request
);
1873 /* Move any buffers on the active list that are no longer referenced
1874 * by the ringbuffer to the flushing/inactive lists as appropriate.
1876 while (!list_empty(&ring
->active_list
)) {
1877 struct drm_gem_object
*obj
;
1878 struct drm_i915_gem_object
*obj_priv
;
1880 obj_priv
= list_first_entry(&ring
->active_list
,
1881 struct drm_i915_gem_object
,
1884 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1887 obj
= &obj_priv
->base
;
1888 if (obj
->write_domain
!= 0)
1889 i915_gem_object_move_to_flushing(obj
);
1891 i915_gem_object_move_to_inactive(obj
);
1894 if (unlikely (dev_priv
->trace_irq_seqno
&&
1895 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1896 ring
->user_irq_put(ring
);
1897 dev_priv
->trace_irq_seqno
= 0;
1900 WARN_ON(i915_verify_lists(dev
));
1904 i915_gem_retire_requests(struct drm_device
*dev
)
1906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1908 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1909 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1911 /* We must be careful that during unbind() we do not
1912 * accidentally infinitely recurse into retire requests.
1914 * retire -> free -> unbind -> wait -> retire_ring
1916 list_for_each_entry_safe(obj_priv
, tmp
,
1917 &dev_priv
->mm
.deferred_free_list
,
1919 i915_gem_free_object_tail(&obj_priv
->base
);
1922 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1923 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1924 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
1928 i915_gem_retire_work_handler(struct work_struct
*work
)
1930 drm_i915_private_t
*dev_priv
;
1931 struct drm_device
*dev
;
1933 dev_priv
= container_of(work
, drm_i915_private_t
,
1934 mm
.retire_work
.work
);
1935 dev
= dev_priv
->dev
;
1937 /* Come back later if the device is busy... */
1938 if (!mutex_trylock(&dev
->struct_mutex
)) {
1939 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1943 i915_gem_retire_requests(dev
);
1945 if (!dev_priv
->mm
.suspended
&&
1946 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1947 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
1948 !list_empty(&dev_priv
->blt_ring
.request_list
)))
1949 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1950 mutex_unlock(&dev
->struct_mutex
);
1954 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1955 bool interruptible
, struct intel_ring_buffer
*ring
)
1957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1963 if (atomic_read(&dev_priv
->mm
.wedged
))
1966 if (ring
->outstanding_lazy_request
) {
1967 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1971 BUG_ON(seqno
== dev_priv
->next_seqno
);
1973 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1974 if (HAS_PCH_SPLIT(dev
))
1975 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1977 ier
= I915_READ(IER
);
1979 DRM_ERROR("something (likely vbetool) disabled "
1980 "interrupts, re-enabling\n");
1981 i915_driver_irq_preinstall(dev
);
1982 i915_driver_irq_postinstall(dev
);
1985 trace_i915_gem_request_wait_begin(dev
, seqno
);
1987 ring
->waiting_gem_seqno
= seqno
;
1988 ring
->user_irq_get(ring
);
1990 ret
= wait_event_interruptible(ring
->irq_queue
,
1991 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1992 || atomic_read(&dev_priv
->mm
.wedged
));
1994 wait_event(ring
->irq_queue
,
1995 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1996 || atomic_read(&dev_priv
->mm
.wedged
));
1998 ring
->user_irq_put(ring
);
1999 ring
->waiting_gem_seqno
= 0;
2001 trace_i915_gem_request_wait_end(dev
, seqno
);
2003 if (atomic_read(&dev_priv
->mm
.wedged
))
2006 if (ret
&& ret
!= -ERESTARTSYS
)
2007 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2008 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2009 dev_priv
->next_seqno
);
2011 /* Directly dispatch request retiring. While we have the work queue
2012 * to handle this, the waiter on a request often wants an associated
2013 * buffer to have made it to the inactive list, and we would need
2014 * a separate wait queue to handle that.
2017 i915_gem_retire_requests_ring(dev
, ring
);
2023 * Waits for a sequence number to be signaled, and cleans up the
2024 * request and object lists appropriately for that event.
2027 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2028 struct intel_ring_buffer
*ring
)
2030 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2034 i915_gem_flush_ring(struct drm_device
*dev
,
2035 struct drm_file
*file_priv
,
2036 struct intel_ring_buffer
*ring
,
2037 uint32_t invalidate_domains
,
2038 uint32_t flush_domains
)
2040 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2041 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2045 i915_gem_flush(struct drm_device
*dev
,
2046 struct drm_file
*file_priv
,
2047 uint32_t invalidate_domains
,
2048 uint32_t flush_domains
,
2049 uint32_t flush_rings
)
2051 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2053 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2054 drm_agp_chipset_flush(dev
);
2056 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2057 if (flush_rings
& RING_RENDER
)
2058 i915_gem_flush_ring(dev
, file_priv
,
2059 &dev_priv
->render_ring
,
2060 invalidate_domains
, flush_domains
);
2061 if (flush_rings
& RING_BSD
)
2062 i915_gem_flush_ring(dev
, file_priv
,
2063 &dev_priv
->bsd_ring
,
2064 invalidate_domains
, flush_domains
);
2065 if (flush_rings
& RING_BLT
)
2066 i915_gem_flush_ring(dev
, file_priv
,
2067 &dev_priv
->blt_ring
,
2068 invalidate_domains
, flush_domains
);
2073 * Ensures that all rendering to the object has completed and the object is
2074 * safe to unbind from the GTT or access from the CPU.
2077 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2080 struct drm_device
*dev
= obj
->dev
;
2081 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2084 /* This function only exists to support waiting for existing rendering,
2085 * not for emitting required flushes.
2087 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2089 /* If there is rendering queued on the buffer being evicted, wait for
2092 if (obj_priv
->active
) {
2093 ret
= i915_do_wait_request(dev
,
2094 obj_priv
->last_rendering_seqno
,
2105 * Unbinds an object from the GTT aperture.
2108 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2110 struct drm_device
*dev
= obj
->dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2115 if (obj_priv
->gtt_space
== NULL
)
2118 if (obj_priv
->pin_count
!= 0) {
2119 DRM_ERROR("Attempting to unbind pinned buffer\n");
2123 /* blow away mappings if mapped through GTT */
2124 i915_gem_release_mmap(obj
);
2126 /* Move the object to the CPU domain to ensure that
2127 * any possible CPU writes while it's not in the GTT
2128 * are flushed when we go to remap it. This will
2129 * also ensure that all pending GPU writes are finished
2132 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2133 if (ret
== -ERESTARTSYS
)
2135 /* Continue on if we fail due to EIO, the GPU is hung so we
2136 * should be safe and we need to cleanup or else we might
2137 * cause memory corruption through use-after-free.
2140 i915_gem_clflush_object(obj
);
2141 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2144 /* release the fence reg _after_ flushing */
2145 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2146 i915_gem_clear_fence_reg(obj
);
2148 drm_unbind_agp(obj_priv
->agp_mem
);
2149 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2151 i915_gem_object_put_pages(obj
);
2152 BUG_ON(obj_priv
->pages_refcount
);
2154 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2155 list_del_init(&obj_priv
->mm_list
);
2157 drm_mm_put_block(obj_priv
->gtt_space
);
2158 obj_priv
->gtt_space
= NULL
;
2159 obj_priv
->gtt_offset
= 0;
2161 if (i915_gem_object_is_purgeable(obj_priv
))
2162 i915_gem_object_truncate(obj
);
2164 trace_i915_gem_object_unbind(obj
);
2169 static int i915_ring_idle(struct drm_device
*dev
,
2170 struct intel_ring_buffer
*ring
)
2172 if (list_empty(&ring
->gpu_write_list
))
2175 i915_gem_flush_ring(dev
, NULL
, ring
,
2176 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2177 return i915_wait_request(dev
,
2178 i915_gem_next_request_seqno(dev
, ring
),
2183 i915_gpu_idle(struct drm_device
*dev
)
2185 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2189 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2190 list_empty(&dev_priv
->render_ring
.active_list
) &&
2191 list_empty(&dev_priv
->bsd_ring
.active_list
) &&
2192 list_empty(&dev_priv
->blt_ring
.active_list
));
2196 /* Flush everything onto the inactive list. */
2197 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2201 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2205 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2213 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2216 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2218 struct address_space
*mapping
;
2219 struct inode
*inode
;
2222 BUG_ON(obj_priv
->pages_refcount
2223 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2225 if (obj_priv
->pages_refcount
++ != 0)
2228 /* Get the list of pages out of our struct file. They'll be pinned
2229 * at this point until we release them.
2231 page_count
= obj
->size
/ PAGE_SIZE
;
2232 BUG_ON(obj_priv
->pages
!= NULL
);
2233 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2234 if (obj_priv
->pages
== NULL
) {
2235 obj_priv
->pages_refcount
--;
2239 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2240 mapping
= inode
->i_mapping
;
2241 for (i
= 0; i
< page_count
; i
++) {
2242 page
= read_cache_page_gfp(mapping
, i
,
2250 obj_priv
->pages
[i
] = page
;
2253 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2254 i915_gem_object_do_bit_17_swizzle(obj
);
2260 page_cache_release(obj_priv
->pages
[i
]);
2262 drm_free_large(obj_priv
->pages
);
2263 obj_priv
->pages
= NULL
;
2264 obj_priv
->pages_refcount
--;
2265 return PTR_ERR(page
);
2268 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2270 struct drm_gem_object
*obj
= reg
->obj
;
2271 struct drm_device
*dev
= obj
->dev
;
2272 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2273 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2274 int regnum
= obj_priv
->fence_reg
;
2277 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2279 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2280 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2281 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2283 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2284 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2285 val
|= I965_FENCE_REG_VALID
;
2287 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2290 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2292 struct drm_gem_object
*obj
= reg
->obj
;
2293 struct drm_device
*dev
= obj
->dev
;
2294 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2295 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2296 int regnum
= obj_priv
->fence_reg
;
2299 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2301 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2302 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2303 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2304 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2305 val
|= I965_FENCE_REG_VALID
;
2307 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2310 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2312 struct drm_gem_object
*obj
= reg
->obj
;
2313 struct drm_device
*dev
= obj
->dev
;
2314 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2315 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2316 int regnum
= obj_priv
->fence_reg
;
2318 uint32_t fence_reg
, val
;
2321 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2322 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2323 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2324 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2328 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2329 HAS_128_BYTE_Y_TILING(dev
))
2334 /* Note: pitch better be a power of two tile widths */
2335 pitch_val
= obj_priv
->stride
/ tile_width
;
2336 pitch_val
= ffs(pitch_val
) - 1;
2338 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2339 HAS_128_BYTE_Y_TILING(dev
))
2340 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2342 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2344 val
= obj_priv
->gtt_offset
;
2345 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2346 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2347 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2348 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2349 val
|= I830_FENCE_REG_VALID
;
2352 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2354 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2355 I915_WRITE(fence_reg
, val
);
2358 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2360 struct drm_gem_object
*obj
= reg
->obj
;
2361 struct drm_device
*dev
= obj
->dev
;
2362 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2363 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2364 int regnum
= obj_priv
->fence_reg
;
2367 uint32_t fence_size_bits
;
2369 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2370 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2371 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2372 __func__
, obj_priv
->gtt_offset
);
2376 pitch_val
= obj_priv
->stride
/ 128;
2377 pitch_val
= ffs(pitch_val
) - 1;
2378 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2380 val
= obj_priv
->gtt_offset
;
2381 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2382 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2383 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2384 WARN_ON(fence_size_bits
& ~0x00000f00);
2385 val
|= fence_size_bits
;
2386 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2387 val
|= I830_FENCE_REG_VALID
;
2389 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2392 static int i915_find_fence_reg(struct drm_device
*dev
,
2395 struct drm_i915_fence_reg
*reg
= NULL
;
2396 struct drm_i915_gem_object
*obj_priv
= NULL
;
2397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2398 struct drm_gem_object
*obj
= NULL
;
2401 /* First try to find a free reg */
2403 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2404 reg
= &dev_priv
->fence_regs
[i
];
2408 obj_priv
= to_intel_bo(reg
->obj
);
2409 if (!obj_priv
->pin_count
)
2416 /* None available, try to steal one or wait for a user to finish */
2417 i
= I915_FENCE_REG_NONE
;
2418 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2421 obj_priv
= to_intel_bo(obj
);
2423 if (obj_priv
->pin_count
)
2427 i
= obj_priv
->fence_reg
;
2431 BUG_ON(i
== I915_FENCE_REG_NONE
);
2433 /* We only have a reference on obj from the active list. put_fence_reg
2434 * might drop that one, causing a use-after-free in it. So hold a
2435 * private reference to obj like the other callers of put_fence_reg
2436 * (set_tiling ioctl) do. */
2437 drm_gem_object_reference(obj
);
2438 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2439 drm_gem_object_unreference(obj
);
2447 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2448 * @obj: object to map through a fence reg
2450 * When mapping objects through the GTT, userspace wants to be able to write
2451 * to them without having to worry about swizzling if the object is tiled.
2453 * This function walks the fence regs looking for a free one for @obj,
2454 * stealing one if it can't find any.
2456 * It then sets up the reg based on the object's properties: address, pitch
2457 * and tiling format.
2460 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2463 struct drm_device
*dev
= obj
->dev
;
2464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2465 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2466 struct drm_i915_fence_reg
*reg
= NULL
;
2469 /* Just update our place in the LRU if our fence is getting used. */
2470 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2471 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2472 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2476 switch (obj_priv
->tiling_mode
) {
2477 case I915_TILING_NONE
:
2478 WARN(1, "allocating a fence for non-tiled object?\n");
2481 if (!obj_priv
->stride
)
2483 WARN((obj_priv
->stride
& (512 - 1)),
2484 "object 0x%08x is X tiled but has non-512B pitch\n",
2485 obj_priv
->gtt_offset
);
2488 if (!obj_priv
->stride
)
2490 WARN((obj_priv
->stride
& (128 - 1)),
2491 "object 0x%08x is Y tiled but has non-128B pitch\n",
2492 obj_priv
->gtt_offset
);
2496 ret
= i915_find_fence_reg(dev
, interruptible
);
2500 obj_priv
->fence_reg
= ret
;
2501 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2502 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2506 switch (INTEL_INFO(dev
)->gen
) {
2508 sandybridge_write_fence_reg(reg
);
2512 i965_write_fence_reg(reg
);
2515 i915_write_fence_reg(reg
);
2518 i830_write_fence_reg(reg
);
2522 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2523 obj_priv
->tiling_mode
);
2529 * i915_gem_clear_fence_reg - clear out fence register info
2530 * @obj: object to clear
2532 * Zeroes out the fence register itself and clears out the associated
2533 * data structures in dev_priv and obj_priv.
2536 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2538 struct drm_device
*dev
= obj
->dev
;
2539 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2540 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2541 struct drm_i915_fence_reg
*reg
=
2542 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2545 switch (INTEL_INFO(dev
)->gen
) {
2547 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2548 (obj_priv
->fence_reg
* 8), 0);
2552 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2555 if (obj_priv
->fence_reg
>= 8)
2556 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2559 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2561 I915_WRITE(fence_reg
, 0);
2566 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2567 list_del_init(®
->lru_list
);
2571 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2572 * to the buffer to finish, and then resets the fence register.
2573 * @obj: tiled object holding a fence register.
2574 * @bool: whether the wait upon the fence is interruptible
2576 * Zeroes out the fence register itself and clears out the associated
2577 * data structures in dev_priv and obj_priv.
2580 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2583 struct drm_device
*dev
= obj
->dev
;
2584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2585 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2586 struct drm_i915_fence_reg
*reg
;
2588 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2591 /* If we've changed tiling, GTT-mappings of the object
2592 * need to re-fault to ensure that the correct fence register
2593 * setup is in place.
2595 i915_gem_release_mmap(obj
);
2597 /* On the i915, GPU access to tiled buffers is via a fence,
2598 * therefore we must wait for any outstanding access to complete
2599 * before clearing the fence.
2601 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2605 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2609 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2616 i915_gem_object_flush_gtt_write_domain(obj
);
2617 i915_gem_clear_fence_reg(obj
);
2623 * Finds free space in the GTT aperture and binds the object there.
2626 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2628 struct drm_device
*dev
= obj
->dev
;
2629 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2630 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2631 struct drm_mm_node
*free_space
;
2632 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2635 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2636 DRM_ERROR("Attempting to bind a purgeable object\n");
2641 alignment
= i915_gem_get_gtt_alignment(obj
);
2642 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2643 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2647 /* If the object is bigger than the entire aperture, reject it early
2648 * before evicting everything in a vain attempt to find space.
2650 if (obj
->size
> dev_priv
->mm
.gtt_total
) {
2651 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2656 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2657 obj
->size
, alignment
, 0);
2658 if (free_space
!= NULL
)
2659 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2661 if (obj_priv
->gtt_space
== NULL
) {
2662 /* If the gtt is empty and we're still having trouble
2663 * fitting our object in, we're out of memory.
2665 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2672 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2674 drm_mm_put_block(obj_priv
->gtt_space
);
2675 obj_priv
->gtt_space
= NULL
;
2677 if (ret
== -ENOMEM
) {
2678 /* first try to clear up some space from the GTT */
2679 ret
= i915_gem_evict_something(dev
, obj
->size
,
2682 /* now try to shrink everyone else */
2697 /* Create an AGP memory structure pointing at our pages, and bind it
2700 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2702 obj
->size
>> PAGE_SHIFT
,
2703 obj_priv
->gtt_space
->start
,
2704 obj_priv
->agp_type
);
2705 if (obj_priv
->agp_mem
== NULL
) {
2706 i915_gem_object_put_pages(obj
);
2707 drm_mm_put_block(obj_priv
->gtt_space
);
2708 obj_priv
->gtt_space
= NULL
;
2710 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2717 /* keep track of bounds object by adding it to the inactive list */
2718 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2719 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2721 /* Assert that the object is not currently in any GPU domain. As it
2722 * wasn't in the GTT, there shouldn't be any way it could have been in
2725 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2726 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2728 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2729 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2735 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2737 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2739 /* If we don't have a page list set up, then we're not pinned
2740 * to GPU, and we can ignore the cache flush because it'll happen
2741 * again at bind time.
2743 if (obj_priv
->pages
== NULL
)
2746 trace_i915_gem_object_clflush(obj
);
2748 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2751 /** Flushes any GPU write domain for the object if it's dirty. */
2753 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2756 struct drm_device
*dev
= obj
->dev
;
2757 uint32_t old_write_domain
;
2759 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2762 /* Queue the GPU write cache flushing we need. */
2763 old_write_domain
= obj
->write_domain
;
2764 i915_gem_flush_ring(dev
, NULL
,
2765 to_intel_bo(obj
)->ring
,
2766 0, obj
->write_domain
);
2767 BUG_ON(obj
->write_domain
);
2769 trace_i915_gem_object_change_domain(obj
,
2776 return i915_gem_object_wait_rendering(obj
, true);
2779 /** Flushes the GTT write domain for the object if it's dirty. */
2781 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2783 uint32_t old_write_domain
;
2785 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2788 /* No actual flushing is required for the GTT write domain. Writes
2789 * to it immediately go to main memory as far as we know, so there's
2790 * no chipset flush. It also doesn't land in render cache.
2792 old_write_domain
= obj
->write_domain
;
2793 obj
->write_domain
= 0;
2795 trace_i915_gem_object_change_domain(obj
,
2800 /** Flushes the CPU write domain for the object if it's dirty. */
2802 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2804 struct drm_device
*dev
= obj
->dev
;
2805 uint32_t old_write_domain
;
2807 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2810 i915_gem_clflush_object(obj
);
2811 drm_agp_chipset_flush(dev
);
2812 old_write_domain
= obj
->write_domain
;
2813 obj
->write_domain
= 0;
2815 trace_i915_gem_object_change_domain(obj
,
2821 * Moves a single object to the GTT read, and possibly write domain.
2823 * This function returns when the move is complete, including waiting on
2827 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2829 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2830 uint32_t old_write_domain
, old_read_domains
;
2833 /* Not valid to be called on unbound objects. */
2834 if (obj_priv
->gtt_space
== NULL
)
2837 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2841 i915_gem_object_flush_cpu_write_domain(obj
);
2844 ret
= i915_gem_object_wait_rendering(obj
, true);
2849 old_write_domain
= obj
->write_domain
;
2850 old_read_domains
= obj
->read_domains
;
2852 /* It should now be out of any other write domains, and we can update
2853 * the domain values for our changes.
2855 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2856 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2858 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2859 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2860 obj_priv
->dirty
= 1;
2863 trace_i915_gem_object_change_domain(obj
,
2871 * Prepare buffer for display plane. Use uninterruptible for possible flush
2872 * wait, as in modesetting process we're not supposed to be interrupted.
2875 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2878 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2879 uint32_t old_read_domains
;
2882 /* Not valid to be called on unbound objects. */
2883 if (obj_priv
->gtt_space
== NULL
)
2886 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2890 /* Currently, we are always called from an non-interruptible context. */
2892 ret
= i915_gem_object_wait_rendering(obj
, false);
2897 i915_gem_object_flush_cpu_write_domain(obj
);
2899 old_read_domains
= obj
->read_domains
;
2900 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2902 trace_i915_gem_object_change_domain(obj
,
2910 * Moves a single object to the CPU read, and possibly write domain.
2912 * This function returns when the move is complete, including waiting on
2916 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2918 uint32_t old_write_domain
, old_read_domains
;
2921 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2925 i915_gem_object_flush_gtt_write_domain(obj
);
2927 /* If we have a partially-valid cache of the object in the CPU,
2928 * finish invalidating it and free the per-page flags.
2930 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2933 ret
= i915_gem_object_wait_rendering(obj
, true);
2938 old_write_domain
= obj
->write_domain
;
2939 old_read_domains
= obj
->read_domains
;
2941 /* Flush the CPU cache if it's still invalid. */
2942 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2943 i915_gem_clflush_object(obj
);
2945 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2948 /* It should now be out of any other write domains, and we can update
2949 * the domain values for our changes.
2951 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2953 /* If we're writing through the CPU, then the GPU read domains will
2954 * need to be invalidated at next use.
2957 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2958 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2961 trace_i915_gem_object_change_domain(obj
,
2969 * Set the next domain for the specified object. This
2970 * may not actually perform the necessary flushing/invaliding though,
2971 * as that may want to be batched with other set_domain operations
2973 * This is (we hope) the only really tricky part of gem. The goal
2974 * is fairly simple -- track which caches hold bits of the object
2975 * and make sure they remain coherent. A few concrete examples may
2976 * help to explain how it works. For shorthand, we use the notation
2977 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2978 * a pair of read and write domain masks.
2980 * Case 1: the batch buffer
2986 * 5. Unmapped from GTT
2989 * Let's take these a step at a time
2992 * Pages allocated from the kernel may still have
2993 * cache contents, so we set them to (CPU, CPU) always.
2994 * 2. Written by CPU (using pwrite)
2995 * The pwrite function calls set_domain (CPU, CPU) and
2996 * this function does nothing (as nothing changes)
2998 * This function asserts that the object is not
2999 * currently in any GPU-based read or write domains
3001 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3002 * As write_domain is zero, this function adds in the
3003 * current read domains (CPU+COMMAND, 0).
3004 * flush_domains is set to CPU.
3005 * invalidate_domains is set to COMMAND
3006 * clflush is run to get data out of the CPU caches
3007 * then i915_dev_set_domain calls i915_gem_flush to
3008 * emit an MI_FLUSH and drm_agp_chipset_flush
3009 * 5. Unmapped from GTT
3010 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3011 * flush_domains and invalidate_domains end up both zero
3012 * so no flushing/invalidating happens
3016 * Case 2: The shared render buffer
3020 * 3. Read/written by GPU
3021 * 4. set_domain to (CPU,CPU)
3022 * 5. Read/written by CPU
3023 * 6. Read/written by GPU
3026 * Same as last example, (CPU, CPU)
3028 * Nothing changes (assertions find that it is not in the GPU)
3029 * 3. Read/written by GPU
3030 * execbuffer calls set_domain (RENDER, RENDER)
3031 * flush_domains gets CPU
3032 * invalidate_domains gets GPU
3034 * MI_FLUSH and drm_agp_chipset_flush
3035 * 4. set_domain (CPU, CPU)
3036 * flush_domains gets GPU
3037 * invalidate_domains gets CPU
3038 * wait_rendering (obj) to make sure all drawing is complete.
3039 * This will include an MI_FLUSH to get the data from GPU
3041 * clflush (obj) to invalidate the CPU cache
3042 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3043 * 5. Read/written by CPU
3044 * cache lines are loaded and dirtied
3045 * 6. Read written by GPU
3046 * Same as last GPU access
3048 * Case 3: The constant buffer
3053 * 4. Updated (written) by CPU again
3062 * flush_domains = CPU
3063 * invalidate_domains = RENDER
3066 * drm_agp_chipset_flush
3067 * 4. Updated (written) by CPU again
3069 * flush_domains = 0 (no previous write domain)
3070 * invalidate_domains = 0 (no new read domains)
3073 * flush_domains = CPU
3074 * invalidate_domains = RENDER
3077 * drm_agp_chipset_flush
3080 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3081 struct intel_ring_buffer
*ring
)
3083 struct drm_device
*dev
= obj
->dev
;
3084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3085 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3086 uint32_t invalidate_domains
= 0;
3087 uint32_t flush_domains
= 0;
3088 uint32_t old_read_domains
;
3090 intel_mark_busy(dev
, obj
);
3093 * If the object isn't moving to a new write domain,
3094 * let the object stay in multiple read domains
3096 if (obj
->pending_write_domain
== 0)
3097 obj
->pending_read_domains
|= obj
->read_domains
;
3099 obj_priv
->dirty
= 1;
3102 * Flush the current write domain if
3103 * the new read domains don't match. Invalidate
3104 * any read domains which differ from the old
3107 if (obj
->write_domain
&&
3108 obj
->write_domain
!= obj
->pending_read_domains
) {
3109 flush_domains
|= obj
->write_domain
;
3110 invalidate_domains
|=
3111 obj
->pending_read_domains
& ~obj
->write_domain
;
3114 * Invalidate any read caches which may have
3115 * stale data. That is, any new read domains.
3117 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3118 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3119 i915_gem_clflush_object(obj
);
3121 old_read_domains
= obj
->read_domains
;
3123 /* The actual obj->write_domain will be updated with
3124 * pending_write_domain after we emit the accumulated flush for all
3125 * of our domain changes in execbuffers (which clears objects'
3126 * write_domains). So if we have a current write domain that we
3127 * aren't changing, set pending_write_domain to that.
3129 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3130 obj
->pending_write_domain
= obj
->write_domain
;
3131 obj
->read_domains
= obj
->pending_read_domains
;
3133 dev
->invalidate_domains
|= invalidate_domains
;
3134 dev
->flush_domains
|= flush_domains
;
3135 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3136 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3137 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3138 dev_priv
->mm
.flush_rings
|= ring
->id
;
3140 trace_i915_gem_object_change_domain(obj
,
3146 * Moves the object from a partially CPU read to a full one.
3148 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3149 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3152 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3154 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3156 if (!obj_priv
->page_cpu_valid
)
3159 /* If we're partially in the CPU read domain, finish moving it in.
3161 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3164 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3165 if (obj_priv
->page_cpu_valid
[i
])
3167 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3171 /* Free the page_cpu_valid mappings which are now stale, whether
3172 * or not we've got I915_GEM_DOMAIN_CPU.
3174 kfree(obj_priv
->page_cpu_valid
);
3175 obj_priv
->page_cpu_valid
= NULL
;
3179 * Set the CPU read domain on a range of the object.
3181 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3182 * not entirely valid. The page_cpu_valid member of the object flags which
3183 * pages have been flushed, and will be respected by
3184 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3185 * of the whole object.
3187 * This function returns when the move is complete, including waiting on
3191 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3192 uint64_t offset
, uint64_t size
)
3194 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3195 uint32_t old_read_domains
;
3198 if (offset
== 0 && size
== obj
->size
)
3199 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3201 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3204 i915_gem_object_flush_gtt_write_domain(obj
);
3206 /* If we're already fully in the CPU read domain, we're done. */
3207 if (obj_priv
->page_cpu_valid
== NULL
&&
3208 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3211 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3212 * newly adding I915_GEM_DOMAIN_CPU
3214 if (obj_priv
->page_cpu_valid
== NULL
) {
3215 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3217 if (obj_priv
->page_cpu_valid
== NULL
)
3219 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3220 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3222 /* Flush the cache on any pages that are still invalid from the CPU's
3225 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3227 if (obj_priv
->page_cpu_valid
[i
])
3230 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3232 obj_priv
->page_cpu_valid
[i
] = 1;
3235 /* It should now be out of any other write domains, and we can update
3236 * the domain values for our changes.
3238 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3240 old_read_domains
= obj
->read_domains
;
3241 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3243 trace_i915_gem_object_change_domain(obj
,
3251 * Pin an object to the GTT and evaluate the relocations landing in it.
3254 i915_gem_execbuffer_relocate(struct drm_i915_gem_object
*obj
,
3255 struct drm_file
*file_priv
,
3256 struct drm_i915_gem_exec_object2
*entry
)
3258 struct drm_device
*dev
= obj
->base
.dev
;
3259 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3260 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3261 struct drm_gem_object
*target_obj
= NULL
;
3262 uint32_t target_handle
= 0;
3265 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3266 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3267 struct drm_i915_gem_relocation_entry reloc
;
3268 uint32_t target_offset
;
3270 if (__copy_from_user_inatomic(&reloc
,
3277 if (reloc
.target_handle
!= target_handle
) {
3278 drm_gem_object_unreference(target_obj
);
3280 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3281 reloc
.target_handle
);
3282 if (target_obj
== NULL
) {
3287 target_handle
= reloc
.target_handle
;
3289 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3292 DRM_INFO("%s: obj %p offset %08x target %d "
3293 "read %08x write %08x gtt %08x "
3294 "presumed %08x delta %08x\n",
3298 (int) reloc
.target_handle
,
3299 (int) reloc
.read_domains
,
3300 (int) reloc
.write_domain
,
3301 (int) target_offset
,
3302 (int) reloc
.presumed_offset
,
3306 /* The target buffer should have appeared before us in the
3307 * exec_object list, so it should have a GTT space bound by now.
3309 if (target_offset
== 0) {
3310 DRM_ERROR("No GTT space found for object %d\n",
3311 reloc
.target_handle
);
3316 /* Validate that the target is in a valid r/w GPU domain */
3317 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3318 DRM_ERROR("reloc with multiple write domains: "
3319 "obj %p target %d offset %d "
3320 "read %08x write %08x",
3321 obj
, reloc
.target_handle
,
3324 reloc
.write_domain
);
3328 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3329 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3330 DRM_ERROR("reloc with read/write CPU domains: "
3331 "obj %p target %d offset %d "
3332 "read %08x write %08x",
3333 obj
, reloc
.target_handle
,
3336 reloc
.write_domain
);
3340 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3341 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3342 DRM_ERROR("Write domain conflict: "
3343 "obj %p target %d offset %d "
3344 "new %08x old %08x\n",
3345 obj
, reloc
.target_handle
,
3348 target_obj
->pending_write_domain
);
3353 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3354 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3356 /* If the relocation already has the right value in it, no
3357 * more work needs to be done.
3359 if (target_offset
== reloc
.presumed_offset
)
3362 /* Check that the relocation address is valid... */
3363 if (reloc
.offset
> obj
->base
.size
- 4) {
3364 DRM_ERROR("Relocation beyond object bounds: "
3365 "obj %p target %d offset %d size %d.\n",
3366 obj
, reloc
.target_handle
,
3367 (int) reloc
.offset
, (int) obj
->base
.size
);
3371 if (reloc
.offset
& 3) {
3372 DRM_ERROR("Relocation not 4-byte aligned: "
3373 "obj %p target %d offset %d.\n",
3374 obj
, reloc
.target_handle
,
3375 (int) reloc
.offset
);
3380 /* and points to somewhere within the target object. */
3381 if (reloc
.delta
>= target_obj
->size
) {
3382 DRM_ERROR("Relocation beyond target object bounds: "
3383 "obj %p target %d delta %d size %d.\n",
3384 obj
, reloc
.target_handle
,
3385 (int) reloc
.delta
, (int) target_obj
->size
);
3390 reloc
.delta
+= target_offset
;
3391 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3392 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3395 vaddr
= kmap_atomic(obj
->pages
[reloc
.offset
>> PAGE_SHIFT
]);
3396 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3397 kunmap_atomic(vaddr
);
3399 uint32_t __iomem
*reloc_entry
;
3400 void __iomem
*reloc_page
;
3402 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3406 /* Map the page containing the relocation we're going to perform. */
3407 reloc
.offset
+= obj
->gtt_offset
;
3408 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3409 reloc
.offset
& PAGE_MASK
);
3410 reloc_entry
= (uint32_t __iomem
*)
3411 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3412 iowrite32(reloc
.delta
, reloc_entry
);
3413 io_mapping_unmap_atomic(reloc_page
);
3416 /* and update the user's relocation entry */
3417 reloc
.presumed_offset
= target_offset
;
3418 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3419 &reloc
.presumed_offset
,
3420 sizeof(reloc
.presumed_offset
))) {
3426 drm_gem_object_unreference(target_obj
);
3431 i915_gem_execbuffer_pin(struct drm_device
*dev
,
3432 struct drm_file
*file
,
3433 struct drm_gem_object
**object_list
,
3434 struct drm_i915_gem_exec_object2
*exec_list
,
3437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3440 /* attempt to pin all of the buffers into the GTT */
3441 for (retry
= 0; retry
< 2; retry
++) {
3443 for (i
= 0; i
< count
; i
++) {
3444 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3445 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3447 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3448 obj
->tiling_mode
!= I915_TILING_NONE
;
3450 /* Check fence reg constraints and rebind if necessary */
3452 !i915_gem_object_fence_offset_ok(&obj
->base
,
3453 obj
->tiling_mode
)) {
3454 ret
= i915_gem_object_unbind(&obj
->base
);
3459 ret
= i915_gem_object_pin(&obj
->base
, entry
->alignment
);
3464 * Pre-965 chips need a fence register set up in order
3465 * to properly handle blits to/from tiled surfaces.
3468 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3470 i915_gem_object_unpin(&obj
->base
);
3474 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3477 entry
->offset
= obj
->gtt_offset
;
3481 i915_gem_object_unpin(object_list
[i
]);
3486 if (ret
!= -ENOSPC
|| retry
)
3489 ret
= i915_gem_evict_everything(dev
);
3497 /* Throttle our rendering by waiting until the ring has completed our requests
3498 * emitted over 20 msec ago.
3500 * Note that if we were to use the current jiffies each time around the loop,
3501 * we wouldn't escape the function with any frames outstanding if the time to
3502 * render a frame was over 20ms.
3504 * This should get us reasonable parallelism between CPU and GPU but also
3505 * relatively low latency when blocking on a particular request to finish.
3508 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3511 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3512 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3513 struct drm_i915_gem_request
*request
;
3514 struct intel_ring_buffer
*ring
= NULL
;
3518 spin_lock(&file_priv
->mm
.lock
);
3519 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3520 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3523 ring
= request
->ring
;
3524 seqno
= request
->seqno
;
3526 spin_unlock(&file_priv
->mm
.lock
);
3532 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3533 /* And wait for the seqno passing without holding any locks and
3534 * causing extra latency for others. This is safe as the irq
3535 * generation is designed to be run atomically and so is
3538 ring
->user_irq_get(ring
);
3539 ret
= wait_event_interruptible(ring
->irq_queue
,
3540 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3541 || atomic_read(&dev_priv
->mm
.wedged
));
3542 ring
->user_irq_put(ring
);
3544 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3549 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3555 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3556 uint64_t exec_offset
)
3558 uint32_t exec_start
, exec_len
;
3560 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3561 exec_len
= (uint32_t) exec
->batch_len
;
3563 if ((exec_start
| exec_len
) & 0x7)
3573 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3578 for (i
= 0; i
< count
; i
++) {
3579 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3580 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3582 if (!access_ok(VERIFY_READ
, ptr
, length
))
3585 /* we may also need to update the presumed offsets */
3586 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3589 if (fault_in_pages_readable(ptr
, length
))
3597 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3598 struct drm_file
*file
,
3599 struct drm_i915_gem_execbuffer2
*args
,
3600 struct drm_i915_gem_exec_object2
*exec_list
)
3602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3603 struct drm_gem_object
**object_list
= NULL
;
3604 struct drm_gem_object
*batch_obj
;
3605 struct drm_i915_gem_object
*obj_priv
;
3606 struct drm_clip_rect
*cliprects
= NULL
;
3607 struct drm_i915_gem_request
*request
= NULL
;
3609 uint64_t exec_offset
;
3611 struct intel_ring_buffer
*ring
= NULL
;
3613 ret
= i915_gem_check_is_wedged(dev
);
3617 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3622 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3623 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3625 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3626 case I915_EXEC_DEFAULT
:
3627 case I915_EXEC_RENDER
:
3628 ring
= &dev_priv
->render_ring
;
3631 if (!HAS_BSD(dev
)) {
3632 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3635 ring
= &dev_priv
->bsd_ring
;
3638 if (!HAS_BLT(dev
)) {
3639 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3642 ring
= &dev_priv
->blt_ring
;
3645 DRM_ERROR("execbuf with unknown ring: %d\n",
3646 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3650 if (args
->buffer_count
< 1) {
3651 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3654 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3655 if (object_list
== NULL
) {
3656 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3657 args
->buffer_count
);
3662 if (args
->num_cliprects
!= 0) {
3663 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3665 if (cliprects
== NULL
) {
3670 ret
= copy_from_user(cliprects
,
3671 (struct drm_clip_rect __user
*)
3672 (uintptr_t) args
->cliprects_ptr
,
3673 sizeof(*cliprects
) * args
->num_cliprects
);
3675 DRM_ERROR("copy %d cliprects failed: %d\n",
3676 args
->num_cliprects
, ret
);
3682 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3683 if (request
== NULL
) {
3688 ret
= i915_mutex_lock_interruptible(dev
);
3692 if (dev_priv
->mm
.suspended
) {
3693 mutex_unlock(&dev
->struct_mutex
);
3698 /* Look up object handles */
3699 for (i
= 0; i
< args
->buffer_count
; i
++) {
3700 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3701 exec_list
[i
].handle
);
3702 if (object_list
[i
] == NULL
) {
3703 DRM_ERROR("Invalid object handle %d at index %d\n",
3704 exec_list
[i
].handle
, i
);
3705 /* prevent error path from reading uninitialized data */
3706 args
->buffer_count
= i
+ 1;
3711 obj_priv
= to_intel_bo(object_list
[i
]);
3712 if (obj_priv
->in_execbuffer
) {
3713 DRM_ERROR("Object %p appears more than once in object list\n",
3715 /* prevent error path from reading uninitialized data */
3716 args
->buffer_count
= i
+ 1;
3720 obj_priv
->in_execbuffer
= true;
3723 /* Move the objects en-masse into the GTT, evicting if necessary. */
3724 ret
= i915_gem_execbuffer_pin(dev
, file
,
3725 object_list
, exec_list
,
3726 args
->buffer_count
);
3730 /* The objects are in their final locations, apply the relocations. */
3731 for (i
= 0; i
< args
->buffer_count
; i
++) {
3732 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3733 obj
->base
.pending_read_domains
= 0;
3734 obj
->base
.pending_write_domain
= 0;
3735 ret
= i915_gem_execbuffer_relocate(obj
, file
, &exec_list
[i
]);
3740 /* Set the pending read domains for the batch buffer to COMMAND */
3741 batch_obj
= object_list
[args
->buffer_count
-1];
3742 if (batch_obj
->pending_write_domain
) {
3743 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3747 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3749 /* Sanity check the batch buffer */
3750 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
3751 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
3753 DRM_ERROR("execbuf with invalid offset/length\n");
3757 /* Zero the global flush/invalidate flags. These
3758 * will be modified as new domains are computed
3761 dev
->invalidate_domains
= 0;
3762 dev
->flush_domains
= 0;
3763 dev_priv
->mm
.flush_rings
= 0;
3765 for (i
= 0; i
< args
->buffer_count
; i
++) {
3766 struct drm_gem_object
*obj
= object_list
[i
];
3768 /* Compute new gpu domains and update invalidate/flush */
3769 i915_gem_object_set_to_gpu_domain(obj
, ring
);
3772 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3774 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3776 dev
->invalidate_domains
,
3777 dev
->flush_domains
);
3779 i915_gem_flush(dev
, file
,
3780 dev
->invalidate_domains
,
3782 dev_priv
->mm
.flush_rings
);
3785 for (i
= 0; i
< args
->buffer_count
; i
++) {
3786 struct drm_gem_object
*obj
= object_list
[i
];
3787 uint32_t old_write_domain
= obj
->write_domain
;
3788 obj
->write_domain
= obj
->pending_write_domain
;
3789 trace_i915_gem_object_change_domain(obj
,
3795 for (i
= 0; i
< args
->buffer_count
; i
++) {
3796 i915_gem_object_check_coherency(object_list
[i
],
3797 exec_list
[i
].handle
);
3802 i915_gem_dump_object(batch_obj
,
3808 /* Check for any pending flips. As we only maintain a flip queue depth
3809 * of 1, we can simply insert a WAIT for the next display flip prior
3810 * to executing the batch and avoid stalling the CPU.
3813 for (i
= 0; i
< args
->buffer_count
; i
++) {
3814 if (object_list
[i
]->write_domain
)
3815 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3818 int plane
, flip_mask
;
3820 for (plane
= 0; flips
>> plane
; plane
++) {
3821 if (((flips
>> plane
) & 1) == 0)
3825 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3827 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3829 ret
= intel_ring_begin(ring
, 2);
3833 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
3834 intel_ring_emit(ring
, MI_NOOP
);
3835 intel_ring_advance(ring
);
3839 /* Exec the batchbuffer */
3840 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
3842 DRM_ERROR("dispatch failed %d\n", ret
);
3847 * Ensure that the commands in the batch buffer are
3848 * finished before the interrupt fires
3850 i915_retire_commands(dev
, ring
);
3852 for (i
= 0; i
< args
->buffer_count
; i
++) {
3853 struct drm_gem_object
*obj
= object_list
[i
];
3855 i915_gem_object_move_to_active(obj
, ring
);
3856 if (obj
->write_domain
)
3857 list_move_tail(&to_intel_bo(obj
)->gpu_write_list
,
3858 &ring
->gpu_write_list
);
3861 i915_add_request(dev
, file
, request
, ring
);
3865 for (i
= 0; i
< args
->buffer_count
; i
++) {
3866 if (object_list
[i
]) {
3867 obj_priv
= to_intel_bo(object_list
[i
]);
3868 obj_priv
->in_execbuffer
= false;
3870 drm_gem_object_unreference(object_list
[i
]);
3873 mutex_unlock(&dev
->struct_mutex
);
3876 drm_free_large(object_list
);
3884 * Legacy execbuffer just creates an exec2 list from the original exec object
3885 * list array and passes it to the real function.
3888 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3889 struct drm_file
*file_priv
)
3891 struct drm_i915_gem_execbuffer
*args
= data
;
3892 struct drm_i915_gem_execbuffer2 exec2
;
3893 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3894 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3898 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3899 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3902 if (args
->buffer_count
< 1) {
3903 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3907 /* Copy in the exec list from userland */
3908 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3909 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3910 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3911 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3912 args
->buffer_count
);
3913 drm_free_large(exec_list
);
3914 drm_free_large(exec2_list
);
3917 ret
= copy_from_user(exec_list
,
3918 (struct drm_i915_relocation_entry __user
*)
3919 (uintptr_t) args
->buffers_ptr
,
3920 sizeof(*exec_list
) * args
->buffer_count
);
3922 DRM_ERROR("copy %d exec entries failed %d\n",
3923 args
->buffer_count
, ret
);
3924 drm_free_large(exec_list
);
3925 drm_free_large(exec2_list
);
3929 for (i
= 0; i
< args
->buffer_count
; i
++) {
3930 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3931 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3932 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3933 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3934 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3935 if (INTEL_INFO(dev
)->gen
< 4)
3936 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3938 exec2_list
[i
].flags
= 0;
3941 exec2
.buffers_ptr
= args
->buffers_ptr
;
3942 exec2
.buffer_count
= args
->buffer_count
;
3943 exec2
.batch_start_offset
= args
->batch_start_offset
;
3944 exec2
.batch_len
= args
->batch_len
;
3945 exec2
.DR1
= args
->DR1
;
3946 exec2
.DR4
= args
->DR4
;
3947 exec2
.num_cliprects
= args
->num_cliprects
;
3948 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3949 exec2
.flags
= I915_EXEC_RENDER
;
3951 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3953 /* Copy the new buffer offsets back to the user's exec list. */
3954 for (i
= 0; i
< args
->buffer_count
; i
++)
3955 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3956 /* ... and back out to userspace */
3957 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3958 (uintptr_t) args
->buffers_ptr
,
3960 sizeof(*exec_list
) * args
->buffer_count
);
3963 DRM_ERROR("failed to copy %d exec entries "
3964 "back to user (%d)\n",
3965 args
->buffer_count
, ret
);
3969 drm_free_large(exec_list
);
3970 drm_free_large(exec2_list
);
3975 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3976 struct drm_file
*file_priv
)
3978 struct drm_i915_gem_execbuffer2
*args
= data
;
3979 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3983 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3984 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3987 if (args
->buffer_count
< 1) {
3988 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3992 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3993 if (exec2_list
== NULL
) {
3994 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3995 args
->buffer_count
);
3998 ret
= copy_from_user(exec2_list
,
3999 (struct drm_i915_relocation_entry __user
*)
4000 (uintptr_t) args
->buffers_ptr
,
4001 sizeof(*exec2_list
) * args
->buffer_count
);
4003 DRM_ERROR("copy %d exec entries failed %d\n",
4004 args
->buffer_count
, ret
);
4005 drm_free_large(exec2_list
);
4009 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4011 /* Copy the new buffer offsets back to the user's exec list. */
4012 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4013 (uintptr_t) args
->buffers_ptr
,
4015 sizeof(*exec2_list
) * args
->buffer_count
);
4018 DRM_ERROR("failed to copy %d exec entries "
4019 "back to user (%d)\n",
4020 args
->buffer_count
, ret
);
4024 drm_free_large(exec2_list
);
4029 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4031 struct drm_device
*dev
= obj
->dev
;
4032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4033 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4036 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4037 WARN_ON(i915_verify_lists(dev
));
4039 if (obj_priv
->gtt_space
!= NULL
) {
4041 alignment
= i915_gem_get_gtt_alignment(obj
);
4042 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4043 WARN(obj_priv
->pin_count
,
4044 "bo is already pinned with incorrect alignment:"
4045 " offset=%x, req.alignment=%x\n",
4046 obj_priv
->gtt_offset
, alignment
);
4047 ret
= i915_gem_object_unbind(obj
);
4053 if (obj_priv
->gtt_space
== NULL
) {
4054 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4059 obj_priv
->pin_count
++;
4061 /* If the object is not active and not pending a flush,
4062 * remove it from the inactive list
4064 if (obj_priv
->pin_count
== 1) {
4065 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4066 if (!obj_priv
->active
)
4067 list_move_tail(&obj_priv
->mm_list
,
4068 &dev_priv
->mm
.pinned_list
);
4071 WARN_ON(i915_verify_lists(dev
));
4076 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4078 struct drm_device
*dev
= obj
->dev
;
4079 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4080 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4082 WARN_ON(i915_verify_lists(dev
));
4083 obj_priv
->pin_count
--;
4084 BUG_ON(obj_priv
->pin_count
< 0);
4085 BUG_ON(obj_priv
->gtt_space
== NULL
);
4087 /* If the object is no longer pinned, and is
4088 * neither active nor being flushed, then stick it on
4091 if (obj_priv
->pin_count
== 0) {
4092 if (!obj_priv
->active
)
4093 list_move_tail(&obj_priv
->mm_list
,
4094 &dev_priv
->mm
.inactive_list
);
4095 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4097 WARN_ON(i915_verify_lists(dev
));
4101 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4102 struct drm_file
*file_priv
)
4104 struct drm_i915_gem_pin
*args
= data
;
4105 struct drm_gem_object
*obj
;
4106 struct drm_i915_gem_object
*obj_priv
;
4109 ret
= i915_mutex_lock_interruptible(dev
);
4113 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4118 obj_priv
= to_intel_bo(obj
);
4120 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4121 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4126 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4127 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4133 obj_priv
->user_pin_count
++;
4134 obj_priv
->pin_filp
= file_priv
;
4135 if (obj_priv
->user_pin_count
== 1) {
4136 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4141 /* XXX - flush the CPU caches for pinned objects
4142 * as the X server doesn't manage domains yet
4144 i915_gem_object_flush_cpu_write_domain(obj
);
4145 args
->offset
= obj_priv
->gtt_offset
;
4147 drm_gem_object_unreference(obj
);
4149 mutex_unlock(&dev
->struct_mutex
);
4154 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4155 struct drm_file
*file_priv
)
4157 struct drm_i915_gem_pin
*args
= data
;
4158 struct drm_gem_object
*obj
;
4159 struct drm_i915_gem_object
*obj_priv
;
4162 ret
= i915_mutex_lock_interruptible(dev
);
4166 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4171 obj_priv
= to_intel_bo(obj
);
4173 if (obj_priv
->pin_filp
!= file_priv
) {
4174 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4179 obj_priv
->user_pin_count
--;
4180 if (obj_priv
->user_pin_count
== 0) {
4181 obj_priv
->pin_filp
= NULL
;
4182 i915_gem_object_unpin(obj
);
4186 drm_gem_object_unreference(obj
);
4188 mutex_unlock(&dev
->struct_mutex
);
4193 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4194 struct drm_file
*file_priv
)
4196 struct drm_i915_gem_busy
*args
= data
;
4197 struct drm_gem_object
*obj
;
4198 struct drm_i915_gem_object
*obj_priv
;
4201 ret
= i915_mutex_lock_interruptible(dev
);
4205 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4210 obj_priv
= to_intel_bo(obj
);
4212 /* Count all active objects as busy, even if they are currently not used
4213 * by the gpu. Users of this interface expect objects to eventually
4214 * become non-busy without any further actions, therefore emit any
4215 * necessary flushes here.
4217 args
->busy
= obj_priv
->active
;
4219 /* Unconditionally flush objects, even when the gpu still uses this
4220 * object. Userspace calling this function indicates that it wants to
4221 * use this buffer rather sooner than later, so issuing the required
4222 * flush earlier is beneficial.
4224 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4225 i915_gem_flush_ring(dev
, file_priv
,
4227 0, obj
->write_domain
);
4229 /* Update the active list for the hardware's current position.
4230 * Otherwise this only updates on a delayed timer or when irqs
4231 * are actually unmasked, and our working set ends up being
4232 * larger than required.
4234 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4236 args
->busy
= obj_priv
->active
;
4239 drm_gem_object_unreference(obj
);
4241 mutex_unlock(&dev
->struct_mutex
);
4246 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4247 struct drm_file
*file_priv
)
4249 return i915_gem_ring_throttle(dev
, file_priv
);
4253 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4254 struct drm_file
*file_priv
)
4256 struct drm_i915_gem_madvise
*args
= data
;
4257 struct drm_gem_object
*obj
;
4258 struct drm_i915_gem_object
*obj_priv
;
4261 switch (args
->madv
) {
4262 case I915_MADV_DONTNEED
:
4263 case I915_MADV_WILLNEED
:
4269 ret
= i915_mutex_lock_interruptible(dev
);
4273 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4278 obj_priv
= to_intel_bo(obj
);
4280 if (obj_priv
->pin_count
) {
4285 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4286 obj_priv
->madv
= args
->madv
;
4288 /* if the object is no longer bound, discard its backing storage */
4289 if (i915_gem_object_is_purgeable(obj_priv
) &&
4290 obj_priv
->gtt_space
== NULL
)
4291 i915_gem_object_truncate(obj
);
4293 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4296 drm_gem_object_unreference(obj
);
4298 mutex_unlock(&dev
->struct_mutex
);
4302 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4306 struct drm_i915_gem_object
*obj
;
4308 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4312 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4317 i915_gem_info_add_obj(dev_priv
, size
);
4319 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4320 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4322 obj
->agp_type
= AGP_USER_MEMORY
;
4323 obj
->base
.driver_private
= NULL
;
4324 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4325 INIT_LIST_HEAD(&obj
->mm_list
);
4326 INIT_LIST_HEAD(&obj
->ring_list
);
4327 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4328 obj
->madv
= I915_MADV_WILLNEED
;
4333 int i915_gem_init_object(struct drm_gem_object
*obj
)
4340 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4342 struct drm_device
*dev
= obj
->dev
;
4343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4344 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4347 ret
= i915_gem_object_unbind(obj
);
4348 if (ret
== -ERESTARTSYS
) {
4349 list_move(&obj_priv
->mm_list
,
4350 &dev_priv
->mm
.deferred_free_list
);
4354 if (obj_priv
->mmap_offset
)
4355 i915_gem_free_mmap_offset(obj
);
4357 drm_gem_object_release(obj
);
4358 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4360 kfree(obj_priv
->page_cpu_valid
);
4361 kfree(obj_priv
->bit_17
);
4365 void i915_gem_free_object(struct drm_gem_object
*obj
)
4367 struct drm_device
*dev
= obj
->dev
;
4368 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4370 trace_i915_gem_object_destroy(obj
);
4372 while (obj_priv
->pin_count
> 0)
4373 i915_gem_object_unpin(obj
);
4375 if (obj_priv
->phys_obj
)
4376 i915_gem_detach_phys_object(dev
, obj
);
4378 i915_gem_free_object_tail(obj
);
4382 i915_gem_idle(struct drm_device
*dev
)
4384 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4387 mutex_lock(&dev
->struct_mutex
);
4389 if (dev_priv
->mm
.suspended
) {
4390 mutex_unlock(&dev
->struct_mutex
);
4394 ret
= i915_gpu_idle(dev
);
4396 mutex_unlock(&dev
->struct_mutex
);
4400 /* Under UMS, be paranoid and evict. */
4401 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4402 ret
= i915_gem_evict_inactive(dev
);
4404 mutex_unlock(&dev
->struct_mutex
);
4409 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4410 * We need to replace this with a semaphore, or something.
4411 * And not confound mm.suspended!
4413 dev_priv
->mm
.suspended
= 1;
4414 del_timer_sync(&dev_priv
->hangcheck_timer
);
4416 i915_kernel_lost_context(dev
);
4417 i915_gem_cleanup_ringbuffer(dev
);
4419 mutex_unlock(&dev
->struct_mutex
);
4421 /* Cancel the retire work handler, which should be idle now. */
4422 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4428 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4429 * over cache flushing.
4432 i915_gem_init_pipe_control(struct drm_device
*dev
)
4434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4435 struct drm_gem_object
*obj
;
4436 struct drm_i915_gem_object
*obj_priv
;
4439 obj
= i915_gem_alloc_object(dev
, 4096);
4441 DRM_ERROR("Failed to allocate seqno page\n");
4445 obj_priv
= to_intel_bo(obj
);
4446 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4448 ret
= i915_gem_object_pin(obj
, 4096);
4452 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4453 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4454 if (dev_priv
->seqno_page
== NULL
)
4457 dev_priv
->seqno_obj
= obj
;
4458 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4463 i915_gem_object_unpin(obj
);
4465 drm_gem_object_unreference(obj
);
4472 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4474 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4475 struct drm_gem_object
*obj
;
4476 struct drm_i915_gem_object
*obj_priv
;
4478 obj
= dev_priv
->seqno_obj
;
4479 obj_priv
= to_intel_bo(obj
);
4480 kunmap(obj_priv
->pages
[0]);
4481 i915_gem_object_unpin(obj
);
4482 drm_gem_object_unreference(obj
);
4483 dev_priv
->seqno_obj
= NULL
;
4485 dev_priv
->seqno_page
= NULL
;
4489 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4491 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4494 if (HAS_PIPE_CONTROL(dev
)) {
4495 ret
= i915_gem_init_pipe_control(dev
);
4500 ret
= intel_init_render_ring_buffer(dev
);
4502 goto cleanup_pipe_control
;
4505 ret
= intel_init_bsd_ring_buffer(dev
);
4507 goto cleanup_render_ring
;
4511 ret
= intel_init_blt_ring_buffer(dev
);
4513 goto cleanup_bsd_ring
;
4516 dev_priv
->next_seqno
= 1;
4521 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4522 cleanup_render_ring
:
4523 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4524 cleanup_pipe_control
:
4525 if (HAS_PIPE_CONTROL(dev
))
4526 i915_gem_cleanup_pipe_control(dev
);
4531 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4533 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4535 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4536 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4537 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4538 if (HAS_PIPE_CONTROL(dev
))
4539 i915_gem_cleanup_pipe_control(dev
);
4543 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4544 struct drm_file
*file_priv
)
4546 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4549 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4552 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4553 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4554 atomic_set(&dev_priv
->mm
.wedged
, 0);
4557 mutex_lock(&dev
->struct_mutex
);
4558 dev_priv
->mm
.suspended
= 0;
4560 ret
= i915_gem_init_ringbuffer(dev
);
4562 mutex_unlock(&dev
->struct_mutex
);
4566 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4567 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4568 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4569 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4570 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4571 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4572 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4573 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4574 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4575 mutex_unlock(&dev
->struct_mutex
);
4577 ret
= drm_irq_install(dev
);
4579 goto cleanup_ringbuffer
;
4584 mutex_lock(&dev
->struct_mutex
);
4585 i915_gem_cleanup_ringbuffer(dev
);
4586 dev_priv
->mm
.suspended
= 1;
4587 mutex_unlock(&dev
->struct_mutex
);
4593 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4594 struct drm_file
*file_priv
)
4596 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4599 drm_irq_uninstall(dev
);
4600 return i915_gem_idle(dev
);
4604 i915_gem_lastclose(struct drm_device
*dev
)
4608 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4611 ret
= i915_gem_idle(dev
);
4613 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4617 init_ring_lists(struct intel_ring_buffer
*ring
)
4619 INIT_LIST_HEAD(&ring
->active_list
);
4620 INIT_LIST_HEAD(&ring
->request_list
);
4621 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4625 i915_gem_load(struct drm_device
*dev
)
4628 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4630 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4631 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4632 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4633 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4634 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4635 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4636 init_ring_lists(&dev_priv
->render_ring
);
4637 init_ring_lists(&dev_priv
->bsd_ring
);
4638 init_ring_lists(&dev_priv
->blt_ring
);
4639 for (i
= 0; i
< 16; i
++)
4640 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4641 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4642 i915_gem_retire_work_handler
);
4643 init_completion(&dev_priv
->error_completion
);
4644 spin_lock(&shrink_list_lock
);
4645 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4646 spin_unlock(&shrink_list_lock
);
4648 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4650 u32 tmp
= I915_READ(MI_ARB_STATE
);
4651 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4652 /* arb state is a masked write, so set bit + bit in mask */
4653 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4654 I915_WRITE(MI_ARB_STATE
, tmp
);
4658 /* Old X drivers will take 0-2 for front, back, depth buffers */
4659 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4660 dev_priv
->fence_reg_start
= 3;
4662 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4663 dev_priv
->num_fence_regs
= 16;
4665 dev_priv
->num_fence_regs
= 8;
4667 /* Initialize fence registers to zero */
4668 switch (INTEL_INFO(dev
)->gen
) {
4670 for (i
= 0; i
< 16; i
++)
4671 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4675 for (i
= 0; i
< 16; i
++)
4676 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4679 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4680 for (i
= 0; i
< 8; i
++)
4681 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4683 for (i
= 0; i
< 8; i
++)
4684 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4687 i915_gem_detect_bit_6_swizzle(dev
);
4688 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4692 * Create a physically contiguous memory object for this object
4693 * e.g. for cursor + overlay regs
4695 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4696 int id
, int size
, int align
)
4698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4699 struct drm_i915_gem_phys_object
*phys_obj
;
4702 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4705 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4711 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4712 if (!phys_obj
->handle
) {
4717 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4720 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4728 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4730 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4731 struct drm_i915_gem_phys_object
*phys_obj
;
4733 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4736 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4737 if (phys_obj
->cur_obj
) {
4738 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4742 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4744 drm_pci_free(dev
, phys_obj
->handle
);
4746 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4749 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4753 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4754 i915_gem_free_phys_object(dev
, i
);
4757 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4758 struct drm_gem_object
*obj
)
4760 struct drm_i915_gem_object
*obj_priv
;
4765 obj_priv
= to_intel_bo(obj
);
4766 if (!obj_priv
->phys_obj
)
4769 ret
= i915_gem_object_get_pages(obj
, 0);
4773 page_count
= obj
->size
/ PAGE_SIZE
;
4775 for (i
= 0; i
< page_count
; i
++) {
4776 char *dst
= kmap_atomic(obj_priv
->pages
[i
]);
4777 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4779 memcpy(dst
, src
, PAGE_SIZE
);
4782 drm_clflush_pages(obj_priv
->pages
, page_count
);
4783 drm_agp_chipset_flush(dev
);
4785 i915_gem_object_put_pages(obj
);
4787 obj_priv
->phys_obj
->cur_obj
= NULL
;
4788 obj_priv
->phys_obj
= NULL
;
4792 i915_gem_attach_phys_object(struct drm_device
*dev
,
4793 struct drm_gem_object
*obj
,
4797 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4798 struct drm_i915_gem_object
*obj_priv
;
4803 if (id
> I915_MAX_PHYS_OBJECT
)
4806 obj_priv
= to_intel_bo(obj
);
4808 if (obj_priv
->phys_obj
) {
4809 if (obj_priv
->phys_obj
->id
== id
)
4811 i915_gem_detach_phys_object(dev
, obj
);
4814 /* create a new object */
4815 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4816 ret
= i915_gem_init_phys_object(dev
, id
,
4819 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4824 /* bind to the object */
4825 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4826 obj_priv
->phys_obj
->cur_obj
= obj
;
4828 ret
= i915_gem_object_get_pages(obj
, 0);
4830 DRM_ERROR("failed to get page list\n");
4834 page_count
= obj
->size
/ PAGE_SIZE
;
4836 for (i
= 0; i
< page_count
; i
++) {
4837 char *src
= kmap_atomic(obj_priv
->pages
[i
]);
4838 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4840 memcpy(dst
, src
, PAGE_SIZE
);
4844 i915_gem_object_put_pages(obj
);
4852 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4853 struct drm_i915_gem_pwrite
*args
,
4854 struct drm_file
*file_priv
)
4856 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4859 char __user
*user_data
;
4861 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4862 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4864 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4865 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4869 drm_agp_chipset_flush(dev
);
4873 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4875 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4877 /* Clean up our request list when the client is going away, so that
4878 * later retire_requests won't dereference our soon-to-be-gone
4881 spin_lock(&file_priv
->mm
.lock
);
4882 while (!list_empty(&file_priv
->mm
.request_list
)) {
4883 struct drm_i915_gem_request
*request
;
4885 request
= list_first_entry(&file_priv
->mm
.request_list
,
4886 struct drm_i915_gem_request
,
4888 list_del(&request
->client_list
);
4889 request
->file_priv
= NULL
;
4891 spin_unlock(&file_priv
->mm
.lock
);
4895 i915_gpu_is_active(struct drm_device
*dev
)
4897 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4900 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4901 list_empty(&dev_priv
->render_ring
.active_list
) &&
4902 list_empty(&dev_priv
->bsd_ring
.active_list
) &&
4903 list_empty(&dev_priv
->blt_ring
.active_list
);
4905 return !lists_empty
;
4909 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4911 drm_i915_private_t
*dev_priv
, *next_dev
;
4912 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4914 int would_deadlock
= 1;
4916 /* "fast-path" to count number of available objects */
4917 if (nr_to_scan
== 0) {
4918 spin_lock(&shrink_list_lock
);
4919 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4920 struct drm_device
*dev
= dev_priv
->dev
;
4922 if (mutex_trylock(&dev
->struct_mutex
)) {
4923 list_for_each_entry(obj_priv
,
4924 &dev_priv
->mm
.inactive_list
,
4927 mutex_unlock(&dev
->struct_mutex
);
4930 spin_unlock(&shrink_list_lock
);
4932 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4935 spin_lock(&shrink_list_lock
);
4938 /* first scan for clean buffers */
4939 list_for_each_entry_safe(dev_priv
, next_dev
,
4940 &shrink_list
, mm
.shrink_list
) {
4941 struct drm_device
*dev
= dev_priv
->dev
;
4943 if (! mutex_trylock(&dev
->struct_mutex
))
4946 spin_unlock(&shrink_list_lock
);
4947 i915_gem_retire_requests(dev
);
4949 list_for_each_entry_safe(obj_priv
, next_obj
,
4950 &dev_priv
->mm
.inactive_list
,
4952 if (i915_gem_object_is_purgeable(obj_priv
)) {
4953 i915_gem_object_unbind(&obj_priv
->base
);
4954 if (--nr_to_scan
<= 0)
4959 spin_lock(&shrink_list_lock
);
4960 mutex_unlock(&dev
->struct_mutex
);
4964 if (nr_to_scan
<= 0)
4968 /* second pass, evict/count anything still on the inactive list */
4969 list_for_each_entry_safe(dev_priv
, next_dev
,
4970 &shrink_list
, mm
.shrink_list
) {
4971 struct drm_device
*dev
= dev_priv
->dev
;
4973 if (! mutex_trylock(&dev
->struct_mutex
))
4976 spin_unlock(&shrink_list_lock
);
4978 list_for_each_entry_safe(obj_priv
, next_obj
,
4979 &dev_priv
->mm
.inactive_list
,
4981 if (nr_to_scan
> 0) {
4982 i915_gem_object_unbind(&obj_priv
->base
);
4988 spin_lock(&shrink_list_lock
);
4989 mutex_unlock(&dev
->struct_mutex
);
4998 * We are desperate for pages, so as a last resort, wait
4999 * for the GPU to finish and discard whatever we can.
5000 * This has a dramatic impact to reduce the number of
5001 * OOM-killer events whilst running the GPU aggressively.
5003 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5004 struct drm_device
*dev
= dev_priv
->dev
;
5006 if (!mutex_trylock(&dev
->struct_mutex
))
5009 spin_unlock(&shrink_list_lock
);
5011 if (i915_gpu_is_active(dev
)) {
5016 spin_lock(&shrink_list_lock
);
5017 mutex_unlock(&dev
->struct_mutex
);
5024 spin_unlock(&shrink_list_lock
);
5029 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5034 static struct shrinker shrinker
= {
5035 .shrink
= i915_gem_shrink
,
5036 .seeks
= DEFAULT_SEEKS
,
5040 i915_gem_shrinker_init(void)
5042 register_shrinker(&shrinker
);
5046 i915_gem_shrinker_exit(void)
5048 unregister_shrinker(&shrinker
);