arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/perf_event.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/uaccess.h>
  22
  23 #include <asm/cputype.h>
  24 #include <asm/irq.h>
  25 #include <asm/irq_regs.h>
  26 #include <asm/pmu.h>
  27 #include <asm/stacktrace.h>
  28
  29 /*
  30  * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
  31  * another platform that supports more, we need to increase this to be the
  32  * largest of all platforms.
  33  *
  34  * ARMv7 supports up to 32 events:
  35  *  cycle counter CCNT + 31 events counters CNT0..30.
  36  *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
  37  */
  38 #define ARMPMU_MAX_HWEVENTS             32
  39
  40 /* The events for a given CPU. */
  41 struct cpu_hw_events {
  42         /*
  43          * The events that are active on the CPU for the given index.
  44          */
  45         struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
  46
  47         /*
  48          * A 1 bit for an index indicates that the counter is being used for
  49          * an event. A 0 means that the counter can be used.
  50          */
  51         unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
  52
  53         /*
  54          * Hardware lock to serialize accesses to PMU registers. Needed for the
  55          * read/modify/write sequences.
  56          */
  57         raw_spinlock_t          pmu_lock;
  58 };
  59 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  60
  61 struct arm_pmu {
  62         enum arm_perf_pmu_ids id;
  63         enum arm_pmu_type type;
  64         cpumask_t       active_irqs;
  65         const char      *name;
  66         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  67         void            (*enable)(struct hw_perf_event *evt, int idx);
  68         void            (*disable)(struct hw_perf_event *evt, int idx);
  69         int             (*get_event_idx)(struct cpu_hw_events *cpuc,
  70                                          struct hw_perf_event *hwc);
  71         int             (*set_event_filter)(struct hw_perf_event *evt,
  72                                             struct perf_event_attr *attr);
  73         u32             (*read_counter)(int idx);
  74         void            (*write_counter)(int idx, u32 val);
  75         void            (*start)(void);
  76         void            (*stop)(void);
  77         void            (*reset)(void *);
  78         int             (*map_event)(struct perf_event *event);
  79         int             num_events;
  80         atomic_t        active_events;
  81         struct mutex    reserve_mutex;
  82         u64             max_period;
  83         struct platform_device  *plat_device;
  84         struct cpu_hw_events    *(*get_hw_events)(void);
  85 };
  86
  87 /* Set at runtime when we know what CPU type we are. */
  88 static struct arm_pmu *armpmu;
  89
  90 enum arm_perf_pmu_ids
  91 armpmu_get_pmu_id(void)
  92 {
  93         int id = -ENODEV;
  94
  95         if (armpmu != NULL)
  96                 id = armpmu->id;
  97
  98         return id;
  99 }
 100 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
 101
 102 int
 103 armpmu_get_max_events(void)
 104 {
 105         int max_events = 0;
 106
 107         if (armpmu != NULL)
 108                 max_events = armpmu->num_events;
 109
 110         return max_events;
 111 }
 112 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
 113
 114 int perf_num_counters(void)
 115 {
 116         return armpmu_get_max_events();
 117 }
 118 EXPORT_SYMBOL_GPL(perf_num_counters);
 119
 120 #define HW_OP_UNSUPPORTED               0xFFFF
 121
 122 #define C(_x) \
 123         PERF_COUNT_HW_CACHE_##_x
 124
 125 #define CACHE_OP_UNSUPPORTED            0xFFFF
 126
 127 static int
 128 armpmu_map_cache_event(const unsigned (*cache_map)
 129                                       [PERF_COUNT_HW_CACHE_MAX]
 130                                       [PERF_COUNT_HW_CACHE_OP_MAX]
 131                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
 132                        u64 config)
 133 {
 134         unsigned int cache_type, cache_op, cache_result, ret;
 135
 136         cache_type = (config >>  0) & 0xff;
 137         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 138                 return -EINVAL;
 139
 140         cache_op = (config >>  8) & 0xff;
 141         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 142                 return -EINVAL;
 143
 144         cache_result = (config >> 16) & 0xff;
 145         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 146                 return -EINVAL;
 147
 148         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
 149
 150         if (ret == CACHE_OP_UNSUPPORTED)
 151                 return -ENOENT;
 152
 153         return ret;
 154 }
 155
 156 static int
 157 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
 158 {
 159         int mapping = (*event_map)[config];
 160         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
 161 }
 162
 163 static int
 164 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
 165 {
 166         return (int)(config & raw_event_mask);
 167 }
 168
 169 static int map_cpu_event(struct perf_event *event,
 170                          const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 171                          const unsigned (*cache_map)
 172                                         [PERF_COUNT_HW_CACHE_MAX]
 173                                         [PERF_COUNT_HW_CACHE_OP_MAX]
 174                                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
 175                          u32 raw_event_mask)
 176 {
 177         u64 config = event->attr.config;
 178
 179         switch (event->attr.type) {
 180         case PERF_TYPE_HARDWARE:
 181                 return armpmu_map_event(event_map, config);
 182         case PERF_TYPE_HW_CACHE:
 183                 return armpmu_map_cache_event(cache_map, config);
 184         case PERF_TYPE_RAW:
 185                 return armpmu_map_raw_event(raw_event_mask, config);
 186         }
 187
 188         return -ENOENT;
 189 }
 190
 191 static int
 192 armpmu_event_set_period(struct perf_event *event,
 193                         struct hw_perf_event *hwc,
 194                         int idx)
 195 {
 196         s64 left = local64_read(&hwc->period_left);
 197         s64 period = hwc->sample_period;
 198         int ret = 0;
 199
 200         if (unlikely(left <= -period)) {
 201                 left = period;
 202                 local64_set(&hwc->period_left, left);
 203                 hwc->last_period = period;
 204                 ret = 1;
 205         }
 206
 207         if (unlikely(left <= 0)) {
 208                 left += period;
 209                 local64_set(&hwc->period_left, left);
 210                 hwc->last_period = period;
 211                 ret = 1;
 212         }
 213
 214         if (left > (s64)armpmu->max_period)
 215                 left = armpmu->max_period;
 216
 217         local64_set(&hwc->prev_count, (u64)-left);
 218
 219         armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
 220
 221         perf_event_update_userpage(event);
 222
 223         return ret;
 224 }
 225
 226 static u64
 227 armpmu_event_update(struct perf_event *event,
 228                     struct hw_perf_event *hwc,
 229                     int idx, int overflow)
 230 {
 231         u64 delta, prev_raw_count, new_raw_count;
 232
 233 again:
 234         prev_raw_count = local64_read(&hwc->prev_count);
 235         new_raw_count = armpmu->read_counter(idx);
 236
 237         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 238                              new_raw_count) != prev_raw_count)
 239                 goto again;
 240
 241         new_raw_count &= armpmu->max_period;
 242         prev_raw_count &= armpmu->max_period;
 243
 244         if (overflow)
 245                 delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
 246         else
 247                 delta = new_raw_count - prev_raw_count;
 248
 249         local64_add(delta, &event->count);
 250         local64_sub(delta, &hwc->period_left);
 251
 252         return new_raw_count;
 253 }
 254
 255 static void
 256 armpmu_read(struct perf_event *event)
 257 {
 258         struct hw_perf_event *hwc = &event->hw;
 259
 260         /* Don't read disabled counters! */
 261         if (hwc->idx < 0)
 262                 return;
 263
 264         armpmu_event_update(event, hwc, hwc->idx, 0);
 265 }
 266
 267 static void
 268 armpmu_stop(struct perf_event *event, int flags)
 269 {
 270         struct hw_perf_event *hwc = &event->hw;
 271
 272         /*
 273          * ARM pmu always has to update the counter, so ignore
 274          * PERF_EF_UPDATE, see comments in armpmu_start().
 275          */
 276         if (!(hwc->state & PERF_HES_STOPPED)) {
 277                 armpmu->disable(hwc, hwc->idx);
 278                 barrier(); /* why? */
 279                 armpmu_event_update(event, hwc, hwc->idx, 0);
 280                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 281         }
 282 }
 283
 284 static void
 285 armpmu_start(struct perf_event *event, int flags)
 286 {
 287         struct hw_perf_event *hwc = &event->hw;
 288
 289         /*
 290          * ARM pmu always has to reprogram the period, so ignore
 291          * PERF_EF_RELOAD, see the comment below.
 292          */
 293         if (flags & PERF_EF_RELOAD)
 294                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 295
 296         hwc->state = 0;
 297         /*
 298          * Set the period again. Some counters can't be stopped, so when we
 299          * were stopped we simply disabled the IRQ source and the counter
 300          * may have been left counting. If we don't do this step then we may
 301          * get an interrupt too soon or *way* too late if the overflow has
 302          * happened since disabling.
 303          */
 304         armpmu_event_set_period(event, hwc, hwc->idx);
 305         armpmu->enable(hwc, hwc->idx);
 306 }
 307
 308 static void
 309 armpmu_del(struct perf_event *event, int flags)
 310 {
 311         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 312         struct hw_perf_event *hwc = &event->hw;
 313         int idx = hwc->idx;
 314
 315         WARN_ON(idx < 0);
 316
 317         armpmu_stop(event, PERF_EF_UPDATE);
 318         cpuc->events[idx] = NULL;
 319         clear_bit(idx, cpuc->used_mask);
 320
 321         perf_event_update_userpage(event);
 322 }
 323
 324 static int
 325 armpmu_add(struct perf_event *event, int flags)
 326 {
 327         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 328         struct hw_perf_event *hwc = &event->hw;
 329         int idx;
 330         int err = 0;
 331
 332         perf_pmu_disable(event->pmu);
 333
 334         /* If we don't have a space for the counter then finish early. */
 335         idx = armpmu->get_event_idx(cpuc, hwc);
 336         if (idx < 0) {
 337                 err = idx;
 338                 goto out;
 339         }
 340
 341         /*
 342          * If there is an event in the counter we are going to use then make
 343          * sure it is disabled.
 344          */
 345         event->hw.idx = idx;
 346         armpmu->disable(hwc, idx);
 347         cpuc->events[idx] = event;
 348
 349         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 350         if (flags & PERF_EF_START)
 351                 armpmu_start(event, PERF_EF_RELOAD);
 352
 353         /* Propagate our changes to the userspace mapping. */
 354         perf_event_update_userpage(event);
 355
 356 out:
 357         perf_pmu_enable(event->pmu);
 358         return err;
 359 }
 360
 361 static struct pmu pmu;
 362
 363 static int
 364 validate_event(struct cpu_hw_events *cpuc,
 365                struct perf_event *event)
 366 {
 367         struct hw_perf_event fake_event = event->hw;
 368         struct pmu *leader_pmu = event->group_leader->pmu;
 369
 370         if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 371                 return 1;
 372
 373         return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
 374 }
 375
 376 static int
 377 validate_group(struct perf_event *event)
 378 {
 379         struct perf_event *sibling, *leader = event->group_leader;
 380         struct cpu_hw_events fake_pmu;
 381
 382         memset(&fake_pmu, 0, sizeof(fake_pmu));
 383
 384         if (!validate_event(&fake_pmu, leader))
 385                 return -ENOSPC;
 386
 387         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 388                 if (!validate_event(&fake_pmu, sibling))
 389                         return -ENOSPC;
 390         }
 391
 392         if (!validate_event(&fake_pmu, event))
 393                 return -ENOSPC;
 394
 395         return 0;
 396 }
 397
 398 static irqreturn_t armpmu_platform_irq(int irq, void *dev)
 399 {
 400         struct platform_device *plat_device = armpmu->plat_device;
 401         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 402
 403         return plat->handle_irq(irq, dev, armpmu->handle_irq);
 404 }
 405
 406 static void
 407 armpmu_release_hardware(void)
 408 {
 409         int i, irq, irqs;
 410         struct platform_device *pmu_device = armpmu->plat_device;
 411
 412         irqs = min(pmu_device->num_resources, num_possible_cpus());
 413
 414         for (i = 0; i < irqs; ++i) {
 415                 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
 416                         continue;
 417                 irq = platform_get_irq(pmu_device, i);
 418                 if (irq >= 0)
 419                         free_irq(irq, NULL);
 420         }
 421
 422         release_pmu(armpmu->type);
 423 }
 424
 425 static int
 426 armpmu_reserve_hardware(void)
 427 {
 428         struct arm_pmu_platdata *plat;
 429         irq_handler_t handle_irq;
 430         int i, err, irq, irqs;
 431         struct platform_device *pmu_device = armpmu->plat_device;
 432
 433         err = reserve_pmu(armpmu->type);
 434         if (err) {
 435                 pr_warning("unable to reserve pmu\n");
 436                 return err;
 437         }
 438
 439         plat = dev_get_platdata(&pmu_device->dev);
 440         if (plat && plat->handle_irq)
 441                 handle_irq = armpmu_platform_irq;
 442         else
 443                 handle_irq = armpmu->handle_irq;
 444
 445         irqs = min(pmu_device->num_resources, num_possible_cpus());
 446         if (irqs < 1) {
 447                 pr_err("no irqs for PMUs defined\n");
 448                 return -ENODEV;
 449         }
 450
 451         for (i = 0; i < irqs; ++i) {
 452                 err = 0;
 453                 irq = platform_get_irq(pmu_device, i);
 454                 if (irq < 0)
 455                         continue;
 456
 457                 /*
 458                  * If we have a single PMU interrupt that we can't shift,
 459                  * assume that we're running on a uniprocessor machine and
 460                  * continue. Otherwise, continue without this interrupt.
 461                  */
 462                 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
 463                         pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
 464                                     irq, i);
 465                         continue;
 466                 }
 467
 468                 err = request_irq(irq, handle_irq,
 469                                   IRQF_DISABLED | IRQF_NOBALANCING,
 470                                   "arm-pmu", NULL);
 471                 if (err) {
 472                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 473                                 irq);
 474                         armpmu_release_hardware();
 475                         return err;
 476                 }
 477
 478                 cpumask_set_cpu(i, &armpmu->active_irqs);
 479         }
 480
 481         return 0;
 482 }
 483
 484 static void
 485 hw_perf_event_destroy(struct perf_event *event)
 486 {
 487         atomic_t *active_events  = &armpmu->active_events;
 488         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 489
 490         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 491                 armpmu_release_hardware();
 492                 mutex_unlock(pmu_reserve_mutex);
 493         }
 494 }
 495
 496 static int
 497 event_requires_mode_exclusion(struct perf_event_attr *attr)
 498 {
 499         return attr->exclude_idle || attr->exclude_user ||
 500                attr->exclude_kernel || attr->exclude_hv;
 501 }
 502
 503 static int
 504 __hw_perf_event_init(struct perf_event *event)
 505 {
 506         struct hw_perf_event *hwc = &event->hw;
 507         int mapping, err;
 508
 509         mapping = armpmu->map_event(event);
 510
 511         if (mapping < 0) {
 512                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 513                          event->attr.config);
 514                 return mapping;
 515         }
 516
 517         /*
 518          * We don't assign an index until we actually place the event onto
 519          * hardware. Use -1 to signify that we haven't decided where to put it
 520          * yet. For SMP systems, each core has it's own PMU so we can't do any
 521          * clever allocation or constraints checking at this point.
 522          */
 523         hwc->idx                = -1;
 524         hwc->config_base        = 0;
 525         hwc->config             = 0;
 526         hwc->event_base         = 0;
 527
 528         /*
 529          * Check whether we need to exclude the counter from certain modes.
 530          */
 531         if ((!armpmu->set_event_filter ||
 532              armpmu->set_event_filter(hwc, &event->attr)) &&
 533              event_requires_mode_exclusion(&event->attr)) {
 534                 pr_debug("ARM performance counters do not support "
 535                          "mode exclusion\n");
 536                 return -EPERM;
 537         }
 538
 539         /*
 540          * Store the event encoding into the config_base field.
 541          */
 542         hwc->config_base            |= (unsigned long)mapping;
 543
 544         if (!hwc->sample_period) {
 545                 hwc->sample_period  = armpmu->max_period;
 546                 hwc->last_period    = hwc->sample_period;
 547                 local64_set(&hwc->period_left, hwc->sample_period);
 548         }
 549
 550         err = 0;
 551         if (event->group_leader != event) {
 552                 err = validate_group(event);
 553                 if (err)
 554                         return -EINVAL;
 555         }
 556
 557         return err;
 558 }
 559
 560 static int armpmu_event_init(struct perf_event *event)
 561 {
 562         int err = 0;
 563         atomic_t *active_events = &armpmu->active_events;
 564
 565         if (armpmu->map_event(event) == -ENOENT)
 566                 return -ENOENT;
 567
 568         event->destroy = hw_perf_event_destroy;
 569
 570         if (!atomic_inc_not_zero(active_events)) {
 571                 mutex_lock(&armpmu->reserve_mutex);
 572                 if (atomic_read(active_events) == 0)
 573                         err = armpmu_reserve_hardware();
 574
 575                 if (!err)
 576                         atomic_inc(active_events);
 577                 mutex_unlock(&armpmu->reserve_mutex);
 578         }
 579
 580         if (err)
 581                 return err;
 582
 583         err = __hw_perf_event_init(event);
 584         if (err)
 585                 hw_perf_event_destroy(event);
 586
 587         return err;
 588 }
 589
 590 static void armpmu_enable(struct pmu *pmu)
 591 {
 592         /* Enable all of the perf events on hardware. */
 593         int idx, enabled = 0;
 594         struct cpu_hw_events *cpuc = armpmu->get_hw_events();
 595
 596         for (idx = 0; idx < armpmu->num_events; ++idx) {
 597                 struct perf_event *event = cpuc->events[idx];
 598
 599                 if (!event)
 600                         continue;
 601
 602                 armpmu->enable(&event->hw, idx);
 603                 enabled = 1;
 604         }
 605
 606         if (enabled)
 607                 armpmu->start();
 608 }
 609
 610 static void armpmu_disable(struct pmu *pmu)
 611 {
 612         armpmu->stop();
 613 }
 614
 615 static struct pmu pmu = {
 616         .pmu_enable     = armpmu_enable,
 617         .pmu_disable    = armpmu_disable,
 618         .event_init     = armpmu_event_init,
 619         .add            = armpmu_add,
 620         .del            = armpmu_del,
 621         .start          = armpmu_start,
 622         .stop           = armpmu_stop,
 623         .read           = armpmu_read,
 624 };
 625
 626 static void __init armpmu_init(struct arm_pmu *armpmu)
 627 {
 628         atomic_set(&armpmu->active_events, 0);
 629         mutex_init(&armpmu->reserve_mutex);
 630 }
 631
 632 /* Include the PMU-specific implementations. */
 633 #include "perf_event_xscale.c"
 634 #include "perf_event_v6.c"
 635 #include "perf_event_v7.c"
 636
 637 /*
 638  * Ensure the PMU has sane values out of reset.
 639  * This requires SMP to be available, so exists as a separate initcall.
 640  */
 641 static int __init
 642 armpmu_reset(void)
 643 {
 644         if (armpmu && armpmu->reset)
 645                 return on_each_cpu(armpmu->reset, NULL, 1);
 646         return 0;
 647 }
 648 arch_initcall(armpmu_reset);
 649
 650 /*
 651  * PMU platform driver and devicetree bindings.
 652  */
 653 static struct of_device_id armpmu_of_device_ids[] = {
 654         {.compatible = "arm,cortex-a9-pmu"},
 655         {.compatible = "arm,cortex-a8-pmu"},
 656         {.compatible = "arm,arm1136-pmu"},
 657         {.compatible = "arm,arm1176-pmu"},
 658         {},
 659 };
 660
 661 static struct platform_device_id armpmu_plat_device_ids[] = {
 662         {.name = "arm-pmu"},
 663         {},
 664 };
 665
 666 static int __devinit armpmu_device_probe(struct platform_device *pdev)
 667 {
 668         armpmu->plat_device = pdev;
 669         return 0;
 670 }
 671
 672 static struct platform_driver armpmu_driver = {
 673         .driver         = {
 674                 .name   = "arm-pmu",
 675                 .of_match_table = armpmu_of_device_ids,
 676         },
 677         .probe          = armpmu_device_probe,
 678         .id_table       = armpmu_plat_device_ids,
 679 };
 680
 681 static int __init register_pmu_driver(void)
 682 {
 683         return platform_driver_register(&armpmu_driver);
 684 }
 685 device_initcall(register_pmu_driver);
 686
 687 static struct cpu_hw_events *armpmu_get_cpu_events(void)
 688 {
 689         return &__get_cpu_var(cpu_hw_events);
 690 }
 691
 692 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
 693 {
 694         int cpu;
 695         for_each_possible_cpu(cpu) {
 696                 struct cpu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
 697                 raw_spin_lock_init(&events->pmu_lock);
 698         }
 699         armpmu->get_hw_events = armpmu_get_cpu_events;
 700         armpmu->type = ARM_PMU_DEVICE_CPU;
 701 }
 702
 703 /*
 704  * CPU PMU identification and registration.
 705  */
 706 static int __init
 707 init_hw_perf_events(void)
 708 {
 709         unsigned long cpuid = read_cpuid_id();
 710         unsigned long implementor = (cpuid & 0xFF000000) >> 24;
 711         unsigned long part_number = (cpuid & 0xFFF0);
 712
 713         /* ARM Ltd CPUs. */
 714         if (0x41 == implementor) {
 715                 switch (part_number) {
 716                 case 0xB360:    /* ARM1136 */
 717                 case 0xB560:    /* ARM1156 */
 718                 case 0xB760:    /* ARM1176 */
 719                         armpmu = armv6pmu_init();
 720                         break;
 721                 case 0xB020:    /* ARM11mpcore */
 722                         armpmu = armv6mpcore_pmu_init();
 723                         break;
 724                 case 0xC080:    /* Cortex-A8 */
 725                         armpmu = armv7_a8_pmu_init();
 726                         break;
 727                 case 0xC090:    /* Cortex-A9 */
 728                         armpmu = armv7_a9_pmu_init();
 729                         break;
 730                 case 0xC050:    /* Cortex-A5 */
 731                         armpmu = armv7_a5_pmu_init();
 732                         break;
 733                 case 0xC0F0:    /* Cortex-A15 */
 734                         armpmu = armv7_a15_pmu_init();
 735                         break;
 736                 }
 737         /* Intel CPUs [xscale]. */
 738         } else if (0x69 == implementor) {
 739                 part_number = (cpuid >> 13) & 0x7;
 740                 switch (part_number) {
 741                 case 1:
 742                         armpmu = xscale1pmu_init();
 743                         break;
 744                 case 2:
 745                         armpmu = xscale2pmu_init();
 746                         break;
 747                 }
 748         }
 749
 750         if (armpmu) {
 751                 pr_info("enabled with %s PMU driver, %d counters available\n",
 752                         armpmu->name, armpmu->num_events);
 753                 cpu_pmu_init(armpmu);
 754                 armpmu_init(armpmu);
 755                 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
 756         } else {
 757                 pr_info("no hardware support available\n");
 758         }
 759
 760         return 0;
 761 }
 762 early_initcall(init_hw_perf_events);
 763
 764 /*
 765  * Callchain handling code.
 766  */
 767
 768 /*
 769  * The registers we're interested in are at the end of the variable
 770  * length saved register structure. The fp points at the end of this
 771  * structure so the address of this struct is:
 772  * (struct frame_tail *)(xxx->fp)-1
 773  *
 774  * This code has been adapted from the ARM OProfile support.
 775  */
 776 struct frame_tail {
 777         struct frame_tail __user *fp;
 778         unsigned long sp;
 779         unsigned long lr;
 780 } __attribute__((packed));
 781
 782 /*
 783  * Get the return address for a single stackframe and return a pointer to the
 784  * next frame tail.
 785  */
 786 static struct frame_tail __user *
 787 user_backtrace(struct frame_tail __user *tail,
 788                struct perf_callchain_entry *entry)
 789 {
 790         struct frame_tail buftail;
 791
 792         /* Also check accessibility of one struct frame_tail beyond */
 793         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 794                 return NULL;
 795         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 796                 return NULL;
 797
 798         perf_callchain_store(entry, buftail.lr);
 799
 800         /*
 801          * Frame pointers should strictly progress back up the stack
 802          * (towards higher addresses).
 803          */
 804         if (tail + 1 >= buftail.fp)
 805                 return NULL;
 806
 807         return buftail.fp - 1;
 808 }
 809
 810 void
 811 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 812 {
 813         struct frame_tail __user *tail;
 814
 815
 816         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 817
 818         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 819                tail && !((unsigned long)tail & 0x3))
 820                 tail = user_backtrace(tail, entry);
 821 }
 822
 823 /*
 824  * Gets called by walk_stackframe() for every stackframe. This will be called
 825  * whist unwinding the stackframe and is like a subroutine return so we use
 826  * the PC.
 827  */
 828 static int
 829 callchain_trace(struct stackframe *fr,
 830                 void *data)
 831 {
 832         struct perf_callchain_entry *entry = data;
 833         perf_callchain_store(entry, fr->pc);
 834         return 0;
 835 }
 836
 837 void
 838 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 839 {
 840         struct stackframe fr;
 841
 842         fr.fp = regs->ARM_fp;
 843         fr.sp = regs->ARM_sp;
 844         fr.lr = regs->ARM_lr;
 845         fr.pc = regs->ARM_pc;
 846         walk_stackframe(&fr, callchain_trace, entry);
 847 }