?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
cnic: Fix ring setup/shutdown code
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / cnic.c
blobbdfe15566ce4af86244dce876ee8bc5c0da42d1c
1 /* cnic.c: Broadcom CNIC core network driver.
2 *
3 * Copyright (c) 2006-2011 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
10 * Modified and maintained by: Michael Chan <mchan@broadcom.com>
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/netdevice.h>
24 #include <linux/uio_driver.h>
25 #include <linux/in.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/delay.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/prefetch.h>
31 #include <linux/random.h>
32 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
33 #define BCM_VLAN 1
34 #endif
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/route.h>
38 #include <net/ipv6.h>
39 #include <net/ip6_route.h>
40 #include <net/ip6_checksum.h>
41 #include <scsi/iscsi_if.h>
42
43 #include "cnic_if.h"
44 #include "bnx2.h"
45 #include "bnx2x/bnx2x_reg.h"
46 #include "bnx2x/bnx2x_fw_defs.h"
47 #include "bnx2x/bnx2x_hsi.h"
48 #include "../scsi/bnx2i/57xx_iscsi_constants.h"
49 #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
50 #include "cnic.h"
51 #include "cnic_defs.h"
52
53 #define DRV_MODULE_NAME "cnic"
54
55 static char version[] __devinitdata =
56 "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
57
58 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
59 "Chen (zongxi@broadcom.com");
60 MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
61 MODULE_LICENSE("GPL");
62 MODULE_VERSION(CNIC_MODULE_VERSION);
63
64 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
65 static LIST_HEAD(cnic_dev_list);
66 static LIST_HEAD(cnic_udev_list);
67 static DEFINE_RWLOCK(cnic_dev_lock);
68 static DEFINE_MUTEX(cnic_lock);
69
70 static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
71
72 /* helper function, assuming cnic_lock is held */
73 static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
74 {
75 return rcu_dereference_protected(cnic_ulp_tbl[type],
76 lockdep_is_held(&cnic_lock));
77 }
78
79 static int cnic_service_bnx2(void *, void *);
80 static int cnic_service_bnx2x(void *, void *);
81 static int cnic_ctl(void *, struct cnic_ctl_info *);
82
83 static struct cnic_ops cnic_bnx2_ops = {
84 .cnic_owner = THIS_MODULE,
85 .cnic_handler = cnic_service_bnx2,
86 .cnic_ctl = cnic_ctl,
87 };
88
89 static struct cnic_ops cnic_bnx2x_ops = {
90 .cnic_owner = THIS_MODULE,
91 .cnic_handler = cnic_service_bnx2x,
92 .cnic_ctl = cnic_ctl,
93 };
94
95 static struct workqueue_struct *cnic_wq;
96
97 static void cnic_shutdown_rings(struct cnic_dev *);
98 static void cnic_init_rings(struct cnic_dev *);
99 static int cnic_cm_set_pg(struct cnic_sock *);
100
101 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
102 {
103 struct cnic_uio_dev *udev = uinfo->priv;
104 struct cnic_dev *dev;
105
106 if (!capable(CAP_NET_ADMIN))
107 return -EPERM;
108
109 if (udev->uio_dev != -1)
110 return -EBUSY;
111
112 rtnl_lock();
113 dev = udev->dev;
114
115 if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
116 rtnl_unlock();
117 return -ENODEV;
118 }
119
120 udev->uio_dev = iminor(inode);
121
122 cnic_shutdown_rings(dev);
123 cnic_init_rings(dev);
124 rtnl_unlock();
125
126 return 0;
127 }
128
129 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
130 {
131 struct cnic_uio_dev *udev = uinfo->priv;
132
133 udev->uio_dev = -1;
134 return 0;
135 }
136
137 static inline void cnic_hold(struct cnic_dev *dev)
138 {
139 atomic_inc(&dev->ref_count);
140 }
141
142 static inline void cnic_put(struct cnic_dev *dev)
143 {
144 atomic_dec(&dev->ref_count);
145 }
146
147 static inline void csk_hold(struct cnic_sock *csk)
148 {
149 atomic_inc(&csk->ref_count);
150 }
151
152 static inline void csk_put(struct cnic_sock *csk)
153 {
154 atomic_dec(&csk->ref_count);
155 }
156
157 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
158 {
159 struct cnic_dev *cdev;
160
161 read_lock(&cnic_dev_lock);
162 list_for_each_entry(cdev, &cnic_dev_list, list) {
163 if (netdev == cdev->netdev) {
164 cnic_hold(cdev);
165 read_unlock(&cnic_dev_lock);
166 return cdev;
167 }
168 }
169 read_unlock(&cnic_dev_lock);
170 return NULL;
171 }
172
173 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
174 {
175 atomic_inc(&ulp_ops->ref_count);
176 }
177
178 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
179 {
180 atomic_dec(&ulp_ops->ref_count);
181 }
182
183 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
184 {
185 struct cnic_local *cp = dev->cnic_priv;
186 struct cnic_eth_dev *ethdev = cp->ethdev;
187 struct drv_ctl_info info;
188 struct drv_ctl_io *io = &info.data.io;
189
190 info.cmd = DRV_CTL_CTX_WR_CMD;
191 io->cid_addr = cid_addr;
192 io->offset = off;
193 io->data = val;
194 ethdev->drv_ctl(dev->netdev, &info);
195 }
196
197 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
198 {
199 struct cnic_local *cp = dev->cnic_priv;
200 struct cnic_eth_dev *ethdev = cp->ethdev;
201 struct drv_ctl_info info;
202 struct drv_ctl_io *io = &info.data.io;
203
204 info.cmd = DRV_CTL_CTXTBL_WR_CMD;
205 io->offset = off;
206 io->dma_addr = addr;
207 ethdev->drv_ctl(dev->netdev, &info);
208 }
209
210 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
211 {
212 struct cnic_local *cp = dev->cnic_priv;
213 struct cnic_eth_dev *ethdev = cp->ethdev;
214 struct drv_ctl_info info;
215 struct drv_ctl_l2_ring *ring = &info.data.ring;
216
217 if (start)
218 info.cmd = DRV_CTL_START_L2_CMD;
219 else
220 info.cmd = DRV_CTL_STOP_L2_CMD;
221
222 ring->cid = cid;
223 ring->client_id = cl_id;
224 ethdev->drv_ctl(dev->netdev, &info);
225 }
226
227 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
228 {
229 struct cnic_local *cp = dev->cnic_priv;
230 struct cnic_eth_dev *ethdev = cp->ethdev;
231 struct drv_ctl_info info;
232 struct drv_ctl_io *io = &info.data.io;
233
234 info.cmd = DRV_CTL_IO_WR_CMD;
235 io->offset = off;
236 io->data = val;
237 ethdev->drv_ctl(dev->netdev, &info);
238 }
239
240 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
241 {
242 struct cnic_local *cp = dev->cnic_priv;
243 struct cnic_eth_dev *ethdev = cp->ethdev;
244 struct drv_ctl_info info;
245 struct drv_ctl_io *io = &info.data.io;
246
247 info.cmd = DRV_CTL_IO_RD_CMD;
248 io->offset = off;
249 ethdev->drv_ctl(dev->netdev, &info);
250 return io->data;
251 }
252
253 static int cnic_in_use(struct cnic_sock *csk)
254 {
255 return test_bit(SK_F_INUSE, &csk->flags);
256 }
257
258 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
259 {
260 struct cnic_local *cp = dev->cnic_priv;
261 struct cnic_eth_dev *ethdev = cp->ethdev;
262 struct drv_ctl_info info;
263
264 info.cmd = cmd;
265 info.data.credit.credit_count = count;
266 ethdev->drv_ctl(dev->netdev, &info);
267 }
268
269 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
270 {
271 u32 i;
272
273 for (i = 0; i < cp->max_cid_space; i++) {
274 if (cp->ctx_tbl[i].cid == cid) {
275 *l5_cid = i;
276 return 0;
277 }
278 }
279 return -EINVAL;
280 }
281
282 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
283 struct cnic_sock *csk)
284 {
285 struct iscsi_path path_req;
286 char *buf = NULL;
287 u16 len = 0;
288 u32 msg_type = ISCSI_KEVENT_IF_DOWN;
289 struct cnic_ulp_ops *ulp_ops;
290 struct cnic_uio_dev *udev = cp->udev;
291 int rc = 0, retry = 0;
292
293 if (!udev || udev->uio_dev == -1)
294 return -ENODEV;
295
296 if (csk) {
297 len = sizeof(path_req);
298 buf = (char *) &path_req;
299 memset(&path_req, 0, len);
300
301 msg_type = ISCSI_KEVENT_PATH_REQ;
302 path_req.handle = (u64) csk->l5_cid;
303 if (test_bit(SK_F_IPV6, &csk->flags)) {
304 memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
305 sizeof(struct in6_addr));
306 path_req.ip_addr_len = 16;
307 } else {
308 memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
309 sizeof(struct in_addr));
310 path_req.ip_addr_len = 4;
311 }
312 path_req.vlan_id = csk->vlan_id;
313 path_req.pmtu = csk->mtu;
314 }
315
316 while (retry < 3) {
317 rc = 0;
318 rcu_read_lock();
319 ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
320 if (ulp_ops)
321 rc = ulp_ops->iscsi_nl_send_msg(
322 cp->ulp_handle[CNIC_ULP_ISCSI],
323 msg_type, buf, len);
324 rcu_read_unlock();
325 if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
326 break;
327
328 msleep(100);
329 retry++;
330 }
331 return 0;
332 }
333
334 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
335
336 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
337 char *buf, u16 len)
338 {
339 int rc = -EINVAL;
340
341 switch (msg_type) {
342 case ISCSI_UEVENT_PATH_UPDATE: {
343 struct cnic_local *cp;
344 u32 l5_cid;
345 struct cnic_sock *csk;
346 struct iscsi_path *path_resp;
347
348 if (len < sizeof(*path_resp))
349 break;
350
351 path_resp = (struct iscsi_path *) buf;
352 cp = dev->cnic_priv;
353 l5_cid = (u32) path_resp->handle;
354 if (l5_cid >= MAX_CM_SK_TBL_SZ)
355 break;
356
357 rcu_read_lock();
358 if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
359 rc = -ENODEV;
360 rcu_read_unlock();
361 break;
362 }
363 csk = &cp->csk_tbl[l5_cid];
364 csk_hold(csk);
365 if (cnic_in_use(csk) &&
366 test_bit(SK_F_CONNECT_START, &csk->flags)) {
367
368 memcpy(csk->ha, path_resp->mac_addr, 6);
369 if (test_bit(SK_F_IPV6, &csk->flags))
370 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
371 sizeof(struct in6_addr));
372 else
373 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
374 sizeof(struct in_addr));
375
376 if (is_valid_ether_addr(csk->ha)) {
377 cnic_cm_set_pg(csk);
378 } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
379 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
380
381 cnic_cm_upcall(cp, csk,
382 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
383 clear_bit(SK_F_CONNECT_START, &csk->flags);
384 }
385 }
386 csk_put(csk);
387 rcu_read_unlock();
388 rc = 0;
389 }
390 }
391
392 return rc;
393 }
394
395 static int cnic_offld_prep(struct cnic_sock *csk)
396 {
397 if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
398 return 0;
399
400 if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
401 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
402 return 0;
403 }
404
405 return 1;
406 }
407
408 static int cnic_close_prep(struct cnic_sock *csk)
409 {
410 clear_bit(SK_F_CONNECT_START, &csk->flags);
411 smp_mb__after_clear_bit();
412
413 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
414 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
415 msleep(1);
416
417 return 1;
418 }
419 return 0;
420 }
421
422 static int cnic_abort_prep(struct cnic_sock *csk)
423 {
424 clear_bit(SK_F_CONNECT_START, &csk->flags);
425 smp_mb__after_clear_bit();
426
427 while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
428 msleep(1);
429
430 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
431 csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
432 return 1;
433 }
434
435 return 0;
436 }
437
438 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
439 {
440 struct cnic_dev *dev;
441
442 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
443 pr_err("%s: Bad type %d\n", __func__, ulp_type);
444 return -EINVAL;
445 }
446 mutex_lock(&cnic_lock);
447 if (cnic_ulp_tbl_prot(ulp_type)) {
448 pr_err("%s: Type %d has already been registered\n",
449 __func__, ulp_type);
450 mutex_unlock(&cnic_lock);
451 return -EBUSY;
452 }
453
454 read_lock(&cnic_dev_lock);
455 list_for_each_entry(dev, &cnic_dev_list, list) {
456 struct cnic_local *cp = dev->cnic_priv;
457
458 clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
459 }
460 read_unlock(&cnic_dev_lock);
461
462 atomic_set(&ulp_ops->ref_count, 0);
463 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
464 mutex_unlock(&cnic_lock);
465
466 /* Prevent race conditions with netdev_event */
467 rtnl_lock();
468 list_for_each_entry(dev, &cnic_dev_list, list) {
469 struct cnic_local *cp = dev->cnic_priv;
470
471 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
472 ulp_ops->cnic_init(dev);
473 }
474 rtnl_unlock();
475
476 return 0;
477 }
478
479 int cnic_unregister_driver(int ulp_type)
480 {
481 struct cnic_dev *dev;
482 struct cnic_ulp_ops *ulp_ops;
483 int i = 0;
484
485 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
486 pr_err("%s: Bad type %d\n", __func__, ulp_type);
487 return -EINVAL;
488 }
489 mutex_lock(&cnic_lock);
490 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
491 if (!ulp_ops) {
492 pr_err("%s: Type %d has not been registered\n",
493 __func__, ulp_type);
494 goto out_unlock;
495 }
496 read_lock(&cnic_dev_lock);
497 list_for_each_entry(dev, &cnic_dev_list, list) {
498 struct cnic_local *cp = dev->cnic_priv;
499
500 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
501 pr_err("%s: Type %d still has devices registered\n",
502 __func__, ulp_type);
503 read_unlock(&cnic_dev_lock);
504 goto out_unlock;
505 }
506 }
507 read_unlock(&cnic_dev_lock);
508
509 rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
510
511 mutex_unlock(&cnic_lock);
512 synchronize_rcu();
513 while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
514 msleep(100);
515 i++;
516 }
517
518 if (atomic_read(&ulp_ops->ref_count) != 0)
519 netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
520 return 0;
521
522 out_unlock:
523 mutex_unlock(&cnic_lock);
524 return -EINVAL;
525 }
526
527 static int cnic_start_hw(struct cnic_dev *);
528 static void cnic_stop_hw(struct cnic_dev *);
529
530 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
531 void *ulp_ctx)
532 {
533 struct cnic_local *cp = dev->cnic_priv;
534 struct cnic_ulp_ops *ulp_ops;
535
536 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
537 pr_err("%s: Bad type %d\n", __func__, ulp_type);
538 return -EINVAL;
539 }
540 mutex_lock(&cnic_lock);
541 if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
542 pr_err("%s: Driver with type %d has not been registered\n",
543 __func__, ulp_type);
544 mutex_unlock(&cnic_lock);
545 return -EAGAIN;
546 }
547 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
548 pr_err("%s: Type %d has already been registered to this device\n",
549 __func__, ulp_type);
550 mutex_unlock(&cnic_lock);
551 return -EBUSY;
552 }
553
554 clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
555 cp->ulp_handle[ulp_type] = ulp_ctx;
556 ulp_ops = cnic_ulp_tbl_prot(ulp_type);
557 rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
558 cnic_hold(dev);
559
560 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
561 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
562 ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
563
564 mutex_unlock(&cnic_lock);
565
566 return 0;
567
568 }
569 EXPORT_SYMBOL(cnic_register_driver);
570
571 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
572 {
573 struct cnic_local *cp = dev->cnic_priv;
574 int i = 0;
575
576 if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
577 pr_err("%s: Bad type %d\n", __func__, ulp_type);
578 return -EINVAL;
579 }
580 mutex_lock(&cnic_lock);
581 if (rcu_dereference(cp->ulp_ops[ulp_type])) {
582 rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
583 cnic_put(dev);
584 } else {
585 pr_err("%s: device not registered to this ulp type %d\n",
586 __func__, ulp_type);
587 mutex_unlock(&cnic_lock);
588 return -EINVAL;
589 }
590 mutex_unlock(&cnic_lock);
591
592 if (ulp_type == CNIC_ULP_ISCSI)
593 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
594
595 synchronize_rcu();
596
597 while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
598 i < 20) {
599 msleep(100);
600 i++;
601 }
602 if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
603 netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
604
605 return 0;
606 }
607 EXPORT_SYMBOL(cnic_unregister_driver);
608
609 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
610 u32 next)
611 {
612 id_tbl->start = start_id;
613 id_tbl->max = size;
614 id_tbl->next = next;
615 spin_lock_init(&id_tbl->lock);
616 id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
617 if (!id_tbl->table)
618 return -ENOMEM;
619
620 return 0;
621 }
622
623 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
624 {
625 kfree(id_tbl->table);
626 id_tbl->table = NULL;
627 }
628
629 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
630 {
631 int ret = -1;
632
633 id -= id_tbl->start;
634 if (id >= id_tbl->max)
635 return ret;
636
637 spin_lock(&id_tbl->lock);
638 if (!test_bit(id, id_tbl->table)) {
639 set_bit(id, id_tbl->table);
640 ret = 0;
641 }
642 spin_unlock(&id_tbl->lock);
643 return ret;
644 }
645
646 /* Returns -1 if not successful */
647 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
648 {
649 u32 id;
650
651 spin_lock(&id_tbl->lock);
652 id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
653 if (id >= id_tbl->max) {
654 id = -1;
655 if (id_tbl->next != 0) {
656 id = find_first_zero_bit(id_tbl->table, id_tbl->next);
657 if (id >= id_tbl->next)
658 id = -1;
659 }
660 }
661
662 if (id < id_tbl->max) {
663 set_bit(id, id_tbl->table);
664 id_tbl->next = (id + 1) & (id_tbl->max - 1);
665 id += id_tbl->start;
666 }
667
668 spin_unlock(&id_tbl->lock);
669
670 return id;
671 }
672
673 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
674 {
675 if (id == -1)
676 return;
677
678 id -= id_tbl->start;
679 if (id >= id_tbl->max)
680 return;
681
682 clear_bit(id, id_tbl->table);
683 }
684
685 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
686 {
687 int i;
688
689 if (!dma->pg_arr)
690 return;
691
692 for (i = 0; i < dma->num_pages; i++) {
693 if (dma->pg_arr[i]) {
694 dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
695 dma->pg_arr[i], dma->pg_map_arr[i]);
696 dma->pg_arr[i] = NULL;
697 }
698 }
699 if (dma->pgtbl) {
700 dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
701 dma->pgtbl, dma->pgtbl_map);
702 dma->pgtbl = NULL;
703 }
704 kfree(dma->pg_arr);
705 dma->pg_arr = NULL;
706 dma->num_pages = 0;
707 }
708
709 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
710 {
711 int i;
712 __le32 *page_table = (__le32 *) dma->pgtbl;
713
714 for (i = 0; i < dma->num_pages; i++) {
715 /* Each entry needs to be in big endian format. */
716 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
717 page_table++;
718 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
719 page_table++;
720 }
721 }
722
723 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
724 {
725 int i;
726 __le32 *page_table = (__le32 *) dma->pgtbl;
727
728 for (i = 0; i < dma->num_pages; i++) {
729 /* Each entry needs to be in little endian format. */
730 *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
731 page_table++;
732 *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
733 page_table++;
734 }
735 }
736
737 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
738 int pages, int use_pg_tbl)
739 {
740 int i, size;
741 struct cnic_local *cp = dev->cnic_priv;
742
743 size = pages * (sizeof(void *) + sizeof(dma_addr_t));
744 dma->pg_arr = kzalloc(size, GFP_ATOMIC);
745 if (dma->pg_arr == NULL)
746 return -ENOMEM;
747
748 dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
749 dma->num_pages = pages;
750
751 for (i = 0; i < pages; i++) {
752 dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
753 BCM_PAGE_SIZE,
754 &dma->pg_map_arr[i],
755 GFP_ATOMIC);
756 if (dma->pg_arr[i] == NULL)
757 goto error;
758 }
759 if (!use_pg_tbl)
760 return 0;
761
762 dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
763 ~(BCM_PAGE_SIZE - 1);
764 dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
765 &dma->pgtbl_map, GFP_ATOMIC);
766 if (dma->pgtbl == NULL)
767 goto error;
768
769 cp->setup_pgtbl(dev, dma);
770
771 return 0;
772
773 error:
774 cnic_free_dma(dev, dma);
775 return -ENOMEM;
776 }
777
778 static void cnic_free_context(struct cnic_dev *dev)
779 {
780 struct cnic_local *cp = dev->cnic_priv;
781 int i;
782
783 for (i = 0; i < cp->ctx_blks; i++) {
784 if (cp->ctx_arr[i].ctx) {
785 dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
786 cp->ctx_arr[i].ctx,
787 cp->ctx_arr[i].mapping);
788 cp->ctx_arr[i].ctx = NULL;
789 }
790 }
791 }
792
793 static void __cnic_free_uio(struct cnic_uio_dev *udev)
794 {
795 uio_unregister_device(&udev->cnic_uinfo);
796
797 if (udev->l2_buf) {
798 dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
799 udev->l2_buf, udev->l2_buf_map);
800 udev->l2_buf = NULL;
801 }
802
803 if (udev->l2_ring) {
804 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
805 udev->l2_ring, udev->l2_ring_map);
806 udev->l2_ring = NULL;
807 }
808
809 pci_dev_put(udev->pdev);
810 kfree(udev);
811 }
812
813 static void cnic_free_uio(struct cnic_uio_dev *udev)
814 {
815 if (!udev)
816 return;
817
818 write_lock(&cnic_dev_lock);
819 list_del_init(&udev->list);
820 write_unlock(&cnic_dev_lock);
821 __cnic_free_uio(udev);
822 }
823
824 static void cnic_free_resc(struct cnic_dev *dev)
825 {
826 struct cnic_local *cp = dev->cnic_priv;
827 struct cnic_uio_dev *udev = cp->udev;
828
829 if (udev) {
830 udev->dev = NULL;
831 cp->udev = NULL;
832 }
833
834 cnic_free_context(dev);
835 kfree(cp->ctx_arr);
836 cp->ctx_arr = NULL;
837 cp->ctx_blks = 0;
838
839 cnic_free_dma(dev, &cp->gbl_buf_info);
840 cnic_free_dma(dev, &cp->kwq_info);
841 cnic_free_dma(dev, &cp->kwq_16_data_info);
842 cnic_free_dma(dev, &cp->kcq2.dma);
843 cnic_free_dma(dev, &cp->kcq1.dma);
844 kfree(cp->iscsi_tbl);
845 cp->iscsi_tbl = NULL;
846 kfree(cp->ctx_tbl);
847 cp->ctx_tbl = NULL;
848
849 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
850 cnic_free_id_tbl(&cp->cid_tbl);
851 }
852
853 static int cnic_alloc_context(struct cnic_dev *dev)
854 {
855 struct cnic_local *cp = dev->cnic_priv;
856
857 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
858 int i, k, arr_size;
859
860 cp->ctx_blk_size = BCM_PAGE_SIZE;
861 cp->cids_per_blk = BCM_PAGE_SIZE / 128;
862 arr_size = BNX2_MAX_CID / cp->cids_per_blk *
863 sizeof(struct cnic_ctx);
864 cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
865 if (cp->ctx_arr == NULL)
866 return -ENOMEM;
867
868 k = 0;
869 for (i = 0; i < 2; i++) {
870 u32 j, reg, off, lo, hi;
871
872 if (i == 0)
873 off = BNX2_PG_CTX_MAP;
874 else
875 off = BNX2_ISCSI_CTX_MAP;
876
877 reg = cnic_reg_rd_ind(dev, off);
878 lo = reg >> 16;
879 hi = reg & 0xffff;
880 for (j = lo; j < hi; j += cp->cids_per_blk, k++)
881 cp->ctx_arr[k].cid = j;
882 }
883
884 cp->ctx_blks = k;
885 if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
886 cp->ctx_blks = 0;
887 return -ENOMEM;
888 }
889
890 for (i = 0; i < cp->ctx_blks; i++) {
891 cp->ctx_arr[i].ctx =
892 dma_alloc_coherent(&dev->pcidev->dev,
893 BCM_PAGE_SIZE,
894 &cp->ctx_arr[i].mapping,
895 GFP_KERNEL);
896 if (cp->ctx_arr[i].ctx == NULL)
897 return -ENOMEM;
898 }
899 }
900 return 0;
901 }
902
903 static u16 cnic_bnx2_next_idx(u16 idx)
904 {
905 return idx + 1;
906 }
907
908 static u16 cnic_bnx2_hw_idx(u16 idx)
909 {
910 return idx;
911 }
912
913 static u16 cnic_bnx2x_next_idx(u16 idx)
914 {
915 idx++;
916 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
917 idx++;
918
919 return idx;
920 }
921
922 static u16 cnic_bnx2x_hw_idx(u16 idx)
923 {
924 if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
925 idx++;
926 return idx;
927 }
928
929 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
930 bool use_pg_tbl)
931 {
932 int err, i, use_page_tbl = 0;
933 struct kcqe **kcq;
934
935 if (use_pg_tbl)
936 use_page_tbl = 1;
937
938 err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
939 if (err)
940 return err;
941
942 kcq = (struct kcqe **) info->dma.pg_arr;
943 info->kcq = kcq;
944
945 info->next_idx = cnic_bnx2_next_idx;
946 info->hw_idx = cnic_bnx2_hw_idx;
947 if (use_pg_tbl)
948 return 0;
949
950 info->next_idx = cnic_bnx2x_next_idx;
951 info->hw_idx = cnic_bnx2x_hw_idx;
952
953 for (i = 0; i < KCQ_PAGE_CNT; i++) {
954 struct bnx2x_bd_chain_next *next =
955 (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
956 int j = i + 1;
957
958 if (j >= KCQ_PAGE_CNT)
959 j = 0;
960 next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
961 next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
962 }
963 return 0;
964 }
965
966 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
967 {
968 struct cnic_local *cp = dev->cnic_priv;
969 struct cnic_uio_dev *udev;
970
971 read_lock(&cnic_dev_lock);
972 list_for_each_entry(udev, &cnic_udev_list, list) {
973 if (udev->pdev == dev->pcidev) {
974 udev->dev = dev;
975 cp->udev = udev;
976 read_unlock(&cnic_dev_lock);
977 return 0;
978 }
979 }
980 read_unlock(&cnic_dev_lock);
981
982 udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
983 if (!udev)
984 return -ENOMEM;
985
986 udev->uio_dev = -1;
987
988 udev->dev = dev;
989 udev->pdev = dev->pcidev;
990 udev->l2_ring_size = pages * BCM_PAGE_SIZE;
991 udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
992 &udev->l2_ring_map,
993 GFP_KERNEL | __GFP_COMP);
994 if (!udev->l2_ring)
995 goto err_udev;
996
997 udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
998 udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
999 udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
1000 &udev->l2_buf_map,
1001 GFP_KERNEL | __GFP_COMP);
1002 if (!udev->l2_buf)
1003 goto err_dma;
1004
1005 write_lock(&cnic_dev_lock);
1006 list_add(&udev->list, &cnic_udev_list);
1007 write_unlock(&cnic_dev_lock);
1008
1009 pci_dev_get(udev->pdev);
1010
1011 cp->udev = udev;
1012
1013 return 0;
1014 err_dma:
1015 dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
1016 udev->l2_ring, udev->l2_ring_map);
1017 err_udev:
1018 kfree(udev);
1019 return -ENOMEM;
1020 }
1021
1022 static int cnic_init_uio(struct cnic_dev *dev)
1023 {
1024 struct cnic_local *cp = dev->cnic_priv;
1025 struct cnic_uio_dev *udev = cp->udev;
1026 struct uio_info *uinfo;
1027 int ret = 0;
1028
1029 if (!udev)
1030 return -ENOMEM;
1031
1032 uinfo = &udev->cnic_uinfo;
1033
1034 uinfo->mem[0].addr = dev->netdev->base_addr;
1035 uinfo->mem[0].internal_addr = dev->regview;
1036 uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
1037 uinfo->mem[0].memtype = UIO_MEM_PHYS;
1038
1039 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1040 uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1041 PAGE_MASK;
1042 if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1043 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1044 else
1045 uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1046
1047 uinfo->name = "bnx2_cnic";
1048 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1049 uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1050 PAGE_MASK;
1051 uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1052
1053 uinfo->name = "bnx2x_cnic";
1054 }
1055
1056 uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1057
1058 uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1059 uinfo->mem[2].size = udev->l2_ring_size;
1060 uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1061
1062 uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1063 uinfo->mem[3].size = udev->l2_buf_size;
1064 uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1065
1066 uinfo->version = CNIC_MODULE_VERSION;
1067 uinfo->irq = UIO_IRQ_CUSTOM;
1068
1069 uinfo->open = cnic_uio_open;
1070 uinfo->release = cnic_uio_close;
1071
1072 if (udev->uio_dev == -1) {
1073 if (!uinfo->priv) {
1074 uinfo->priv = udev;
1075
1076 ret = uio_register_device(&udev->pdev->dev, uinfo);
1077 }
1078 } else {
1079 cnic_init_rings(dev);
1080 }
1081
1082 return ret;
1083 }
1084
1085 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1086 {
1087 struct cnic_local *cp = dev->cnic_priv;
1088 int ret;
1089
1090 ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1091 if (ret)
1092 goto error;
1093 cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1094
1095 ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
1096 if (ret)
1097 goto error;
1098
1099 ret = cnic_alloc_context(dev);
1100 if (ret)
1101 goto error;
1102
1103 ret = cnic_alloc_uio_rings(dev, 2);
1104 if (ret)
1105 goto error;
1106
1107 ret = cnic_init_uio(dev);
1108 if (ret)
1109 goto error;
1110
1111 return 0;
1112
1113 error:
1114 cnic_free_resc(dev);
1115 return ret;
1116 }
1117
1118 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1119 {
1120 struct cnic_local *cp = dev->cnic_priv;
1121 int ctx_blk_size = cp->ethdev->ctx_blk_size;
1122 int total_mem, blks, i;
1123
1124 total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1125 blks = total_mem / ctx_blk_size;
1126 if (total_mem % ctx_blk_size)
1127 blks++;
1128
1129 if (blks > cp->ethdev->ctx_tbl_len)
1130 return -ENOMEM;
1131
1132 cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1133 if (cp->ctx_arr == NULL)
1134 return -ENOMEM;
1135
1136 cp->ctx_blks = blks;
1137 cp->ctx_blk_size = ctx_blk_size;
1138 if (!BNX2X_CHIP_IS_57710(cp->chip_id))
1139 cp->ctx_align = 0;
1140 else
1141 cp->ctx_align = ctx_blk_size;
1142
1143 cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1144
1145 for (i = 0; i < blks; i++) {
1146 cp->ctx_arr[i].ctx =
1147 dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1148 &cp->ctx_arr[i].mapping,
1149 GFP_KERNEL);
1150 if (cp->ctx_arr[i].ctx == NULL)
1151 return -ENOMEM;
1152
1153 if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1154 if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1155 cnic_free_context(dev);
1156 cp->ctx_blk_size += cp->ctx_align;
1157 i = -1;
1158 continue;
1159 }
1160 }
1161 }
1162 return 0;
1163 }
1164
1165 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1166 {
1167 struct cnic_local *cp = dev->cnic_priv;
1168 struct cnic_eth_dev *ethdev = cp->ethdev;
1169 u32 start_cid = ethdev->starting_cid;
1170 int i, j, n, ret, pages;
1171 struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1172
1173 cp->iro_arr = ethdev->iro_arr;
1174
1175 cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
1176 cp->iscsi_start_cid = start_cid;
1177 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1178
1179 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
1180 cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
1181 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1182 if (!cp->fcoe_init_cid)
1183 cp->fcoe_init_cid = 0x10;
1184 }
1185
1186 if (start_cid < BNX2X_ISCSI_START_CID) {
1187 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1188
1189 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1190 cp->fcoe_start_cid += delta;
1191 cp->max_cid_space += delta;
1192 }
1193
1194 cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
1195 GFP_KERNEL);
1196 if (!cp->iscsi_tbl)
1197 goto error;
1198
1199 cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
1200 cp->max_cid_space, GFP_KERNEL);
1201 if (!cp->ctx_tbl)
1202 goto error;
1203
1204 for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1205 cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1206 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1207 }
1208
1209 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1210 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1211
1212 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1213 PAGE_SIZE;
1214
1215 ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1216 if (ret)
1217 return -ENOMEM;
1218
1219 n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1220 for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1221 long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1222
1223 cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1224 cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1225 off;
1226
1227 if ((i % n) == (n - 1))
1228 j++;
1229 }
1230
1231 ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
1232 if (ret)
1233 goto error;
1234
1235 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
1236 ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
1237 if (ret)
1238 goto error;
1239 }
1240
1241 pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
1242 ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1243 if (ret)
1244 goto error;
1245
1246 ret = cnic_alloc_bnx2x_context(dev);
1247 if (ret)
1248 goto error;
1249
1250 cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1251
1252 cp->l2_rx_ring_size = 15;
1253
1254 ret = cnic_alloc_uio_rings(dev, 4);
1255 if (ret)
1256 goto error;
1257
1258 ret = cnic_init_uio(dev);
1259 if (ret)
1260 goto error;
1261
1262 return 0;
1263
1264 error:
1265 cnic_free_resc(dev);
1266 return -ENOMEM;
1267 }
1268
1269 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1270 {
1271 return cp->max_kwq_idx -
1272 ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1273 }
1274
1275 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1276 u32 num_wqes)
1277 {
1278 struct cnic_local *cp = dev->cnic_priv;
1279 struct kwqe *prod_qe;
1280 u16 prod, sw_prod, i;
1281
1282 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1283 return -EAGAIN; /* bnx2 is down */
1284
1285 spin_lock_bh(&cp->cnic_ulp_lock);
1286 if (num_wqes > cnic_kwq_avail(cp) &&
1287 !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1288 spin_unlock_bh(&cp->cnic_ulp_lock);
1289 return -EAGAIN;
1290 }
1291
1292 clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1293
1294 prod = cp->kwq_prod_idx;
1295 sw_prod = prod & MAX_KWQ_IDX;
1296 for (i = 0; i < num_wqes; i++) {
1297 prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1298 memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1299 prod++;
1300 sw_prod = prod & MAX_KWQ_IDX;
1301 }
1302 cp->kwq_prod_idx = prod;
1303
1304 CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1305
1306 spin_unlock_bh(&cp->cnic_ulp_lock);
1307 return 0;
1308 }
1309
1310 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1311 union l5cm_specific_data *l5_data)
1312 {
1313 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1314 dma_addr_t map;
1315
1316 map = ctx->kwqe_data_mapping;
1317 l5_data->phy_address.lo = (u64) map & 0xffffffff;
1318 l5_data->phy_address.hi = (u64) map >> 32;
1319 return ctx->kwqe_data;
1320 }
1321
1322 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1323 u32 type, union l5cm_specific_data *l5_data)
1324 {
1325 struct cnic_local *cp = dev->cnic_priv;
1326 struct l5cm_spe kwqe;
1327 struct kwqe_16 *kwq[1];
1328 u16 type_16;
1329 int ret;
1330
1331 kwqe.hdr.conn_and_cmd_data =
1332 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1333 BNX2X_HW_CID(cp, cid)));
1334
1335 type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1336 type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1337 SPE_HDR_FUNCTION_ID;
1338
1339 kwqe.hdr.type = cpu_to_le16(type_16);
1340 kwqe.hdr.reserved1 = 0;
1341 kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1342 kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1343
1344 kwq[0] = (struct kwqe_16 *) &kwqe;
1345
1346 spin_lock_bh(&cp->cnic_ulp_lock);
1347 ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1348 spin_unlock_bh(&cp->cnic_ulp_lock);
1349
1350 if (ret == 1)
1351 return 0;
1352
1353 return -EBUSY;
1354 }
1355
1356 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1357 struct kcqe *cqes[], u32 num_cqes)
1358 {
1359 struct cnic_local *cp = dev->cnic_priv;
1360 struct cnic_ulp_ops *ulp_ops;
1361
1362 rcu_read_lock();
1363 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1364 if (likely(ulp_ops)) {
1365 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1366 cqes, num_cqes);
1367 }
1368 rcu_read_unlock();
1369 }
1370
1371 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1372 {
1373 struct cnic_local *cp = dev->cnic_priv;
1374 struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1375 int hq_bds, pages;
1376 u32 pfid = cp->pfid;
1377
1378 cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1379 cp->num_ccells = req1->num_ccells_per_conn;
1380 cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1381 cp->num_iscsi_tasks;
1382 cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1383 BNX2X_ISCSI_R2TQE_SIZE;
1384 cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1385 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1386 hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1387 cp->num_cqs = req1->num_cqs;
1388
1389 if (!dev->max_iscsi_conn)
1390 return 0;
1391
1392 /* init Tstorm RAM */
1393 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1394 req1->rq_num_wqes);
1395 CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1396 PAGE_SIZE);
1397 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1398 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1399 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1400 TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1401 req1->num_tasks_per_conn);
1402
1403 /* init Ustorm RAM */
1404 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1405 USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1406 req1->rq_buffer_size);
1407 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1408 PAGE_SIZE);
1409 CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1410 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1411 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1412 USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1413 req1->num_tasks_per_conn);
1414 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1415 req1->rq_num_wqes);
1416 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1417 req1->cq_num_wqes);
1418 CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1419 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1420
1421 /* init Xstorm RAM */
1422 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1423 PAGE_SIZE);
1424 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1425 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1426 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1427 XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1428 req1->num_tasks_per_conn);
1429 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1430 hq_bds);
1431 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1432 req1->num_tasks_per_conn);
1433 CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1434 cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1435
1436 /* init Cstorm RAM */
1437 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1438 PAGE_SIZE);
1439 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1440 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
1441 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1442 CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1443 req1->num_tasks_per_conn);
1444 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1445 req1->cq_num_wqes);
1446 CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1447 hq_bds);
1448
1449 return 0;
1450 }
1451
1452 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1453 {
1454 struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1455 struct cnic_local *cp = dev->cnic_priv;
1456 u32 pfid = cp->pfid;
1457 struct iscsi_kcqe kcqe;
1458 struct kcqe *cqes[1];
1459
1460 memset(&kcqe, 0, sizeof(kcqe));
1461 if (!dev->max_iscsi_conn) {
1462 kcqe.completion_status =
1463 ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1464 goto done;
1465 }
1466
1467 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1468 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1469 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1470 TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1471 req2->error_bit_map[1]);
1472
1473 CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1474 USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1475 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1476 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1477 CNIC_WR(dev, BAR_USTRORM_INTMEM +
1478 USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1479 req2->error_bit_map[1]);
1480
1481 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1482 CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1483
1484 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1485
1486 done:
1487 kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1488 cqes[0] = (struct kcqe *) &kcqe;
1489 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1490
1491 return 0;
1492 }
1493
1494 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1495 {
1496 struct cnic_local *cp = dev->cnic_priv;
1497 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1498
1499 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1500 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1501
1502 cnic_free_dma(dev, &iscsi->hq_info);
1503 cnic_free_dma(dev, &iscsi->r2tq_info);
1504 cnic_free_dma(dev, &iscsi->task_array_info);
1505 cnic_free_id(&cp->cid_tbl, ctx->cid);
1506 } else {
1507 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1508 }
1509
1510 ctx->cid = 0;
1511 }
1512
1513 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1514 {
1515 u32 cid;
1516 int ret, pages;
1517 struct cnic_local *cp = dev->cnic_priv;
1518 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1519 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1520
1521 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1522 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1523 if (cid == -1) {
1524 ret = -ENOMEM;
1525 goto error;
1526 }
1527 ctx->cid = cid;
1528 return 0;
1529 }
1530
1531 cid = cnic_alloc_new_id(&cp->cid_tbl);
1532 if (cid == -1) {
1533 ret = -ENOMEM;
1534 goto error;
1535 }
1536
1537 ctx->cid = cid;
1538 pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
1539
1540 ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1541 if (ret)
1542 goto error;
1543
1544 pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
1545 ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1546 if (ret)
1547 goto error;
1548
1549 pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
1550 ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1551 if (ret)
1552 goto error;
1553
1554 return 0;
1555
1556 error:
1557 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1558 return ret;
1559 }
1560
1561 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1562 struct regpair *ctx_addr)
1563 {
1564 struct cnic_local *cp = dev->cnic_priv;
1565 struct cnic_eth_dev *ethdev = cp->ethdev;
1566 int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1567 int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1568 unsigned long align_off = 0;
1569 dma_addr_t ctx_map;
1570 void *ctx;
1571
1572 if (cp->ctx_align) {
1573 unsigned long mask = cp->ctx_align - 1;
1574
1575 if (cp->ctx_arr[blk].mapping & mask)
1576 align_off = cp->ctx_align -
1577 (cp->ctx_arr[blk].mapping & mask);
1578 }
1579 ctx_map = cp->ctx_arr[blk].mapping + align_off +
1580 (off * BNX2X_CONTEXT_MEM_SIZE);
1581 ctx = cp->ctx_arr[blk].ctx + align_off +
1582 (off * BNX2X_CONTEXT_MEM_SIZE);
1583 if (init)
1584 memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1585
1586 ctx_addr->lo = ctx_map & 0xffffffff;
1587 ctx_addr->hi = (u64) ctx_map >> 32;
1588 return ctx;
1589 }
1590
1591 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1592 u32 num)
1593 {
1594 struct cnic_local *cp = dev->cnic_priv;
1595 struct iscsi_kwqe_conn_offload1 *req1 =
1596 (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1597 struct iscsi_kwqe_conn_offload2 *req2 =
1598 (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1599 struct iscsi_kwqe_conn_offload3 *req3;
1600 struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1601 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1602 u32 cid = ctx->cid;
1603 u32 hw_cid = BNX2X_HW_CID(cp, cid);
1604 struct iscsi_context *ictx;
1605 struct regpair context_addr;
1606 int i, j, n = 2, n_max;
1607 u8 port = CNIC_PORT(cp);
1608
1609 ctx->ctx_flags = 0;
1610 if (!req2->num_additional_wqes)
1611 return -EINVAL;
1612
1613 n_max = req2->num_additional_wqes + 2;
1614
1615 ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1616 if (ictx == NULL)
1617 return -ENOMEM;
1618
1619 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1620
1621 ictx->xstorm_ag_context.hq_prod = 1;
1622
1623 ictx->xstorm_st_context.iscsi.first_burst_length =
1624 ISCSI_DEF_FIRST_BURST_LEN;
1625 ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1626 ISCSI_DEF_MAX_RECV_SEG_LEN;
1627 ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1628 req1->sq_page_table_addr_lo;
1629 ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1630 req1->sq_page_table_addr_hi;
1631 ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1632 ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1633 ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1634 iscsi->hq_info.pgtbl_map & 0xffffffff;
1635 ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1636 (u64) iscsi->hq_info.pgtbl_map >> 32;
1637 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1638 iscsi->hq_info.pgtbl[0];
1639 ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1640 iscsi->hq_info.pgtbl[1];
1641 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1642 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1643 ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1644 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1645 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1646 iscsi->r2tq_info.pgtbl[0];
1647 ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1648 iscsi->r2tq_info.pgtbl[1];
1649 ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1650 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1651 ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1652 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1653 ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1654 BNX2X_ISCSI_PBL_NOT_CACHED;
1655 ictx->xstorm_st_context.iscsi.flags.flags |=
1656 XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1657 ictx->xstorm_st_context.iscsi.flags.flags |=
1658 XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1659 ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
1660 ETH_P_8021Q;
1661 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
1662 cp->port_mode == CHIP_2_PORT_MODE) {
1663
1664 port = 0;
1665 }
1666 ictx->xstorm_st_context.common.flags =
1667 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
1668 ictx->xstorm_st_context.common.flags =
1669 port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
1670
1671 ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1672 /* TSTORM requires the base address of RQ DB & not PTE */
1673 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1674 req2->rq_page_table_addr_lo & PAGE_MASK;
1675 ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1676 req2->rq_page_table_addr_hi;
1677 ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1678 ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1679 ictx->tstorm_st_context.tcp.flags2 |=
1680 TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1681 ictx->tstorm_st_context.tcp.ooo_support_mode =
1682 TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1683
1684 ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1685
1686 ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1687 req2->rq_page_table_addr_lo;
1688 ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1689 req2->rq_page_table_addr_hi;
1690 ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1691 ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1692 ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1693 iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1694 ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1695 (u64) iscsi->r2tq_info.pgtbl_map >> 32;
1696 ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1697 iscsi->r2tq_info.pgtbl[0];
1698 ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1699 iscsi->r2tq_info.pgtbl[1];
1700 ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1701 req1->cq_page_table_addr_lo;
1702 ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1703 req1->cq_page_table_addr_hi;
1704 ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1705 ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1706 ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1707 ictx->ustorm_st_context.task_pbe_cache_index =
1708 BNX2X_ISCSI_PBL_NOT_CACHED;
1709 ictx->ustorm_st_context.task_pdu_cache_index =
1710 BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1711
1712 for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1713 if (j == 3) {
1714 if (n >= n_max)
1715 break;
1716 req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1717 j = 0;
1718 }
1719 ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1720 ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1721 req3->qp_first_pte[j].hi;
1722 ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1723 req3->qp_first_pte[j].lo;
1724 }
1725
1726 ictx->ustorm_st_context.task_pbl_base.lo =
1727 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1728 ictx->ustorm_st_context.task_pbl_base.hi =
1729 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1730 ictx->ustorm_st_context.tce_phy_addr.lo =
1731 iscsi->task_array_info.pgtbl[0];
1732 ictx->ustorm_st_context.tce_phy_addr.hi =
1733 iscsi->task_array_info.pgtbl[1];
1734 ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1735 ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1736 ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1737 ictx->ustorm_st_context.negotiated_rx_and_flags |=
1738 ISCSI_DEF_MAX_BURST_LEN;
1739 ictx->ustorm_st_context.negotiated_rx |=
1740 ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1741 USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1742
1743 ictx->cstorm_st_context.hq_pbl_base.lo =
1744 iscsi->hq_info.pgtbl_map & 0xffffffff;
1745 ictx->cstorm_st_context.hq_pbl_base.hi =
1746 (u64) iscsi->hq_info.pgtbl_map >> 32;
1747 ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1748 ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1749 ictx->cstorm_st_context.task_pbl_base.lo =
1750 iscsi->task_array_info.pgtbl_map & 0xffffffff;
1751 ictx->cstorm_st_context.task_pbl_base.hi =
1752 (u64) iscsi->task_array_info.pgtbl_map >> 32;
1753 /* CSTORM and USTORM initialization is different, CSTORM requires
1754 * CQ DB base & not PTE addr */
1755 ictx->cstorm_st_context.cq_db_base.lo =
1756 req1->cq_page_table_addr_lo & PAGE_MASK;
1757 ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1758 ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1759 ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1760 for (i = 0; i < cp->num_cqs; i++) {
1761 ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1762 ISCSI_INITIAL_SN;
1763 ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1764 ISCSI_INITIAL_SN;
1765 }
1766
1767 ictx->xstorm_ag_context.cdu_reserved =
1768 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1769 ISCSI_CONNECTION_TYPE);
1770 ictx->ustorm_ag_context.cdu_usage =
1771 CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1772 ISCSI_CONNECTION_TYPE);
1773 return 0;
1774
1775 }
1776
1777 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1778 u32 num, int *work)
1779 {
1780 struct iscsi_kwqe_conn_offload1 *req1;
1781 struct iscsi_kwqe_conn_offload2 *req2;
1782 struct cnic_local *cp = dev->cnic_priv;
1783 struct cnic_context *ctx;
1784 struct iscsi_kcqe kcqe;
1785 struct kcqe *cqes[1];
1786 u32 l5_cid;
1787 int ret = 0;
1788
1789 if (num < 2) {
1790 *work = num;
1791 return -EINVAL;
1792 }
1793
1794 req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1795 req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1796 if ((num - 2) < req2->num_additional_wqes) {
1797 *work = num;
1798 return -EINVAL;
1799 }
1800 *work = 2 + req2->num_additional_wqes;
1801
1802 l5_cid = req1->iscsi_conn_id;
1803 if (l5_cid >= MAX_ISCSI_TBL_SZ)
1804 return -EINVAL;
1805
1806 memset(&kcqe, 0, sizeof(kcqe));
1807 kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1808 kcqe.iscsi_conn_id = l5_cid;
1809 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1810
1811 ctx = &cp->ctx_tbl[l5_cid];
1812 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1813 kcqe.completion_status =
1814 ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1815 goto done;
1816 }
1817
1818 if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1819 atomic_dec(&cp->iscsi_conn);
1820 goto done;
1821 }
1822 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1823 if (ret) {
1824 atomic_dec(&cp->iscsi_conn);
1825 ret = 0;
1826 goto done;
1827 }
1828 ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1829 if (ret < 0) {
1830 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1831 atomic_dec(&cp->iscsi_conn);
1832 goto done;
1833 }
1834
1835 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1836 kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
1837
1838 done:
1839 cqes[0] = (struct kcqe *) &kcqe;
1840 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1841 return ret;
1842 }
1843
1844
1845 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1846 {
1847 struct cnic_local *cp = dev->cnic_priv;
1848 struct iscsi_kwqe_conn_update *req =
1849 (struct iscsi_kwqe_conn_update *) kwqe;
1850 void *data;
1851 union l5cm_specific_data l5_data;
1852 u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1853 int ret;
1854
1855 if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1856 return -EINVAL;
1857
1858 data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1859 if (!data)
1860 return -ENOMEM;
1861
1862 memcpy(data, kwqe, sizeof(struct kwqe));
1863
1864 ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1865 req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1866 return ret;
1867 }
1868
1869 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1870 {
1871 struct cnic_local *cp = dev->cnic_priv;
1872 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1873 union l5cm_specific_data l5_data;
1874 int ret;
1875 u32 hw_cid;
1876
1877 init_waitqueue_head(&ctx->waitq);
1878 ctx->wait_cond = 0;
1879 memset(&l5_data, 0, sizeof(l5_data));
1880 hw_cid = BNX2X_HW_CID(cp, ctx->cid);
1881
1882 ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1883 hw_cid, NONE_CONNECTION_TYPE, &l5_data);
1884
1885 if (ret == 0) {
1886 wait_event(ctx->waitq, ctx->wait_cond);
1887 if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
1888 return -EBUSY;
1889 }
1890
1891 return ret;
1892 }
1893
1894 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1895 {
1896 struct cnic_local *cp = dev->cnic_priv;
1897 struct iscsi_kwqe_conn_destroy *req =
1898 (struct iscsi_kwqe_conn_destroy *) kwqe;
1899 u32 l5_cid = req->reserved0;
1900 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1901 int ret = 0;
1902 struct iscsi_kcqe kcqe;
1903 struct kcqe *cqes[1];
1904
1905 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
1906 goto skip_cfc_delete;
1907
1908 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
1909 unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
1910
1911 if (delta > (2 * HZ))
1912 delta = 0;
1913
1914 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
1915 queue_delayed_work(cnic_wq, &cp->delete_task, delta);
1916 goto destroy_reply;
1917 }
1918
1919 ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
1920
1921 skip_cfc_delete:
1922 cnic_free_bnx2x_conn_resc(dev, l5_cid);
1923
1924 if (!ret) {
1925 atomic_dec(&cp->iscsi_conn);
1926 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
1927 }
1928
1929 destroy_reply:
1930 memset(&kcqe, 0, sizeof(kcqe));
1931 kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
1932 kcqe.iscsi_conn_id = l5_cid;
1933 kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1934 kcqe.iscsi_conn_context_id = req->context_id;
1935
1936 cqes[0] = (struct kcqe *) &kcqe;
1937 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1938
1939 return ret;
1940 }
1941
1942 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
1943 struct l4_kwq_connect_req1 *kwqe1,
1944 struct l4_kwq_connect_req3 *kwqe3,
1945 struct l5cm_active_conn_buffer *conn_buf)
1946 {
1947 struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
1948 struct l5cm_xstorm_conn_buffer *xstorm_buf =
1949 &conn_buf->xstorm_conn_buffer;
1950 struct l5cm_tstorm_conn_buffer *tstorm_buf =
1951 &conn_buf->tstorm_conn_buffer;
1952 struct regpair context_addr;
1953 u32 cid = BNX2X_SW_CID(kwqe1->cid);
1954 struct in6_addr src_ip, dst_ip;
1955 int i;
1956 u32 *addrp;
1957
1958 addrp = (u32 *) &conn_addr->local_ip_addr;
1959 for (i = 0; i < 4; i++, addrp++)
1960 src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1961
1962 addrp = (u32 *) &conn_addr->remote_ip_addr;
1963 for (i = 0; i < 4; i++, addrp++)
1964 dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
1965
1966 cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
1967
1968 xstorm_buf->context_addr.hi = context_addr.hi;
1969 xstorm_buf->context_addr.lo = context_addr.lo;
1970 xstorm_buf->mss = 0xffff;
1971 xstorm_buf->rcv_buf = kwqe3->rcv_buf;
1972 if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
1973 xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
1974 xstorm_buf->pseudo_header_checksum =
1975 swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
1976
1977 if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
1978 tstorm_buf->params |=
1979 L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
1980 if (kwqe3->ka_timeout) {
1981 tstorm_buf->ka_enable = 1;
1982 tstorm_buf->ka_timeout = kwqe3->ka_timeout;
1983 tstorm_buf->ka_interval = kwqe3->ka_interval;
1984 tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
1985 }
1986 tstorm_buf->max_rt_time = 0xffffffff;
1987 }
1988
1989 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
1990 {
1991 struct cnic_local *cp = dev->cnic_priv;
1992 u32 pfid = cp->pfid;
1993 u8 *mac = dev->mac_addr;
1994
1995 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1996 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
1997 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1998 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
1999 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2000 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
2001 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2002 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
2003 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2004 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
2005 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2006 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
2007
2008 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2009 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
2010 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2011 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2012 mac[4]);
2013 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2014 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
2015 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2016 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2017 mac[2]);
2018 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2019 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
2020 CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2021 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2022 mac[0]);
2023 }
2024
2025 static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
2026 {
2027 struct cnic_local *cp = dev->cnic_priv;
2028 u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
2029 u16 tstorm_flags = 0;
2030
2031 if (tcp_ts) {
2032 xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
2033 tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
2034 }
2035
2036 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2037 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
2038
2039 CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
2040 TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
2041 }
2042
2043 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
2044 u32 num, int *work)
2045 {
2046 struct cnic_local *cp = dev->cnic_priv;
2047 struct l4_kwq_connect_req1 *kwqe1 =
2048 (struct l4_kwq_connect_req1 *) wqes[0];
2049 struct l4_kwq_connect_req3 *kwqe3;
2050 struct l5cm_active_conn_buffer *conn_buf;
2051 struct l5cm_conn_addr_params *conn_addr;
2052 union l5cm_specific_data l5_data;
2053 u32 l5_cid = kwqe1->pg_cid;
2054 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2055 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2056 int ret;
2057
2058 if (num < 2) {
2059 *work = num;
2060 return -EINVAL;
2061 }
2062
2063 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2064 *work = 3;
2065 else
2066 *work = 2;
2067
2068 if (num < *work) {
2069 *work = num;
2070 return -EINVAL;
2071 }
2072
2073 if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2074 netdev_err(dev->netdev, "conn_buf size too big\n");
2075 return -ENOMEM;
2076 }
2077 conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2078 if (!conn_buf)
2079 return -ENOMEM;
2080
2081 memset(conn_buf, 0, sizeof(*conn_buf));
2082
2083 conn_addr = &conn_buf->conn_addr_buf;
2084 conn_addr->remote_addr_0 = csk->ha[0];
2085 conn_addr->remote_addr_1 = csk->ha[1];
2086 conn_addr->remote_addr_2 = csk->ha[2];
2087 conn_addr->remote_addr_3 = csk->ha[3];
2088 conn_addr->remote_addr_4 = csk->ha[4];
2089 conn_addr->remote_addr_5 = csk->ha[5];
2090
2091 if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2092 struct l4_kwq_connect_req2 *kwqe2 =
2093 (struct l4_kwq_connect_req2 *) wqes[1];
2094
2095 conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2096 conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2097 conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2098
2099 conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2100 conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2101 conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2102 conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2103 }
2104 kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2105
2106 conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2107 conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2108 conn_addr->local_tcp_port = kwqe1->src_port;
2109 conn_addr->remote_tcp_port = kwqe1->dst_port;
2110
2111 conn_addr->pmtu = kwqe3->pmtu;
2112 cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2113
2114 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2115 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
2116
2117 cnic_bnx2x_set_tcp_timestamp(dev,
2118 kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
2119
2120 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2121 kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2122 if (!ret)
2123 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2124
2125 return ret;
2126 }
2127
2128 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2129 {
2130 struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2131 union l5cm_specific_data l5_data;
2132 int ret;
2133
2134 memset(&l5_data, 0, sizeof(l5_data));
2135 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2136 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2137 return ret;
2138 }
2139
2140 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2141 {
2142 struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2143 union l5cm_specific_data l5_data;
2144 int ret;
2145
2146 memset(&l5_data, 0, sizeof(l5_data));
2147 ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2148 req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2149 return ret;
2150 }
2151 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2152 {
2153 struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2154 struct l4_kcq kcqe;
2155 struct kcqe *cqes[1];
2156
2157 memset(&kcqe, 0, sizeof(kcqe));
2158 kcqe.pg_host_opaque = req->host_opaque;
2159 kcqe.pg_cid = req->host_opaque;
2160 kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2161 cqes[0] = (struct kcqe *) &kcqe;
2162 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2163 return 0;
2164 }
2165
2166 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2167 {
2168 struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2169 struct l4_kcq kcqe;
2170 struct kcqe *cqes[1];
2171
2172 memset(&kcqe, 0, sizeof(kcqe));
2173 kcqe.pg_host_opaque = req->pg_host_opaque;
2174 kcqe.pg_cid = req->pg_cid;
2175 kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2176 cqes[0] = (struct kcqe *) &kcqe;
2177 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2178 return 0;
2179 }
2180
2181 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2182 {
2183 struct fcoe_kwqe_stat *req;
2184 struct fcoe_stat_ramrod_params *fcoe_stat;
2185 union l5cm_specific_data l5_data;
2186 struct cnic_local *cp = dev->cnic_priv;
2187 int ret;
2188 u32 cid;
2189
2190 req = (struct fcoe_kwqe_stat *) kwqe;
2191 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2192
2193 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2194 if (!fcoe_stat)
2195 return -ENOMEM;
2196
2197 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2198 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2199
2200 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
2201 FCOE_CONNECTION_TYPE, &l5_data);
2202 return ret;
2203 }
2204
2205 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2206 u32 num, int *work)
2207 {
2208 int ret;
2209 struct cnic_local *cp = dev->cnic_priv;
2210 u32 cid;
2211 struct fcoe_init_ramrod_params *fcoe_init;
2212 struct fcoe_kwqe_init1 *req1;
2213 struct fcoe_kwqe_init2 *req2;
2214 struct fcoe_kwqe_init3 *req3;
2215 union l5cm_specific_data l5_data;
2216
2217 if (num < 3) {
2218 *work = num;
2219 return -EINVAL;
2220 }
2221 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2222 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2223 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2224 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2225 *work = 1;
2226 return -EINVAL;
2227 }
2228 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2229 *work = 2;
2230 return -EINVAL;
2231 }
2232
2233 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2234 netdev_err(dev->netdev, "fcoe_init size too big\n");
2235 return -ENOMEM;
2236 }
2237 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2238 if (!fcoe_init)
2239 return -ENOMEM;
2240
2241 memset(fcoe_init, 0, sizeof(*fcoe_init));
2242 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2243 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2244 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2245 fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
2246 fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
2247 fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
2248
2249 fcoe_init->sb_num = cp->status_blk_num;
2250 fcoe_init->eq_prod = MAX_KCQ_IDX;
2251 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2252 cp->kcq2.sw_prod_idx = 0;
2253
2254 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2255 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
2256 FCOE_CONNECTION_TYPE, &l5_data);
2257 *work = 3;
2258 return ret;
2259 }
2260
2261 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2262 u32 num, int *work)
2263 {
2264 int ret = 0;
2265 u32 cid = -1, l5_cid;
2266 struct cnic_local *cp = dev->cnic_priv;
2267 struct fcoe_kwqe_conn_offload1 *req1;
2268 struct fcoe_kwqe_conn_offload2 *req2;
2269 struct fcoe_kwqe_conn_offload3 *req3;
2270 struct fcoe_kwqe_conn_offload4 *req4;
2271 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2272 struct cnic_context *ctx;
2273 struct fcoe_context *fctx;
2274 struct regpair ctx_addr;
2275 union l5cm_specific_data l5_data;
2276 struct fcoe_kcqe kcqe;
2277 struct kcqe *cqes[1];
2278
2279 if (num < 4) {
2280 *work = num;
2281 return -EINVAL;
2282 }
2283 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2284 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2285 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2286 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2287
2288 *work = 4;
2289
2290 l5_cid = req1->fcoe_conn_id;
2291 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2292 goto err_reply;
2293
2294 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2295
2296 ctx = &cp->ctx_tbl[l5_cid];
2297 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2298 goto err_reply;
2299
2300 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2301 if (ret) {
2302 ret = 0;
2303 goto err_reply;
2304 }
2305 cid = ctx->cid;
2306
2307 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2308 if (fctx) {
2309 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2310 u32 val;
2311
2312 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2313 FCOE_CONNECTION_TYPE);
2314 fctx->xstorm_ag_context.cdu_reserved = val;
2315 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2316 FCOE_CONNECTION_TYPE);
2317 fctx->ustorm_ag_context.cdu_usage = val;
2318 }
2319 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2320 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2321 goto err_reply;
2322 }
2323 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2324 if (!fcoe_offload)
2325 goto err_reply;
2326
2327 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2328 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2329 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2330 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2331 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2332
2333 cid = BNX2X_HW_CID(cp, cid);
2334 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2335 FCOE_CONNECTION_TYPE, &l5_data);
2336 if (!ret)
2337 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2338
2339 return ret;
2340
2341 err_reply:
2342 if (cid != -1)
2343 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2344
2345 memset(&kcqe, 0, sizeof(kcqe));
2346 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2347 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2348 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2349
2350 cqes[0] = (struct kcqe *) &kcqe;
2351 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2352 return ret;
2353 }
2354
2355 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2356 {
2357 struct fcoe_kwqe_conn_enable_disable *req;
2358 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2359 union l5cm_specific_data l5_data;
2360 int ret;
2361 u32 cid, l5_cid;
2362 struct cnic_local *cp = dev->cnic_priv;
2363
2364 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2365 cid = req->context_id;
2366 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2367
2368 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2369 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2370 return -ENOMEM;
2371 }
2372 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2373 if (!fcoe_enable)
2374 return -ENOMEM;
2375
2376 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2377 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2378 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2379 FCOE_CONNECTION_TYPE, &l5_data);
2380 return ret;
2381 }
2382
2383 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2384 {
2385 struct fcoe_kwqe_conn_enable_disable *req;
2386 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2387 union l5cm_specific_data l5_data;
2388 int ret;
2389 u32 cid, l5_cid;
2390 struct cnic_local *cp = dev->cnic_priv;
2391
2392 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2393 cid = req->context_id;
2394 l5_cid = req->conn_id;
2395 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2396 return -EINVAL;
2397
2398 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2399
2400 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2401 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2402 return -ENOMEM;
2403 }
2404 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2405 if (!fcoe_disable)
2406 return -ENOMEM;
2407
2408 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2409 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2410 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2411 FCOE_CONNECTION_TYPE, &l5_data);
2412 return ret;
2413 }
2414
2415 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2416 {
2417 struct fcoe_kwqe_conn_destroy *req;
2418 union l5cm_specific_data l5_data;
2419 int ret;
2420 u32 cid, l5_cid;
2421 struct cnic_local *cp = dev->cnic_priv;
2422 struct cnic_context *ctx;
2423 struct fcoe_kcqe kcqe;
2424 struct kcqe *cqes[1];
2425
2426 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2427 cid = req->context_id;
2428 l5_cid = req->conn_id;
2429 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2430 return -EINVAL;
2431
2432 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2433
2434 ctx = &cp->ctx_tbl[l5_cid];
2435
2436 init_waitqueue_head(&ctx->waitq);
2437 ctx->wait_cond = 0;
2438
2439 memset(&l5_data, 0, sizeof(l5_data));
2440 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2441 FCOE_CONNECTION_TYPE, &l5_data);
2442 if (ret == 0) {
2443 wait_event(ctx->waitq, ctx->wait_cond);
2444 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2445 queue_delayed_work(cnic_wq, &cp->delete_task,
2446 msecs_to_jiffies(2000));
2447 }
2448
2449 memset(&kcqe, 0, sizeof(kcqe));
2450 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2451 kcqe.fcoe_conn_id = req->conn_id;
2452 kcqe.fcoe_conn_context_id = cid;
2453
2454 cqes[0] = (struct kcqe *) &kcqe;
2455 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2456 return ret;
2457 }
2458
2459 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2460 {
2461 struct fcoe_kwqe_destroy *req;
2462 union l5cm_specific_data l5_data;
2463 struct cnic_local *cp = dev->cnic_priv;
2464 int ret;
2465 u32 cid;
2466
2467 req = (struct fcoe_kwqe_destroy *) kwqe;
2468 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2469
2470 memset(&l5_data, 0, sizeof(l5_data));
2471 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
2472 FCOE_CONNECTION_TYPE, &l5_data);
2473 return ret;
2474 }
2475
2476 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2477 struct kwqe *wqes[], u32 num_wqes)
2478 {
2479 int i, work, ret;
2480 u32 opcode;
2481 struct kwqe *kwqe;
2482
2483 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2484 return -EAGAIN; /* bnx2 is down */
2485
2486 for (i = 0; i < num_wqes; ) {
2487 kwqe = wqes[i];
2488 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2489 work = 1;
2490
2491 switch (opcode) {
2492 case ISCSI_KWQE_OPCODE_INIT1:
2493 ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2494 break;
2495 case ISCSI_KWQE_OPCODE_INIT2:
2496 ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2497 break;
2498 case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2499 ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2500 num_wqes - i, &work);
2501 break;
2502 case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2503 ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2504 break;
2505 case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2506 ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2507 break;
2508 case L4_KWQE_OPCODE_VALUE_CONNECT1:
2509 ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2510 &work);
2511 break;
2512 case L4_KWQE_OPCODE_VALUE_CLOSE:
2513 ret = cnic_bnx2x_close(dev, kwqe);
2514 break;
2515 case L4_KWQE_OPCODE_VALUE_RESET:
2516 ret = cnic_bnx2x_reset(dev, kwqe);
2517 break;
2518 case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2519 ret = cnic_bnx2x_offload_pg(dev, kwqe);
2520 break;
2521 case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2522 ret = cnic_bnx2x_update_pg(dev, kwqe);
2523 break;
2524 case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2525 ret = 0;
2526 break;
2527 default:
2528 ret = 0;
2529 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2530 opcode);
2531 break;
2532 }
2533 if (ret < 0)
2534 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2535 opcode);
2536 i += work;
2537 }
2538 return 0;
2539 }
2540
2541 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2542 struct kwqe *wqes[], u32 num_wqes)
2543 {
2544 struct cnic_local *cp = dev->cnic_priv;
2545 int i, work, ret;
2546 u32 opcode;
2547 struct kwqe *kwqe;
2548
2549 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2550 return -EAGAIN; /* bnx2 is down */
2551
2552 if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
2553 return -EINVAL;
2554
2555 for (i = 0; i < num_wqes; ) {
2556 kwqe = wqes[i];
2557 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2558 work = 1;
2559
2560 switch (opcode) {
2561 case FCOE_KWQE_OPCODE_INIT1:
2562 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2563 num_wqes - i, &work);
2564 break;
2565 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2566 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2567 num_wqes - i, &work);
2568 break;
2569 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2570 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2571 break;
2572 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2573 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2574 break;
2575 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2576 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2577 break;
2578 case FCOE_KWQE_OPCODE_DESTROY:
2579 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2580 break;
2581 case FCOE_KWQE_OPCODE_STAT:
2582 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2583 break;
2584 default:
2585 ret = 0;
2586 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2587 opcode);
2588 break;
2589 }
2590 if (ret < 0)
2591 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2592 opcode);
2593 i += work;
2594 }
2595 return 0;
2596 }
2597
2598 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2599 u32 num_wqes)
2600 {
2601 int ret = -EINVAL;
2602 u32 layer_code;
2603
2604 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2605 return -EAGAIN; /* bnx2x is down */
2606
2607 if (!num_wqes)
2608 return 0;
2609
2610 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2611 switch (layer_code) {
2612 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2613 case KWQE_FLAGS_LAYER_MASK_L4:
2614 case KWQE_FLAGS_LAYER_MASK_L2:
2615 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2616 break;
2617
2618 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2619 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2620 break;
2621 }
2622 return ret;
2623 }
2624
2625 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2626 {
2627 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2628 return KCQE_FLAGS_LAYER_MASK_L4;
2629
2630 return opflag & KCQE_FLAGS_LAYER_MASK;
2631 }
2632
2633 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2634 {
2635 struct cnic_local *cp = dev->cnic_priv;
2636 int i, j, comp = 0;
2637
2638 i = 0;
2639 j = 1;
2640 while (num_cqes) {
2641 struct cnic_ulp_ops *ulp_ops;
2642 int ulp_type;
2643 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2644 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2645
2646 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2647 comp++;
2648
2649 while (j < num_cqes) {
2650 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2651
2652 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2653 break;
2654
2655 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2656 comp++;
2657 j++;
2658 }
2659
2660 if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2661 ulp_type = CNIC_ULP_RDMA;
2662 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2663 ulp_type = CNIC_ULP_ISCSI;
2664 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2665 ulp_type = CNIC_ULP_FCOE;
2666 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2667 ulp_type = CNIC_ULP_L4;
2668 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2669 goto end;
2670 else {
2671 netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2672 kcqe_op_flag);
2673 goto end;
2674 }
2675
2676 rcu_read_lock();
2677 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2678 if (likely(ulp_ops)) {
2679 ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2680 cp->completed_kcq + i, j);
2681 }
2682 rcu_read_unlock();
2683 end:
2684 num_cqes -= j;
2685 i += j;
2686 j = 1;
2687 }
2688 if (unlikely(comp))
2689 cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2690 }
2691
2692 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2693 {
2694 struct cnic_local *cp = dev->cnic_priv;
2695 u16 i, ri, hw_prod, last;
2696 struct kcqe *kcqe;
2697 int kcqe_cnt = 0, last_cnt = 0;
2698
2699 i = ri = last = info->sw_prod_idx;
2700 ri &= MAX_KCQ_IDX;
2701 hw_prod = *info->hw_prod_idx_ptr;
2702 hw_prod = info->hw_idx(hw_prod);
2703
2704 while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2705 kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2706 cp->completed_kcq[kcqe_cnt++] = kcqe;
2707 i = info->next_idx(i);
2708 ri = i & MAX_KCQ_IDX;
2709 if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2710 last_cnt = kcqe_cnt;
2711 last = i;
2712 }
2713 }
2714
2715 info->sw_prod_idx = last;
2716 return last_cnt;
2717 }
2718
2719 static int cnic_l2_completion(struct cnic_local *cp)
2720 {
2721 u16 hw_cons, sw_cons;
2722 struct cnic_uio_dev *udev = cp->udev;
2723 union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2724 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
2725 u32 cmd;
2726 int comp = 0;
2727
2728 if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2729 return 0;
2730
2731 hw_cons = *cp->rx_cons_ptr;
2732 if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2733 hw_cons++;
2734
2735 sw_cons = cp->rx_cons;
2736 while (sw_cons != hw_cons) {
2737 u8 cqe_fp_flags;
2738
2739 cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2740 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2741 if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2742 cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2743 cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2744 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2745 cmd == RAMROD_CMD_ID_ETH_HALT)
2746 comp++;
2747 }
2748 sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2749 }
2750 return comp;
2751 }
2752
2753 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2754 {
2755 u16 rx_cons, tx_cons;
2756 int comp = 0;
2757
2758 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2759 return;
2760
2761 rx_cons = *cp->rx_cons_ptr;
2762 tx_cons = *cp->tx_cons_ptr;
2763 if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2764 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2765 comp = cnic_l2_completion(cp);
2766
2767 cp->tx_cons = tx_cons;
2768 cp->rx_cons = rx_cons;
2769
2770 if (cp->udev)
2771 uio_event_notify(&cp->udev->cnic_uinfo);
2772 }
2773 if (comp)
2774 clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2775 }
2776
2777 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2778 {
2779 struct cnic_local *cp = dev->cnic_priv;
2780 u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2781 int kcqe_cnt;
2782
2783 /* status block index must be read before reading other fields */
2784 rmb();
2785 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2786
2787 while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2788
2789 service_kcqes(dev, kcqe_cnt);
2790
2791 /* Tell compiler that status_blk fields can change. */
2792 barrier();
2793 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2794 /* status block index must be read first */
2795 rmb();
2796 cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2797 }
2798
2799 CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2800
2801 cnic_chk_pkt_rings(cp);
2802
2803 return status_idx;
2804 }
2805
2806 static int cnic_service_bnx2(void *data, void *status_blk)
2807 {
2808 struct cnic_dev *dev = data;
2809
2810 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2811 struct status_block *sblk = status_blk;
2812
2813 return sblk->status_idx;
2814 }
2815
2816 return cnic_service_bnx2_queues(dev);
2817 }
2818
2819 static void cnic_service_bnx2_msix(unsigned long data)
2820 {
2821 struct cnic_dev *dev = (struct cnic_dev *) data;
2822 struct cnic_local *cp = dev->cnic_priv;
2823
2824 cp->last_status_idx = cnic_service_bnx2_queues(dev);
2825
2826 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
2827 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
2828 }
2829
2830 static void cnic_doirq(struct cnic_dev *dev)
2831 {
2832 struct cnic_local *cp = dev->cnic_priv;
2833
2834 if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
2835 u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
2836
2837 prefetch(cp->status_blk.gen);
2838 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
2839
2840 tasklet_schedule(&cp->cnic_irq_task);
2841 }
2842 }
2843
2844 static irqreturn_t cnic_irq(int irq, void *dev_instance)
2845 {
2846 struct cnic_dev *dev = dev_instance;
2847 struct cnic_local *cp = dev->cnic_priv;
2848
2849 if (cp->ack_int)
2850 cp->ack_int(dev);
2851
2852 cnic_doirq(dev);
2853
2854 return IRQ_HANDLED;
2855 }
2856
2857 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
2858 u16 index, u8 op, u8 update)
2859 {
2860 struct cnic_local *cp = dev->cnic_priv;
2861 u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
2862 COMMAND_REG_INT_ACK);
2863 struct igu_ack_register igu_ack;
2864
2865 igu_ack.status_block_index = index;
2866 igu_ack.sb_id_and_flags =
2867 ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2868 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2869 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2870 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2871
2872 CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
2873 }
2874
2875 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
2876 u16 index, u8 op, u8 update)
2877 {
2878 struct igu_regular cmd_data;
2879 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
2880
2881 cmd_data.sb_id_and_flags =
2882 (index << IGU_REGULAR_SB_INDEX_SHIFT) |
2883 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2884 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2885 (op << IGU_REGULAR_ENABLE_INT_SHIFT);
2886
2887
2888 CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
2889 }
2890
2891 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
2892 {
2893 struct cnic_local *cp = dev->cnic_priv;
2894
2895 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
2896 IGU_INT_DISABLE, 0);
2897 }
2898
2899 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
2900 {
2901 struct cnic_local *cp = dev->cnic_priv;
2902
2903 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
2904 IGU_INT_DISABLE, 0);
2905 }
2906
2907 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
2908 {
2909 u32 last_status = *info->status_idx_ptr;
2910 int kcqe_cnt;
2911
2912 /* status block index must be read before reading the KCQ */
2913 rmb();
2914 while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
2915
2916 service_kcqes(dev, kcqe_cnt);
2917
2918 /* Tell compiler that sblk fields can change. */
2919 barrier();
2920
2921 last_status = *info->status_idx_ptr;
2922 /* status block index must be read before reading the KCQ */
2923 rmb();
2924 }
2925 return last_status;
2926 }
2927
2928 static void cnic_service_bnx2x_bh(unsigned long data)
2929 {
2930 struct cnic_dev *dev = (struct cnic_dev *) data;
2931 struct cnic_local *cp = dev->cnic_priv;
2932 u32 status_idx, new_status_idx;
2933
2934 if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
2935 return;
2936
2937 while (1) {
2938 status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
2939
2940 CNIC_WR16(dev, cp->kcq1.io_addr,
2941 cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
2942
2943 if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
2944 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
2945 status_idx, IGU_INT_ENABLE, 1);
2946 break;
2947 }
2948
2949 new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
2950
2951 if (new_status_idx != status_idx)
2952 continue;
2953
2954 CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
2955 MAX_KCQ_IDX);
2956
2957 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
2958 status_idx, IGU_INT_ENABLE, 1);
2959
2960 break;
2961 }
2962 }
2963
2964 static int cnic_service_bnx2x(void *data, void *status_blk)
2965 {
2966 struct cnic_dev *dev = data;
2967 struct cnic_local *cp = dev->cnic_priv;
2968
2969 if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
2970 cnic_doirq(dev);
2971
2972 cnic_chk_pkt_rings(cp);
2973
2974 return 0;
2975 }
2976
2977 static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
2978 {
2979 struct cnic_ulp_ops *ulp_ops;
2980
2981 if (if_type == CNIC_ULP_ISCSI)
2982 cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
2983
2984 mutex_lock(&cnic_lock);
2985 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
2986 lockdep_is_held(&cnic_lock));
2987 if (!ulp_ops) {
2988 mutex_unlock(&cnic_lock);
2989 return;
2990 }
2991 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2992 mutex_unlock(&cnic_lock);
2993
2994 if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
2995 ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
2996
2997 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
2998 }
2999
3000 static void cnic_ulp_stop(struct cnic_dev *dev)
3001 {
3002 struct cnic_local *cp = dev->cnic_priv;
3003 int if_type;
3004
3005 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
3006 cnic_ulp_stop_one(cp, if_type);
3007 }
3008
3009 static void cnic_ulp_start(struct cnic_dev *dev)
3010 {
3011 struct cnic_local *cp = dev->cnic_priv;
3012 int if_type;
3013
3014 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
3015 struct cnic_ulp_ops *ulp_ops;
3016
3017 mutex_lock(&cnic_lock);
3018 ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3019 lockdep_is_held(&cnic_lock));
3020 if (!ulp_ops || !ulp_ops->cnic_start) {
3021 mutex_unlock(&cnic_lock);
3022 continue;
3023 }
3024 set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3025 mutex_unlock(&cnic_lock);
3026
3027 if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3028 ulp_ops->cnic_start(cp->ulp_handle[if_type]);
3029
3030 clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3031 }
3032 }
3033
3034 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
3035 {
3036 struct cnic_dev *dev = data;
3037
3038 switch (info->cmd) {
3039 case CNIC_CTL_STOP_CMD:
3040 cnic_hold(dev);
3041
3042 cnic_ulp_stop(dev);
3043 cnic_stop_hw(dev);
3044
3045 cnic_put(dev);
3046 break;
3047 case CNIC_CTL_START_CMD:
3048 cnic_hold(dev);
3049
3050 if (!cnic_start_hw(dev))
3051 cnic_ulp_start(dev);
3052
3053 cnic_put(dev);
3054 break;
3055 case CNIC_CTL_STOP_ISCSI_CMD: {
3056 struct cnic_local *cp = dev->cnic_priv;
3057 set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
3058 queue_delayed_work(cnic_wq, &cp->delete_task, 0);
3059 break;
3060 }
3061 case CNIC_CTL_COMPLETION_CMD: {
3062 struct cnic_ctl_completion *comp = &info->data.comp;
3063 u32 cid = BNX2X_SW_CID(comp->cid);
3064 u32 l5_cid;
3065 struct cnic_local *cp = dev->cnic_priv;
3066
3067 if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3068 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3069
3070 if (unlikely(comp->error)) {
3071 set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
3072 netdev_err(dev->netdev,
3073 "CID %x CFC delete comp error %x\n",
3074 cid, comp->error);
3075 }
3076
3077 ctx->wait_cond = 1;
3078 wake_up(&ctx->waitq);
3079 }
3080 break;
3081 }
3082 default:
3083 return -EINVAL;
3084 }
3085 return 0;
3086 }
3087
3088 static void cnic_ulp_init(struct cnic_dev *dev)
3089 {
3090 int i;
3091 struct cnic_local *cp = dev->cnic_priv;
3092
3093 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3094 struct cnic_ulp_ops *ulp_ops;
3095
3096 mutex_lock(&cnic_lock);
3097 ulp_ops = cnic_ulp_tbl_prot(i);
3098 if (!ulp_ops || !ulp_ops->cnic_init) {
3099 mutex_unlock(&cnic_lock);
3100 continue;
3101 }
3102 ulp_get(ulp_ops);
3103 mutex_unlock(&cnic_lock);
3104
3105 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3106 ulp_ops->cnic_init(dev);
3107
3108 ulp_put(ulp_ops);
3109 }
3110 }
3111
3112 static void cnic_ulp_exit(struct cnic_dev *dev)
3113 {
3114 int i;
3115 struct cnic_local *cp = dev->cnic_priv;
3116
3117 for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3118 struct cnic_ulp_ops *ulp_ops;
3119
3120 mutex_lock(&cnic_lock);
3121 ulp_ops = cnic_ulp_tbl_prot(i);
3122 if (!ulp_ops || !ulp_ops->cnic_exit) {
3123 mutex_unlock(&cnic_lock);
3124 continue;
3125 }
3126 ulp_get(ulp_ops);
3127 mutex_unlock(&cnic_lock);
3128
3129 if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3130 ulp_ops->cnic_exit(dev);
3131
3132 ulp_put(ulp_ops);
3133 }
3134 }
3135
3136 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3137 {
3138 struct cnic_dev *dev = csk->dev;
3139 struct l4_kwq_offload_pg *l4kwqe;
3140 struct kwqe *wqes[1];
3141
3142 l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3143 memset(l4kwqe, 0, sizeof(*l4kwqe));
3144 wqes[0] = (struct kwqe *) l4kwqe;
3145
3146 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3147 l4kwqe->flags =
3148 L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3149 l4kwqe->l2hdr_nbytes = ETH_HLEN;
3150
3151 l4kwqe->da0 = csk->ha[0];
3152 l4kwqe->da1 = csk->ha[1];
3153 l4kwqe->da2 = csk->ha[2];
3154 l4kwqe->da3 = csk->ha[3];
3155 l4kwqe->da4 = csk->ha[4];
3156 l4kwqe->da5 = csk->ha[5];
3157
3158 l4kwqe->sa0 = dev->mac_addr[0];
3159 l4kwqe->sa1 = dev->mac_addr[1];
3160 l4kwqe->sa2 = dev->mac_addr[2];
3161 l4kwqe->sa3 = dev->mac_addr[3];
3162 l4kwqe->sa4 = dev->mac_addr[4];
3163 l4kwqe->sa5 = dev->mac_addr[5];
3164
3165 l4kwqe->etype = ETH_P_IP;
3166 l4kwqe->ipid_start = DEF_IPID_START;
3167 l4kwqe->host_opaque = csk->l5_cid;
3168
3169 if (csk->vlan_id) {
3170 l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3171 l4kwqe->vlan_tag = csk->vlan_id;
3172 l4kwqe->l2hdr_nbytes += 4;
3173 }
3174
3175 return dev->submit_kwqes(dev, wqes, 1);
3176 }
3177
3178 static int cnic_cm_update_pg(struct cnic_sock *csk)
3179 {
3180 struct cnic_dev *dev = csk->dev;
3181 struct l4_kwq_update_pg *l4kwqe;
3182 struct kwqe *wqes[1];
3183
3184 l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3185 memset(l4kwqe, 0, sizeof(*l4kwqe));
3186 wqes[0] = (struct kwqe *) l4kwqe;
3187
3188 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3189 l4kwqe->flags =
3190 L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3191 l4kwqe->pg_cid = csk->pg_cid;
3192
3193 l4kwqe->da0 = csk->ha[0];
3194 l4kwqe->da1 = csk->ha[1];
3195 l4kwqe->da2 = csk->ha[2];
3196 l4kwqe->da3 = csk->ha[3];
3197 l4kwqe->da4 = csk->ha[4];
3198 l4kwqe->da5 = csk->ha[5];
3199
3200 l4kwqe->pg_host_opaque = csk->l5_cid;
3201 l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3202
3203 return dev->submit_kwqes(dev, wqes, 1);
3204 }
3205
3206 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3207 {
3208 struct cnic_dev *dev = csk->dev;
3209 struct l4_kwq_upload *l4kwqe;
3210 struct kwqe *wqes[1];
3211
3212 l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3213 memset(l4kwqe, 0, sizeof(*l4kwqe));
3214 wqes[0] = (struct kwqe *) l4kwqe;
3215
3216 l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3217 l4kwqe->flags =
3218 L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3219 l4kwqe->cid = csk->pg_cid;
3220
3221 return dev->submit_kwqes(dev, wqes, 1);
3222 }
3223
3224 static int cnic_cm_conn_req(struct cnic_sock *csk)
3225 {
3226 struct cnic_dev *dev = csk->dev;
3227 struct l4_kwq_connect_req1 *l4kwqe1;
3228 struct l4_kwq_connect_req2 *l4kwqe2;
3229 struct l4_kwq_connect_req3 *l4kwqe3;
3230 struct kwqe *wqes[3];
3231 u8 tcp_flags = 0;
3232 int num_wqes = 2;
3233
3234 l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3235 l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3236 l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3237 memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3238 memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3239 memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3240
3241 l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3242 l4kwqe3->flags =
3243 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3244 l4kwqe3->ka_timeout = csk->ka_timeout;
3245 l4kwqe3->ka_interval = csk->ka_interval;
3246 l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3247 l4kwqe3->tos = csk->tos;
3248 l4kwqe3->ttl = csk->ttl;
3249 l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3250 l4kwqe3->pmtu = csk->mtu;
3251 l4kwqe3->rcv_buf = csk->rcv_buf;
3252 l4kwqe3->snd_buf = csk->snd_buf;
3253 l4kwqe3->seed = csk->seed;
3254
3255 wqes[0] = (struct kwqe *) l4kwqe1;
3256 if (test_bit(SK_F_IPV6, &csk->flags)) {
3257 wqes[1] = (struct kwqe *) l4kwqe2;
3258 wqes[2] = (struct kwqe *) l4kwqe3;
3259 num_wqes = 3;
3260
3261 l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3262 l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3263 l4kwqe2->flags =
3264 L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3265 L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3266 l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3267 l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3268 l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3269 l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3270 l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3271 l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3272 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3273 sizeof(struct tcphdr);
3274 } else {
3275 wqes[1] = (struct kwqe *) l4kwqe3;
3276 l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3277 sizeof(struct tcphdr);
3278 }
3279
3280 l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3281 l4kwqe1->flags =
3282 (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3283 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3284 l4kwqe1->cid = csk->cid;
3285 l4kwqe1->pg_cid = csk->pg_cid;
3286 l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3287 l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3288 l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3289 l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3290 if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3291 tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3292 if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3293 tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3294 if (csk->tcp_flags & SK_TCP_NAGLE)
3295 tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3296 if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3297 tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3298 if (csk->tcp_flags & SK_TCP_SACK)
3299 tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3300 if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3301 tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3302
3303 l4kwqe1->tcp_flags = tcp_flags;
3304
3305 return dev->submit_kwqes(dev, wqes, num_wqes);
3306 }
3307
3308 static int cnic_cm_close_req(struct cnic_sock *csk)
3309 {
3310 struct cnic_dev *dev = csk->dev;
3311 struct l4_kwq_close_req *l4kwqe;
3312 struct kwqe *wqes[1];
3313
3314 l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3315 memset(l4kwqe, 0, sizeof(*l4kwqe));
3316 wqes[0] = (struct kwqe *) l4kwqe;
3317
3318 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3319 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3320 l4kwqe->cid = csk->cid;
3321
3322 return dev->submit_kwqes(dev, wqes, 1);
3323 }
3324
3325 static int cnic_cm_abort_req(struct cnic_sock *csk)
3326 {
3327 struct cnic_dev *dev = csk->dev;
3328 struct l4_kwq_reset_req *l4kwqe;
3329 struct kwqe *wqes[1];
3330
3331 l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3332 memset(l4kwqe, 0, sizeof(*l4kwqe));
3333 wqes[0] = (struct kwqe *) l4kwqe;
3334
3335 l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3336 l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3337 l4kwqe->cid = csk->cid;
3338
3339 return dev->submit_kwqes(dev, wqes, 1);
3340 }
3341
3342 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3343 u32 l5_cid, struct cnic_sock **csk, void *context)
3344 {
3345 struct cnic_local *cp = dev->cnic_priv;
3346 struct cnic_sock *csk1;
3347
3348 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3349 return -EINVAL;
3350
3351 if (cp->ctx_tbl) {
3352 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3353
3354 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3355 return -EAGAIN;
3356 }
3357
3358 csk1 = &cp->csk_tbl[l5_cid];
3359 if (atomic_read(&csk1->ref_count))
3360 return -EAGAIN;
3361
3362 if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3363 return -EBUSY;
3364
3365 csk1->dev = dev;
3366 csk1->cid = cid;
3367 csk1->l5_cid = l5_cid;
3368 csk1->ulp_type = ulp_type;
3369 csk1->context = context;
3370
3371 csk1->ka_timeout = DEF_KA_TIMEOUT;
3372 csk1->ka_interval = DEF_KA_INTERVAL;
3373 csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3374 csk1->tos = DEF_TOS;
3375 csk1->ttl = DEF_TTL;
3376 csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3377 csk1->rcv_buf = DEF_RCV_BUF;
3378 csk1->snd_buf = DEF_SND_BUF;
3379 csk1->seed = DEF_SEED;
3380
3381 *csk = csk1;
3382 return 0;
3383 }
3384
3385 static void cnic_cm_cleanup(struct cnic_sock *csk)
3386 {
3387 if (csk->src_port) {
3388 struct cnic_dev *dev = csk->dev;
3389 struct cnic_local *cp = dev->cnic_priv;
3390
3391 cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3392 csk->src_port = 0;
3393 }
3394 }
3395
3396 static void cnic_close_conn(struct cnic_sock *csk)
3397 {
3398 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3399 cnic_cm_upload_pg(csk);
3400 clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3401 }
3402 cnic_cm_cleanup(csk);
3403 }
3404
3405 static int cnic_cm_destroy(struct cnic_sock *csk)
3406 {
3407 if (!cnic_in_use(csk))
3408 return -EINVAL;
3409
3410 csk_hold(csk);
3411 clear_bit(SK_F_INUSE, &csk->flags);
3412 smp_mb__after_clear_bit();
3413 while (atomic_read(&csk->ref_count) != 1)
3414 msleep(1);
3415 cnic_cm_cleanup(csk);
3416
3417 csk->flags = 0;
3418 csk_put(csk);
3419 return 0;
3420 }
3421
3422 static inline u16 cnic_get_vlan(struct net_device *dev,
3423 struct net_device **vlan_dev)
3424 {
3425 if (dev->priv_flags & IFF_802_1Q_VLAN) {
3426 *vlan_dev = vlan_dev_real_dev(dev);
3427 return vlan_dev_vlan_id(dev);
3428 }
3429 *vlan_dev = dev;
3430 return 0;
3431 }
3432
3433 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3434 struct dst_entry **dst)
3435 {
3436 #if defined(CONFIG_INET)
3437 struct rtable *rt;
3438
3439 rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
3440 if (!IS_ERR(rt)) {
3441 *dst = &rt->dst;
3442 return 0;
3443 }
3444 return PTR_ERR(rt);
3445 #else
3446 return -ENETUNREACH;
3447 #endif
3448 }
3449
3450 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3451 struct dst_entry **dst)
3452 {
3453 #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
3454 struct flowi6 fl6;
3455
3456 memset(&fl6, 0, sizeof(fl6));
3457 ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
3458 if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
3459 fl6.flowi6_oif = dst_addr->sin6_scope_id;
3460
3461 *dst = ip6_route_output(&init_net, NULL, &fl6);
3462 if (*dst)
3463 return 0;
3464 #endif
3465
3466 return -ENETUNREACH;
3467 }
3468
3469 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3470 int ulp_type)
3471 {
3472 struct cnic_dev *dev = NULL;
3473 struct dst_entry *dst;
3474 struct net_device *netdev = NULL;
3475 int err = -ENETUNREACH;
3476
3477 if (dst_addr->sin_family == AF_INET)
3478 err = cnic_get_v4_route(dst_addr, &dst);
3479 else if (dst_addr->sin_family == AF_INET6) {
3480 struct sockaddr_in6 *dst_addr6 =
3481 (struct sockaddr_in6 *) dst_addr;
3482
3483 err = cnic_get_v6_route(dst_addr6, &dst);
3484 } else
3485 return NULL;
3486
3487 if (err)
3488 return NULL;
3489
3490 if (!dst->dev)
3491 goto done;
3492
3493 cnic_get_vlan(dst->dev, &netdev);
3494
3495 dev = cnic_from_netdev(netdev);
3496
3497 done:
3498 dst_release(dst);
3499 if (dev)
3500 cnic_put(dev);
3501 return dev;
3502 }
3503
3504 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3505 {
3506 struct cnic_dev *dev = csk->dev;
3507 struct cnic_local *cp = dev->cnic_priv;
3508
3509 return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3510 }
3511
3512 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3513 {
3514 struct cnic_dev *dev = csk->dev;
3515 struct cnic_local *cp = dev->cnic_priv;
3516 int is_v6, rc = 0;
3517 struct dst_entry *dst = NULL;
3518 struct net_device *realdev;
3519 __be16 local_port;
3520 u32 port_id;
3521
3522 if (saddr->local.v6.sin6_family == AF_INET6 &&
3523 saddr->remote.v6.sin6_family == AF_INET6)
3524 is_v6 = 1;
3525 else if (saddr->local.v4.sin_family == AF_INET &&
3526 saddr->remote.v4.sin_family == AF_INET)
3527 is_v6 = 0;
3528 else
3529 return -EINVAL;
3530
3531 clear_bit(SK_F_IPV6, &csk->flags);
3532
3533 if (is_v6) {
3534 set_bit(SK_F_IPV6, &csk->flags);
3535 cnic_get_v6_route(&saddr->remote.v6, &dst);
3536
3537 memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3538 sizeof(struct in6_addr));
3539 csk->dst_port = saddr->remote.v6.sin6_port;
3540 local_port = saddr->local.v6.sin6_port;
3541
3542 } else {
3543 cnic_get_v4_route(&saddr->remote.v4, &dst);
3544
3545 csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3546 csk->dst_port = saddr->remote.v4.sin_port;
3547 local_port = saddr->local.v4.sin_port;
3548 }
3549
3550 csk->vlan_id = 0;
3551 csk->mtu = dev->netdev->mtu;
3552 if (dst && dst->dev) {
3553 u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3554 if (realdev == dev->netdev) {
3555 csk->vlan_id = vlan;
3556 csk->mtu = dst_mtu(dst);
3557 }
3558 }
3559
3560 port_id = be16_to_cpu(local_port);
3561 if (port_id >= CNIC_LOCAL_PORT_MIN &&
3562 port_id < CNIC_LOCAL_PORT_MAX) {
3563 if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3564 port_id = 0;
3565 } else
3566 port_id = 0;
3567
3568 if (!port_id) {
3569 port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3570 if (port_id == -1) {
3571 rc = -ENOMEM;
3572 goto err_out;
3573 }
3574 local_port = cpu_to_be16(port_id);
3575 }
3576 csk->src_port = local_port;
3577
3578 err_out:
3579 dst_release(dst);
3580 return rc;
3581 }
3582
3583 static void cnic_init_csk_state(struct cnic_sock *csk)
3584 {
3585 csk->state = 0;
3586 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3587 clear_bit(SK_F_CLOSING, &csk->flags);
3588 }
3589
3590 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3591 {
3592 struct cnic_local *cp = csk->dev->cnic_priv;
3593 int err = 0;
3594
3595 if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
3596 return -EOPNOTSUPP;
3597
3598 if (!cnic_in_use(csk))
3599 return -EINVAL;
3600
3601 if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3602 return -EINVAL;
3603
3604 cnic_init_csk_state(csk);
3605
3606 err = cnic_get_route(csk, saddr);
3607 if (err)
3608 goto err_out;
3609
3610 err = cnic_resolve_addr(csk, saddr);
3611 if (!err)
3612 return 0;
3613
3614 err_out:
3615 clear_bit(SK_F_CONNECT_START, &csk->flags);
3616 return err;
3617 }
3618
3619 static int cnic_cm_abort(struct cnic_sock *csk)
3620 {
3621 struct cnic_local *cp = csk->dev->cnic_priv;
3622 u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3623
3624 if (!cnic_in_use(csk))
3625 return -EINVAL;
3626
3627 if (cnic_abort_prep(csk))
3628 return cnic_cm_abort_req(csk);
3629
3630 /* Getting here means that we haven't started connect, or
3631 * connect was not successful.
3632 */
3633
3634 cp->close_conn(csk, opcode);
3635 if (csk->state != opcode)
3636 return -EALREADY;
3637
3638 return 0;
3639 }
3640
3641 static int cnic_cm_close(struct cnic_sock *csk)
3642 {
3643 if (!cnic_in_use(csk))
3644 return -EINVAL;
3645
3646 if (cnic_close_prep(csk)) {
3647 csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3648 return cnic_cm_close_req(csk);
3649 } else {
3650 return -EALREADY;
3651 }
3652 return 0;
3653 }
3654
3655 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3656 u8 opcode)
3657 {
3658 struct cnic_ulp_ops *ulp_ops;
3659 int ulp_type = csk->ulp_type;
3660
3661 rcu_read_lock();
3662 ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3663 if (ulp_ops) {
3664 if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3665 ulp_ops->cm_connect_complete(csk);
3666 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3667 ulp_ops->cm_close_complete(csk);
3668 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3669 ulp_ops->cm_remote_abort(csk);
3670 else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3671 ulp_ops->cm_abort_complete(csk);
3672 else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3673 ulp_ops->cm_remote_close(csk);
3674 }
3675 rcu_read_unlock();
3676 }
3677
3678 static int cnic_cm_set_pg(struct cnic_sock *csk)
3679 {
3680 if (cnic_offld_prep(csk)) {
3681 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3682 cnic_cm_update_pg(csk);
3683 else
3684 cnic_cm_offload_pg(csk);
3685 }
3686 return 0;
3687 }
3688
3689 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3690 {
3691 struct cnic_local *cp = dev->cnic_priv;
3692 u32 l5_cid = kcqe->pg_host_opaque;
3693 u8 opcode = kcqe->op_code;
3694 struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3695
3696 csk_hold(csk);
3697 if (!cnic_in_use(csk))
3698 goto done;
3699
3700 if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3701 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3702 goto done;
3703 }
3704 /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3705 if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3706 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3707 cnic_cm_upcall(cp, csk,
3708 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3709 goto done;
3710 }
3711
3712 csk->pg_cid = kcqe->pg_cid;
3713 set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3714 cnic_cm_conn_req(csk);
3715
3716 done:
3717 csk_put(csk);
3718 }
3719
3720 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3721 {
3722 struct cnic_local *cp = dev->cnic_priv;
3723 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3724 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3725 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3726
3727 ctx->timestamp = jiffies;
3728 ctx->wait_cond = 1;
3729 wake_up(&ctx->waitq);
3730 }
3731
3732 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3733 {
3734 struct cnic_local *cp = dev->cnic_priv;
3735 struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3736 u8 opcode = l4kcqe->op_code;
3737 u32 l5_cid;
3738 struct cnic_sock *csk;
3739
3740 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3741 cnic_process_fcoe_term_conn(dev, kcqe);
3742 return;
3743 }
3744 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3745 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3746 cnic_cm_process_offld_pg(dev, l4kcqe);
3747 return;
3748 }
3749
3750 l5_cid = l4kcqe->conn_id;
3751 if (opcode & 0x80)
3752 l5_cid = l4kcqe->cid;
3753 if (l5_cid >= MAX_CM_SK_TBL_SZ)
3754 return;
3755
3756 csk = &cp->csk_tbl[l5_cid];
3757 csk_hold(csk);
3758
3759 if (!cnic_in_use(csk)) {
3760 csk_put(csk);
3761 return;
3762 }
3763
3764 switch (opcode) {
3765 case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
3766 if (l4kcqe->status != 0) {
3767 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3768 cnic_cm_upcall(cp, csk,
3769 L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3770 }
3771 break;
3772 case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
3773 if (l4kcqe->status == 0)
3774 set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
3775
3776 smp_mb__before_clear_bit();
3777 clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3778 cnic_cm_upcall(cp, csk, opcode);
3779 break;
3780
3781 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3782 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3783 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3784 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3785 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3786 cp->close_conn(csk, opcode);
3787 break;
3788
3789 case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
3790 /* after we already sent CLOSE_REQ */
3791 if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
3792 !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
3793 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3794 cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
3795 else
3796 cnic_cm_upcall(cp, csk, opcode);
3797 break;
3798 }
3799 csk_put(csk);
3800 }
3801
3802 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
3803 {
3804 struct cnic_dev *dev = data;
3805 int i;
3806
3807 for (i = 0; i < num; i++)
3808 cnic_cm_process_kcqe(dev, kcqe[i]);
3809 }
3810
3811 static struct cnic_ulp_ops cm_ulp_ops = {
3812 .indicate_kcqes = cnic_cm_indicate_kcqe,
3813 };
3814
3815 static void cnic_cm_free_mem(struct cnic_dev *dev)
3816 {
3817 struct cnic_local *cp = dev->cnic_priv;
3818
3819 kfree(cp->csk_tbl);
3820 cp->csk_tbl = NULL;
3821 cnic_free_id_tbl(&cp->csk_port_tbl);
3822 }
3823
3824 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
3825 {
3826 struct cnic_local *cp = dev->cnic_priv;
3827 u32 port_id;
3828
3829 cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
3830 GFP_KERNEL);
3831 if (!cp->csk_tbl)
3832 return -ENOMEM;
3833
3834 port_id = random32();
3835 port_id %= CNIC_LOCAL_PORT_RANGE;
3836 if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
3837 CNIC_LOCAL_PORT_MIN, port_id)) {
3838 cnic_cm_free_mem(dev);
3839 return -ENOMEM;
3840 }
3841 return 0;
3842 }
3843
3844 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
3845 {
3846 if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
3847 /* Unsolicited RESET_COMP or RESET_RECEIVED */
3848 opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
3849 csk->state = opcode;
3850 }
3851
3852 /* 1. If event opcode matches the expected event in csk->state
3853 * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
3854 * event
3855 * 3. If the expected event is 0, meaning the connection was never
3856 * never established, we accept the opcode from cm_abort.
3857 */
3858 if (opcode == csk->state || csk->state == 0 ||
3859 csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
3860 csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
3861 if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
3862 if (csk->state == 0)
3863 csk->state = opcode;
3864 return 1;
3865 }
3866 }
3867 return 0;
3868 }
3869
3870 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
3871 {
3872 struct cnic_dev *dev = csk->dev;
3873 struct cnic_local *cp = dev->cnic_priv;
3874
3875 if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
3876 cnic_cm_upcall(cp, csk, opcode);
3877 return;
3878 }
3879
3880 clear_bit(SK_F_CONNECT_START, &csk->flags);
3881 cnic_close_conn(csk);
3882 csk->state = opcode;
3883 cnic_cm_upcall(cp, csk, opcode);
3884 }
3885
3886 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
3887 {
3888 }
3889
3890 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
3891 {
3892 u32 seed;
3893
3894 seed = random32();
3895 cnic_ctx_wr(dev, 45, 0, seed);
3896 return 0;
3897 }
3898
3899 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
3900 {
3901 struct cnic_dev *dev = csk->dev;
3902 struct cnic_local *cp = dev->cnic_priv;
3903 struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
3904 union l5cm_specific_data l5_data;
3905 u32 cmd = 0;
3906 int close_complete = 0;
3907
3908 switch (opcode) {
3909 case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
3910 case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
3911 case L4_KCQE_OPCODE_VALUE_RESET_COMP:
3912 if (cnic_ready_to_close(csk, opcode)) {
3913 if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3914 cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
3915 else
3916 close_complete = 1;
3917 }
3918 break;
3919 case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
3920 cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
3921 break;
3922 case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
3923 close_complete = 1;
3924 break;
3925 }
3926 if (cmd) {
3927 memset(&l5_data, 0, sizeof(l5_data));
3928
3929 cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
3930 &l5_data);
3931 } else if (close_complete) {
3932 ctx->timestamp = jiffies;
3933 cnic_close_conn(csk);
3934 cnic_cm_upcall(cp, csk, csk->state);
3935 }
3936 }
3937
3938 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
3939 {
3940 struct cnic_local *cp = dev->cnic_priv;
3941 int i;
3942
3943 if (!cp->ctx_tbl)
3944 return;
3945
3946 if (!netif_running(dev->netdev))
3947 return;
3948
3949 for (i = 0; i < cp->max_cid_space; i++) {
3950 struct cnic_context *ctx = &cp->ctx_tbl[i];
3951 int j;
3952
3953 while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
3954 msleep(10);
3955
3956 for (j = 0; j < 5; j++) {
3957 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3958 break;
3959 msleep(20);
3960 }
3961
3962 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3963 netdev_warn(dev->netdev, "CID %x not deleted\n",
3964 ctx->cid);
3965 }
3966
3967 cancel_delayed_work(&cp->delete_task);
3968 flush_workqueue(cnic_wq);
3969
3970 if (atomic_read(&cp->iscsi_conn) != 0)
3971 netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
3972 atomic_read(&cp->iscsi_conn));
3973 }
3974
3975 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
3976 {
3977 struct cnic_local *cp = dev->cnic_priv;
3978 u32 pfid = cp->pfid;
3979 u32 port = CNIC_PORT(cp);
3980
3981 cnic_init_bnx2x_mac(dev);
3982 cnic_bnx2x_set_tcp_timestamp(dev, 1);
3983
3984 CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
3985 XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
3986
3987 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3988 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
3989 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
3990 XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
3991 DEF_MAX_DA_COUNT);
3992
3993 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3994 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
3995 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3996 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
3997 CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
3998 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
3999 CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4000 XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
4001
4002 CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
4003 DEF_MAX_CWND);
4004 return 0;
4005 }
4006
4007 static void cnic_delete_task(struct work_struct *work)
4008 {
4009 struct cnic_local *cp;
4010 struct cnic_dev *dev;
4011 u32 i;
4012 int need_resched = 0;
4013
4014 cp = container_of(work, struct cnic_local, delete_task.work);
4015 dev = cp->dev;
4016
4017 if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
4018 struct drv_ctl_info info;
4019
4020 cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
4021
4022 info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
4023 cp->ethdev->drv_ctl(dev->netdev, &info);
4024 }
4025
4026 for (i = 0; i < cp->max_cid_space; i++) {
4027 struct cnic_context *ctx = &cp->ctx_tbl[i];
4028 int err;
4029
4030 if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
4031 !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4032 continue;
4033
4034 if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
4035 need_resched = 1;
4036 continue;
4037 }
4038
4039 if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4040 continue;
4041
4042 err = cnic_bnx2x_destroy_ramrod(dev, i);
4043
4044 cnic_free_bnx2x_conn_resc(dev, i);
4045 if (!err) {
4046 if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
4047 atomic_dec(&cp->iscsi_conn);
4048
4049 clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
4050 }
4051 }
4052
4053 if (need_resched)
4054 queue_delayed_work(cnic_wq, &cp->delete_task,
4055 msecs_to_jiffies(10));
4056
4057 }
4058
4059 static int cnic_cm_open(struct cnic_dev *dev)
4060 {
4061 struct cnic_local *cp = dev->cnic_priv;
4062 int err;
4063
4064 err = cnic_cm_alloc_mem(dev);
4065 if (err)
4066 return err;
4067
4068 err = cp->start_cm(dev);
4069
4070 if (err)
4071 goto err_out;
4072
4073 INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
4074
4075 dev->cm_create = cnic_cm_create;
4076 dev->cm_destroy = cnic_cm_destroy;
4077 dev->cm_connect = cnic_cm_connect;
4078 dev->cm_abort = cnic_cm_abort;
4079 dev->cm_close = cnic_cm_close;
4080 dev->cm_select_dev = cnic_cm_select_dev;
4081
4082 cp->ulp_handle[CNIC_ULP_L4] = dev;
4083 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
4084 return 0;
4085
4086 err_out:
4087 cnic_cm_free_mem(dev);
4088 return err;
4089 }
4090
4091 static int cnic_cm_shutdown(struct cnic_dev *dev)
4092 {
4093 struct cnic_local *cp = dev->cnic_priv;
4094 int i;
4095
4096 cp->stop_cm(dev);
4097
4098 if (!cp->csk_tbl)
4099 return 0;
4100
4101 for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4102 struct cnic_sock *csk = &cp->csk_tbl[i];
4103
4104 clear_bit(SK_F_INUSE, &csk->flags);
4105 cnic_cm_cleanup(csk);
4106 }
4107 cnic_cm_free_mem(dev);
4108
4109 return 0;
4110 }
4111
4112 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4113 {
4114 u32 cid_addr;
4115 int i;
4116
4117 cid_addr = GET_CID_ADDR(cid);
4118
4119 for (i = 0; i < CTX_SIZE; i += 4)
4120 cnic_ctx_wr(dev, cid_addr, i, 0);
4121 }
4122
4123 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4124 {
4125 struct cnic_local *cp = dev->cnic_priv;
4126 int ret = 0, i;
4127 u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4128
4129 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4130 return 0;
4131
4132 for (i = 0; i < cp->ctx_blks; i++) {
4133 int j;
4134 u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4135 u32 val;
4136
4137 memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
4138
4139 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4140 (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4141 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4142 (u64) cp->ctx_arr[i].mapping >> 32);
4143 CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4144 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4145 for (j = 0; j < 10; j++) {
4146
4147 val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4148 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4149 break;
4150 udelay(5);
4151 }
4152 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4153 ret = -EBUSY;
4154 break;
4155 }
4156 }
4157 return ret;
4158 }
4159
4160 static void cnic_free_irq(struct cnic_dev *dev)
4161 {
4162 struct cnic_local *cp = dev->cnic_priv;
4163 struct cnic_eth_dev *ethdev = cp->ethdev;
4164
4165 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4166 cp->disable_int_sync(dev);
4167 tasklet_kill(&cp->cnic_irq_task);
4168 free_irq(ethdev->irq_arr[0].vector, dev);
4169 }
4170 }
4171
4172 static int cnic_request_irq(struct cnic_dev *dev)
4173 {
4174 struct cnic_local *cp = dev->cnic_priv;
4175 struct cnic_eth_dev *ethdev = cp->ethdev;
4176 int err;
4177
4178 err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4179 if (err)
4180 tasklet_disable(&cp->cnic_irq_task);
4181
4182 return err;
4183 }
4184
4185 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4186 {
4187 struct cnic_local *cp = dev->cnic_priv;
4188 struct cnic_eth_dev *ethdev = cp->ethdev;
4189
4190 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4191 int err, i = 0;
4192 int sblk_num = cp->status_blk_num;
4193 u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4194 BNX2_HC_SB_CONFIG_1;
4195
4196 CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4197
4198 CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4199 CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4200 CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4201
4202 cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4203 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
4204 (unsigned long) dev);
4205 err = cnic_request_irq(dev);
4206 if (err)
4207 return err;
4208
4209 while (cp->status_blk.bnx2->status_completion_producer_index &&
4210 i < 10) {
4211 CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4212 1 << (11 + sblk_num));
4213 udelay(10);
4214 i++;
4215 barrier();
4216 }
4217 if (cp->status_blk.bnx2->status_completion_producer_index) {
4218 cnic_free_irq(dev);
4219 goto failed;
4220 }
4221
4222 } else {
4223 struct status_block *sblk = cp->status_blk.gen;
4224 u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4225 int i = 0;
4226
4227 while (sblk->status_completion_producer_index && i < 10) {
4228 CNIC_WR(dev, BNX2_HC_COMMAND,
4229 hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4230 udelay(10);
4231 i++;
4232 barrier();
4233 }
4234 if (sblk->status_completion_producer_index)
4235 goto failed;
4236
4237 }
4238 return 0;
4239
4240 failed:
4241 netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4242 return -EBUSY;
4243 }
4244
4245 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4246 {
4247 struct cnic_local *cp = dev->cnic_priv;
4248 struct cnic_eth_dev *ethdev = cp->ethdev;
4249
4250 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4251 return;
4252
4253 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4254 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4255 }
4256
4257 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4258 {
4259 struct cnic_local *cp = dev->cnic_priv;
4260 struct cnic_eth_dev *ethdev = cp->ethdev;
4261
4262 if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4263 return;
4264
4265 CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4266 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4267 CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4268 synchronize_irq(ethdev->irq_arr[0].vector);
4269 }
4270
4271 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4272 {
4273 struct cnic_local *cp = dev->cnic_priv;
4274 struct cnic_eth_dev *ethdev = cp->ethdev;
4275 struct cnic_uio_dev *udev = cp->udev;
4276 u32 cid_addr, tx_cid, sb_id;
4277 u32 val, offset0, offset1, offset2, offset3;
4278 int i;
4279 struct tx_bd *txbd;
4280 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4281 struct status_block *s_blk = cp->status_blk.gen;
4282
4283 sb_id = cp->status_blk_num;
4284 tx_cid = 20;
4285 cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4286 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4287 struct status_block_msix *sblk = cp->status_blk.bnx2;
4288
4289 tx_cid = TX_TSS_CID + sb_id - 1;
4290 CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4291 (TX_TSS_CID << 7));
4292 cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4293 }
4294 cp->tx_cons = *cp->tx_cons_ptr;
4295
4296 cid_addr = GET_CID_ADDR(tx_cid);
4297 if (CHIP_NUM(cp) == CHIP_NUM_5709) {
4298 u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4299
4300 for (i = 0; i < PHY_CTX_SIZE; i += 4)
4301 cnic_ctx_wr(dev, cid_addr2, i, 0);
4302
4303 offset0 = BNX2_L2CTX_TYPE_XI;
4304 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4305 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4306 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4307 } else {
4308 cnic_init_context(dev, tx_cid);
4309 cnic_init_context(dev, tx_cid + 1);
4310
4311 offset0 = BNX2_L2CTX_TYPE;
4312 offset1 = BNX2_L2CTX_CMD_TYPE;
4313 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4314 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4315 }
4316 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4317 cnic_ctx_wr(dev, cid_addr, offset0, val);
4318
4319 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4320 cnic_ctx_wr(dev, cid_addr, offset1, val);
4321
4322 txbd = udev->l2_ring;
4323
4324 buf_map = udev->l2_buf_map;
4325 for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
4326 txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4327 txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4328 }
4329 val = (u64) ring_map >> 32;
4330 cnic_ctx_wr(dev, cid_addr, offset2, val);
4331 txbd->tx_bd_haddr_hi = val;
4332
4333 val = (u64) ring_map & 0xffffffff;
4334 cnic_ctx_wr(dev, cid_addr, offset3, val);
4335 txbd->tx_bd_haddr_lo = val;
4336 }
4337
4338 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4339 {
4340 struct cnic_local *cp = dev->cnic_priv;
4341 struct cnic_eth_dev *ethdev = cp->ethdev;
4342 struct cnic_uio_dev *udev = cp->udev;
4343 u32 cid_addr, sb_id, val, coal_reg, coal_val;
4344 int i;
4345 struct rx_bd *rxbd;
4346 struct status_block *s_blk = cp->status_blk.gen;
4347 dma_addr_t ring_map = udev->l2_ring_map;
4348
4349 sb_id = cp->status_blk_num;
4350 cnic_init_context(dev, 2);
4351 cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4352 coal_reg = BNX2_HC_COMMAND;
4353 coal_val = CNIC_RD(dev, coal_reg);
4354 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4355 struct status_block_msix *sblk = cp->status_blk.bnx2;
4356
4357 cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4358 coal_reg = BNX2_HC_COALESCE_NOW;
4359 coal_val = 1 << (11 + sb_id);
4360 }
4361 i = 0;
4362 while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4363 CNIC_WR(dev, coal_reg, coal_val);
4364 udelay(10);
4365 i++;
4366 barrier();
4367 }
4368 cp->rx_cons = *cp->rx_cons_ptr;
4369
4370 cid_addr = GET_CID_ADDR(2);
4371 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4372 BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4373 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4374
4375 if (sb_id == 0)
4376 val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4377 else
4378 val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4379 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4380
4381 rxbd = udev->l2_ring + BCM_PAGE_SIZE;
4382 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
4383 dma_addr_t buf_map;
4384 int n = (i % cp->l2_rx_ring_size) + 1;
4385
4386 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4387 rxbd->rx_bd_len = cp->l2_single_buf_size;
4388 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4389 rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4390 rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4391 }
4392 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4393 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4394 rxbd->rx_bd_haddr_hi = val;
4395
4396 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4397 cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4398 rxbd->rx_bd_haddr_lo = val;
4399
4400 val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4401 cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4402 }
4403
4404 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4405 {
4406 struct kwqe *wqes[1], l2kwqe;
4407
4408 memset(&l2kwqe, 0, sizeof(l2kwqe));
4409 wqes[0] = &l2kwqe;
4410 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4411 (L2_KWQE_OPCODE_VALUE_FLUSH <<
4412 KWQE_OPCODE_SHIFT) | 2;
4413 dev->submit_kwqes(dev, wqes, 1);
4414 }
4415
4416 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4417 {
4418 struct cnic_local *cp = dev->cnic_priv;
4419 u32 val;
4420
4421 val = cp->func << 2;
4422
4423 cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4424
4425 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4426 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4427 dev->mac_addr[0] = (u8) (val >> 8);
4428 dev->mac_addr[1] = (u8) val;
4429
4430 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4431
4432 val = cnic_reg_rd_ind(dev, cp->shmem_base +
4433 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4434 dev->mac_addr[2] = (u8) (val >> 24);
4435 dev->mac_addr[3] = (u8) (val >> 16);
4436 dev->mac_addr[4] = (u8) (val >> 8);
4437 dev->mac_addr[5] = (u8) val;
4438
4439 CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4440
4441 val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4442 if (CHIP_NUM(cp) != CHIP_NUM_5709)
4443 val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4444
4445 CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4446 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4447 CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4448 }
4449
4450 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4451 {
4452 struct cnic_local *cp = dev->cnic_priv;
4453 struct cnic_eth_dev *ethdev = cp->ethdev;
4454 struct status_block *sblk = cp->status_blk.gen;
4455 u32 val, kcq_cid_addr, kwq_cid_addr;
4456 int err;
4457
4458 cnic_set_bnx2_mac(dev);
4459
4460 val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4461 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4462 if (BCM_PAGE_BITS > 12)
4463 val |= (12 - 8) << 4;
4464 else
4465 val |= (BCM_PAGE_BITS - 8) << 4;
4466
4467 CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4468
4469 CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4470 CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4471 CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4472
4473 err = cnic_setup_5709_context(dev, 1);
4474 if (err)
4475 return err;
4476
4477 cnic_init_context(dev, KWQ_CID);
4478 cnic_init_context(dev, KCQ_CID);
4479
4480 kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4481 cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4482
4483 cp->max_kwq_idx = MAX_KWQ_IDX;
4484 cp->kwq_prod_idx = 0;
4485 cp->kwq_con_idx = 0;
4486 set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4487
4488 if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
4489 cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4490 else
4491 cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4492
4493 /* Initialize the kernel work queue context. */
4494 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4495 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4496 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4497
4498 val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4499 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4500
4501 val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4502 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4503
4504 val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4505 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4506
4507 val = (u32) cp->kwq_info.pgtbl_map;
4508 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4509
4510 kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4511 cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4512
4513 cp->kcq1.sw_prod_idx = 0;
4514 cp->kcq1.hw_prod_idx_ptr =
4515 (u16 *) &sblk->status_completion_producer_index;
4516
4517 cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
4518
4519 /* Initialize the kernel complete queue context. */
4520 val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4521 (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4522 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4523
4524 val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4525 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4526
4527 val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4528 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4529
4530 val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4531 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4532
4533 val = (u32) cp->kcq1.dma.pgtbl_map;
4534 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4535
4536 cp->int_num = 0;
4537 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4538 struct status_block_msix *msblk = cp->status_blk.bnx2;
4539 u32 sb_id = cp->status_blk_num;
4540 u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4541
4542 cp->kcq1.hw_prod_idx_ptr =
4543 (u16 *) &msblk->status_completion_producer_index;
4544 cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
4545 cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
4546 cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4547 cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4548 cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4549 }
4550
4551 /* Enable Commnad Scheduler notification when we write to the
4552 * host producer index of the kernel contexts. */
4553 CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4554
4555 /* Enable Command Scheduler notification when we write to either
4556 * the Send Queue or Receive Queue producer indexes of the kernel
4557 * bypass contexts. */
4558 CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4559 CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4560
4561 /* Notify COM when the driver post an application buffer. */
4562 CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4563
4564 /* Set the CP and COM doorbells. These two processors polls the
4565 * doorbell for a non zero value before running. This must be done
4566 * after setting up the kernel queue contexts. */
4567 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4568 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4569
4570 cnic_init_bnx2_tx_ring(dev);
4571 cnic_init_bnx2_rx_ring(dev);
4572
4573 err = cnic_init_bnx2_irq(dev);
4574 if (err) {
4575 netdev_err(dev->netdev, "cnic_init_irq failed\n");
4576 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4577 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4578 return err;
4579 }
4580
4581 return 0;
4582 }
4583
4584 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4585 {
4586 struct cnic_local *cp = dev->cnic_priv;
4587 struct cnic_eth_dev *ethdev = cp->ethdev;
4588 u32 start_offset = ethdev->ctx_tbl_offset;
4589 int i;
4590
4591 for (i = 0; i < cp->ctx_blks; i++) {
4592 struct cnic_ctx *ctx = &cp->ctx_arr[i];
4593 dma_addr_t map = ctx->mapping;
4594
4595 if (cp->ctx_align) {
4596 unsigned long mask = cp->ctx_align - 1;
4597
4598 map = (map + mask) & ~mask;
4599 }
4600
4601 cnic_ctx_tbl_wr(dev, start_offset + i, map);
4602 }
4603 }
4604
4605 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4606 {
4607 struct cnic_local *cp = dev->cnic_priv;
4608 struct cnic_eth_dev *ethdev = cp->ethdev;
4609 int err = 0;
4610
4611 tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
4612 (unsigned long) dev);
4613 if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4614 err = cnic_request_irq(dev);
4615
4616 return err;
4617 }
4618
4619 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4620 u16 sb_id, u8 sb_index,
4621 u8 disable)
4622 {
4623
4624 u32 addr = BAR_CSTRORM_INTMEM +
4625 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4626 offsetof(struct hc_status_block_data_e1x, index_data) +
4627 sizeof(struct hc_index_data)*sb_index +
4628 offsetof(struct hc_index_data, flags);
4629 u16 flags = CNIC_RD16(dev, addr);
4630 /* clear and set */
4631 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4632 flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4633 HC_INDEX_DATA_HC_ENABLED);
4634 CNIC_WR16(dev, addr, flags);
4635 }
4636
4637 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4638 {
4639 struct cnic_local *cp = dev->cnic_priv;
4640 u8 sb_id = cp->status_blk_num;
4641
4642 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4643 CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4644 offsetof(struct hc_status_block_data_e1x, index_data) +
4645 sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4646 offsetof(struct hc_index_data, timeout), 64 / 4);
4647 cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4648 }
4649
4650 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4651 {
4652 }
4653
4654 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4655 struct client_init_ramrod_data *data)
4656 {
4657 struct cnic_local *cp = dev->cnic_priv;
4658 struct cnic_uio_dev *udev = cp->udev;
4659 union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4660 dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4661 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4662 int i;
4663 u32 cli = cp->ethdev->iscsi_l2_client_id;
4664 u32 val;
4665
4666 memset(txbd, 0, BCM_PAGE_SIZE);
4667
4668 buf_map = udev->l2_buf_map;
4669 for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4670 struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4671 struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4672
4673 start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4674 start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4675 reg_bd->addr_hi = start_bd->addr_hi;
4676 reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4677 start_bd->nbytes = cpu_to_le16(0x10);
4678 start_bd->nbd = cpu_to_le16(3);
4679 start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4680 start_bd->general_data = (UNICAST_ADDRESS <<
4681 ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
4682 start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4683
4684 }
4685
4686 val = (u64) ring_map >> 32;
4687 txbd->next_bd.addr_hi = cpu_to_le32(val);
4688
4689 data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4690
4691 val = (u64) ring_map & 0xffffffff;
4692 txbd->next_bd.addr_lo = cpu_to_le32(val);
4693
4694 data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4695
4696 /* Other ramrod params */
4697 data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4698 data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4699
4700 /* reset xstorm per client statistics */
4701 if (cli < MAX_STAT_COUNTER_ID) {
4702 data->general.statistics_zero_flg = 1;
4703 data->general.statistics_en_flg = 1;
4704 data->general.statistics_counter_id = cli;
4705 }
4706
4707 cp->tx_cons_ptr =
4708 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4709 }
4710
4711 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4712 struct client_init_ramrod_data *data)
4713 {
4714 struct cnic_local *cp = dev->cnic_priv;
4715 struct cnic_uio_dev *udev = cp->udev;
4716 struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4717 BCM_PAGE_SIZE);
4718 struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4719 (udev->l2_ring + (2 * BCM_PAGE_SIZE));
4720 struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4721 int i;
4722 u32 cli = cp->ethdev->iscsi_l2_client_id;
4723 int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4724 u32 val;
4725 dma_addr_t ring_map = udev->l2_ring_map;
4726
4727 /* General data */
4728 data->general.client_id = cli;
4729 data->general.activate_flg = 1;
4730 data->general.sp_client_id = cli;
4731 data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
4732 data->general.func_id = cp->pfid;
4733
4734 for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
4735 dma_addr_t buf_map;
4736 int n = (i % cp->l2_rx_ring_size) + 1;
4737
4738 buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4739 rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4740 rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4741 }
4742
4743 val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
4744 rxbd->addr_hi = cpu_to_le32(val);
4745 data->rx.bd_page_base.hi = cpu_to_le32(val);
4746
4747 val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
4748 rxbd->addr_lo = cpu_to_le32(val);
4749 data->rx.bd_page_base.lo = cpu_to_le32(val);
4750
4751 rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
4752 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
4753 rxcqe->addr_hi = cpu_to_le32(val);
4754 data->rx.cqe_page_base.hi = cpu_to_le32(val);
4755
4756 val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
4757 rxcqe->addr_lo = cpu_to_le32(val);
4758 data->rx.cqe_page_base.lo = cpu_to_le32(val);
4759
4760 /* Other ramrod params */
4761 data->rx.client_qzone_id = cl_qzone_id;
4762 data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
4763 data->rx.status_block_id = BNX2X_DEF_SB_ID;
4764
4765 data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
4766
4767 data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
4768 data->rx.outer_vlan_removal_enable_flg = 1;
4769 data->rx.silent_vlan_removal_flg = 1;
4770 data->rx.silent_vlan_value = 0;
4771 data->rx.silent_vlan_mask = 0xffff;
4772
4773 cp->rx_cons_ptr =
4774 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
4775 cp->rx_cons = *cp->rx_cons_ptr;
4776 }
4777
4778 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
4779 {
4780 struct cnic_local *cp = dev->cnic_priv;
4781 u32 pfid = cp->pfid;
4782
4783 cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
4784 CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
4785 cp->kcq1.sw_prod_idx = 0;
4786
4787 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
4788 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4789
4790 cp->kcq1.hw_prod_idx_ptr =
4791 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4792 cp->kcq1.status_idx_ptr =
4793 &sb->sb.running_index[SM_RX_ID];
4794 } else {
4795 struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
4796
4797 cp->kcq1.hw_prod_idx_ptr =
4798 &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
4799 cp->kcq1.status_idx_ptr =
4800 &sb->sb.running_index[SM_RX_ID];
4801 }
4802
4803 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
4804 struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
4805
4806 cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
4807 USTORM_FCOE_EQ_PROD_OFFSET(pfid);
4808 cp->kcq2.sw_prod_idx = 0;
4809 cp->kcq2.hw_prod_idx_ptr =
4810 &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
4811 cp->kcq2.status_idx_ptr =
4812 &sb->sb.running_index[SM_RX_ID];
4813 }
4814 }
4815
4816 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4817 {
4818 struct cnic_local *cp = dev->cnic_priv;
4819 struct cnic_eth_dev *ethdev = cp->ethdev;
4820 int func = CNIC_FUNC(cp), ret;
4821 u32 pfid;
4822
4823 cp->port_mode = CHIP_PORT_MODE_NONE;
4824
4825 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
4826 u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
4827
4828 if (!(val & 1))
4829 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
4830 else
4831 val = (val >> 1) & 1;
4832
4833 if (val) {
4834 cp->port_mode = CHIP_4_PORT_MODE;
4835 cp->pfid = func >> 1;
4836 } else {
4837 cp->port_mode = CHIP_2_PORT_MODE;
4838 cp->pfid = func & 0x6;
4839 }
4840 } else {
4841 cp->pfid = func;
4842 }
4843 pfid = cp->pfid;
4844
4845 ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
4846 cp->iscsi_start_cid, 0);
4847
4848 if (ret)
4849 return -ENOMEM;
4850
4851 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
4852 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
4853 BNX2X_FCOE_NUM_CONNECTIONS,
4854 cp->fcoe_start_cid, 0);
4855
4856 if (ret)
4857 return -ENOMEM;
4858 }
4859
4860 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4861
4862 cnic_init_bnx2x_kcq(dev);
4863
4864 /* Only 1 EQ */
4865 CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
4866 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4867 CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
4868 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4869 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
4870 cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
4871 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4872 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
4873 (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
4874 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4875 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
4876 cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
4877 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
4878 CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
4879 (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
4880 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4881 CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
4882 CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
4883 CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
4884 CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4885 CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
4886 HC_INDEX_ISCSI_EQ_CONS);
4887
4888 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4889 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
4890 cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
4891 CNIC_WR(dev, BAR_USTRORM_INTMEM +
4892 USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
4893 (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
4894
4895 CNIC_WR(dev, BAR_TSTRORM_INTMEM +
4896 TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
4897
4898 cnic_setup_bnx2x_context(dev);
4899
4900 ret = cnic_init_bnx2x_irq(dev);
4901 if (ret)
4902 return ret;
4903
4904 return 0;
4905 }
4906
4907 static void cnic_init_rings(struct cnic_dev *dev)
4908 {
4909 struct cnic_local *cp = dev->cnic_priv;
4910 struct cnic_uio_dev *udev = cp->udev;
4911
4912 if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4913 return;
4914
4915 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4916 cnic_init_bnx2_tx_ring(dev);
4917 cnic_init_bnx2_rx_ring(dev);
4918 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4919 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4920 u32 cli = cp->ethdev->iscsi_l2_client_id;
4921 u32 cid = cp->ethdev->iscsi_l2_cid;
4922 u32 cl_qzone_id;
4923 struct client_init_ramrod_data *data;
4924 union l5cm_specific_data l5_data;
4925 struct ustorm_eth_rx_producers rx_prods = {0};
4926 u32 off, i, *cid_ptr;
4927
4928 rx_prods.bd_prod = 0;
4929 rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
4930 barrier();
4931
4932 cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
4933
4934 off = BAR_USTRORM_INTMEM +
4935 (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
4936 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
4937 USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
4938
4939 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
4940 CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
4941
4942 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4943
4944 data = udev->l2_buf;
4945 cid_ptr = udev->l2_buf + 12;
4946
4947 memset(data, 0, sizeof(*data));
4948
4949 cnic_init_bnx2x_tx_ring(dev, data);
4950 cnic_init_bnx2x_rx_ring(dev, data);
4951
4952 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
4953 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
4954
4955 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
4956
4957 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4958 cid, ETH_CONNECTION_TYPE, &l5_data);
4959
4960 i = 0;
4961 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
4962 ++i < 10)
4963 msleep(1);
4964
4965 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
4966 netdev_err(dev->netdev,
4967 "iSCSI CLIENT_SETUP did not complete\n");
4968 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
4969 cnic_ring_ctl(dev, cid, cli, 1);
4970 *cid_ptr = cid;
4971 }
4972 }
4973
4974 static void cnic_shutdown_rings(struct cnic_dev *dev)
4975 {
4976 struct cnic_local *cp = dev->cnic_priv;
4977 struct cnic_uio_dev *udev = cp->udev;
4978 void *rx_ring;
4979
4980 if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
4981 return;
4982
4983 if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
4984 cnic_shutdown_bnx2_rx_ring(dev);
4985 } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
4986 u32 cli = cp->ethdev->iscsi_l2_client_id;
4987 u32 cid = cp->ethdev->iscsi_l2_cid;
4988 union l5cm_specific_data l5_data;
4989 int i;
4990
4991 cnic_ring_ctl(dev, cid, cli, 0);
4992
4993 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
4994
4995 l5_data.phy_address.lo = cli;
4996 l5_data.phy_address.hi = 0;
4997 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
4998 cid, ETH_CONNECTION_TYPE, &l5_data);
4999 i = 0;
5000 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5001 ++i < 10)
5002 msleep(1);
5003
5004 if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5005 netdev_err(dev->netdev,
5006 "iSCSI CLIENT_HALT did not complete\n");
5007 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5008
5009 memset(&l5_data, 0, sizeof(l5_data));
5010 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
5011 cid, NONE_CONNECTION_TYPE, &l5_data);
5012 msleep(10);
5013 }
5014 clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5015 rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
5016 memset(rx_ring, 0, BCM_PAGE_SIZE);
5017 }
5018
5019 static int cnic_register_netdev(struct cnic_dev *dev)
5020 {
5021 struct cnic_local *cp = dev->cnic_priv;
5022 struct cnic_eth_dev *ethdev = cp->ethdev;
5023 int err;
5024
5025 if (!ethdev)
5026 return -ENODEV;
5027
5028 if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
5029 return 0;
5030
5031 err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
5032 if (err)
5033 netdev_err(dev->netdev, "register_cnic failed\n");
5034
5035 return err;
5036 }
5037
5038 static void cnic_unregister_netdev(struct cnic_dev *dev)
5039 {
5040 struct cnic_local *cp = dev->cnic_priv;
5041 struct cnic_eth_dev *ethdev = cp->ethdev;
5042
5043 if (!ethdev)
5044 return;
5045
5046 ethdev->drv_unregister_cnic(dev->netdev);
5047 }
5048
5049 static int cnic_start_hw(struct cnic_dev *dev)
5050 {
5051 struct cnic_local *cp = dev->cnic_priv;
5052 struct cnic_eth_dev *ethdev = cp->ethdev;
5053 int err;
5054
5055 if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5056 return -EALREADY;
5057
5058 dev->regview = ethdev->io_base;
5059 pci_dev_get(dev->pcidev);
5060 cp->func = PCI_FUNC(dev->pcidev->devfn);
5061 cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5062 cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5063
5064 err = cp->alloc_resc(dev);
5065 if (err) {
5066 netdev_err(dev->netdev, "allocate resource failure\n");
5067 goto err1;
5068 }
5069
5070 err = cp->start_hw(dev);
5071 if (err)
5072 goto err1;
5073
5074 err = cnic_cm_open(dev);
5075 if (err)
5076 goto err1;
5077
5078 set_bit(CNIC_F_CNIC_UP, &dev->flags);
5079
5080 cp->enable_int(dev);
5081
5082 return 0;
5083
5084 err1:
5085 cp->free_resc(dev);
5086 pci_dev_put(dev->pcidev);
5087 return err;
5088 }
5089
5090 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5091 {
5092 cnic_disable_bnx2_int_sync(dev);
5093
5094 cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5095 cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5096
5097 cnic_init_context(dev, KWQ_CID);
5098 cnic_init_context(dev, KCQ_CID);
5099
5100 cnic_setup_5709_context(dev, 0);
5101 cnic_free_irq(dev);
5102
5103 cnic_free_resc(dev);
5104 }
5105
5106
5107 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5108 {
5109 struct cnic_local *cp = dev->cnic_priv;
5110
5111 cnic_free_irq(dev);
5112 *cp->kcq1.hw_prod_idx_ptr = 0;
5113 CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5114 CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
5115 CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5116 cnic_free_resc(dev);
5117 }
5118
5119 static void cnic_stop_hw(struct cnic_dev *dev)
5120 {
5121 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5122 struct cnic_local *cp = dev->cnic_priv;
5123 int i = 0;
5124
5125 /* Need to wait for the ring shutdown event to complete
5126 * before clearing the CNIC_UP flag.
5127 */
5128 while (cp->udev->uio_dev != -1 && i < 15) {
5129 msleep(100);
5130 i++;
5131 }
5132 cnic_shutdown_rings(dev);
5133 clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5134 rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
5135 synchronize_rcu();
5136 cnic_cm_shutdown(dev);
5137 cp->stop_hw(dev);
5138 pci_dev_put(dev->pcidev);
5139 }
5140 }
5141
5142 static void cnic_free_dev(struct cnic_dev *dev)
5143 {
5144 int i = 0;
5145
5146 while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5147 msleep(100);
5148 i++;
5149 }
5150 if (atomic_read(&dev->ref_count) != 0)
5151 netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5152
5153 netdev_info(dev->netdev, "Removed CNIC device\n");
5154 dev_put(dev->netdev);
5155 kfree(dev);
5156 }
5157
5158 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5159 struct pci_dev *pdev)
5160 {
5161 struct cnic_dev *cdev;
5162 struct cnic_local *cp;
5163 int alloc_size;
5164
5165 alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5166
5167 cdev = kzalloc(alloc_size , GFP_KERNEL);
5168 if (cdev == NULL) {
5169 netdev_err(dev, "allocate dev struct failure\n");
5170 return NULL;
5171 }
5172
5173 cdev->netdev = dev;
5174 cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5175 cdev->register_device = cnic_register_device;
5176 cdev->unregister_device = cnic_unregister_device;
5177 cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5178
5179 cp = cdev->cnic_priv;
5180 cp->dev = cdev;
5181 cp->l2_single_buf_size = 0x400;
5182 cp->l2_rx_ring_size = 3;
5183
5184 spin_lock_init(&cp->cnic_ulp_lock);
5185
5186 netdev_info(dev, "Added CNIC device\n");
5187
5188 return cdev;
5189 }
5190
5191 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5192 {
5193 struct pci_dev *pdev;
5194 struct cnic_dev *cdev;
5195 struct cnic_local *cp;
5196 struct cnic_eth_dev *ethdev = NULL;
5197 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5198
5199 probe = symbol_get(bnx2_cnic_probe);
5200 if (probe) {
5201 ethdev = (*probe)(dev);
5202 symbol_put(bnx2_cnic_probe);
5203 }
5204 if (!ethdev)
5205 return NULL;
5206
5207 pdev = ethdev->pdev;
5208 if (!pdev)
5209 return NULL;
5210
5211 dev_hold(dev);
5212 pci_dev_get(pdev);
5213 if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5214 pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
5215 (pdev->revision < 0x10)) {
5216 pci_dev_put(pdev);
5217 goto cnic_err;
5218 }
5219 pci_dev_put(pdev);
5220
5221 cdev = cnic_alloc_dev(dev, pdev);
5222 if (cdev == NULL)
5223 goto cnic_err;
5224
5225 set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5226 cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5227
5228 cp = cdev->cnic_priv;
5229 cp->ethdev = ethdev;
5230 cdev->pcidev = pdev;
5231 cp->chip_id = ethdev->chip_id;
5232
5233 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5234
5235 cp->cnic_ops = &cnic_bnx2_ops;
5236 cp->start_hw = cnic_start_bnx2_hw;
5237 cp->stop_hw = cnic_stop_bnx2_hw;
5238 cp->setup_pgtbl = cnic_setup_page_tbl;
5239 cp->alloc_resc = cnic_alloc_bnx2_resc;
5240 cp->free_resc = cnic_free_resc;
5241 cp->start_cm = cnic_cm_init_bnx2_hw;
5242 cp->stop_cm = cnic_cm_stop_bnx2_hw;
5243 cp->enable_int = cnic_enable_bnx2_int;
5244 cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5245 cp->close_conn = cnic_close_bnx2_conn;
5246 return cdev;
5247
5248 cnic_err:
5249 dev_put(dev);
5250 return NULL;
5251 }
5252
5253 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5254 {
5255 struct pci_dev *pdev;
5256 struct cnic_dev *cdev;
5257 struct cnic_local *cp;
5258 struct cnic_eth_dev *ethdev = NULL;
5259 struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
5260
5261 probe = symbol_get(bnx2x_cnic_probe);
5262 if (probe) {
5263 ethdev = (*probe)(dev);
5264 symbol_put(bnx2x_cnic_probe);
5265 }
5266 if (!ethdev)
5267 return NULL;
5268
5269 pdev = ethdev->pdev;
5270 if (!pdev)
5271 return NULL;
5272
5273 dev_hold(dev);
5274 cdev = cnic_alloc_dev(dev, pdev);
5275 if (cdev == NULL) {
5276 dev_put(dev);
5277 return NULL;
5278 }
5279
5280 set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5281 cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5282
5283 cp = cdev->cnic_priv;
5284 cp->ethdev = ethdev;
5285 cdev->pcidev = pdev;
5286 cp->chip_id = ethdev->chip_id;
5287
5288 if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
5289 cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5290 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
5291 !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
5292 cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
5293
5294 memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
5295
5296 cp->cnic_ops = &cnic_bnx2x_ops;
5297 cp->start_hw = cnic_start_bnx2x_hw;
5298 cp->stop_hw = cnic_stop_bnx2x_hw;
5299 cp->setup_pgtbl = cnic_setup_page_tbl_le;
5300 cp->alloc_resc = cnic_alloc_bnx2x_resc;
5301 cp->free_resc = cnic_free_resc;
5302 cp->start_cm = cnic_cm_init_bnx2x_hw;
5303 cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5304 cp->enable_int = cnic_enable_bnx2x_int;
5305 cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5306 if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
5307 cp->ack_int = cnic_ack_bnx2x_e2_msix;
5308 else
5309 cp->ack_int = cnic_ack_bnx2x_msix;
5310 cp->close_conn = cnic_close_bnx2x_conn;
5311 return cdev;
5312 }
5313
5314 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5315 {
5316 struct ethtool_drvinfo drvinfo;
5317 struct cnic_dev *cdev = NULL;
5318
5319 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5320 memset(&drvinfo, 0, sizeof(drvinfo));
5321 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5322
5323 if (!strcmp(drvinfo.driver, "bnx2"))
5324 cdev = init_bnx2_cnic(dev);
5325 if (!strcmp(drvinfo.driver, "bnx2x"))
5326 cdev = init_bnx2x_cnic(dev);
5327 if (cdev) {
5328 write_lock(&cnic_dev_lock);
5329 list_add(&cdev->list, &cnic_dev_list);
5330 write_unlock(&cnic_dev_lock);
5331 }
5332 }
5333 return cdev;
5334 }
5335
5336 /**
5337 * netdev event handler
5338 */
5339 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5340 void *ptr)
5341 {
5342 struct net_device *netdev = ptr;
5343 struct cnic_dev *dev;
5344 int if_type;
5345 int new_dev = 0;
5346
5347 dev = cnic_from_netdev(netdev);
5348
5349 if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
5350 /* Check for the hot-plug device */
5351 dev = is_cnic_dev(netdev);
5352 if (dev) {
5353 new_dev = 1;
5354 cnic_hold(dev);
5355 }
5356 }
5357 if (dev) {
5358 struct cnic_local *cp = dev->cnic_priv;
5359
5360 if (new_dev)
5361 cnic_ulp_init(dev);
5362 else if (event == NETDEV_UNREGISTER)
5363 cnic_ulp_exit(dev);
5364
5365 if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
5366 if (cnic_register_netdev(dev) != 0) {
5367 cnic_put(dev);
5368 goto done;
5369 }
5370 if (!cnic_start_hw(dev))
5371 cnic_ulp_start(dev);
5372 }
5373
5374 rcu_read_lock();
5375 for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5376 struct cnic_ulp_ops *ulp_ops;
5377 void *ctx;
5378
5379 ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
5380 if (!ulp_ops || !ulp_ops->indicate_netevent)
5381 continue;
5382
5383 ctx = cp->ulp_handle[if_type];
5384
5385 ulp_ops->indicate_netevent(ctx, event);
5386 }
5387 rcu_read_unlock();
5388
5389 if (event == NETDEV_GOING_DOWN) {
5390 cnic_ulp_stop(dev);
5391 cnic_stop_hw(dev);
5392 cnic_unregister_netdev(dev);
5393 } else if (event == NETDEV_UNREGISTER) {
5394 write_lock(&cnic_dev_lock);
5395 list_del_init(&dev->list);
5396 write_unlock(&cnic_dev_lock);
5397
5398 cnic_put(dev);
5399 cnic_free_dev(dev);
5400 goto done;
5401 }
5402 cnic_put(dev);
5403 }
5404 done:
5405 return NOTIFY_DONE;
5406 }
5407
5408 static struct notifier_block cnic_netdev_notifier = {
5409 .notifier_call = cnic_netdev_event
5410 };
5411
5412 static void cnic_release(void)
5413 {
5414 struct cnic_dev *dev;
5415 struct cnic_uio_dev *udev;
5416
5417 while (!list_empty(&cnic_dev_list)) {
5418 dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
5419 if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5420 cnic_ulp_stop(dev);
5421 cnic_stop_hw(dev);
5422 }
5423
5424 cnic_ulp_exit(dev);
5425 cnic_unregister_netdev(dev);
5426 list_del_init(&dev->list);
5427 cnic_free_dev(dev);
5428 }
5429 while (!list_empty(&cnic_udev_list)) {
5430 udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5431 list);
5432 cnic_free_uio(udev);
5433 }
5434 }
5435
5436 static int __init cnic_init(void)
5437 {
5438 int rc = 0;
5439
5440 pr_info("%s", version);
5441
5442 rc = register_netdevice_notifier(&cnic_netdev_notifier);
5443 if (rc) {
5444 cnic_release();
5445 return rc;
5446 }
5447
5448 cnic_wq = create_singlethread_workqueue("cnic_wq");
5449 if (!cnic_wq) {
5450 cnic_release();
5451 unregister_netdevice_notifier(&cnic_netdev_notifier);
5452 return -ENOMEM;
5453 }
5454
5455 return 0;
5456 }
5457
5458 static void __exit cnic_exit(void)
5459 {
5460 unregister_netdevice_notifier(&cnic_netdev_notifier);
5461 cnic_release();
5462 destroy_workqueue(cnic_wq);
5463 }
5464
5465 module_init(cnic_init);
5466 module_exit(cnic_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree