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net: convert print_mac to %pM
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tc35815.c
blobc666448fc7e36f3af41c7e431492e05eea5d7d7a
1 /*
2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 *
4 * Based on skelton.c by Donald Becker.
5 *
6 * This driver is a replacement of older and less maintained version.
7 * This is a header of the older version:
8 * -----<snip>-----
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: MontaVista Software, Inc.
11 * ahennessy@mvista.com
12 * Copyright (C) 2000-2001 Toshiba Corporation
13 * static const char *version =
14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
15 * -----<snip>-----
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 *
21 * (C) Copyright TOSHIBA CORPORATION 2004-2005
22 * All Rights Reserved.
23 */
24
25 #ifdef TC35815_NAPI
26 #define DRV_VERSION "1.37-NAPI"
27 #else
28 #define DRV_VERSION "1.37"
29 #endif
30 static const char *version = "tc35815.c:v" DRV_VERSION "\n";
31 #define MODNAME "tc35815"
32
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/fcntl.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/in.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/spinlock.h>
43 #include <linux/errno.h>
44 #include <linux/init.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/delay.h>
49 #include <linux/pci.h>
50 #include <linux/phy.h>
51 #include <linux/workqueue.h>
52 #include <linux/platform_device.h>
53 #include <asm/io.h>
54 #include <asm/byteorder.h>
55
56 /* First, a few definitions that the brave might change. */
57
58 #define GATHER_TXINT /* On-Demand Tx Interrupt */
59 #define WORKAROUND_LOSTCAR
60 #define WORKAROUND_100HALF_PROMISC
61 /* #define TC35815_USE_PACKEDBUFFER */
62
63 enum tc35815_chiptype {
64 TC35815CF = 0,
65 TC35815_NWU,
66 TC35815_TX4939,
67 };
68
69 /* indexed by tc35815_chiptype, above */
70 static const struct {
71 const char *name;
72 } chip_info[] __devinitdata = {
73 { "TOSHIBA TC35815CF 10/100BaseTX" },
74 { "TOSHIBA TC35815 with Wake on LAN" },
75 { "TOSHIBA TC35815/TX4939" },
76 };
77
78 static const struct pci_device_id tc35815_pci_tbl[] = {
79 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
80 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
81 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
82 {0,}
83 };
84 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
85
86 /* see MODULE_PARM_DESC */
87 static struct tc35815_options {
88 int speed;
89 int duplex;
90 } options;
91
92 /*
93 * Registers
94 */
95 struct tc35815_regs {
96 __u32 DMA_Ctl; /* 0x00 */
97 __u32 TxFrmPtr;
98 __u32 TxThrsh;
99 __u32 TxPollCtr;
100 __u32 BLFrmPtr;
101 __u32 RxFragSize;
102 __u32 Int_En;
103 __u32 FDA_Bas;
104 __u32 FDA_Lim; /* 0x20 */
105 __u32 Int_Src;
106 __u32 unused0[2];
107 __u32 PauseCnt;
108 __u32 RemPauCnt;
109 __u32 TxCtlFrmStat;
110 __u32 unused1;
111 __u32 MAC_Ctl; /* 0x40 */
112 __u32 CAM_Ctl;
113 __u32 Tx_Ctl;
114 __u32 Tx_Stat;
115 __u32 Rx_Ctl;
116 __u32 Rx_Stat;
117 __u32 MD_Data;
118 __u32 MD_CA;
119 __u32 CAM_Adr; /* 0x60 */
120 __u32 CAM_Data;
121 __u32 CAM_Ena;
122 __u32 PROM_Ctl;
123 __u32 PROM_Data;
124 __u32 Algn_Cnt;
125 __u32 CRC_Cnt;
126 __u32 Miss_Cnt;
127 };
128
129 /*
130 * Bit assignments
131 */
132 /* DMA_Ctl bit asign ------------------------------------------------------- */
133 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */
134 #define DMA_RxAlign_1 0x00400000
135 #define DMA_RxAlign_2 0x00800000
136 #define DMA_RxAlign_3 0x00c00000
137 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */
138 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
139 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
140 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
141 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
142 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
143 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
144 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
145 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
146
147 /* RxFragSize bit asign ---------------------------------------------------- */
148 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
149 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
150
151 /* MAC_Ctl bit asign ------------------------------------------------------- */
152 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
153 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
154 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
155 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
156 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
157 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
158 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
159 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
160 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
161 #define MAC_Reset 0x00000004 /* 1:Software Reset */
162 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
163 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
164
165 /* PROM_Ctl bit asign ------------------------------------------------------ */
166 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
167 #define PROM_Read 0x00004000 /*10:Read operation */
168 #define PROM_Write 0x00002000 /*01:Write operation */
169 #define PROM_Erase 0x00006000 /*11:Erase operation */
170 /*00:Enable or Disable Writting, */
171 /* as specified in PROM_Addr. */
172 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
173 /*00xxxx: disable */
174
175 /* CAM_Ctl bit asign ------------------------------------------------------- */
176 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
177 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
178 /* accept other */
179 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
180 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
181 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
182
183 /* CAM_Ena bit asign ------------------------------------------------------- */
184 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
185 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
186 #define CAM_Ena_Bit(index) (1 << (index))
187 #define CAM_ENTRY_DESTINATION 0
188 #define CAM_ENTRY_SOURCE 1
189 #define CAM_ENTRY_MACCTL 20
190
191 /* Tx_Ctl bit asign -------------------------------------------------------- */
192 #define Tx_En 0x00000001 /* 1:Transmit enable */
193 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
194 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
195 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
196 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
197 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
198 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
199 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
200 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
201 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
202 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
203 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
204
205 /* Tx_Stat bit asign ------------------------------------------------------- */
206 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
207 #define Tx_ExColl 0x00000010 /* Excessive Collision */
208 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
209 #define Tx_Paused 0x00000040 /* Transmit Paused */
210 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
211 #define Tx_Under 0x00000100 /* Underrun */
212 #define Tx_Defer 0x00000200 /* Deferral */
213 #define Tx_NCarr 0x00000400 /* No Carrier */
214 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
215 #define Tx_LateColl 0x00001000 /* Late Collision */
216 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
217 #define Tx_Comp 0x00004000 /* Completion */
218 #define Tx_Halted 0x00008000 /* Tx Halted */
219 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
220
221 /* Rx_Ctl bit asign -------------------------------------------------------- */
222 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
223 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
224 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
225 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
226 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
227 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
228 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
229 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
230 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
231 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
232 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
233 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
234
235 /* Rx_Stat bit asign ------------------------------------------------------- */
236 #define Rx_Halted 0x00008000 /* Rx Halted */
237 #define Rx_Good 0x00004000 /* Rx Good */
238 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
239 /* 0x00001000 not use */
240 #define Rx_LongErr 0x00000800 /* Rx Long Error */
241 #define Rx_Over 0x00000400 /* Rx Overflow */
242 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
243 #define Rx_Align 0x00000100 /* Rx Alignment Error */
244 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
245 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
246 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
247
248 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
249
250 /* Int_En bit asign -------------------------------------------------------- */
251 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
252 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */
253 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
254 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
255 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
256 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
257 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
258 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
259 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
260 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
261 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
262 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
263 /* Exhausted Enable */
264
265 /* Int_Src bit asign ------------------------------------------------------- */
266 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
267 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
268 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
269 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
270 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
271 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
272 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
273 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
274 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
275 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
276 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
277 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
278 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
279 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
280 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
281
282 /* MD_CA bit asign --------------------------------------------------------- */
283 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
284 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
285 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
286
287
288 /*
289 * Descriptors
290 */
291
292 /* Frame descripter */
293 struct FDesc {
294 volatile __u32 FDNext;
295 volatile __u32 FDSystem;
296 volatile __u32 FDStat;
297 volatile __u32 FDCtl;
298 };
299
300 /* Buffer descripter */
301 struct BDesc {
302 volatile __u32 BuffData;
303 volatile __u32 BDCtl;
304 };
305
306 #define FD_ALIGN 16
307
308 /* Frame Descripter bit asign ---------------------------------------------- */
309 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
310 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
311 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
312 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
313 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
314 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
315 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
316 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
317 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
318 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
319 #define FD_BDCnt_SHIFT 16
320
321 /* Buffer Descripter bit asign --------------------------------------------- */
322 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
323 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
324 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
325 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
326 #define BD_RxBDID_SHIFT 16
327 #define BD_RxBDSeqN_SHIFT 24
328
329
330 /* Some useful constants. */
331 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
332
333 #ifdef NO_CHECK_CARRIER
334 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
335 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
336 Tx_En) /* maybe 0x7b01 */
337 #else
338 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
339 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
340 Tx_En) /* maybe 0x7b01 */
341 #endif
342 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
343 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
344 #define INT_EN_CMD (Int_NRAbtEn | \
345 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
346 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
347 Int_STargAbtEn | \
348 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
349 #define DMA_CTL_CMD DMA_BURST_SIZE
350 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF)
351
352 /* Tuning parameters */
353 #define DMA_BURST_SIZE 32
354 #define TX_THRESHOLD 1024
355 /* used threshold with packet max byte for low pci transfer ability.*/
356 #define TX_THRESHOLD_MAX 1536
357 /* setting threshold max value when overrun error occured this count. */
358 #define TX_THRESHOLD_KEEP_LIMIT 10
359
360 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
361 #ifdef TC35815_USE_PACKEDBUFFER
362 #define FD_PAGE_NUM 2
363 #define RX_BUF_NUM 8 /* >= 2 */
364 #define RX_FD_NUM 250 /* >= 32 */
365 #define TX_FD_NUM 128
366 #define RX_BUF_SIZE PAGE_SIZE
367 #else /* TC35815_USE_PACKEDBUFFER */
368 #define FD_PAGE_NUM 4
369 #define RX_BUF_NUM 128 /* < 256 */
370 #define RX_FD_NUM 256 /* >= 32 */
371 #define TX_FD_NUM 128
372 #if RX_CTL_CMD & Rx_LongEn
373 #define RX_BUF_SIZE PAGE_SIZE
374 #elif RX_CTL_CMD & Rx_StripCRC
375 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 4 + 2, 32) /* +2: reserve */
376 #else
377 #define RX_BUF_SIZE ALIGN(ETH_FRAME_LEN + 2, 32) /* +2: reserve */
378 #endif
379 #endif /* TC35815_USE_PACKEDBUFFER */
380 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */
381 #define NAPI_WEIGHT 16
382
383 struct TxFD {
384 struct FDesc fd;
385 struct BDesc bd;
386 struct BDesc unused;
387 };
388
389 struct RxFD {
390 struct FDesc fd;
391 struct BDesc bd[0]; /* variable length */
392 };
393
394 struct FrFD {
395 struct FDesc fd;
396 struct BDesc bd[RX_BUF_NUM];
397 };
398
399
400 #define tc_readl(addr) ioread32(addr)
401 #define tc_writel(d, addr) iowrite32(d, addr)
402
403 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400)
404
405 /* Information that need to be kept for each controller. */
406 struct tc35815_local {
407 struct pci_dev *pci_dev;
408
409 struct net_device *dev;
410 struct napi_struct napi;
411
412 /* statistics */
413 struct {
414 int max_tx_qlen;
415 int tx_ints;
416 int rx_ints;
417 int tx_underrun;
418 } lstats;
419
420 /* Tx control lock. This protects the transmit buffer ring
421 * state along with the "tx full" state of the driver. This
422 * means all netif_queue flow control actions are protected
423 * by this lock as well.
424 */
425 spinlock_t lock;
426
427 struct mii_bus *mii_bus;
428 struct phy_device *phy_dev;
429 int duplex;
430 int speed;
431 int link;
432 struct work_struct restart_work;
433
434 /*
435 * Transmitting: Batch Mode.
436 * 1 BD in 1 TxFD.
437 * Receiving: Packing Mode. (TC35815_USE_PACKEDBUFFER)
438 * 1 circular FD for Free Buffer List.
439 * RX_BUF_NUM BD in Free Buffer FD.
440 * One Free Buffer BD has PAGE_SIZE data buffer.
441 * Or Non-Packing Mode.
442 * 1 circular FD for Free Buffer List.
443 * RX_BUF_NUM BD in Free Buffer FD.
444 * One Free Buffer BD has ETH_FRAME_LEN data buffer.
445 */
446 void *fd_buf; /* for TxFD, RxFD, FrFD */
447 dma_addr_t fd_buf_dma;
448 struct TxFD *tfd_base;
449 unsigned int tfd_start;
450 unsigned int tfd_end;
451 struct RxFD *rfd_base;
452 struct RxFD *rfd_limit;
453 struct RxFD *rfd_cur;
454 struct FrFD *fbl_ptr;
455 #ifdef TC35815_USE_PACKEDBUFFER
456 unsigned char fbl_curid;
457 void *data_buf[RX_BUF_NUM]; /* packing */
458 dma_addr_t data_buf_dma[RX_BUF_NUM];
459 struct {
460 struct sk_buff *skb;
461 dma_addr_t skb_dma;
462 } tx_skbs[TX_FD_NUM];
463 #else
464 unsigned int fbl_count;
465 struct {
466 struct sk_buff *skb;
467 dma_addr_t skb_dma;
468 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
469 #endif
470 u32 msg_enable;
471 enum tc35815_chiptype chiptype;
472 };
473
474 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
475 {
476 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
477 }
478 #ifdef DEBUG
479 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
480 {
481 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
482 }
483 #endif
484 #ifdef TC35815_USE_PACKEDBUFFER
485 static inline void *rxbuf_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
486 {
487 int i;
488 for (i = 0; i < RX_BUF_NUM; i++) {
489 if (bus >= lp->data_buf_dma[i] &&
490 bus < lp->data_buf_dma[i] + PAGE_SIZE)
491 return (void *)((u8 *)lp->data_buf[i] +
492 (bus - lp->data_buf_dma[i]));
493 }
494 return NULL;
495 }
496
497 #define TC35815_DMA_SYNC_ONDEMAND
498 static void *alloc_rxbuf_page(struct pci_dev *hwdev, dma_addr_t *dma_handle)
499 {
500 #ifdef TC35815_DMA_SYNC_ONDEMAND
501 void *buf;
502 /* pci_map + pci_dma_sync will be more effective than
503 * pci_alloc_consistent on some archs. */
504 buf = (void *)__get_free_page(GFP_ATOMIC);
505 if (!buf)
506 return NULL;
507 *dma_handle = pci_map_single(hwdev, buf, PAGE_SIZE,
508 PCI_DMA_FROMDEVICE);
509 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
510 free_page((unsigned long)buf);
511 return NULL;
512 }
513 return buf;
514 #else
515 return pci_alloc_consistent(hwdev, PAGE_SIZE, dma_handle);
516 #endif
517 }
518
519 static void free_rxbuf_page(struct pci_dev *hwdev, void *buf, dma_addr_t dma_handle)
520 {
521 #ifdef TC35815_DMA_SYNC_ONDEMAND
522 pci_unmap_single(hwdev, dma_handle, PAGE_SIZE, PCI_DMA_FROMDEVICE);
523 free_page((unsigned long)buf);
524 #else
525 pci_free_consistent(hwdev, PAGE_SIZE, buf, dma_handle);
526 #endif
527 }
528 #else /* TC35815_USE_PACKEDBUFFER */
529 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
530 struct pci_dev *hwdev,
531 dma_addr_t *dma_handle)
532 {
533 struct sk_buff *skb;
534 skb = dev_alloc_skb(RX_BUF_SIZE);
535 if (!skb)
536 return NULL;
537 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
538 PCI_DMA_FROMDEVICE);
539 if (pci_dma_mapping_error(hwdev, *dma_handle)) {
540 dev_kfree_skb_any(skb);
541 return NULL;
542 }
543 skb_reserve(skb, 2); /* make IP header 4byte aligned */
544 return skb;
545 }
546
547 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
548 {
549 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
550 PCI_DMA_FROMDEVICE);
551 dev_kfree_skb_any(skb);
552 }
553 #endif /* TC35815_USE_PACKEDBUFFER */
554
555 /* Index to functions, as function prototypes. */
556
557 static int tc35815_open(struct net_device *dev);
558 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
559 static irqreturn_t tc35815_interrupt(int irq, void *dev_id);
560 #ifdef TC35815_NAPI
561 static int tc35815_rx(struct net_device *dev, int limit);
562 static int tc35815_poll(struct napi_struct *napi, int budget);
563 #else
564 static void tc35815_rx(struct net_device *dev);
565 #endif
566 static void tc35815_txdone(struct net_device *dev);
567 static int tc35815_close(struct net_device *dev);
568 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
569 static void tc35815_set_multicast_list(struct net_device *dev);
570 static void tc35815_tx_timeout(struct net_device *dev);
571 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
572 #ifdef CONFIG_NET_POLL_CONTROLLER
573 static void tc35815_poll_controller(struct net_device *dev);
574 #endif
575 static const struct ethtool_ops tc35815_ethtool_ops;
576
577 /* Example routines you must write ;->. */
578 static void tc35815_chip_reset(struct net_device *dev);
579 static void tc35815_chip_init(struct net_device *dev);
580
581 #ifdef DEBUG
582 static void panic_queues(struct net_device *dev);
583 #endif
584
585 static void tc35815_restart_work(struct work_struct *work);
586
587 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
588 {
589 struct net_device *dev = bus->priv;
590 struct tc35815_regs __iomem *tr =
591 (struct tc35815_regs __iomem *)dev->base_addr;
592 unsigned long timeout = jiffies + 10;
593
594 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
595 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
596 if (time_after(jiffies, timeout))
597 return -EIO;
598 cpu_relax();
599 }
600 return tc_readl(&tr->MD_Data) & 0xffff;
601 }
602
603 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
604 {
605 struct net_device *dev = bus->priv;
606 struct tc35815_regs __iomem *tr =
607 (struct tc35815_regs __iomem *)dev->base_addr;
608 unsigned long timeout = jiffies + 10;
609
610 tc_writel(val, &tr->MD_Data);
611 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
612 &tr->MD_CA);
613 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
614 if (time_after(jiffies, timeout))
615 return -EIO;
616 cpu_relax();
617 }
618 return 0;
619 }
620
621 static void tc_handle_link_change(struct net_device *dev)
622 {
623 struct tc35815_local *lp = netdev_priv(dev);
624 struct phy_device *phydev = lp->phy_dev;
625 unsigned long flags;
626 int status_change = 0;
627
628 spin_lock_irqsave(&lp->lock, flags);
629 if (phydev->link &&
630 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
631 struct tc35815_regs __iomem *tr =
632 (struct tc35815_regs __iomem *)dev->base_addr;
633 u32 reg;
634
635 reg = tc_readl(&tr->MAC_Ctl);
636 reg |= MAC_HaltReq;
637 tc_writel(reg, &tr->MAC_Ctl);
638 if (phydev->duplex == DUPLEX_FULL)
639 reg |= MAC_FullDup;
640 else
641 reg &= ~MAC_FullDup;
642 tc_writel(reg, &tr->MAC_Ctl);
643 reg &= ~MAC_HaltReq;
644 tc_writel(reg, &tr->MAC_Ctl);
645
646 /*
647 * TX4939 PCFG.SPEEDn bit will be changed on
648 * NETDEV_CHANGE event.
649 */
650
651 #if !defined(NO_CHECK_CARRIER) && defined(WORKAROUND_LOSTCAR)
652 /*
653 * WORKAROUND: enable LostCrS only if half duplex
654 * operation.
655 * (TX4939 does not have EnLCarr)
656 */
657 if (phydev->duplex == DUPLEX_HALF &&
658 lp->chiptype != TC35815_TX4939)
659 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
660 &tr->Tx_Ctl);
661 #endif
662
663 lp->speed = phydev->speed;
664 lp->duplex = phydev->duplex;
665 status_change = 1;
666 }
667
668 if (phydev->link != lp->link) {
669 if (phydev->link) {
670 #ifdef WORKAROUND_100HALF_PROMISC
671 /* delayed promiscuous enabling */
672 if (dev->flags & IFF_PROMISC)
673 tc35815_set_multicast_list(dev);
674 #endif
675 } else {
676 lp->speed = 0;
677 lp->duplex = -1;
678 }
679 lp->link = phydev->link;
680
681 status_change = 1;
682 }
683 spin_unlock_irqrestore(&lp->lock, flags);
684
685 if (status_change && netif_msg_link(lp)) {
686 phy_print_status(phydev);
687 #ifdef DEBUG
688 printk(KERN_DEBUG
689 "%s: MII BMCR %04x BMSR %04x LPA %04x\n",
690 dev->name,
691 phy_read(phydev, MII_BMCR),
692 phy_read(phydev, MII_BMSR),
693 phy_read(phydev, MII_LPA));
694 #endif
695 }
696 }
697
698 static int tc_mii_probe(struct net_device *dev)
699 {
700 struct tc35815_local *lp = netdev_priv(dev);
701 struct phy_device *phydev = NULL;
702 int phy_addr;
703 u32 dropmask;
704
705 /* find the first phy */
706 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
707 if (lp->mii_bus->phy_map[phy_addr]) {
708 if (phydev) {
709 printk(KERN_ERR "%s: multiple PHYs found\n",
710 dev->name);
711 return -EINVAL;
712 }
713 phydev = lp->mii_bus->phy_map[phy_addr];
714 break;
715 }
716 }
717
718 if (!phydev) {
719 printk(KERN_ERR "%s: no PHY found\n", dev->name);
720 return -ENODEV;
721 }
722
723 /* attach the mac to the phy */
724 phydev = phy_connect(dev, phydev->dev.bus_id,
725 &tc_handle_link_change, 0,
726 lp->chiptype == TC35815_TX4939 ?
727 PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
728 if (IS_ERR(phydev)) {
729 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
730 return PTR_ERR(phydev);
731 }
732 printk(KERN_INFO "%s: attached PHY driver [%s] "
733 "(mii_bus:phy_addr=%s, id=%x)\n",
734 dev->name, phydev->drv->name, phydev->dev.bus_id,
735 phydev->phy_id);
736
737 /* mask with MAC supported features */
738 phydev->supported &= PHY_BASIC_FEATURES;
739 dropmask = 0;
740 if (options.speed == 10)
741 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
742 else if (options.speed == 100)
743 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
744 if (options.duplex == 1)
745 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
746 else if (options.duplex == 2)
747 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
748 phydev->supported &= ~dropmask;
749 phydev->advertising = phydev->supported;
750
751 lp->link = 0;
752 lp->speed = 0;
753 lp->duplex = -1;
754 lp->phy_dev = phydev;
755
756 return 0;
757 }
758
759 static int tc_mii_init(struct net_device *dev)
760 {
761 struct tc35815_local *lp = netdev_priv(dev);
762 int err;
763 int i;
764
765 lp->mii_bus = mdiobus_alloc();
766 if (lp->mii_bus == NULL) {
767 err = -ENOMEM;
768 goto err_out;
769 }
770
771 lp->mii_bus->name = "tc35815_mii_bus";
772 lp->mii_bus->read = tc_mdio_read;
773 lp->mii_bus->write = tc_mdio_write;
774 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
775 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
776 lp->mii_bus->priv = dev;
777 lp->mii_bus->parent = &lp->pci_dev->dev;
778 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
779 if (!lp->mii_bus->irq) {
780 err = -ENOMEM;
781 goto err_out_free_mii_bus;
782 }
783
784 for (i = 0; i < PHY_MAX_ADDR; i++)
785 lp->mii_bus->irq[i] = PHY_POLL;
786
787 err = mdiobus_register(lp->mii_bus);
788 if (err)
789 goto err_out_free_mdio_irq;
790 err = tc_mii_probe(dev);
791 if (err)
792 goto err_out_unregister_bus;
793 return 0;
794
795 err_out_unregister_bus:
796 mdiobus_unregister(lp->mii_bus);
797 err_out_free_mdio_irq:
798 kfree(lp->mii_bus->irq);
799 err_out_free_mii_bus:
800 mdiobus_free(lp->mii_bus);
801 err_out:
802 return err;
803 }
804
805 #ifdef CONFIG_CPU_TX49XX
806 /*
807 * Find a platform_device providing a MAC address. The platform code
808 * should provide a "tc35815-mac" device with a MAC address in its
809 * platform_data.
810 */
811 static int __devinit tc35815_mac_match(struct device *dev, void *data)
812 {
813 struct platform_device *plat_dev = to_platform_device(dev);
814 struct pci_dev *pci_dev = data;
815 unsigned int id = pci_dev->irq;
816 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
817 }
818
819 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
820 {
821 struct tc35815_local *lp = netdev_priv(dev);
822 struct device *pd = bus_find_device(&platform_bus_type, NULL,
823 lp->pci_dev, tc35815_mac_match);
824 if (pd) {
825 if (pd->platform_data)
826 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
827 put_device(pd);
828 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
829 }
830 return -ENODEV;
831 }
832 #else
833 static int __devinit tc35815_read_plat_dev_addr(struct net_device *dev)
834 {
835 return -ENODEV;
836 }
837 #endif
838
839 static int __devinit tc35815_init_dev_addr(struct net_device *dev)
840 {
841 struct tc35815_regs __iomem *tr =
842 (struct tc35815_regs __iomem *)dev->base_addr;
843 int i;
844
845 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
846 ;
847 for (i = 0; i < 6; i += 2) {
848 unsigned short data;
849 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
850 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
851 ;
852 data = tc_readl(&tr->PROM_Data);
853 dev->dev_addr[i] = data & 0xff;
854 dev->dev_addr[i+1] = data >> 8;
855 }
856 if (!is_valid_ether_addr(dev->dev_addr))
857 return tc35815_read_plat_dev_addr(dev);
858 return 0;
859 }
860
861 static int __devinit tc35815_init_one(struct pci_dev *pdev,
862 const struct pci_device_id *ent)
863 {
864 void __iomem *ioaddr = NULL;
865 struct net_device *dev;
866 struct tc35815_local *lp;
867 int rc;
868
869 static int printed_version;
870 if (!printed_version++) {
871 printk(version);
872 dev_printk(KERN_DEBUG, &pdev->dev,
873 "speed:%d duplex:%d\n",
874 options.speed, options.duplex);
875 }
876
877 if (!pdev->irq) {
878 dev_warn(&pdev->dev, "no IRQ assigned.\n");
879 return -ENODEV;
880 }
881
882 /* dev zeroed in alloc_etherdev */
883 dev = alloc_etherdev(sizeof(*lp));
884 if (dev == NULL) {
885 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
886 return -ENOMEM;
887 }
888 SET_NETDEV_DEV(dev, &pdev->dev);
889 lp = netdev_priv(dev);
890 lp->dev = dev;
891
892 /* enable device (incl. PCI PM wakeup), and bus-mastering */
893 rc = pcim_enable_device(pdev);
894 if (rc)
895 goto err_out;
896 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
897 if (rc)
898 goto err_out;
899 pci_set_master(pdev);
900 ioaddr = pcim_iomap_table(pdev)[1];
901
902 /* Initialize the device structure. */
903 dev->open = tc35815_open;
904 dev->hard_start_xmit = tc35815_send_packet;
905 dev->stop = tc35815_close;
906 dev->get_stats = tc35815_get_stats;
907 dev->set_multicast_list = tc35815_set_multicast_list;
908 dev->do_ioctl = tc35815_ioctl;
909 dev->ethtool_ops = &tc35815_ethtool_ops;
910 dev->tx_timeout = tc35815_tx_timeout;
911 dev->watchdog_timeo = TC35815_TX_TIMEOUT;
912 #ifdef TC35815_NAPI
913 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
914 #endif
915 #ifdef CONFIG_NET_POLL_CONTROLLER
916 dev->poll_controller = tc35815_poll_controller;
917 #endif
918
919 dev->irq = pdev->irq;
920 dev->base_addr = (unsigned long)ioaddr;
921
922 INIT_WORK(&lp->restart_work, tc35815_restart_work);
923 spin_lock_init(&lp->lock);
924 lp->pci_dev = pdev;
925 lp->chiptype = ent->driver_data;
926
927 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
928 pci_set_drvdata(pdev, dev);
929
930 /* Soft reset the chip. */
931 tc35815_chip_reset(dev);
932
933 /* Retrieve the ethernet address. */
934 if (tc35815_init_dev_addr(dev)) {
935 dev_warn(&pdev->dev, "not valid ether addr\n");
936 random_ether_addr(dev->dev_addr);
937 }
938
939 rc = register_netdev(dev);
940 if (rc)
941 goto err_out;
942
943 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
944 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
945 dev->name,
946 chip_info[ent->driver_data].name,
947 dev->base_addr,
948 dev->dev_addr,
949 dev->irq);
950
951 rc = tc_mii_init(dev);
952 if (rc)
953 goto err_out_unregister;
954
955 return 0;
956
957 err_out_unregister:
958 unregister_netdev(dev);
959 err_out:
960 free_netdev(dev);
961 return rc;
962 }
963
964
965 static void __devexit tc35815_remove_one(struct pci_dev *pdev)
966 {
967 struct net_device *dev = pci_get_drvdata(pdev);
968 struct tc35815_local *lp = netdev_priv(dev);
969
970 phy_disconnect(lp->phy_dev);
971 mdiobus_unregister(lp->mii_bus);
972 kfree(lp->mii_bus->irq);
973 mdiobus_free(lp->mii_bus);
974 unregister_netdev(dev);
975 free_netdev(dev);
976 pci_set_drvdata(pdev, NULL);
977 }
978
979 static int
980 tc35815_init_queues(struct net_device *dev)
981 {
982 struct tc35815_local *lp = netdev_priv(dev);
983 int i;
984 unsigned long fd_addr;
985
986 if (!lp->fd_buf) {
987 BUG_ON(sizeof(struct FDesc) +
988 sizeof(struct BDesc) * RX_BUF_NUM +
989 sizeof(struct FDesc) * RX_FD_NUM +
990 sizeof(struct TxFD) * TX_FD_NUM >
991 PAGE_SIZE * FD_PAGE_NUM);
992
993 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
994 PAGE_SIZE * FD_PAGE_NUM,
995 &lp->fd_buf_dma);
996 if (!lp->fd_buf)
997 return -ENOMEM;
998 for (i = 0; i < RX_BUF_NUM; i++) {
999 #ifdef TC35815_USE_PACKEDBUFFER
1000 lp->data_buf[i] =
1001 alloc_rxbuf_page(lp->pci_dev,
1002 &lp->data_buf_dma[i]);
1003 if (!lp->data_buf[i]) {
1004 while (--i >= 0) {
1005 free_rxbuf_page(lp->pci_dev,
1006 lp->data_buf[i],
1007 lp->data_buf_dma[i]);
1008 lp->data_buf[i] = NULL;
1009 }
1010 pci_free_consistent(lp->pci_dev,
1011 PAGE_SIZE * FD_PAGE_NUM,
1012 lp->fd_buf,
1013 lp->fd_buf_dma);
1014 lp->fd_buf = NULL;
1015 return -ENOMEM;
1016 }
1017 #else
1018 lp->rx_skbs[i].skb =
1019 alloc_rxbuf_skb(dev, lp->pci_dev,
1020 &lp->rx_skbs[i].skb_dma);
1021 if (!lp->rx_skbs[i].skb) {
1022 while (--i >= 0) {
1023 free_rxbuf_skb(lp->pci_dev,
1024 lp->rx_skbs[i].skb,
1025 lp->rx_skbs[i].skb_dma);
1026 lp->rx_skbs[i].skb = NULL;
1027 }
1028 pci_free_consistent(lp->pci_dev,
1029 PAGE_SIZE * FD_PAGE_NUM,
1030 lp->fd_buf,
1031 lp->fd_buf_dma);
1032 lp->fd_buf = NULL;
1033 return -ENOMEM;
1034 }
1035 #endif
1036 }
1037 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
1038 dev->name, lp->fd_buf);
1039 #ifdef TC35815_USE_PACKEDBUFFER
1040 printk(" DataBuf");
1041 for (i = 0; i < RX_BUF_NUM; i++)
1042 printk(" %p", lp->data_buf[i]);
1043 #endif
1044 printk("\n");
1045 } else {
1046 for (i = 0; i < FD_PAGE_NUM; i++)
1047 clear_page((void *)((unsigned long)lp->fd_buf +
1048 i * PAGE_SIZE));
1049 }
1050 fd_addr = (unsigned long)lp->fd_buf;
1051
1052 /* Free Descriptors (for Receive) */
1053 lp->rfd_base = (struct RxFD *)fd_addr;
1054 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
1055 for (i = 0; i < RX_FD_NUM; i++)
1056 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
1057 lp->rfd_cur = lp->rfd_base;
1058 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
1059
1060 /* Transmit Descriptors */
1061 lp->tfd_base = (struct TxFD *)fd_addr;
1062 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
1063 for (i = 0; i < TX_FD_NUM; i++) {
1064 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
1065 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1066 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
1067 }
1068 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
1069 lp->tfd_start = 0;
1070 lp->tfd_end = 0;
1071
1072 /* Buffer List (for Receive) */
1073 lp->fbl_ptr = (struct FrFD *)fd_addr;
1074 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
1075 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
1076 #ifndef TC35815_USE_PACKEDBUFFER
1077 /*
1078 * move all allocated skbs to head of rx_skbs[] array.
1079 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
1080 * tc35815_rx() had failed.
1081 */
1082 lp->fbl_count = 0;
1083 for (i = 0; i < RX_BUF_NUM; i++) {
1084 if (lp->rx_skbs[i].skb) {
1085 if (i != lp->fbl_count) {
1086 lp->rx_skbs[lp->fbl_count].skb =
1087 lp->rx_skbs[i].skb;
1088 lp->rx_skbs[lp->fbl_count].skb_dma =
1089 lp->rx_skbs[i].skb_dma;
1090 }
1091 lp->fbl_count++;
1092 }
1093 }
1094 #endif
1095 for (i = 0; i < RX_BUF_NUM; i++) {
1096 #ifdef TC35815_USE_PACKEDBUFFER
1097 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(lp->data_buf_dma[i]);
1098 #else
1099 if (i >= lp->fbl_count) {
1100 lp->fbl_ptr->bd[i].BuffData = 0;
1101 lp->fbl_ptr->bd[i].BDCtl = 0;
1102 continue;
1103 }
1104 lp->fbl_ptr->bd[i].BuffData =
1105 cpu_to_le32(lp->rx_skbs[i].skb_dma);
1106 #endif
1107 /* BDID is index of FrFD.bd[] */
1108 lp->fbl_ptr->bd[i].BDCtl =
1109 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
1110 RX_BUF_SIZE);
1111 }
1112 #ifdef TC35815_USE_PACKEDBUFFER
1113 lp->fbl_curid = 0;
1114 #endif
1115
1116 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
1117 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
1118 return 0;
1119 }
1120
1121 static void
1122 tc35815_clear_queues(struct net_device *dev)
1123 {
1124 struct tc35815_local *lp = netdev_priv(dev);
1125 int i;
1126
1127 for (i = 0; i < TX_FD_NUM; i++) {
1128 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1129 struct sk_buff *skb =
1130 fdsystem != 0xffffffff ?
1131 lp->tx_skbs[fdsystem].skb : NULL;
1132 #ifdef DEBUG
1133 if (lp->tx_skbs[i].skb != skb) {
1134 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1135 panic_queues(dev);
1136 }
1137 #else
1138 BUG_ON(lp->tx_skbs[i].skb != skb);
1139 #endif
1140 if (skb) {
1141 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1142 lp->tx_skbs[i].skb = NULL;
1143 lp->tx_skbs[i].skb_dma = 0;
1144 dev_kfree_skb_any(skb);
1145 }
1146 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1147 }
1148
1149 tc35815_init_queues(dev);
1150 }
1151
1152 static void
1153 tc35815_free_queues(struct net_device *dev)
1154 {
1155 struct tc35815_local *lp = netdev_priv(dev);
1156 int i;
1157
1158 if (lp->tfd_base) {
1159 for (i = 0; i < TX_FD_NUM; i++) {
1160 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1161 struct sk_buff *skb =
1162 fdsystem != 0xffffffff ?
1163 lp->tx_skbs[fdsystem].skb : NULL;
1164 #ifdef DEBUG
1165 if (lp->tx_skbs[i].skb != skb) {
1166 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1167 panic_queues(dev);
1168 }
1169 #else
1170 BUG_ON(lp->tx_skbs[i].skb != skb);
1171 #endif
1172 if (skb) {
1173 dev_kfree_skb(skb);
1174 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1175 lp->tx_skbs[i].skb = NULL;
1176 lp->tx_skbs[i].skb_dma = 0;
1177 }
1178 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1179 }
1180 }
1181
1182 lp->rfd_base = NULL;
1183 lp->rfd_limit = NULL;
1184 lp->rfd_cur = NULL;
1185 lp->fbl_ptr = NULL;
1186
1187 for (i = 0; i < RX_BUF_NUM; i++) {
1188 #ifdef TC35815_USE_PACKEDBUFFER
1189 if (lp->data_buf[i]) {
1190 free_rxbuf_page(lp->pci_dev,
1191 lp->data_buf[i], lp->data_buf_dma[i]);
1192 lp->data_buf[i] = NULL;
1193 }
1194 #else
1195 if (lp->rx_skbs[i].skb) {
1196 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1197 lp->rx_skbs[i].skb_dma);
1198 lp->rx_skbs[i].skb = NULL;
1199 }
1200 #endif
1201 }
1202 if (lp->fd_buf) {
1203 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1204 lp->fd_buf, lp->fd_buf_dma);
1205 lp->fd_buf = NULL;
1206 }
1207 }
1208
1209 static void
1210 dump_txfd(struct TxFD *fd)
1211 {
1212 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1213 le32_to_cpu(fd->fd.FDNext),
1214 le32_to_cpu(fd->fd.FDSystem),
1215 le32_to_cpu(fd->fd.FDStat),
1216 le32_to_cpu(fd->fd.FDCtl));
1217 printk("BD: ");
1218 printk(" %08x %08x",
1219 le32_to_cpu(fd->bd.BuffData),
1220 le32_to_cpu(fd->bd.BDCtl));
1221 printk("\n");
1222 }
1223
1224 static int
1225 dump_rxfd(struct RxFD *fd)
1226 {
1227 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1228 if (bd_count > 8)
1229 bd_count = 8;
1230 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1231 le32_to_cpu(fd->fd.FDNext),
1232 le32_to_cpu(fd->fd.FDSystem),
1233 le32_to_cpu(fd->fd.FDStat),
1234 le32_to_cpu(fd->fd.FDCtl));
1235 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1236 return 0;
1237 printk("BD: ");
1238 for (i = 0; i < bd_count; i++)
1239 printk(" %08x %08x",
1240 le32_to_cpu(fd->bd[i].BuffData),
1241 le32_to_cpu(fd->bd[i].BDCtl));
1242 printk("\n");
1243 return bd_count;
1244 }
1245
1246 #if defined(DEBUG) || defined(TC35815_USE_PACKEDBUFFER)
1247 static void
1248 dump_frfd(struct FrFD *fd)
1249 {
1250 int i;
1251 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1252 le32_to_cpu(fd->fd.FDNext),
1253 le32_to_cpu(fd->fd.FDSystem),
1254 le32_to_cpu(fd->fd.FDStat),
1255 le32_to_cpu(fd->fd.FDCtl));
1256 printk("BD: ");
1257 for (i = 0; i < RX_BUF_NUM; i++)
1258 printk(" %08x %08x",
1259 le32_to_cpu(fd->bd[i].BuffData),
1260 le32_to_cpu(fd->bd[i].BDCtl));
1261 printk("\n");
1262 }
1263 #endif
1264
1265 #ifdef DEBUG
1266 static void
1267 panic_queues(struct net_device *dev)
1268 {
1269 struct tc35815_local *lp = netdev_priv(dev);
1270 int i;
1271
1272 printk("TxFD base %p, start %u, end %u\n",
1273 lp->tfd_base, lp->tfd_start, lp->tfd_end);
1274 printk("RxFD base %p limit %p cur %p\n",
1275 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1276 printk("FrFD %p\n", lp->fbl_ptr);
1277 for (i = 0; i < TX_FD_NUM; i++)
1278 dump_txfd(&lp->tfd_base[i]);
1279 for (i = 0; i < RX_FD_NUM; i++) {
1280 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1281 i += (bd_count + 1) / 2; /* skip BDs */
1282 }
1283 dump_frfd(lp->fbl_ptr);
1284 panic("%s: Illegal queue state.", dev->name);
1285 }
1286 #endif
1287
1288 static void print_eth(const u8 *add)
1289 {
1290 printk(KERN_DEBUG "print_eth(%p)\n", add);
1291 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1292 add + 6, add, add[12], add[13]);
1293 }
1294
1295 static int tc35815_tx_full(struct net_device *dev)
1296 {
1297 struct tc35815_local *lp = netdev_priv(dev);
1298 return ((lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end);
1299 }
1300
1301 static void tc35815_restart(struct net_device *dev)
1302 {
1303 struct tc35815_local *lp = netdev_priv(dev);
1304
1305 if (lp->phy_dev) {
1306 int timeout;
1307
1308 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET);
1309 timeout = 100;
1310 while (--timeout) {
1311 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET))
1312 break;
1313 udelay(1);
1314 }
1315 if (!timeout)
1316 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name);
1317 }
1318
1319 spin_lock_irq(&lp->lock);
1320 tc35815_chip_reset(dev);
1321 tc35815_clear_queues(dev);
1322 tc35815_chip_init(dev);
1323 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1324 tc35815_set_multicast_list(dev);
1325 spin_unlock_irq(&lp->lock);
1326
1327 netif_wake_queue(dev);
1328 }
1329
1330 static void tc35815_restart_work(struct work_struct *work)
1331 {
1332 struct tc35815_local *lp =
1333 container_of(work, struct tc35815_local, restart_work);
1334 struct net_device *dev = lp->dev;
1335
1336 tc35815_restart(dev);
1337 }
1338
1339 static void tc35815_schedule_restart(struct net_device *dev)
1340 {
1341 struct tc35815_local *lp = netdev_priv(dev);
1342 struct tc35815_regs __iomem *tr =
1343 (struct tc35815_regs __iomem *)dev->base_addr;
1344
1345 /* disable interrupts */
1346 tc_writel(0, &tr->Int_En);
1347 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1348 schedule_work(&lp->restart_work);
1349 }
1350
1351 static void tc35815_tx_timeout(struct net_device *dev)
1352 {
1353 struct tc35815_regs __iomem *tr =
1354 (struct tc35815_regs __iomem *)dev->base_addr;
1355
1356 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1357 dev->name, tc_readl(&tr->Tx_Stat));
1358
1359 /* Try to restart the adaptor. */
1360 tc35815_schedule_restart(dev);
1361 dev->stats.tx_errors++;
1362 }
1363
1364 /*
1365 * Open/initialize the controller. This is called (in the current kernel)
1366 * sometime after booting when the 'ifconfig' program is run.
1367 *
1368 * This routine should set everything up anew at each open, even
1369 * registers that "should" only need to be set once at boot, so that
1370 * there is non-reboot way to recover if something goes wrong.
1371 */
1372 static int
1373 tc35815_open(struct net_device *dev)
1374 {
1375 struct tc35815_local *lp = netdev_priv(dev);
1376
1377 /*
1378 * This is used if the interrupt line can turned off (shared).
1379 * See 3c503.c for an example of selecting the IRQ at config-time.
1380 */
1381 if (request_irq(dev->irq, &tc35815_interrupt, IRQF_SHARED,
1382 dev->name, dev))
1383 return -EAGAIN;
1384
1385 tc35815_chip_reset(dev);
1386
1387 if (tc35815_init_queues(dev) != 0) {
1388 free_irq(dev->irq, dev);
1389 return -EAGAIN;
1390 }
1391
1392 #ifdef TC35815_NAPI
1393 napi_enable(&lp->napi);
1394 #endif
1395
1396 /* Reset the hardware here. Don't forget to set the station address. */
1397 spin_lock_irq(&lp->lock);
1398 tc35815_chip_init(dev);
1399 spin_unlock_irq(&lp->lock);
1400
1401 netif_carrier_off(dev);
1402 /* schedule a link state check */
1403 phy_start(lp->phy_dev);
1404
1405 /* We are now ready to accept transmit requeusts from
1406 * the queueing layer of the networking.
1407 */
1408 netif_start_queue(dev);
1409
1410 return 0;
1411 }
1412
1413 /* This will only be invoked if your driver is _not_ in XOFF state.
1414 * What this means is that you need not check it, and that this
1415 * invariant will hold if you make sure that the netif_*_queue()
1416 * calls are done at the proper times.
1417 */
1418 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1419 {
1420 struct tc35815_local *lp = netdev_priv(dev);
1421 struct TxFD *txfd;
1422 unsigned long flags;
1423
1424 /* If some error occurs while trying to transmit this
1425 * packet, you should return '1' from this function.
1426 * In such a case you _may not_ do anything to the
1427 * SKB, it is still owned by the network queueing
1428 * layer when an error is returned. This means you
1429 * may not modify any SKB fields, you may not free
1430 * the SKB, etc.
1431 */
1432
1433 /* This is the most common case for modern hardware.
1434 * The spinlock protects this code from the TX complete
1435 * hardware interrupt handler. Queue flow control is
1436 * thus managed under this lock as well.
1437 */
1438 spin_lock_irqsave(&lp->lock, flags);
1439
1440 /* failsafe... (handle txdone now if half of FDs are used) */
1441 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1442 TX_FD_NUM / 2)
1443 tc35815_txdone(dev);
1444
1445 if (netif_msg_pktdata(lp))
1446 print_eth(skb->data);
1447 #ifdef DEBUG
1448 if (lp->tx_skbs[lp->tfd_start].skb) {
1449 printk("%s: tx_skbs conflict.\n", dev->name);
1450 panic_queues(dev);
1451 }
1452 #else
1453 BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1454 #endif
1455 lp->tx_skbs[lp->tfd_start].skb = skb;
1456 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1457
1458 /*add to ring */
1459 txfd = &lp->tfd_base[lp->tfd_start];
1460 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1461 txfd->bd.BDCtl = cpu_to_le32(skb->len);
1462 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1463 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1464
1465 if (lp->tfd_start == lp->tfd_end) {
1466 struct tc35815_regs __iomem *tr =
1467 (struct tc35815_regs __iomem *)dev->base_addr;
1468 /* Start DMA Transmitter. */
1469 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1470 #ifdef GATHER_TXINT
1471 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1472 #endif
1473 if (netif_msg_tx_queued(lp)) {
1474 printk("%s: starting TxFD.\n", dev->name);
1475 dump_txfd(txfd);
1476 }
1477 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1478 } else {
1479 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1480 if (netif_msg_tx_queued(lp)) {
1481 printk("%s: queueing TxFD.\n", dev->name);
1482 dump_txfd(txfd);
1483 }
1484 }
1485 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1486
1487 dev->trans_start = jiffies;
1488
1489 /* If we just used up the very last entry in the
1490 * TX ring on this device, tell the queueing
1491 * layer to send no more.
1492 */
1493 if (tc35815_tx_full(dev)) {
1494 if (netif_msg_tx_queued(lp))
1495 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1496 netif_stop_queue(dev);
1497 }
1498
1499 /* When the TX completion hw interrupt arrives, this
1500 * is when the transmit statistics are updated.
1501 */
1502
1503 spin_unlock_irqrestore(&lp->lock, flags);
1504 return 0;
1505 }
1506
1507 #define FATAL_ERROR_INT \
1508 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1509 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1510 {
1511 static int count;
1512 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1513 dev->name, status);
1514 if (status & Int_IntPCI)
1515 printk(" IntPCI");
1516 if (status & Int_DmParErr)
1517 printk(" DmParErr");
1518 if (status & Int_IntNRAbt)
1519 printk(" IntNRAbt");
1520 printk("\n");
1521 if (count++ > 100)
1522 panic("%s: Too many fatal errors.", dev->name);
1523 printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1524 /* Try to restart the adaptor. */
1525 tc35815_schedule_restart(dev);
1526 }
1527
1528 #ifdef TC35815_NAPI
1529 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1530 #else
1531 static int tc35815_do_interrupt(struct net_device *dev, u32 status)
1532 #endif
1533 {
1534 struct tc35815_local *lp = netdev_priv(dev);
1535 struct tc35815_regs __iomem *tr =
1536 (struct tc35815_regs __iomem *)dev->base_addr;
1537 int ret = -1;
1538
1539 /* Fatal errors... */
1540 if (status & FATAL_ERROR_INT) {
1541 tc35815_fatal_error_interrupt(dev, status);
1542 return 0;
1543 }
1544 /* recoverable errors */
1545 if (status & Int_IntFDAEx) {
1546 /* disable FDAEx int. (until we make rooms...) */
1547 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1548 printk(KERN_WARNING
1549 "%s: Free Descriptor Area Exhausted (%#x).\n",
1550 dev->name, status);
1551 dev->stats.rx_dropped++;
1552 ret = 0;
1553 }
1554 if (status & Int_IntBLEx) {
1555 /* disable BLEx int. (until we make rooms...) */
1556 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1557 printk(KERN_WARNING
1558 "%s: Buffer List Exhausted (%#x).\n",
1559 dev->name, status);
1560 dev->stats.rx_dropped++;
1561 ret = 0;
1562 }
1563 if (status & Int_IntExBD) {
1564 printk(KERN_WARNING
1565 "%s: Excessive Buffer Descriptiors (%#x).\n",
1566 dev->name, status);
1567 dev->stats.rx_length_errors++;
1568 ret = 0;
1569 }
1570
1571 /* normal notification */
1572 if (status & Int_IntMacRx) {
1573 /* Got a packet(s). */
1574 #ifdef TC35815_NAPI
1575 ret = tc35815_rx(dev, limit);
1576 #else
1577 tc35815_rx(dev);
1578 ret = 0;
1579 #endif
1580 lp->lstats.rx_ints++;
1581 }
1582 if (status & Int_IntMacTx) {
1583 /* Transmit complete. */
1584 lp->lstats.tx_ints++;
1585 tc35815_txdone(dev);
1586 netif_wake_queue(dev);
1587 ret = 0;
1588 }
1589 return ret;
1590 }
1591
1592 /*
1593 * The typical workload of the driver:
1594 * Handle the network interface interrupts.
1595 */
1596 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1597 {
1598 struct net_device *dev = dev_id;
1599 struct tc35815_local *lp = netdev_priv(dev);
1600 struct tc35815_regs __iomem *tr =
1601 (struct tc35815_regs __iomem *)dev->base_addr;
1602 #ifdef TC35815_NAPI
1603 u32 dmactl = tc_readl(&tr->DMA_Ctl);
1604
1605 if (!(dmactl & DMA_IntMask)) {
1606 /* disable interrupts */
1607 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1608 if (netif_rx_schedule_prep(dev, &lp->napi))
1609 __netif_rx_schedule(dev, &lp->napi);
1610 else {
1611 printk(KERN_ERR "%s: interrupt taken in poll\n",
1612 dev->name);
1613 BUG();
1614 }
1615 (void)tc_readl(&tr->Int_Src); /* flush */
1616 return IRQ_HANDLED;
1617 }
1618 return IRQ_NONE;
1619 #else
1620 int handled;
1621 u32 status;
1622
1623 spin_lock(&lp->lock);
1624 status = tc_readl(&tr->Int_Src);
1625 tc_writel(status, &tr->Int_Src); /* write to clear */
1626 handled = tc35815_do_interrupt(dev, status);
1627 (void)tc_readl(&tr->Int_Src); /* flush */
1628 spin_unlock(&lp->lock);
1629 return IRQ_RETVAL(handled >= 0);
1630 #endif /* TC35815_NAPI */
1631 }
1632
1633 #ifdef CONFIG_NET_POLL_CONTROLLER
1634 static void tc35815_poll_controller(struct net_device *dev)
1635 {
1636 disable_irq(dev->irq);
1637 tc35815_interrupt(dev->irq, dev);
1638 enable_irq(dev->irq);
1639 }
1640 #endif
1641
1642 /* We have a good packet(s), get it/them out of the buffers. */
1643 #ifdef TC35815_NAPI
1644 static int
1645 tc35815_rx(struct net_device *dev, int limit)
1646 #else
1647 static void
1648 tc35815_rx(struct net_device *dev)
1649 #endif
1650 {
1651 struct tc35815_local *lp = netdev_priv(dev);
1652 unsigned int fdctl;
1653 int i;
1654 int buf_free_count = 0;
1655 int fd_free_count = 0;
1656 #ifdef TC35815_NAPI
1657 int received = 0;
1658 #endif
1659
1660 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1661 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1662 int pkt_len = fdctl & FD_FDLength_MASK;
1663 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1664 #ifdef DEBUG
1665 struct RxFD *next_rfd;
1666 #endif
1667 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1668 pkt_len -= 4;
1669 #endif
1670
1671 if (netif_msg_rx_status(lp))
1672 dump_rxfd(lp->rfd_cur);
1673 if (status & Rx_Good) {
1674 struct sk_buff *skb;
1675 unsigned char *data;
1676 int cur_bd;
1677 #ifdef TC35815_USE_PACKEDBUFFER
1678 int offset;
1679 #endif
1680
1681 #ifdef TC35815_NAPI
1682 if (--limit < 0)
1683 break;
1684 #endif
1685 #ifdef TC35815_USE_PACKEDBUFFER
1686 BUG_ON(bd_count > 2);
1687 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1688 if (skb == NULL) {
1689 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1690 dev->name);
1691 dev->stats.rx_dropped++;
1692 break;
1693 }
1694 skb_reserve(skb, 2); /* 16 bit alignment */
1695
1696 data = skb_put(skb, pkt_len);
1697
1698 /* copy from receive buffer */
1699 cur_bd = 0;
1700 offset = 0;
1701 while (offset < pkt_len && cur_bd < bd_count) {
1702 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1703 BD_BuffLength_MASK;
1704 dma_addr_t dma = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData);
1705 void *rxbuf = rxbuf_bus_to_virt(lp, dma);
1706 if (offset + len > pkt_len)
1707 len = pkt_len - offset;
1708 #ifdef TC35815_DMA_SYNC_ONDEMAND
1709 pci_dma_sync_single_for_cpu(lp->pci_dev,
1710 dma, len,
1711 PCI_DMA_FROMDEVICE);
1712 #endif
1713 memcpy(data + offset, rxbuf, len);
1714 #ifdef TC35815_DMA_SYNC_ONDEMAND
1715 pci_dma_sync_single_for_device(lp->pci_dev,
1716 dma, len,
1717 PCI_DMA_FROMDEVICE);
1718 #endif
1719 offset += len;
1720 cur_bd++;
1721 }
1722 #else /* TC35815_USE_PACKEDBUFFER */
1723 BUG_ON(bd_count > 1);
1724 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1725 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1726 #ifdef DEBUG
1727 if (cur_bd >= RX_BUF_NUM) {
1728 printk("%s: invalid BDID.\n", dev->name);
1729 panic_queues(dev);
1730 }
1731 BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1732 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1733 if (!lp->rx_skbs[cur_bd].skb) {
1734 printk("%s: NULL skb.\n", dev->name);
1735 panic_queues(dev);
1736 }
1737 #else
1738 BUG_ON(cur_bd >= RX_BUF_NUM);
1739 #endif
1740 skb = lp->rx_skbs[cur_bd].skb;
1741 prefetch(skb->data);
1742 lp->rx_skbs[cur_bd].skb = NULL;
1743 pci_unmap_single(lp->pci_dev,
1744 lp->rx_skbs[cur_bd].skb_dma,
1745 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1746 if (!HAVE_DMA_RXALIGN(lp))
1747 memmove(skb->data, skb->data - 2, pkt_len);
1748 data = skb_put(skb, pkt_len);
1749 #endif /* TC35815_USE_PACKEDBUFFER */
1750 if (netif_msg_pktdata(lp))
1751 print_eth(data);
1752 skb->protocol = eth_type_trans(skb, dev);
1753 #ifdef TC35815_NAPI
1754 netif_receive_skb(skb);
1755 received++;
1756 #else
1757 netif_rx(skb);
1758 #endif
1759 dev->last_rx = jiffies;
1760 dev->stats.rx_packets++;
1761 dev->stats.rx_bytes += pkt_len;
1762 } else {
1763 dev->stats.rx_errors++;
1764 printk(KERN_DEBUG "%s: Rx error (status %x)\n",
1765 dev->name, status & Rx_Stat_Mask);
1766 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1767 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1768 status &= ~(Rx_LongErr|Rx_CRCErr);
1769 status |= Rx_Over;
1770 }
1771 if (status & Rx_LongErr)
1772 dev->stats.rx_length_errors++;
1773 if (status & Rx_Over)
1774 dev->stats.rx_fifo_errors++;
1775 if (status & Rx_CRCErr)
1776 dev->stats.rx_crc_errors++;
1777 if (status & Rx_Align)
1778 dev->stats.rx_frame_errors++;
1779 }
1780
1781 if (bd_count > 0) {
1782 /* put Free Buffer back to controller */
1783 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1784 unsigned char id =
1785 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1786 #ifdef DEBUG
1787 if (id >= RX_BUF_NUM) {
1788 printk("%s: invalid BDID.\n", dev->name);
1789 panic_queues(dev);
1790 }
1791 #else
1792 BUG_ON(id >= RX_BUF_NUM);
1793 #endif
1794 /* free old buffers */
1795 #ifdef TC35815_USE_PACKEDBUFFER
1796 while (lp->fbl_curid != id)
1797 #else
1798 lp->fbl_count--;
1799 while (lp->fbl_count < RX_BUF_NUM)
1800 #endif
1801 {
1802 #ifdef TC35815_USE_PACKEDBUFFER
1803 unsigned char curid = lp->fbl_curid;
1804 #else
1805 unsigned char curid =
1806 (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1807 #endif
1808 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1809 #ifdef DEBUG
1810 bdctl = le32_to_cpu(bd->BDCtl);
1811 if (bdctl & BD_CownsBD) {
1812 printk("%s: Freeing invalid BD.\n",
1813 dev->name);
1814 panic_queues(dev);
1815 }
1816 #endif
1817 /* pass BD to controller */
1818 #ifndef TC35815_USE_PACKEDBUFFER
1819 if (!lp->rx_skbs[curid].skb) {
1820 lp->rx_skbs[curid].skb =
1821 alloc_rxbuf_skb(dev,
1822 lp->pci_dev,
1823 &lp->rx_skbs[curid].skb_dma);
1824 if (!lp->rx_skbs[curid].skb)
1825 break; /* try on next reception */
1826 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1827 }
1828 #endif /* TC35815_USE_PACKEDBUFFER */
1829 /* Note: BDLength was modified by chip. */
1830 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1831 (curid << BD_RxBDID_SHIFT) |
1832 RX_BUF_SIZE);
1833 #ifdef TC35815_USE_PACKEDBUFFER
1834 lp->fbl_curid = (curid + 1) % RX_BUF_NUM;
1835 if (netif_msg_rx_status(lp)) {
1836 printk("%s: Entering new FBD %d\n",
1837 dev->name, lp->fbl_curid);
1838 dump_frfd(lp->fbl_ptr);
1839 }
1840 #else
1841 lp->fbl_count++;
1842 #endif
1843 buf_free_count++;
1844 }
1845 }
1846
1847 /* put RxFD back to controller */
1848 #ifdef DEBUG
1849 next_rfd = fd_bus_to_virt(lp,
1850 le32_to_cpu(lp->rfd_cur->fd.FDNext));
1851 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1852 printk("%s: RxFD FDNext invalid.\n", dev->name);
1853 panic_queues(dev);
1854 }
1855 #endif
1856 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1857 /* pass FD to controller */
1858 #ifdef DEBUG
1859 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1860 #else
1861 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1862 #endif
1863 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1864 lp->rfd_cur++;
1865 fd_free_count++;
1866 }
1867 if (lp->rfd_cur > lp->rfd_limit)
1868 lp->rfd_cur = lp->rfd_base;
1869 #ifdef DEBUG
1870 if (lp->rfd_cur != next_rfd)
1871 printk("rfd_cur = %p, next_rfd %p\n",
1872 lp->rfd_cur, next_rfd);
1873 #endif
1874 }
1875
1876 /* re-enable BL/FDA Exhaust interrupts. */
1877 if (fd_free_count) {
1878 struct tc35815_regs __iomem *tr =
1879 (struct tc35815_regs __iomem *)dev->base_addr;
1880 u32 en, en_old = tc_readl(&tr->Int_En);
1881 en = en_old | Int_FDAExEn;
1882 if (buf_free_count)
1883 en |= Int_BLExEn;
1884 if (en != en_old)
1885 tc_writel(en, &tr->Int_En);
1886 }
1887 #ifdef TC35815_NAPI
1888 return received;
1889 #endif
1890 }
1891
1892 #ifdef TC35815_NAPI
1893 static int tc35815_poll(struct napi_struct *napi, int budget)
1894 {
1895 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1896 struct net_device *dev = lp->dev;
1897 struct tc35815_regs __iomem *tr =
1898 (struct tc35815_regs __iomem *)dev->base_addr;
1899 int received = 0, handled;
1900 u32 status;
1901
1902 spin_lock(&lp->lock);
1903 status = tc_readl(&tr->Int_Src);
1904 do {
1905 tc_writel(status, &tr->Int_Src); /* write to clear */
1906
1907 handled = tc35815_do_interrupt(dev, status, limit);
1908 if (handled >= 0) {
1909 received += handled;
1910 if (received >= budget)
1911 break;
1912 }
1913 status = tc_readl(&tr->Int_Src);
1914 } while (status);
1915 spin_unlock(&lp->lock);
1916
1917 if (received < budget) {
1918 netif_rx_complete(dev, napi);
1919 /* enable interrupts */
1920 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1921 }
1922 return received;
1923 }
1924 #endif
1925
1926 #ifdef NO_CHECK_CARRIER
1927 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1928 #else
1929 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1930 #endif
1931
1932 static void
1933 tc35815_check_tx_stat(struct net_device *dev, int status)
1934 {
1935 struct tc35815_local *lp = netdev_priv(dev);
1936 const char *msg = NULL;
1937
1938 /* count collisions */
1939 if (status & Tx_ExColl)
1940 dev->stats.collisions += 16;
1941 if (status & Tx_TxColl_MASK)
1942 dev->stats.collisions += status & Tx_TxColl_MASK;
1943
1944 #ifndef NO_CHECK_CARRIER
1945 /* TX4939 does not have NCarr */
1946 if (lp->chiptype == TC35815_TX4939)
1947 status &= ~Tx_NCarr;
1948 #ifdef WORKAROUND_LOSTCAR
1949 /* WORKAROUND: ignore LostCrS in full duplex operation */
1950 if (!lp->link || lp->duplex == DUPLEX_FULL)
1951 status &= ~Tx_NCarr;
1952 #endif
1953 #endif
1954
1955 if (!(status & TX_STA_ERR)) {
1956 /* no error. */
1957 dev->stats.tx_packets++;
1958 return;
1959 }
1960
1961 dev->stats.tx_errors++;
1962 if (status & Tx_ExColl) {
1963 dev->stats.tx_aborted_errors++;
1964 msg = "Excessive Collision.";
1965 }
1966 if (status & Tx_Under) {
1967 dev->stats.tx_fifo_errors++;
1968 msg = "Tx FIFO Underrun.";
1969 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1970 lp->lstats.tx_underrun++;
1971 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1972 struct tc35815_regs __iomem *tr =
1973 (struct tc35815_regs __iomem *)dev->base_addr;
1974 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1975 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1976 }
1977 }
1978 }
1979 if (status & Tx_Defer) {
1980 dev->stats.tx_fifo_errors++;
1981 msg = "Excessive Deferral.";
1982 }
1983 #ifndef NO_CHECK_CARRIER
1984 if (status & Tx_NCarr) {
1985 dev->stats.tx_carrier_errors++;
1986 msg = "Lost Carrier Sense.";
1987 }
1988 #endif
1989 if (status & Tx_LateColl) {
1990 dev->stats.tx_aborted_errors++;
1991 msg = "Late Collision.";
1992 }
1993 if (status & Tx_TxPar) {
1994 dev->stats.tx_fifo_errors++;
1995 msg = "Transmit Parity Error.";
1996 }
1997 if (status & Tx_SQErr) {
1998 dev->stats.tx_heartbeat_errors++;
1999 msg = "Signal Quality Error.";
2000 }
2001 if (msg && netif_msg_tx_err(lp))
2002 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
2003 }
2004
2005 /* This handles TX complete events posted by the device
2006 * via interrupts.
2007 */
2008 static void
2009 tc35815_txdone(struct net_device *dev)
2010 {
2011 struct tc35815_local *lp = netdev_priv(dev);
2012 struct TxFD *txfd;
2013 unsigned int fdctl;
2014
2015 txfd = &lp->tfd_base[lp->tfd_end];
2016 while (lp->tfd_start != lp->tfd_end &&
2017 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
2018 int status = le32_to_cpu(txfd->fd.FDStat);
2019 struct sk_buff *skb;
2020 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
2021 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
2022
2023 if (netif_msg_tx_done(lp)) {
2024 printk("%s: complete TxFD.\n", dev->name);
2025 dump_txfd(txfd);
2026 }
2027 tc35815_check_tx_stat(dev, status);
2028
2029 skb = fdsystem != 0xffffffff ?
2030 lp->tx_skbs[fdsystem].skb : NULL;
2031 #ifdef DEBUG
2032 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
2033 printk("%s: tx_skbs mismatch.\n", dev->name);
2034 panic_queues(dev);
2035 }
2036 #else
2037 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
2038 #endif
2039 if (skb) {
2040 dev->stats.tx_bytes += skb->len;
2041 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
2042 lp->tx_skbs[lp->tfd_end].skb = NULL;
2043 lp->tx_skbs[lp->tfd_end].skb_dma = 0;
2044 #ifdef TC35815_NAPI
2045 dev_kfree_skb_any(skb);
2046 #else
2047 dev_kfree_skb_irq(skb);
2048 #endif
2049 }
2050 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
2051
2052 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
2053 txfd = &lp->tfd_base[lp->tfd_end];
2054 #ifdef DEBUG
2055 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
2056 printk("%s: TxFD FDNext invalid.\n", dev->name);
2057 panic_queues(dev);
2058 }
2059 #endif
2060 if (fdnext & FD_Next_EOL) {
2061 /* DMA Transmitter has been stopping... */
2062 if (lp->tfd_end != lp->tfd_start) {
2063 struct tc35815_regs __iomem *tr =
2064 (struct tc35815_regs __iomem *)dev->base_addr;
2065 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
2066 struct TxFD *txhead = &lp->tfd_base[head];
2067 int qlen = (lp->tfd_start + TX_FD_NUM
2068 - lp->tfd_end) % TX_FD_NUM;
2069
2070 #ifdef DEBUG
2071 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
2072 printk("%s: TxFD FDCtl invalid.\n", dev->name);
2073 panic_queues(dev);
2074 }
2075 #endif
2076 /* log max queue length */
2077 if (lp->lstats.max_tx_qlen < qlen)
2078 lp->lstats.max_tx_qlen = qlen;
2079
2080
2081 /* start DMA Transmitter again */
2082 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
2083 #ifdef GATHER_TXINT
2084 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
2085 #endif
2086 if (netif_msg_tx_queued(lp)) {
2087 printk("%s: start TxFD on queue.\n",
2088 dev->name);
2089 dump_txfd(txfd);
2090 }
2091 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
2092 }
2093 break;
2094 }
2095 }
2096
2097 /* If we had stopped the queue due to a "tx full"
2098 * condition, and space has now been made available,
2099 * wake up the queue.
2100 */
2101 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
2102 netif_wake_queue(dev);
2103 }
2104
2105 /* The inverse routine to tc35815_open(). */
2106 static int
2107 tc35815_close(struct net_device *dev)
2108 {
2109 struct tc35815_local *lp = netdev_priv(dev);
2110
2111 netif_stop_queue(dev);
2112 #ifdef TC35815_NAPI
2113 napi_disable(&lp->napi);
2114 #endif
2115 if (lp->phy_dev)
2116 phy_stop(lp->phy_dev);
2117 cancel_work_sync(&lp->restart_work);
2118
2119 /* Flush the Tx and disable Rx here. */
2120 tc35815_chip_reset(dev);
2121 free_irq(dev->irq, dev);
2122
2123 tc35815_free_queues(dev);
2124
2125 return 0;
2126
2127 }
2128
2129 /*
2130 * Get the current statistics.
2131 * This may be called with the card open or closed.
2132 */
2133 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
2134 {
2135 struct tc35815_regs __iomem *tr =
2136 (struct tc35815_regs __iomem *)dev->base_addr;
2137 if (netif_running(dev))
2138 /* Update the statistics from the device registers. */
2139 dev->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
2140
2141 return &dev->stats;
2142 }
2143
2144 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
2145 {
2146 struct tc35815_local *lp = netdev_priv(dev);
2147 struct tc35815_regs __iomem *tr =
2148 (struct tc35815_regs __iomem *)dev->base_addr;
2149 int cam_index = index * 6;
2150 u32 cam_data;
2151 u32 saved_addr;
2152
2153 saved_addr = tc_readl(&tr->CAM_Adr);
2154
2155 if (netif_msg_hw(lp))
2156 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
2157 dev->name, index, addr);
2158 if (index & 1) {
2159 /* read modify write */
2160 tc_writel(cam_index - 2, &tr->CAM_Adr);
2161 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
2162 cam_data |= addr[0] << 8 | addr[1];
2163 tc_writel(cam_data, &tr->CAM_Data);
2164 /* write whole word */
2165 tc_writel(cam_index + 2, &tr->CAM_Adr);
2166 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
2167 tc_writel(cam_data, &tr->CAM_Data);
2168 } else {
2169 /* write whole word */
2170 tc_writel(cam_index, &tr->CAM_Adr);
2171 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
2172 tc_writel(cam_data, &tr->CAM_Data);
2173 /* read modify write */
2174 tc_writel(cam_index + 4, &tr->CAM_Adr);
2175 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
2176 cam_data |= addr[4] << 24 | (addr[5] << 16);
2177 tc_writel(cam_data, &tr->CAM_Data);
2178 }
2179
2180 tc_writel(saved_addr, &tr->CAM_Adr);
2181 }
2182
2183
2184 /*
2185 * Set or clear the multicast filter for this adaptor.
2186 * num_addrs == -1 Promiscuous mode, receive all packets
2187 * num_addrs == 0 Normal mode, clear multicast list
2188 * num_addrs > 0 Multicast mode, receive normal and MC packets,
2189 * and do best-effort filtering.
2190 */
2191 static void
2192 tc35815_set_multicast_list(struct net_device *dev)
2193 {
2194 struct tc35815_regs __iomem *tr =
2195 (struct tc35815_regs __iomem *)dev->base_addr;
2196
2197 if (dev->flags & IFF_PROMISC) {
2198 #ifdef WORKAROUND_100HALF_PROMISC
2199 /* With some (all?) 100MHalf HUB, controller will hang
2200 * if we enabled promiscuous mode before linkup... */
2201 struct tc35815_local *lp = netdev_priv(dev);
2202
2203 if (!lp->link)
2204 return;
2205 #endif
2206 /* Enable promiscuous mode */
2207 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
2208 } else if ((dev->flags & IFF_ALLMULTI) ||
2209 dev->mc_count > CAM_ENTRY_MAX - 3) {
2210 /* CAM 0, 1, 20 are reserved. */
2211 /* Disable promiscuous mode, use normal mode. */
2212 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
2213 } else if (dev->mc_count) {
2214 struct dev_mc_list *cur_addr = dev->mc_list;
2215 int i;
2216 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
2217
2218 tc_writel(0, &tr->CAM_Ctl);
2219 /* Walk the address list, and load the filter */
2220 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
2221 if (!cur_addr)
2222 break;
2223 /* entry 0,1 is reserved. */
2224 tc35815_set_cam_entry(dev, i + 2, cur_addr->dmi_addr);
2225 ena_bits |= CAM_Ena_Bit(i + 2);
2226 }
2227 tc_writel(ena_bits, &tr->CAM_Ena);
2228 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2229 } else {
2230 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2231 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2232 }
2233 }
2234
2235 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2236 {
2237 struct tc35815_local *lp = netdev_priv(dev);
2238 strcpy(info->driver, MODNAME);
2239 strcpy(info->version, DRV_VERSION);
2240 strcpy(info->bus_info, pci_name(lp->pci_dev));
2241 }
2242
2243 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2244 {
2245 struct tc35815_local *lp = netdev_priv(dev);
2246
2247 if (!lp->phy_dev)
2248 return -ENODEV;
2249 return phy_ethtool_gset(lp->phy_dev, cmd);
2250 }
2251
2252 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2253 {
2254 struct tc35815_local *lp = netdev_priv(dev);
2255
2256 if (!lp->phy_dev)
2257 return -ENODEV;
2258 return phy_ethtool_sset(lp->phy_dev, cmd);
2259 }
2260
2261 static u32 tc35815_get_msglevel(struct net_device *dev)
2262 {
2263 struct tc35815_local *lp = netdev_priv(dev);
2264 return lp->msg_enable;
2265 }
2266
2267 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
2268 {
2269 struct tc35815_local *lp = netdev_priv(dev);
2270 lp->msg_enable = datum;
2271 }
2272
2273 static int tc35815_get_sset_count(struct net_device *dev, int sset)
2274 {
2275 struct tc35815_local *lp = netdev_priv(dev);
2276
2277 switch (sset) {
2278 case ETH_SS_STATS:
2279 return sizeof(lp->lstats) / sizeof(int);
2280 default:
2281 return -EOPNOTSUPP;
2282 }
2283 }
2284
2285 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2286 {
2287 struct tc35815_local *lp = netdev_priv(dev);
2288 data[0] = lp->lstats.max_tx_qlen;
2289 data[1] = lp->lstats.tx_ints;
2290 data[2] = lp->lstats.rx_ints;
2291 data[3] = lp->lstats.tx_underrun;
2292 }
2293
2294 static struct {
2295 const char str[ETH_GSTRING_LEN];
2296 } ethtool_stats_keys[] = {
2297 { "max_tx_qlen" },
2298 { "tx_ints" },
2299 { "rx_ints" },
2300 { "tx_underrun" },
2301 };
2302
2303 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2304 {
2305 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2306 }
2307
2308 static const struct ethtool_ops tc35815_ethtool_ops = {
2309 .get_drvinfo = tc35815_get_drvinfo,
2310 .get_settings = tc35815_get_settings,
2311 .set_settings = tc35815_set_settings,
2312 .get_link = ethtool_op_get_link,
2313 .get_msglevel = tc35815_get_msglevel,
2314 .set_msglevel = tc35815_set_msglevel,
2315 .get_strings = tc35815_get_strings,
2316 .get_sset_count = tc35815_get_sset_count,
2317 .get_ethtool_stats = tc35815_get_ethtool_stats,
2318 };
2319
2320 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2321 {
2322 struct tc35815_local *lp = netdev_priv(dev);
2323
2324 if (!netif_running(dev))
2325 return -EINVAL;
2326 if (!lp->phy_dev)
2327 return -ENODEV;
2328 return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
2329 }
2330
2331 static void tc35815_chip_reset(struct net_device *dev)
2332 {
2333 struct tc35815_regs __iomem *tr =
2334 (struct tc35815_regs __iomem *)dev->base_addr;
2335 int i;
2336 /* reset the controller */
2337 tc_writel(MAC_Reset, &tr->MAC_Ctl);
2338 udelay(4); /* 3200ns */
2339 i = 0;
2340 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2341 if (i++ > 100) {
2342 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2343 break;
2344 }
2345 mdelay(1);
2346 }
2347 tc_writel(0, &tr->MAC_Ctl);
2348
2349 /* initialize registers to default value */
2350 tc_writel(0, &tr->DMA_Ctl);
2351 tc_writel(0, &tr->TxThrsh);
2352 tc_writel(0, &tr->TxPollCtr);
2353 tc_writel(0, &tr->RxFragSize);
2354 tc_writel(0, &tr->Int_En);
2355 tc_writel(0, &tr->FDA_Bas);
2356 tc_writel(0, &tr->FDA_Lim);
2357 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
2358 tc_writel(0, &tr->CAM_Ctl);
2359 tc_writel(0, &tr->Tx_Ctl);
2360 tc_writel(0, &tr->Rx_Ctl);
2361 tc_writel(0, &tr->CAM_Ena);
2362 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
2363
2364 /* initialize internal SRAM */
2365 tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2366 for (i = 0; i < 0x1000; i += 4) {
2367 tc_writel(i, &tr->CAM_Adr);
2368 tc_writel(0, &tr->CAM_Data);
2369 }
2370 tc_writel(0, &tr->DMA_Ctl);
2371 }
2372
2373 static void tc35815_chip_init(struct net_device *dev)
2374 {
2375 struct tc35815_local *lp = netdev_priv(dev);
2376 struct tc35815_regs __iomem *tr =
2377 (struct tc35815_regs __iomem *)dev->base_addr;
2378 unsigned long txctl = TX_CTL_CMD;
2379
2380 /* load station address to CAM */
2381 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2382
2383 /* Enable CAM (broadcast and unicast) */
2384 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2385 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2386
2387 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2388 if (HAVE_DMA_RXALIGN(lp))
2389 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2390 else
2391 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2392 #ifdef TC35815_USE_PACKEDBUFFER
2393 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
2394 #else
2395 tc_writel(ETH_ZLEN, &tr->RxFragSize);
2396 #endif
2397 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
2398 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2399 tc_writel(INT_EN_CMD, &tr->Int_En);
2400
2401 /* set queues */
2402 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2403 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2404 &tr->FDA_Lim);
2405 /*
2406 * Activation method:
2407 * First, enable the MAC Transmitter and the DMA Receive circuits.
2408 * Then enable the DMA Transmitter and the MAC Receive circuits.
2409 */
2410 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
2411 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
2412
2413 /* start MAC transmitter */
2414 #ifndef NO_CHECK_CARRIER
2415 /* TX4939 does not have EnLCarr */
2416 if (lp->chiptype == TC35815_TX4939)
2417 txctl &= ~Tx_EnLCarr;
2418 #ifdef WORKAROUND_LOSTCAR
2419 /* WORKAROUND: ignore LostCrS in full duplex operation */
2420 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL)
2421 txctl &= ~Tx_EnLCarr;
2422 #endif
2423 #endif /* !NO_CHECK_CARRIER */
2424 #ifdef GATHER_TXINT
2425 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
2426 #endif
2427 tc_writel(txctl, &tr->Tx_Ctl);
2428 }
2429
2430 #ifdef CONFIG_PM
2431 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2432 {
2433 struct net_device *dev = pci_get_drvdata(pdev);
2434 struct tc35815_local *lp = netdev_priv(dev);
2435 unsigned long flags;
2436
2437 pci_save_state(pdev);
2438 if (!netif_running(dev))
2439 return 0;
2440 netif_device_detach(dev);
2441 if (lp->phy_dev)
2442 phy_stop(lp->phy_dev);
2443 spin_lock_irqsave(&lp->lock, flags);
2444 tc35815_chip_reset(dev);
2445 spin_unlock_irqrestore(&lp->lock, flags);
2446 pci_set_power_state(pdev, PCI_D3hot);
2447 return 0;
2448 }
2449
2450 static int tc35815_resume(struct pci_dev *pdev)
2451 {
2452 struct net_device *dev = pci_get_drvdata(pdev);
2453 struct tc35815_local *lp = netdev_priv(dev);
2454
2455 pci_restore_state(pdev);
2456 if (!netif_running(dev))
2457 return 0;
2458 pci_set_power_state(pdev, PCI_D0);
2459 tc35815_restart(dev);
2460 netif_carrier_off(dev);
2461 if (lp->phy_dev)
2462 phy_start(lp->phy_dev);
2463 netif_device_attach(dev);
2464 return 0;
2465 }
2466 #endif /* CONFIG_PM */
2467
2468 static struct pci_driver tc35815_pci_driver = {
2469 .name = MODNAME,
2470 .id_table = tc35815_pci_tbl,
2471 .probe = tc35815_init_one,
2472 .remove = __devexit_p(tc35815_remove_one),
2473 #ifdef CONFIG_PM
2474 .suspend = tc35815_suspend,
2475 .resume = tc35815_resume,
2476 #endif
2477 };
2478
2479 module_param_named(speed, options.speed, int, 0);
2480 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2481 module_param_named(duplex, options.duplex, int, 0);
2482 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2483
2484 static int __init tc35815_init_module(void)
2485 {
2486 return pci_register_driver(&tc35815_pci_driver);
2487 }
2488
2489 static void __exit tc35815_cleanup_module(void)
2490 {
2491 pci_unregister_driver(&tc35815_pci_driver);
2492 }
2493
2494 module_init(tc35815_init_module);
2495 module_exit(tc35815_cleanup_module);
2496
2497 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2498 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree