1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
28 #include "psb_intel_reg.h"
29 #include "psb_powermgmt.h"
37 psb_pipestat(int pipe
)
49 mid_pipe_event(int pipe
)
52 return _PSB_PIPEA_EVENT_FLAG
;
54 return _MDFLD_PIPEB_EVENT_FLAG
;
56 return _MDFLD_PIPEC_EVENT_FLAG
;
61 mid_pipe_vsync(int pipe
)
64 return _PSB_VSYNC_PIPEA_FLAG
;
66 return _PSB_VSYNC_PIPEB_FLAG
;
68 return _MDFLD_PIPEC_VBLANK_FLAG
;
73 mid_pipeconf(int pipe
)
85 psb_enable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
87 if ((dev_priv
->pipestat
[pipe
] & mask
) != mask
) {
88 u32 reg
= psb_pipestat(pipe
);
89 dev_priv
->pipestat
[pipe
] |= mask
;
90 /* Enable the interrupt, clear any pending status */
91 if (gma_power_begin(dev_priv
->dev
, false)) {
92 u32 writeVal
= PSB_RVDC32(reg
);
93 writeVal
|= (mask
| (mask
>> 16));
94 PSB_WVDC32(writeVal
, reg
);
95 (void) PSB_RVDC32(reg
);
96 gma_power_end(dev_priv
->dev
);
102 psb_disable_pipestat(struct drm_psb_private
*dev_priv
, int pipe
, u32 mask
)
104 if ((dev_priv
->pipestat
[pipe
] & mask
) != 0) {
105 u32 reg
= psb_pipestat(pipe
);
106 dev_priv
->pipestat
[pipe
] &= ~mask
;
107 if (gma_power_begin(dev_priv
->dev
, false)) {
108 u32 writeVal
= PSB_RVDC32(reg
);
110 PSB_WVDC32(writeVal
, reg
);
111 (void) PSB_RVDC32(reg
);
112 gma_power_end(dev_priv
->dev
);
117 void mid_enable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
119 if (gma_power_begin(dev_priv
->dev
, false)) {
120 u32 pipe_event
= mid_pipe_event(pipe
);
121 dev_priv
->vdc_irq_mask
|= pipe_event
;
122 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
123 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
124 gma_power_end(dev_priv
->dev
);
128 void mid_disable_pipe_event(struct drm_psb_private
*dev_priv
, int pipe
)
130 if (dev_priv
->pipestat
[pipe
] == 0) {
131 if (gma_power_begin(dev_priv
->dev
, false)) {
132 u32 pipe_event
= mid_pipe_event(pipe
);
133 dev_priv
->vdc_irq_mask
&= ~pipe_event
;
134 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
135 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
136 gma_power_end(dev_priv
->dev
);
142 * Display controller interrupt handler for vsync/vblank.
145 static void mid_vblank_handler(struct drm_device
*dev
, uint32_t pipe
)
147 drm_handle_vblank(dev
, pipe
);
152 * Display controller interrupt handler for pipe event.
155 #define WAIT_STATUS_CLEAR_LOOP_COUNT 0xffff
156 static void mid_pipe_event_handler(struct drm_device
*dev
, uint32_t pipe
)
158 struct drm_psb_private
*dev_priv
=
159 (struct drm_psb_private
*) dev
->dev_private
;
161 uint32_t pipe_stat_val
= 0;
162 uint32_t pipe_stat_reg
= psb_pipestat(pipe
);
163 uint32_t pipe_enable
= dev_priv
->pipestat
[pipe
];
164 uint32_t pipe_status
= dev_priv
->pipestat
[pipe
] >> 16;
167 spin_lock(&dev_priv
->irqmask_lock
);
169 pipe_stat_val
= PSB_RVDC32(pipe_stat_reg
);
170 pipe_stat_val
&= pipe_enable
| pipe_status
;
171 pipe_stat_val
&= pipe_stat_val
>> 16;
173 spin_unlock(&dev_priv
->irqmask_lock
);
175 /* clear the 2nd level interrupt status bits */
177 * FIXME: shouldn't use while loop here. However, the interrupt
178 * status 'sticky' bits cannot be cleared by setting '1' to that
181 for (i
= 0; i
< WAIT_STATUS_CLEAR_LOOP_COUNT
; i
++) {
182 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg
), pipe_stat_reg
);
183 (void) PSB_RVDC32(pipe_stat_reg
);
185 if ((PSB_RVDC32(pipe_stat_reg
) & pipe_status
) == 0)
189 if (i
== WAIT_STATUS_CLEAR_LOOP_COUNT
)
190 DRM_ERROR("%s, can't clear the status bits in pipe_stat_reg, its value = 0x%x.\n",
191 __func__
, PSB_RVDC32(pipe_stat_reg
));
193 if (pipe_stat_val
& PIPE_VBLANK_STATUS
)
194 mid_vblank_handler(dev
, pipe
);
196 if (pipe_stat_val
& PIPE_TE_STATUS
)
197 drm_handle_vblank(dev
, pipe
);
201 * Display controller interrupt handler.
203 static void psb_vdc_interrupt(struct drm_device
*dev
, uint32_t vdc_stat
)
205 if (vdc_stat
& _PSB_PIPEA_EVENT_FLAG
)
206 mid_pipe_event_handler(dev
, 0);
209 irqreturn_t
psb_irq_handler(DRM_IRQ_ARGS
)
211 struct drm_device
*dev
= (struct drm_device
*) arg
;
212 struct drm_psb_private
*dev_priv
=
213 (struct drm_psb_private
*) dev
->dev_private
;
215 uint32_t vdc_stat
, dsp_int
= 0, sgx_int
= 0;
218 spin_lock(&dev_priv
->irqmask_lock
);
220 vdc_stat
= PSB_RVDC32(PSB_INT_IDENTITY_R
);
222 if (vdc_stat
& _MDFLD_DISP_ALL_IRQ_FLAG
) {
223 PSB_DEBUG_IRQ("Got DISP interrupt\n");
227 if (vdc_stat
& _PSB_IRQ_SGX_FLAG
) {
228 PSB_DEBUG_IRQ("Got SGX interrupt\n");
231 if (vdc_stat
& _PSB_IRQ_MSVDX_FLAG
)
232 PSB_DEBUG_IRQ("Got MSVDX interrupt\n");
234 if (vdc_stat
& _LNC_IRQ_TOPAZ_FLAG
)
235 PSB_DEBUG_IRQ("Got TOPAZ interrupt\n");
238 vdc_stat
&= dev_priv
->vdc_irq_mask
;
239 spin_unlock(&dev_priv
->irqmask_lock
);
241 if (dsp_int
&& gma_power_is_on(dev
)) {
242 psb_vdc_interrupt(dev
, vdc_stat
);
247 /* Not expected - we have it masked, shut it up */
249 s
= PSB_RSGX32(PSB_CR_EVENT_STATUS
);
250 s2
= PSB_RSGX32(PSB_CR_EVENT_STATUS2
);
251 PSB_WSGX32(s
, PSB_CR_EVENT_HOST_CLEAR
);
252 PSB_WSGX32(s2
, PSB_CR_EVENT_HOST_CLEAR2
);
253 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
254 we may as well poll even if we add that ! */
258 PSB_WVDC32(vdc_stat
, PSB_INT_IDENTITY_R
);
259 (void) PSB_RVDC32(PSB_INT_IDENTITY_R
);
260 DRM_READMEMORYBARRIER();
268 void psb_irq_preinstall(struct drm_device
*dev
)
270 struct drm_psb_private
*dev_priv
=
271 (struct drm_psb_private
*) dev
->dev_private
;
272 unsigned long irqflags
;
274 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
276 if (gma_power_is_on(dev
))
277 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
278 if (dev
->vblank_enabled
[0])
279 dev_priv
->vdc_irq_mask
|= _PSB_PIPEA_EVENT_FLAG
;
280 if (dev
->vblank_enabled
[1])
281 dev_priv
->vdc_irq_mask
|= _MDFLD_PIPEB_EVENT_FLAG
;
282 if (dev
->vblank_enabled
[2])
283 dev_priv
->vdc_irq_mask
|= _MDFLD_PIPEC_EVENT_FLAG
;
285 /*This register is safe even if display island is off*/
286 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
287 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
290 int psb_irq_postinstall(struct drm_device
*dev
)
292 struct drm_psb_private
*dev_priv
=
293 (struct drm_psb_private
*) dev
->dev_private
;
294 unsigned long irqflags
;
296 PSB_DEBUG_ENTRY("\n");
298 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
300 /* This register is safe even if display island is off */
301 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
302 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
304 if (dev
->vblank_enabled
[0])
305 psb_enable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
307 psb_disable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
309 if (dev
->vblank_enabled
[1])
310 psb_enable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
312 psb_disable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
314 if (dev
->vblank_enabled
[2])
315 psb_enable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
317 psb_disable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
319 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
323 void psb_irq_uninstall(struct drm_device
*dev
)
325 struct drm_psb_private
*dev_priv
=
326 (struct drm_psb_private
*) dev
->dev_private
;
327 unsigned long irqflags
;
329 PSB_DEBUG_ENTRY("\n");
331 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
333 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM
);
335 if (dev
->vblank_enabled
[0])
336 psb_disable_pipestat(dev_priv
, 0, PIPE_VBLANK_INTERRUPT_ENABLE
);
338 if (dev
->vblank_enabled
[1])
339 psb_disable_pipestat(dev_priv
, 1, PIPE_VBLANK_INTERRUPT_ENABLE
);
341 if (dev
->vblank_enabled
[2])
342 psb_disable_pipestat(dev_priv
, 2, PIPE_VBLANK_INTERRUPT_ENABLE
);
344 dev_priv
->vdc_irq_mask
&= _PSB_IRQ_SGX_FLAG
|
345 _PSB_IRQ_MSVDX_FLAG
|
348 /* These two registers are safe even if display island is off */
349 PSB_WVDC32(~dev_priv
->vdc_irq_mask
, PSB_INT_MASK_R
);
350 PSB_WVDC32(dev_priv
->vdc_irq_mask
, PSB_INT_ENABLE_R
);
354 /* This register is safe even if display island is off */
355 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R
), PSB_INT_IDENTITY_R
);
356 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
359 void psb_irq_turn_on_dpst(struct drm_device
*dev
)
361 struct drm_psb_private
*dev_priv
=
362 (struct drm_psb_private
*) dev
->dev_private
;
366 if (gma_power_begin(dev
, false)) {
367 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL
);
368 hist_reg
= PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL
);
369 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL
);
370 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
372 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC
);
373 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
374 PSB_WVDC32(pwm_reg
| PWM_PHASEIN_ENABLE
375 | PWM_PHASEIN_INT_ENABLE
,
377 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
379 psb_enable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
381 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
382 PSB_WVDC32(hist_reg
| HISTOGRAM_INT_CTRL_CLEAR
,
383 HISTOGRAM_INT_CONTROL
);
384 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
385 PSB_WVDC32(pwm_reg
| 0x80010100 | PWM_PHASEIN_ENABLE
,
392 int psb_irq_enable_dpst(struct drm_device
*dev
)
394 struct drm_psb_private
*dev_priv
=
395 (struct drm_psb_private
*) dev
->dev_private
;
396 unsigned long irqflags
;
398 PSB_DEBUG_ENTRY("\n");
400 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
403 mid_enable_pipe_event(dev_priv
, 0);
404 psb_irq_turn_on_dpst(dev
);
406 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
410 void psb_irq_turn_off_dpst(struct drm_device
*dev
)
412 struct drm_psb_private
*dev_priv
=
413 (struct drm_psb_private
*) dev
->dev_private
;
417 if (gma_power_begin(dev
, false)) {
418 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL
);
419 hist_reg
= PSB_RVDC32(HISTOGRAM_INT_CONTROL
);
421 psb_disable_pipestat(dev_priv
, 0, PIPE_DPST_EVENT_ENABLE
);
423 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
424 PSB_WVDC32(pwm_reg
& !(PWM_PHASEIN_INT_ENABLE
),
426 pwm_reg
= PSB_RVDC32(PWM_CONTROL_LOGIC
);
432 int psb_irq_disable_dpst(struct drm_device
*dev
)
434 struct drm_psb_private
*dev_priv
=
435 (struct drm_psb_private
*) dev
->dev_private
;
436 unsigned long irqflags
;
438 PSB_DEBUG_ENTRY("\n");
440 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
442 mid_disable_pipe_event(dev_priv
, 0);
443 psb_irq_turn_off_dpst(dev
);
445 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
451 static int psb_vblank_do_wait(struct drm_device
*dev
,
452 unsigned int *sequence
, atomic_t
*counter
)
454 unsigned int cur_vblank
;
456 DRM_WAIT_ON(ret
, dev
->vbl_queue
, 3 * DRM_HZ
,
457 (((cur_vblank
= atomic_read(counter
))
458 - *sequence
) <= (1 << 23)));
459 *sequence
= cur_vblank
;
466 * It is used to enable VBLANK interrupt
468 int psb_enable_vblank(struct drm_device
*dev
, int pipe
)
470 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
471 unsigned long irqflags
;
472 uint32_t reg_val
= 0;
473 uint32_t pipeconf_reg
= mid_pipeconf(pipe
);
475 PSB_DEBUG_ENTRY("\n");
477 if (gma_power_begin(dev
, false)) {
478 reg_val
= REG_READ(pipeconf_reg
);
482 if (!(reg_val
& PIPEACONF_ENABLE
))
485 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
487 mid_enable_pipe_event(dev_priv
, pipe
);
488 psb_enable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
490 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
496 * It is used to disable VBLANK interrupt
498 void psb_disable_vblank(struct drm_device
*dev
, int pipe
)
500 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
501 unsigned long irqflags
;
503 PSB_DEBUG_ENTRY("\n");
505 spin_lock_irqsave(&dev_priv
->irqmask_lock
, irqflags
);
507 mid_disable_pipe_event(dev_priv
, pipe
);
508 psb_disable_pipestat(dev_priv
, pipe
, PIPE_VBLANK_INTERRUPT_ENABLE
);
510 spin_unlock_irqrestore(&dev_priv
->irqmask_lock
, irqflags
);
513 /* Called from drm generic code, passed a 'crtc', which
514 * we use as a pipe index
516 u32
psb_get_vblank_counter(struct drm_device
*dev
, int pipe
)
518 uint32_t high_frame
= PIPEAFRAMEHIGH
;
519 uint32_t low_frame
= PIPEAFRAMEPIXEL
;
520 uint32_t pipeconf_reg
= PIPEACONF
;
521 uint32_t reg_val
= 0;
522 uint32_t high1
= 0, high2
= 0, low
= 0, count
= 0;
528 high_frame
= PIPEBFRAMEHIGH
;
529 low_frame
= PIPEBFRAMEPIXEL
;
530 pipeconf_reg
= PIPEBCONF
;
533 high_frame
= PIPECFRAMEHIGH
;
534 low_frame
= PIPECFRAMEPIXEL
;
535 pipeconf_reg
= PIPECCONF
;
538 DRM_ERROR("%s, invalded pipe.\n", __func__
);
542 if (!gma_power_begin(dev
, false))
545 reg_val
= REG_READ(pipeconf_reg
);
547 if (!(reg_val
& PIPEACONF_ENABLE
)) {
548 DRM_ERROR("trying to get vblank count for disabled pipe %d\n",
550 goto psb_get_vblank_counter_exit
;
554 * High & low register fields aren't synchronized, so make sure
555 * we get a low value that's stable across two reads of the high
559 high1
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
560 PIPE_FRAME_HIGH_SHIFT
);
561 low
= ((REG_READ(low_frame
) & PIPE_FRAME_LOW_MASK
) >>
562 PIPE_FRAME_LOW_SHIFT
);
563 high2
= ((REG_READ(high_frame
) & PIPE_FRAME_HIGH_MASK
) >>
564 PIPE_FRAME_HIGH_SHIFT
);
565 } while (high1
!= high2
);
567 count
= (high1
<< 8) | low
;
569 psb_get_vblank_counter_exit
: