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ath9k_hw: order phy.c code and integrate spur mitigation
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / phy.c
blob8e4c3bd84bc0b9f382b96fcdfd79ff7525611127
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 /**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42 #include "hw.h"
43
44 /**
45 * ath9k_hw_write_regs - ??
46 *
47 * @ah: atheros hardware structure
48 * @modesIndex:
49 * @freqIndex:
50 * @regWrites:
51 *
52 * Used for both the chipsets with an external AR2133/AR5133 radios and
53 * single-chip devices.
54 */
55 void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,
56 u32 freqIndex, int regWrites)
57 {
58 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
59 }
60
61 /**
62 * ath9k_hw_ar9280_set_channel - set channel on single-chip device
63 * @ah: atheros hardware structure
64 * @chan:
65 *
66 * This is the function to change channel on single-chip devices, that is
67 * all devices after ar9280.
68 *
69 * This function takes the channel value in MHz and sets
70 * hardware channel value. Assumes writes have been enabled to analog bus.
71 *
72 * Actual Expression,
73 *
74 * For 2GHz channel,
75 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
76 * (freq_ref = 40MHz)
77 *
78 * For 5GHz channel,
79 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
80 * (freq_ref = 40MHz/(24>>amodeRefSel))
81 */
82 int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
83 {
84 u16 bMode, fracMode, aModeRefSel = 0;
85 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
86 struct chan_centers centers;
87 u32 refDivA = 24;
88
89 ath9k_hw_get_channel_centers(ah, chan, &centers);
90 freq = centers.synth_center;
91
92 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
93 reg32 &= 0xc0000000;
94
95 if (freq < 4800) { /* 2 GHz, fractional mode */
96 u32 txctl;
97 int regWrites = 0;
98
99 bMode = 1;
100 fracMode = 1;
101 aModeRefSel = 0;
102 channelSel = (freq * 0x10000) / 15;
103
104 if (AR_SREV_9287_11_OR_LATER(ah)) {
105 if (freq == 2484) {
106 /* Enable channel spreading for channel 14 */
107 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
108 1, regWrites);
109 } else {
110 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
111 1, regWrites);
112 }
113 } else {
114 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
115 if (freq == 2484) {
116 /* Enable channel spreading for channel 14 */
117 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
118 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
119 } else {
120 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
121 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
122 }
123 }
124 } else {
125 bMode = 0;
126 fracMode = 0;
127
128 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
129 case 0:
130 if ((freq % 20) == 0) {
131 aModeRefSel = 3;
132 } else if ((freq % 10) == 0) {
133 aModeRefSel = 2;
134 }
135 if (aModeRefSel)
136 break;
137 case 1:
138 default:
139 aModeRefSel = 0;
140 /*
141 * Enable 2G (fractional) mode for channels
142 * which are 5MHz spaced.
143 */
144 fracMode = 1;
145 refDivA = 1;
146 channelSel = (freq * 0x8000) / 15;
147
148 /* RefDivA setting */
149 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
150 AR_AN_SYNTH9_REFDIVA, refDivA);
151
152 }
153
154 if (!fracMode) {
155 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
156 channelSel = ndiv & 0x1ff;
157 channelFrac = (ndiv & 0xfffffe00) * 2;
158 channelSel = (channelSel << 17) | channelFrac;
159 }
160 }
161
162 reg32 = reg32 |
163 (bMode << 29) |
164 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
165
166 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
167
168 ah->curchan = chan;
169 ah->curchan_rad_index = -1;
170
171 return 0;
172 }
173
174 /**
175 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
176 * @ah: atheros hardware structure
177 * @chan:
178 *
179 * For single-chip solutions. Converts to baseband spur frequency given the
180 * input channel frequency and compute register settings below.
181 */
182 void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
183 {
184 int bb_spur = AR_NO_SPUR;
185 int freq;
186 int bin, cur_bin;
187 int bb_spur_off, spur_subchannel_sd;
188 int spur_freq_sd;
189 int spur_delta_phase;
190 int denominator;
191 int upper, lower, cur_vit_mask;
192 int tmp, newVal;
193 int i;
194 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
195 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
196 };
197 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
198 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
199 };
200 int inc[4] = { 0, 100, 0, 0 };
201 struct chan_centers centers;
202
203 int8_t mask_m[123];
204 int8_t mask_p[123];
205 int8_t mask_amt;
206 int tmp_mask;
207 int cur_bb_spur;
208 bool is2GHz = IS_CHAN_2GHZ(chan);
209
210 memset(&mask_m, 0, sizeof(int8_t) * 123);
211 memset(&mask_p, 0, sizeof(int8_t) * 123);
212
213 ath9k_hw_get_channel_centers(ah, chan, &centers);
214 freq = centers.synth_center;
215
216 ah->config.spurmode = SPUR_ENABLE_EEPROM;
217 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
218 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
219
220 if (is2GHz)
221 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
222 else
223 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
224
225 if (AR_NO_SPUR == cur_bb_spur)
226 break;
227 cur_bb_spur = cur_bb_spur - freq;
228
229 if (IS_CHAN_HT40(chan)) {
230 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
231 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
232 bb_spur = cur_bb_spur;
233 break;
234 }
235 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
236 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
237 bb_spur = cur_bb_spur;
238 break;
239 }
240 }
241
242 if (AR_NO_SPUR == bb_spur) {
243 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
244 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
245 return;
246 } else {
247 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
248 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
249 }
250
251 bin = bb_spur * 320;
252
253 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
254
255 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
256 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
257 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
258 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
259 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
260
261 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
262 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
263 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
264 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
265 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
266 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
267
268 if (IS_CHAN_HT40(chan)) {
269 if (bb_spur < 0) {
270 spur_subchannel_sd = 1;
271 bb_spur_off = bb_spur + 10;
272 } else {
273 spur_subchannel_sd = 0;
274 bb_spur_off = bb_spur - 10;
275 }
276 } else {
277 spur_subchannel_sd = 0;
278 bb_spur_off = bb_spur;
279 }
280
281 if (IS_CHAN_HT40(chan))
282 spur_delta_phase =
283 ((bb_spur * 262144) /
284 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
285 else
286 spur_delta_phase =
287 ((bb_spur * 524288) /
288 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
289
290 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
291 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
292
293 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
294 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
295 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
296 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
297
298 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
299 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
300
301 cur_bin = -6000;
302 upper = bin + 100;
303 lower = bin - 100;
304
305 for (i = 0; i < 4; i++) {
306 int pilot_mask = 0;
307 int chan_mask = 0;
308 int bp = 0;
309 for (bp = 0; bp < 30; bp++) {
310 if ((cur_bin > lower) && (cur_bin < upper)) {
311 pilot_mask = pilot_mask | 0x1 << bp;
312 chan_mask = chan_mask | 0x1 << bp;
313 }
314 cur_bin += 100;
315 }
316 cur_bin += inc[i];
317 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
318 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
319 }
320
321 cur_vit_mask = 6100;
322 upper = bin + 120;
323 lower = bin - 120;
324
325 for (i = 0; i < 123; i++) {
326 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
327
328 /* workaround for gcc bug #37014 */
329 volatile int tmp_v = abs(cur_vit_mask - bin);
330
331 if (tmp_v < 75)
332 mask_amt = 1;
333 else
334 mask_amt = 0;
335 if (cur_vit_mask < 0)
336 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
337 else
338 mask_p[cur_vit_mask / 100] = mask_amt;
339 }
340 cur_vit_mask -= 100;
341 }
342
343 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
344 | (mask_m[48] << 26) | (mask_m[49] << 24)
345 | (mask_m[50] << 22) | (mask_m[51] << 20)
346 | (mask_m[52] << 18) | (mask_m[53] << 16)
347 | (mask_m[54] << 14) | (mask_m[55] << 12)
348 | (mask_m[56] << 10) | (mask_m[57] << 8)
349 | (mask_m[58] << 6) | (mask_m[59] << 4)
350 | (mask_m[60] << 2) | (mask_m[61] << 0);
351 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
352 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
353
354 tmp_mask = (mask_m[31] << 28)
355 | (mask_m[32] << 26) | (mask_m[33] << 24)
356 | (mask_m[34] << 22) | (mask_m[35] << 20)
357 | (mask_m[36] << 18) | (mask_m[37] << 16)
358 | (mask_m[48] << 14) | (mask_m[39] << 12)
359 | (mask_m[40] << 10) | (mask_m[41] << 8)
360 | (mask_m[42] << 6) | (mask_m[43] << 4)
361 | (mask_m[44] << 2) | (mask_m[45] << 0);
362 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
363 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
364
365 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
366 | (mask_m[18] << 26) | (mask_m[18] << 24)
367 | (mask_m[20] << 22) | (mask_m[20] << 20)
368 | (mask_m[22] << 18) | (mask_m[22] << 16)
369 | (mask_m[24] << 14) | (mask_m[24] << 12)
370 | (mask_m[25] << 10) | (mask_m[26] << 8)
371 | (mask_m[27] << 6) | (mask_m[28] << 4)
372 | (mask_m[29] << 2) | (mask_m[30] << 0);
373 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
374 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
375
376 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
377 | (mask_m[2] << 26) | (mask_m[3] << 24)
378 | (mask_m[4] << 22) | (mask_m[5] << 20)
379 | (mask_m[6] << 18) | (mask_m[7] << 16)
380 | (mask_m[8] << 14) | (mask_m[9] << 12)
381 | (mask_m[10] << 10) | (mask_m[11] << 8)
382 | (mask_m[12] << 6) | (mask_m[13] << 4)
383 | (mask_m[14] << 2) | (mask_m[15] << 0);
384 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
385 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
386
387 tmp_mask = (mask_p[15] << 28)
388 | (mask_p[14] << 26) | (mask_p[13] << 24)
389 | (mask_p[12] << 22) | (mask_p[11] << 20)
390 | (mask_p[10] << 18) | (mask_p[9] << 16)
391 | (mask_p[8] << 14) | (mask_p[7] << 12)
392 | (mask_p[6] << 10) | (mask_p[5] << 8)
393 | (mask_p[4] << 6) | (mask_p[3] << 4)
394 | (mask_p[2] << 2) | (mask_p[1] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
397
398 tmp_mask = (mask_p[30] << 28)
399 | (mask_p[29] << 26) | (mask_p[28] << 24)
400 | (mask_p[27] << 22) | (mask_p[26] << 20)
401 | (mask_p[25] << 18) | (mask_p[24] << 16)
402 | (mask_p[23] << 14) | (mask_p[22] << 12)
403 | (mask_p[21] << 10) | (mask_p[20] << 8)
404 | (mask_p[19] << 6) | (mask_p[18] << 4)
405 | (mask_p[17] << 2) | (mask_p[16] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
408
409 tmp_mask = (mask_p[45] << 28)
410 | (mask_p[44] << 26) | (mask_p[43] << 24)
411 | (mask_p[42] << 22) | (mask_p[41] << 20)
412 | (mask_p[40] << 18) | (mask_p[39] << 16)
413 | (mask_p[38] << 14) | (mask_p[37] << 12)
414 | (mask_p[36] << 10) | (mask_p[35] << 8)
415 | (mask_p[34] << 6) | (mask_p[33] << 4)
416 | (mask_p[32] << 2) | (mask_p[31] << 0);
417 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
419
420 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
421 | (mask_p[59] << 26) | (mask_p[58] << 24)
422 | (mask_p[57] << 22) | (mask_p[56] << 20)
423 | (mask_p[55] << 18) | (mask_p[54] << 16)
424 | (mask_p[53] << 14) | (mask_p[52] << 12)
425 | (mask_p[51] << 10) | (mask_p[50] << 8)
426 | (mask_p[49] << 6) | (mask_p[48] << 4)
427 | (mask_p[47] << 2) | (mask_p[46] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
430 }
431
432 /* All code below is for non single-chip solutions */
433
434 /**
435 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
436 * @ah: atheros hardware stucture
437 * @chan:
438 *
439 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
440 * the channel value. Assumes writes enabled to analog bus and bank6 register
441 * cache in ah->analogBank6Data.
442 */
443 int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
444 {
445 struct ath_common *common = ath9k_hw_common(ah);
446 u32 channelSel = 0;
447 u32 bModeSynth = 0;
448 u32 aModeRefSel = 0;
449 u32 reg32 = 0;
450 u16 freq;
451 struct chan_centers centers;
452
453 ath9k_hw_get_channel_centers(ah, chan, &centers);
454 freq = centers.synth_center;
455
456 if (freq < 4800) {
457 u32 txctl;
458
459 if (((freq - 2192) % 5) == 0) {
460 channelSel = ((freq - 672) * 2 - 3040) / 10;
461 bModeSynth = 0;
462 } else if (((freq - 2224) % 5) == 0) {
463 channelSel = ((freq - 704) * 2 - 3040) / 10;
464 bModeSynth = 1;
465 } else {
466 ath_print(common, ATH_DBG_FATAL,
467 "Invalid channel %u MHz\n", freq);
468 return -EINVAL;
469 }
470
471 channelSel = (channelSel << 2) & 0xff;
472 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
473
474 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
475 if (freq == 2484) {
476
477 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
478 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
479 } else {
480 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
481 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
482 }
483
484 } else if ((freq % 20) == 0 && freq >= 5120) {
485 channelSel =
486 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
487 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
488 } else if ((freq % 10) == 0) {
489 channelSel =
490 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
491 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
492 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
493 else
494 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
495 } else if ((freq % 5) == 0) {
496 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
497 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
498 } else {
499 ath_print(common, ATH_DBG_FATAL,
500 "Invalid channel %u MHz\n", freq);
501 return -EINVAL;
502 }
503
504 reg32 =
505 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
506 (1 << 5) | 0x1;
507
508 REG_WRITE(ah, AR_PHY(0x37), reg32);
509
510 ah->curchan = chan;
511 ah->curchan_rad_index = -1;
512
513 return 0;
514 }
515
516 /**
517 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios
518 * @ah: atheros hardware structure
519 * @chan:
520 *
521 * For non single-chip solutions. Converts to baseband spur frequency given the
522 * input channel frequency and compute register settings below.
523 */
524 void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
525 {
526 int bb_spur = AR_NO_SPUR;
527 int bin, cur_bin;
528 int spur_freq_sd;
529 int spur_delta_phase;
530 int denominator;
531 int upper, lower, cur_vit_mask;
532 int tmp, new;
533 int i;
534 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
535 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
536 };
537 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
538 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
539 };
540 int inc[4] = { 0, 100, 0, 0 };
541
542 int8_t mask_m[123];
543 int8_t mask_p[123];
544 int8_t mask_amt;
545 int tmp_mask;
546 int cur_bb_spur;
547 bool is2GHz = IS_CHAN_2GHZ(chan);
548
549 memset(&mask_m, 0, sizeof(int8_t) * 123);
550 memset(&mask_p, 0, sizeof(int8_t) * 123);
551
552 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
553 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
554 if (AR_NO_SPUR == cur_bb_spur)
555 break;
556 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
557 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
558 bb_spur = cur_bb_spur;
559 break;
560 }
561 }
562
563 if (AR_NO_SPUR == bb_spur)
564 return;
565
566 bin = bb_spur * 32;
567
568 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
569 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
570 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
571 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
572 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
573
574 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
575
576 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
577 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
578 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
579 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
580 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
581 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
582
583 spur_delta_phase = ((bb_spur * 524288) / 100) &
584 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
585
586 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
587 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
588
589 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
590 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
591 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
592 REG_WRITE(ah, AR_PHY_TIMING11, new);
593
594 cur_bin = -6000;
595 upper = bin + 100;
596 lower = bin - 100;
597
598 for (i = 0; i < 4; i++) {
599 int pilot_mask = 0;
600 int chan_mask = 0;
601 int bp = 0;
602 for (bp = 0; bp < 30; bp++) {
603 if ((cur_bin > lower) && (cur_bin < upper)) {
604 pilot_mask = pilot_mask | 0x1 << bp;
605 chan_mask = chan_mask | 0x1 << bp;
606 }
607 cur_bin += 100;
608 }
609 cur_bin += inc[i];
610 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
611 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
612 }
613
614 cur_vit_mask = 6100;
615 upper = bin + 120;
616 lower = bin - 120;
617
618 for (i = 0; i < 123; i++) {
619 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
620
621 /* workaround for gcc bug #37014 */
622 volatile int tmp_v = abs(cur_vit_mask - bin);
623
624 if (tmp_v < 75)
625 mask_amt = 1;
626 else
627 mask_amt = 0;
628 if (cur_vit_mask < 0)
629 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
630 else
631 mask_p[cur_vit_mask / 100] = mask_amt;
632 }
633 cur_vit_mask -= 100;
634 }
635
636 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
637 | (mask_m[48] << 26) | (mask_m[49] << 24)
638 | (mask_m[50] << 22) | (mask_m[51] << 20)
639 | (mask_m[52] << 18) | (mask_m[53] << 16)
640 | (mask_m[54] << 14) | (mask_m[55] << 12)
641 | (mask_m[56] << 10) | (mask_m[57] << 8)
642 | (mask_m[58] << 6) | (mask_m[59] << 4)
643 | (mask_m[60] << 2) | (mask_m[61] << 0);
644 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
645 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
646
647 tmp_mask = (mask_m[31] << 28)
648 | (mask_m[32] << 26) | (mask_m[33] << 24)
649 | (mask_m[34] << 22) | (mask_m[35] << 20)
650 | (mask_m[36] << 18) | (mask_m[37] << 16)
651 | (mask_m[48] << 14) | (mask_m[39] << 12)
652 | (mask_m[40] << 10) | (mask_m[41] << 8)
653 | (mask_m[42] << 6) | (mask_m[43] << 4)
654 | (mask_m[44] << 2) | (mask_m[45] << 0);
655 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
656 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
657
658 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
659 | (mask_m[18] << 26) | (mask_m[18] << 24)
660 | (mask_m[20] << 22) | (mask_m[20] << 20)
661 | (mask_m[22] << 18) | (mask_m[22] << 16)
662 | (mask_m[24] << 14) | (mask_m[24] << 12)
663 | (mask_m[25] << 10) | (mask_m[26] << 8)
664 | (mask_m[27] << 6) | (mask_m[28] << 4)
665 | (mask_m[29] << 2) | (mask_m[30] << 0);
666 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
667 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
668
669 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
670 | (mask_m[2] << 26) | (mask_m[3] << 24)
671 | (mask_m[4] << 22) | (mask_m[5] << 20)
672 | (mask_m[6] << 18) | (mask_m[7] << 16)
673 | (mask_m[8] << 14) | (mask_m[9] << 12)
674 | (mask_m[10] << 10) | (mask_m[11] << 8)
675 | (mask_m[12] << 6) | (mask_m[13] << 4)
676 | (mask_m[14] << 2) | (mask_m[15] << 0);
677 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
678 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
679
680 tmp_mask = (mask_p[15] << 28)
681 | (mask_p[14] << 26) | (mask_p[13] << 24)
682 | (mask_p[12] << 22) | (mask_p[11] << 20)
683 | (mask_p[10] << 18) | (mask_p[9] << 16)
684 | (mask_p[8] << 14) | (mask_p[7] << 12)
685 | (mask_p[6] << 10) | (mask_p[5] << 8)
686 | (mask_p[4] << 6) | (mask_p[3] << 4)
687 | (mask_p[2] << 2) | (mask_p[1] << 0);
688 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
689 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
690
691 tmp_mask = (mask_p[30] << 28)
692 | (mask_p[29] << 26) | (mask_p[28] << 24)
693 | (mask_p[27] << 22) | (mask_p[26] << 20)
694 | (mask_p[25] << 18) | (mask_p[24] << 16)
695 | (mask_p[23] << 14) | (mask_p[22] << 12)
696 | (mask_p[21] << 10) | (mask_p[20] << 8)
697 | (mask_p[19] << 6) | (mask_p[18] << 4)
698 | (mask_p[17] << 2) | (mask_p[16] << 0);
699 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
700 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
701
702 tmp_mask = (mask_p[45] << 28)
703 | (mask_p[44] << 26) | (mask_p[43] << 24)
704 | (mask_p[42] << 22) | (mask_p[41] << 20)
705 | (mask_p[40] << 18) | (mask_p[39] << 16)
706 | (mask_p[38] << 14) | (mask_p[37] << 12)
707 | (mask_p[36] << 10) | (mask_p[35] << 8)
708 | (mask_p[34] << 6) | (mask_p[33] << 4)
709 | (mask_p[32] << 2) | (mask_p[31] << 0);
710 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
711 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
712
713 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
714 | (mask_p[59] << 26) | (mask_p[58] << 24)
715 | (mask_p[57] << 22) | (mask_p[56] << 20)
716 | (mask_p[55] << 18) | (mask_p[54] << 16)
717 | (mask_p[53] << 14) | (mask_p[52] << 12)
718 | (mask_p[51] << 10) | (mask_p[50] << 8)
719 | (mask_p[49] << 6) | (mask_p[48] << 4)
720 | (mask_p[47] << 2) | (mask_p[46] << 0);
721 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
722 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
723 }
724
725 /**
726 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming
727 * @ah: atheros hardware structure
728 *
729 * Only required for older devices with external AR2133/AR5133 radios.
730 */
731 int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
732 {
733 #define ATH_ALLOC_BANK(bank, size) do { \
734 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
735 if (!bank) { \
736 ath_print(common, ATH_DBG_FATAL, \
737 "Cannot allocate RF banks\n"); \
738 return -ENOMEM; \
739 } \
740 } while (0);
741
742 struct ath_common *common = ath9k_hw_common(ah);
743
744 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
745
746 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
747 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
748 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
749 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
750 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
751 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
752 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
753 ATH_ALLOC_BANK(ah->addac5416_21,
754 ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
755 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
756
757 return 0;
758 #undef ATH_ALLOC_BANK
759 }
760
761
762 /**
763 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
764 * @ah: atheros hardware struture
765 * For the external AR2133/AR5133 radios banks.
766 */
767 void
768 ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
769 {
770 #define ATH_FREE_BANK(bank) do { \
771 kfree(bank); \
772 bank = NULL; \
773 } while (0);
774
775 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
776
777 ATH_FREE_BANK(ah->analogBank0Data);
778 ATH_FREE_BANK(ah->analogBank1Data);
779 ATH_FREE_BANK(ah->analogBank2Data);
780 ATH_FREE_BANK(ah->analogBank3Data);
781 ATH_FREE_BANK(ah->analogBank6Data);
782 ATH_FREE_BANK(ah->analogBank6TPCData);
783 ATH_FREE_BANK(ah->analogBank7Data);
784 ATH_FREE_BANK(ah->addac5416_21);
785 ATH_FREE_BANK(ah->bank6Temp);
786
787 #undef ATH_FREE_BANK
788 }
789
790 /**
791 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters
792 * @rfbuf:
793 * @reg32:
794 * @numBits:
795 * @firstBit:
796 * @column:
797 *
798 * Performs analog "swizzling" of parameters into their location.
799 * Used on external AR2133/AR5133 radios.
800 */
801 static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
802 u32 numBits, u32 firstBit,
803 u32 column)
804 {
805 u32 tmp32, mask, arrayEntry, lastBit;
806 int32_t bitPosition, bitsLeft;
807
808 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
809 arrayEntry = (firstBit - 1) / 8;
810 bitPosition = (firstBit - 1) % 8;
811 bitsLeft = numBits;
812 while (bitsLeft > 0) {
813 lastBit = (bitPosition + bitsLeft > 8) ?
814 8 : bitPosition + bitsLeft;
815 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
816 (column * 8);
817 rfBuf[arrayEntry] &= ~mask;
818 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
819 (column * 8)) & mask;
820 bitsLeft -= 8 - bitPosition;
821 tmp32 = tmp32 >> (8 - bitPosition);
822 bitPosition = 0;
823 arrayEntry++;
824 }
825 }
826
827 /* *
828 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM
829 * @ah: atheros hardware structure
830 * @chan:
831 * @modesIndex:
832 *
833 * Used for the external AR2133/AR5133 radios.
834 *
835 * Reads the EEPROM header info from the device structure and programs
836 * all rf registers. This routine requires access to the analog
837 * rf device. This is not required for single-chip devices.
838 */
839 bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
840 u16 modesIndex)
841 {
842 u32 eepMinorRev;
843 u32 ob5GHz = 0, db5GHz = 0;
844 u32 ob2GHz = 0, db2GHz = 0;
845 int regWrites = 0;
846
847 /*
848 * Software does not need to program bank data
849 * for single chip devices, that is AR9280 or anything
850 * after that.
851 */
852 if (AR_SREV_9280_10_OR_LATER(ah))
853 return true;
854
855 /* Setup rf parameters */
856 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
857
858 /* Setup Bank 0 Write */
859 RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
860
861 /* Setup Bank 1 Write */
862 RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
863
864 /* Setup Bank 2 Write */
865 RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
866
867 /* Setup Bank 6 Write */
868 RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
869 modesIndex);
870 {
871 int i;
872 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
873 ah->analogBank6Data[i] =
874 INI_RA(&ah->iniBank6TPC, i, modesIndex);
875 }
876 }
877
878 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
879 if (eepMinorRev >= 2) {
880 if (IS_CHAN_2GHZ(chan)) {
881 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
882 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
883 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
884 ob2GHz, 3, 197, 0);
885 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
886 db2GHz, 3, 194, 0);
887 } else {
888 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
889 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
890 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
891 ob5GHz, 3, 203, 0);
892 ath9k_phy_modify_rx_buffer(ah->analogBank6Data,
893 db5GHz, 3, 200, 0);
894 }
895 }
896
897 /* Setup Bank 7 Setup */
898 RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
899
900 /* Write Analog registers */
901 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
902 regWrites);
903 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
904 regWrites);
905 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
906 regWrites);
907 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
908 regWrites);
909 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
910 regWrites);
911 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
912 regWrites);
913
914 return true;
915 }
916
917 /**
918 * ath9k_hw_decrease_chain_power()
919 *
920 * @ah: atheros hardware structure
921 * @chan:
922 *
923 * Only used on the AR5416 and AR5418 with the external AR2133/AR5133 radios.
924 *
925 * Sets a chain internal RF path to the lowest output power. Any
926 * further writes to bank6 after this setting will override these
927 * changes. Thus this function must be the last function in the
928 * sequence to modify bank 6.
929 *
930 * This function must be called after ar5416SetRfRegs() which is
931 * called from ath9k_hw_process_ini() due to swizzling of bank 6.
932 * Depends on ah->analogBank6Data being initialized by
933 * ath9k_hw_set_rf_regs()
934 *
935 * Additional additive reduction in power -
936 * change chain's switch table so chain's tx state is actually the rx
937 * state value. May produce different results in 2GHz/5GHz as well as
938 * board to board but in general should be a reduction.
939 *
940 * Activated by #ifdef ALTER_SWITCH. Not tried yet. If so, must be
941 * called after ah->eep_ops->set_board_values() due to RMW of
942 * PHY_SWITCH_CHAIN_0.
943 */
944 void
945 ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
946 {
947 int i, regWrites = 0;
948 u32 bank6SelMask;
949 u32 *bank6Temp = ah->bank6Temp;
950
951 switch (ah->config.diversity_control) {
952 case ATH9K_ANT_FIXED_A:
953 bank6SelMask =
954 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
955 REDUCE_CHAIN_0 : /* swapped, reduce chain 0 */
956 REDUCE_CHAIN_1; /* normal, select chain 1/2 to reduce */
957 break;
958 case ATH9K_ANT_FIXED_B:
959 bank6SelMask =
960 (ah->config.antenna_switch_swap & ANTSWAP_AB) ?
961 REDUCE_CHAIN_1 : /* swapped, reduce chain 1/2 */
962 REDUCE_CHAIN_0; /* normal, select chain 0 to reduce */
963 break;
964 case ATH9K_ANT_VARIABLE:
965 return; /* do not change anything */
966 break;
967 default:
968 return; /* do not change anything */
969 break;
970 }
971
972 for (i = 0; i < ah->iniBank6.ia_rows; i++)
973 bank6Temp[i] = ah->analogBank6Data[i];
974
975 /* Write Bank 5 to switch Bank 6 write to selected chain only */
976 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
977
978 /*
979 * Modify Bank6 selected chain to use lowest amplification.
980 * Modifies the parameters to a value of 1.
981 * Depends on existing bank 6 values to be cached in
982 * ah->analogBank6Data
983 */
984 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
985 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
986 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
987 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
988 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
989 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
990 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
991 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
992 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
993
994 REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites);
995
996 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
997 #ifdef ALTER_SWITCH
998 REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
999 (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
1000 | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
1001 #endif
1002 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree