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KVM: MMU: flush remote tlbs when overwriting spte with different pfn
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / mmu.c
blobca850d4b0997021487e1b585fe2e71a75adb4e66
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
19
20 #include "mmu.h"
21 #include "x86.h"
22 #include "kvm_cache_regs.h"
23
24 #include <linux/kvm_host.h>
25 #include <linux/types.h>
26 #include <linux/string.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/module.h>
30 #include <linux/swap.h>
31 #include <linux/hugetlb.h>
32 #include <linux/compiler.h>
33 #include <linux/srcu.h>
34 #include <linux/slab.h>
35
36 #include <asm/page.h>
37 #include <asm/cmpxchg.h>
38 #include <asm/io.h>
39 #include <asm/vmx.h>
40
41 /*
42 * When setting this variable to true it enables Two-Dimensional-Paging
43 * where the hardware walks 2 page tables:
44 * 1. the guest-virtual to guest-physical
45 * 2. while doing 1. it walks guest-physical to host-physical
46 * If the hardware supports that we don't need to do shadow paging.
47 */
48 bool tdp_enabled = false;
49
50 #undef MMU_DEBUG
51
52 #undef AUDIT
53
54 #ifdef AUDIT
55 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
56 #else
57 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
58 #endif
59
60 #ifdef MMU_DEBUG
61
62 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
63 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
64
65 #else
66
67 #define pgprintk(x...) do { } while (0)
68 #define rmap_printk(x...) do { } while (0)
69
70 #endif
71
72 #if defined(MMU_DEBUG) || defined(AUDIT)
73 static int dbg = 0;
74 module_param(dbg, bool, 0644);
75 #endif
76
77 static int oos_shadow = 1;
78 module_param(oos_shadow, bool, 0644);
79
80 #ifndef MMU_DEBUG
81 #define ASSERT(x) do { } while (0)
82 #else
83 #define ASSERT(x) \
84 if (!(x)) { \
85 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
86 __FILE__, __LINE__, #x); \
87 }
88 #endif
89
90 #define PT_FIRST_AVAIL_BITS_SHIFT 9
91 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
92
93 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
94
95 #define PT64_LEVEL_BITS 9
96
97 #define PT64_LEVEL_SHIFT(level) \
98 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
99
100 #define PT64_LEVEL_MASK(level) \
101 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
102
103 #define PT64_INDEX(address, level)\
104 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
105
106
107 #define PT32_LEVEL_BITS 10
108
109 #define PT32_LEVEL_SHIFT(level) \
110 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
111
112 #define PT32_LEVEL_MASK(level) \
113 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
114 #define PT32_LVL_OFFSET_MASK(level) \
115 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
116 * PT32_LEVEL_BITS))) - 1))
117
118 #define PT32_INDEX(address, level)\
119 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
120
121
122 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
123 #define PT64_DIR_BASE_ADDR_MASK \
124 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
125 #define PT64_LVL_ADDR_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128 #define PT64_LVL_OFFSET_MASK(level) \
129 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
130 * PT64_LEVEL_BITS))) - 1))
131
132 #define PT32_BASE_ADDR_MASK PAGE_MASK
133 #define PT32_DIR_BASE_ADDR_MASK \
134 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
135 #define PT32_LVL_ADDR_MASK(level) \
136 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
137 * PT32_LEVEL_BITS))) - 1))
138
139 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
140 | PT64_NX_MASK)
141
142 #define RMAP_EXT 4
143
144 #define ACC_EXEC_MASK 1
145 #define ACC_WRITE_MASK PT_WRITABLE_MASK
146 #define ACC_USER_MASK PT_USER_MASK
147 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
148
149 #include <trace/events/kvm.h>
150
151 #undef TRACE_INCLUDE_FILE
152 #define CREATE_TRACE_POINTS
153 #include "mmutrace.h"
154
155 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
156
157 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
158
159 struct kvm_rmap_desc {
160 u64 *sptes[RMAP_EXT];
161 struct kvm_rmap_desc *more;
162 };
163
164 struct kvm_shadow_walk_iterator {
165 u64 addr;
166 hpa_t shadow_addr;
167 int level;
168 u64 *sptep;
169 unsigned index;
170 };
171
172 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
173 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
174 shadow_walk_okay(&(_walker)); \
175 shadow_walk_next(&(_walker)))
176
177
178 struct kvm_unsync_walk {
179 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
180 };
181
182 typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
183
184 static struct kmem_cache *pte_chain_cache;
185 static struct kmem_cache *rmap_desc_cache;
186 static struct kmem_cache *mmu_page_header_cache;
187
188 static u64 __read_mostly shadow_trap_nonpresent_pte;
189 static u64 __read_mostly shadow_notrap_nonpresent_pte;
190 static u64 __read_mostly shadow_base_present_pte;
191 static u64 __read_mostly shadow_nx_mask;
192 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
193 static u64 __read_mostly shadow_user_mask;
194 static u64 __read_mostly shadow_accessed_mask;
195 static u64 __read_mostly shadow_dirty_mask;
196
197 static inline u64 rsvd_bits(int s, int e)
198 {
199 return ((1ULL << (e - s + 1)) - 1) << s;
200 }
201
202 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
203 {
204 shadow_trap_nonpresent_pte = trap_pte;
205 shadow_notrap_nonpresent_pte = notrap_pte;
206 }
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
208
209 void kvm_mmu_set_base_ptes(u64 base_pte)
210 {
211 shadow_base_present_pte = base_pte;
212 }
213 EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
214
215 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
216 u64 dirty_mask, u64 nx_mask, u64 x_mask)
217 {
218 shadow_user_mask = user_mask;
219 shadow_accessed_mask = accessed_mask;
220 shadow_dirty_mask = dirty_mask;
221 shadow_nx_mask = nx_mask;
222 shadow_x_mask = x_mask;
223 }
224 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
225
226 static bool is_write_protection(struct kvm_vcpu *vcpu)
227 {
228 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
229 }
230
231 static int is_cpuid_PSE36(void)
232 {
233 return 1;
234 }
235
236 static int is_nx(struct kvm_vcpu *vcpu)
237 {
238 return vcpu->arch.efer & EFER_NX;
239 }
240
241 static int is_shadow_present_pte(u64 pte)
242 {
243 return pte != shadow_trap_nonpresent_pte
244 && pte != shadow_notrap_nonpresent_pte;
245 }
246
247 static int is_large_pte(u64 pte)
248 {
249 return pte & PT_PAGE_SIZE_MASK;
250 }
251
252 static int is_writable_pte(unsigned long pte)
253 {
254 return pte & PT_WRITABLE_MASK;
255 }
256
257 static int is_dirty_gpte(unsigned long pte)
258 {
259 return pte & PT_DIRTY_MASK;
260 }
261
262 static int is_rmap_spte(u64 pte)
263 {
264 return is_shadow_present_pte(pte);
265 }
266
267 static int is_last_spte(u64 pte, int level)
268 {
269 if (level == PT_PAGE_TABLE_LEVEL)
270 return 1;
271 if (is_large_pte(pte))
272 return 1;
273 return 0;
274 }
275
276 static pfn_t spte_to_pfn(u64 pte)
277 {
278 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
279 }
280
281 static gfn_t pse36_gfn_delta(u32 gpte)
282 {
283 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
284
285 return (gpte & PT32_DIR_PSE36_MASK) << shift;
286 }
287
288 static void __set_spte(u64 *sptep, u64 spte)
289 {
290 #ifdef CONFIG_X86_64
291 set_64bit((unsigned long *)sptep, spte);
292 #else
293 set_64bit((unsigned long long *)sptep, spte);
294 #endif
295 }
296
297 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
298 struct kmem_cache *base_cache, int min)
299 {
300 void *obj;
301
302 if (cache->nobjs >= min)
303 return 0;
304 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
305 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
306 if (!obj)
307 return -ENOMEM;
308 cache->objects[cache->nobjs++] = obj;
309 }
310 return 0;
311 }
312
313 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
314 {
315 while (mc->nobjs)
316 kfree(mc->objects[--mc->nobjs]);
317 }
318
319 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
320 int min)
321 {
322 struct page *page;
323
324 if (cache->nobjs >= min)
325 return 0;
326 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
327 page = alloc_page(GFP_KERNEL);
328 if (!page)
329 return -ENOMEM;
330 set_page_private(page, 0);
331 cache->objects[cache->nobjs++] = page_address(page);
332 }
333 return 0;
334 }
335
336 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
337 {
338 while (mc->nobjs)
339 free_page((unsigned long)mc->objects[--mc->nobjs]);
340 }
341
342 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
343 {
344 int r;
345
346 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
347 pte_chain_cache, 4);
348 if (r)
349 goto out;
350 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
351 rmap_desc_cache, 4);
352 if (r)
353 goto out;
354 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
355 if (r)
356 goto out;
357 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
358 mmu_page_header_cache, 4);
359 out:
360 return r;
361 }
362
363 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
364 {
365 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
366 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
367 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
368 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
369 }
370
371 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
372 size_t size)
373 {
374 void *p;
375
376 BUG_ON(!mc->nobjs);
377 p = mc->objects[--mc->nobjs];
378 return p;
379 }
380
381 static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
382 {
383 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
384 sizeof(struct kvm_pte_chain));
385 }
386
387 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
388 {
389 kfree(pc);
390 }
391
392 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
393 {
394 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
395 sizeof(struct kvm_rmap_desc));
396 }
397
398 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
399 {
400 kfree(rd);
401 }
402
403 /*
404 * Return the pointer to the largepage write count for a given
405 * gfn, handling slots that are not large page aligned.
406 */
407 static int *slot_largepage_idx(gfn_t gfn,
408 struct kvm_memory_slot *slot,
409 int level)
410 {
411 unsigned long idx;
412
413 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
414 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
415 return &slot->lpage_info[level - 2][idx].write_count;
416 }
417
418 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
419 {
420 struct kvm_memory_slot *slot;
421 int *write_count;
422 int i;
423
424 gfn = unalias_gfn(kvm, gfn);
425
426 slot = gfn_to_memslot_unaliased(kvm, gfn);
427 for (i = PT_DIRECTORY_LEVEL;
428 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
429 write_count = slot_largepage_idx(gfn, slot, i);
430 *write_count += 1;
431 }
432 }
433
434 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
435 {
436 struct kvm_memory_slot *slot;
437 int *write_count;
438 int i;
439
440 gfn = unalias_gfn(kvm, gfn);
441 for (i = PT_DIRECTORY_LEVEL;
442 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
443 slot = gfn_to_memslot_unaliased(kvm, gfn);
444 write_count = slot_largepage_idx(gfn, slot, i);
445 *write_count -= 1;
446 WARN_ON(*write_count < 0);
447 }
448 }
449
450 static int has_wrprotected_page(struct kvm *kvm,
451 gfn_t gfn,
452 int level)
453 {
454 struct kvm_memory_slot *slot;
455 int *largepage_idx;
456
457 gfn = unalias_gfn(kvm, gfn);
458 slot = gfn_to_memslot_unaliased(kvm, gfn);
459 if (slot) {
460 largepage_idx = slot_largepage_idx(gfn, slot, level);
461 return *largepage_idx;
462 }
463
464 return 1;
465 }
466
467 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
468 {
469 unsigned long page_size;
470 int i, ret = 0;
471
472 page_size = kvm_host_page_size(kvm, gfn);
473
474 for (i = PT_PAGE_TABLE_LEVEL;
475 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
476 if (page_size >= KVM_HPAGE_SIZE(i))
477 ret = i;
478 else
479 break;
480 }
481
482 return ret;
483 }
484
485 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
486 {
487 struct kvm_memory_slot *slot;
488 int host_level, level, max_level;
489
490 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
491 if (slot && slot->dirty_bitmap)
492 return PT_PAGE_TABLE_LEVEL;
493
494 host_level = host_mapping_level(vcpu->kvm, large_gfn);
495
496 if (host_level == PT_PAGE_TABLE_LEVEL)
497 return host_level;
498
499 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
500 kvm_x86_ops->get_lpage_level() : host_level;
501
502 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
503 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
504 break;
505
506 return level - 1;
507 }
508
509 /*
510 * Take gfn and return the reverse mapping to it.
511 * Note: gfn must be unaliased before this function get called
512 */
513
514 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
515 {
516 struct kvm_memory_slot *slot;
517 unsigned long idx;
518
519 slot = gfn_to_memslot(kvm, gfn);
520 if (likely(level == PT_PAGE_TABLE_LEVEL))
521 return &slot->rmap[gfn - slot->base_gfn];
522
523 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
524 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
525
526 return &slot->lpage_info[level - 2][idx].rmap_pde;
527 }
528
529 /*
530 * Reverse mapping data structures:
531 *
532 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
533 * that points to page_address(page).
534 *
535 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
536 * containing more mappings.
537 *
538 * Returns the number of rmap entries before the spte was added or zero if
539 * the spte was not added.
540 *
541 */
542 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
543 {
544 struct kvm_mmu_page *sp;
545 struct kvm_rmap_desc *desc;
546 unsigned long *rmapp;
547 int i, count = 0;
548
549 if (!is_rmap_spte(*spte))
550 return count;
551 gfn = unalias_gfn(vcpu->kvm, gfn);
552 sp = page_header(__pa(spte));
553 sp->gfns[spte - sp->spt] = gfn;
554 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
555 if (!*rmapp) {
556 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
557 *rmapp = (unsigned long)spte;
558 } else if (!(*rmapp & 1)) {
559 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
560 desc = mmu_alloc_rmap_desc(vcpu);
561 desc->sptes[0] = (u64 *)*rmapp;
562 desc->sptes[1] = spte;
563 *rmapp = (unsigned long)desc | 1;
564 } else {
565 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
566 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
567 while (desc->sptes[RMAP_EXT-1] && desc->more) {
568 desc = desc->more;
569 count += RMAP_EXT;
570 }
571 if (desc->sptes[RMAP_EXT-1]) {
572 desc->more = mmu_alloc_rmap_desc(vcpu);
573 desc = desc->more;
574 }
575 for (i = 0; desc->sptes[i]; ++i)
576 ;
577 desc->sptes[i] = spte;
578 }
579 return count;
580 }
581
582 static void rmap_desc_remove_entry(unsigned long *rmapp,
583 struct kvm_rmap_desc *desc,
584 int i,
585 struct kvm_rmap_desc *prev_desc)
586 {
587 int j;
588
589 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
590 ;
591 desc->sptes[i] = desc->sptes[j];
592 desc->sptes[j] = NULL;
593 if (j != 0)
594 return;
595 if (!prev_desc && !desc->more)
596 *rmapp = (unsigned long)desc->sptes[0];
597 else
598 if (prev_desc)
599 prev_desc->more = desc->more;
600 else
601 *rmapp = (unsigned long)desc->more | 1;
602 mmu_free_rmap_desc(desc);
603 }
604
605 static void rmap_remove(struct kvm *kvm, u64 *spte)
606 {
607 struct kvm_rmap_desc *desc;
608 struct kvm_rmap_desc *prev_desc;
609 struct kvm_mmu_page *sp;
610 pfn_t pfn;
611 unsigned long *rmapp;
612 int i;
613
614 if (!is_rmap_spte(*spte))
615 return;
616 sp = page_header(__pa(spte));
617 pfn = spte_to_pfn(*spte);
618 if (*spte & shadow_accessed_mask)
619 kvm_set_pfn_accessed(pfn);
620 if (is_writable_pte(*spte))
621 kvm_set_pfn_dirty(pfn);
622 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
623 if (!*rmapp) {
624 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
625 BUG();
626 } else if (!(*rmapp & 1)) {
627 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
628 if ((u64 *)*rmapp != spte) {
629 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
630 spte, *spte);
631 BUG();
632 }
633 *rmapp = 0;
634 } else {
635 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
636 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
637 prev_desc = NULL;
638 while (desc) {
639 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
640 if (desc->sptes[i] == spte) {
641 rmap_desc_remove_entry(rmapp,
642 desc, i,
643 prev_desc);
644 return;
645 }
646 prev_desc = desc;
647 desc = desc->more;
648 }
649 pr_err("rmap_remove: %p %llx many->many\n", spte, *spte);
650 BUG();
651 }
652 }
653
654 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
655 {
656 struct kvm_rmap_desc *desc;
657 struct kvm_rmap_desc *prev_desc;
658 u64 *prev_spte;
659 int i;
660
661 if (!*rmapp)
662 return NULL;
663 else if (!(*rmapp & 1)) {
664 if (!spte)
665 return (u64 *)*rmapp;
666 return NULL;
667 }
668 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
669 prev_desc = NULL;
670 prev_spte = NULL;
671 while (desc) {
672 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
673 if (prev_spte == spte)
674 return desc->sptes[i];
675 prev_spte = desc->sptes[i];
676 }
677 desc = desc->more;
678 }
679 return NULL;
680 }
681
682 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
683 {
684 unsigned long *rmapp;
685 u64 *spte;
686 int i, write_protected = 0;
687
688 gfn = unalias_gfn(kvm, gfn);
689 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
690
691 spte = rmap_next(kvm, rmapp, NULL);
692 while (spte) {
693 BUG_ON(!spte);
694 BUG_ON(!(*spte & PT_PRESENT_MASK));
695 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
696 if (is_writable_pte(*spte)) {
697 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
698 write_protected = 1;
699 }
700 spte = rmap_next(kvm, rmapp, spte);
701 }
702 if (write_protected) {
703 pfn_t pfn;
704
705 spte = rmap_next(kvm, rmapp, NULL);
706 pfn = spte_to_pfn(*spte);
707 kvm_set_pfn_dirty(pfn);
708 }
709
710 /* check for huge page mappings */
711 for (i = PT_DIRECTORY_LEVEL;
712 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
713 rmapp = gfn_to_rmap(kvm, gfn, i);
714 spte = rmap_next(kvm, rmapp, NULL);
715 while (spte) {
716 BUG_ON(!spte);
717 BUG_ON(!(*spte & PT_PRESENT_MASK));
718 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
719 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
720 if (is_writable_pte(*spte)) {
721 rmap_remove(kvm, spte);
722 --kvm->stat.lpages;
723 __set_spte(spte, shadow_trap_nonpresent_pte);
724 spte = NULL;
725 write_protected = 1;
726 }
727 spte = rmap_next(kvm, rmapp, spte);
728 }
729 }
730
731 return write_protected;
732 }
733
734 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
735 unsigned long data)
736 {
737 u64 *spte;
738 int need_tlb_flush = 0;
739
740 while ((spte = rmap_next(kvm, rmapp, NULL))) {
741 BUG_ON(!(*spte & PT_PRESENT_MASK));
742 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
743 rmap_remove(kvm, spte);
744 __set_spte(spte, shadow_trap_nonpresent_pte);
745 need_tlb_flush = 1;
746 }
747 return need_tlb_flush;
748 }
749
750 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
751 unsigned long data)
752 {
753 int need_flush = 0;
754 u64 *spte, new_spte;
755 pte_t *ptep = (pte_t *)data;
756 pfn_t new_pfn;
757
758 WARN_ON(pte_huge(*ptep));
759 new_pfn = pte_pfn(*ptep);
760 spte = rmap_next(kvm, rmapp, NULL);
761 while (spte) {
762 BUG_ON(!is_shadow_present_pte(*spte));
763 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
764 need_flush = 1;
765 if (pte_write(*ptep)) {
766 rmap_remove(kvm, spte);
767 __set_spte(spte, shadow_trap_nonpresent_pte);
768 spte = rmap_next(kvm, rmapp, NULL);
769 } else {
770 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
771 new_spte |= (u64)new_pfn << PAGE_SHIFT;
772
773 new_spte &= ~PT_WRITABLE_MASK;
774 new_spte &= ~SPTE_HOST_WRITEABLE;
775 if (is_writable_pte(*spte))
776 kvm_set_pfn_dirty(spte_to_pfn(*spte));
777 __set_spte(spte, new_spte);
778 spte = rmap_next(kvm, rmapp, spte);
779 }
780 }
781 if (need_flush)
782 kvm_flush_remote_tlbs(kvm);
783
784 return 0;
785 }
786
787 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
788 unsigned long data,
789 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
790 unsigned long data))
791 {
792 int i, j;
793 int ret;
794 int retval = 0;
795 struct kvm_memslots *slots;
796
797 slots = rcu_dereference(kvm->memslots);
798
799 for (i = 0; i < slots->nmemslots; i++) {
800 struct kvm_memory_slot *memslot = &slots->memslots[i];
801 unsigned long start = memslot->userspace_addr;
802 unsigned long end;
803
804 end = start + (memslot->npages << PAGE_SHIFT);
805 if (hva >= start && hva < end) {
806 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
807
808 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
809
810 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
811 int idx = gfn_offset;
812 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
813 ret |= handler(kvm,
814 &memslot->lpage_info[j][idx].rmap_pde,
815 data);
816 }
817 trace_kvm_age_page(hva, memslot, ret);
818 retval |= ret;
819 }
820 }
821
822 return retval;
823 }
824
825 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
826 {
827 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
828 }
829
830 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
831 {
832 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
833 }
834
835 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
836 unsigned long data)
837 {
838 u64 *spte;
839 int young = 0;
840
841 /*
842 * Emulate the accessed bit for EPT, by checking if this page has
843 * an EPT mapping, and clearing it if it does. On the next access,
844 * a new EPT mapping will be established.
845 * This has some overhead, but not as much as the cost of swapping
846 * out actively used pages or breaking up actively used hugepages.
847 */
848 if (!shadow_accessed_mask)
849 return kvm_unmap_rmapp(kvm, rmapp, data);
850
851 spte = rmap_next(kvm, rmapp, NULL);
852 while (spte) {
853 int _young;
854 u64 _spte = *spte;
855 BUG_ON(!(_spte & PT_PRESENT_MASK));
856 _young = _spte & PT_ACCESSED_MASK;
857 if (_young) {
858 young = 1;
859 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
860 }
861 spte = rmap_next(kvm, rmapp, spte);
862 }
863 return young;
864 }
865
866 #define RMAP_RECYCLE_THRESHOLD 1000
867
868 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
869 {
870 unsigned long *rmapp;
871 struct kvm_mmu_page *sp;
872
873 sp = page_header(__pa(spte));
874
875 gfn = unalias_gfn(vcpu->kvm, gfn);
876 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
877
878 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
879 kvm_flush_remote_tlbs(vcpu->kvm);
880 }
881
882 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
883 {
884 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
885 }
886
887 #ifdef MMU_DEBUG
888 static int is_empty_shadow_page(u64 *spt)
889 {
890 u64 *pos;
891 u64 *end;
892
893 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
894 if (is_shadow_present_pte(*pos)) {
895 printk(KERN_ERR "%s: %p %llx\n", __func__,
896 pos, *pos);
897 return 0;
898 }
899 return 1;
900 }
901 #endif
902
903 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
904 {
905 ASSERT(is_empty_shadow_page(sp->spt));
906 list_del(&sp->link);
907 __free_page(virt_to_page(sp->spt));
908 __free_page(virt_to_page(sp->gfns));
909 kfree(sp);
910 ++kvm->arch.n_free_mmu_pages;
911 }
912
913 static unsigned kvm_page_table_hashfn(gfn_t gfn)
914 {
915 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
916 }
917
918 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
919 u64 *parent_pte)
920 {
921 struct kvm_mmu_page *sp;
922
923 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
924 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
925 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
926 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
927 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
928 INIT_LIST_HEAD(&sp->oos_link);
929 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
930 sp->multimapped = 0;
931 sp->parent_pte = parent_pte;
932 --vcpu->kvm->arch.n_free_mmu_pages;
933 return sp;
934 }
935
936 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
937 struct kvm_mmu_page *sp, u64 *parent_pte)
938 {
939 struct kvm_pte_chain *pte_chain;
940 struct hlist_node *node;
941 int i;
942
943 if (!parent_pte)
944 return;
945 if (!sp->multimapped) {
946 u64 *old = sp->parent_pte;
947
948 if (!old) {
949 sp->parent_pte = parent_pte;
950 return;
951 }
952 sp->multimapped = 1;
953 pte_chain = mmu_alloc_pte_chain(vcpu);
954 INIT_HLIST_HEAD(&sp->parent_ptes);
955 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
956 pte_chain->parent_ptes[0] = old;
957 }
958 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
959 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
960 continue;
961 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
962 if (!pte_chain->parent_ptes[i]) {
963 pte_chain->parent_ptes[i] = parent_pte;
964 return;
965 }
966 }
967 pte_chain = mmu_alloc_pte_chain(vcpu);
968 BUG_ON(!pte_chain);
969 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
970 pte_chain->parent_ptes[0] = parent_pte;
971 }
972
973 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
974 u64 *parent_pte)
975 {
976 struct kvm_pte_chain *pte_chain;
977 struct hlist_node *node;
978 int i;
979
980 if (!sp->multimapped) {
981 BUG_ON(sp->parent_pte != parent_pte);
982 sp->parent_pte = NULL;
983 return;
984 }
985 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
986 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
987 if (!pte_chain->parent_ptes[i])
988 break;
989 if (pte_chain->parent_ptes[i] != parent_pte)
990 continue;
991 while (i + 1 < NR_PTE_CHAIN_ENTRIES
992 && pte_chain->parent_ptes[i + 1]) {
993 pte_chain->parent_ptes[i]
994 = pte_chain->parent_ptes[i + 1];
995 ++i;
996 }
997 pte_chain->parent_ptes[i] = NULL;
998 if (i == 0) {
999 hlist_del(&pte_chain->link);
1000 mmu_free_pte_chain(pte_chain);
1001 if (hlist_empty(&sp->parent_ptes)) {
1002 sp->multimapped = 0;
1003 sp->parent_pte = NULL;
1004 }
1005 }
1006 return;
1007 }
1008 BUG();
1009 }
1010
1011
1012 static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1013 mmu_parent_walk_fn fn)
1014 {
1015 struct kvm_pte_chain *pte_chain;
1016 struct hlist_node *node;
1017 struct kvm_mmu_page *parent_sp;
1018 int i;
1019
1020 if (!sp->multimapped && sp->parent_pte) {
1021 parent_sp = page_header(__pa(sp->parent_pte));
1022 fn(vcpu, parent_sp);
1023 mmu_parent_walk(vcpu, parent_sp, fn);
1024 return;
1025 }
1026 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1027 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1028 if (!pte_chain->parent_ptes[i])
1029 break;
1030 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1031 fn(vcpu, parent_sp);
1032 mmu_parent_walk(vcpu, parent_sp, fn);
1033 }
1034 }
1035
1036 static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1037 {
1038 unsigned int index;
1039 struct kvm_mmu_page *sp = page_header(__pa(spte));
1040
1041 index = spte - sp->spt;
1042 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1043 sp->unsync_children++;
1044 WARN_ON(!sp->unsync_children);
1045 }
1046
1047 static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1048 {
1049 struct kvm_pte_chain *pte_chain;
1050 struct hlist_node *node;
1051 int i;
1052
1053 if (!sp->parent_pte)
1054 return;
1055
1056 if (!sp->multimapped) {
1057 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1058 return;
1059 }
1060
1061 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1062 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1063 if (!pte_chain->parent_ptes[i])
1064 break;
1065 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1066 }
1067 }
1068
1069 static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1070 {
1071 kvm_mmu_update_parents_unsync(sp);
1072 return 1;
1073 }
1074
1075 static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1076 struct kvm_mmu_page *sp)
1077 {
1078 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1079 kvm_mmu_update_parents_unsync(sp);
1080 }
1081
1082 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1083 struct kvm_mmu_page *sp)
1084 {
1085 int i;
1086
1087 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1088 sp->spt[i] = shadow_trap_nonpresent_pte;
1089 }
1090
1091 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1092 struct kvm_mmu_page *sp)
1093 {
1094 return 1;
1095 }
1096
1097 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1098 {
1099 }
1100
1101 #define KVM_PAGE_ARRAY_NR 16
1102
1103 struct kvm_mmu_pages {
1104 struct mmu_page_and_offset {
1105 struct kvm_mmu_page *sp;
1106 unsigned int idx;
1107 } page[KVM_PAGE_ARRAY_NR];
1108 unsigned int nr;
1109 };
1110
1111 #define for_each_unsync_children(bitmap, idx) \
1112 for (idx = find_first_bit(bitmap, 512); \
1113 idx < 512; \
1114 idx = find_next_bit(bitmap, 512, idx+1))
1115
1116 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1117 int idx)
1118 {
1119 int i;
1120
1121 if (sp->unsync)
1122 for (i=0; i < pvec->nr; i++)
1123 if (pvec->page[i].sp == sp)
1124 return 0;
1125
1126 pvec->page[pvec->nr].sp = sp;
1127 pvec->page[pvec->nr].idx = idx;
1128 pvec->nr++;
1129 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1130 }
1131
1132 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1133 struct kvm_mmu_pages *pvec)
1134 {
1135 int i, ret, nr_unsync_leaf = 0;
1136
1137 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1138 u64 ent = sp->spt[i];
1139
1140 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
1141 struct kvm_mmu_page *child;
1142 child = page_header(ent & PT64_BASE_ADDR_MASK);
1143
1144 if (child->unsync_children) {
1145 if (mmu_pages_add(pvec, child, i))
1146 return -ENOSPC;
1147
1148 ret = __mmu_unsync_walk(child, pvec);
1149 if (!ret)
1150 __clear_bit(i, sp->unsync_child_bitmap);
1151 else if (ret > 0)
1152 nr_unsync_leaf += ret;
1153 else
1154 return ret;
1155 }
1156
1157 if (child->unsync) {
1158 nr_unsync_leaf++;
1159 if (mmu_pages_add(pvec, child, i))
1160 return -ENOSPC;
1161 }
1162 }
1163 }
1164
1165 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
1166 sp->unsync_children = 0;
1167
1168 return nr_unsync_leaf;
1169 }
1170
1171 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1172 struct kvm_mmu_pages *pvec)
1173 {
1174 if (!sp->unsync_children)
1175 return 0;
1176
1177 mmu_pages_add(pvec, sp, 0);
1178 return __mmu_unsync_walk(sp, pvec);
1179 }
1180
1181 static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
1182 {
1183 unsigned index;
1184 struct hlist_head *bucket;
1185 struct kvm_mmu_page *sp;
1186 struct hlist_node *node;
1187
1188 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1189 index = kvm_page_table_hashfn(gfn);
1190 bucket = &kvm->arch.mmu_page_hash[index];
1191 hlist_for_each_entry(sp, node, bucket, hash_link)
1192 if (sp->gfn == gfn && !sp->role.direct
1193 && !sp->role.invalid) {
1194 pgprintk("%s: found role %x\n",
1195 __func__, sp->role.word);
1196 return sp;
1197 }
1198 return NULL;
1199 }
1200
1201 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1202 {
1203 WARN_ON(!sp->unsync);
1204 sp->unsync = 0;
1205 --kvm->stat.mmu_unsync;
1206 }
1207
1208 static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1209
1210 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1211 {
1212 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1213 kvm_mmu_zap_page(vcpu->kvm, sp);
1214 return 1;
1215 }
1216
1217 trace_kvm_mmu_sync_page(sp);
1218 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1219 kvm_flush_remote_tlbs(vcpu->kvm);
1220 kvm_unlink_unsync_page(vcpu->kvm, sp);
1221 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1222 kvm_mmu_zap_page(vcpu->kvm, sp);
1223 return 1;
1224 }
1225
1226 kvm_mmu_flush_tlb(vcpu);
1227 return 0;
1228 }
1229
1230 struct mmu_page_path {
1231 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1232 unsigned int idx[PT64_ROOT_LEVEL-1];
1233 };
1234
1235 #define for_each_sp(pvec, sp, parents, i) \
1236 for (i = mmu_pages_next(&pvec, &parents, -1), \
1237 sp = pvec.page[i].sp; \
1238 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1239 i = mmu_pages_next(&pvec, &parents, i))
1240
1241 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1242 struct mmu_page_path *parents,
1243 int i)
1244 {
1245 int n;
1246
1247 for (n = i+1; n < pvec->nr; n++) {
1248 struct kvm_mmu_page *sp = pvec->page[n].sp;
1249
1250 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1251 parents->idx[0] = pvec->page[n].idx;
1252 return n;
1253 }
1254
1255 parents->parent[sp->role.level-2] = sp;
1256 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1257 }
1258
1259 return n;
1260 }
1261
1262 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1263 {
1264 struct kvm_mmu_page *sp;
1265 unsigned int level = 0;
1266
1267 do {
1268 unsigned int idx = parents->idx[level];
1269
1270 sp = parents->parent[level];
1271 if (!sp)
1272 return;
1273
1274 --sp->unsync_children;
1275 WARN_ON((int)sp->unsync_children < 0);
1276 __clear_bit(idx, sp->unsync_child_bitmap);
1277 level++;
1278 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1279 }
1280
1281 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1282 struct mmu_page_path *parents,
1283 struct kvm_mmu_pages *pvec)
1284 {
1285 parents->parent[parent->role.level-1] = NULL;
1286 pvec->nr = 0;
1287 }
1288
1289 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1290 struct kvm_mmu_page *parent)
1291 {
1292 int i;
1293 struct kvm_mmu_page *sp;
1294 struct mmu_page_path parents;
1295 struct kvm_mmu_pages pages;
1296
1297 kvm_mmu_pages_init(parent, &parents, &pages);
1298 while (mmu_unsync_walk(parent, &pages)) {
1299 int protected = 0;
1300
1301 for_each_sp(pages, sp, parents, i)
1302 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1303
1304 if (protected)
1305 kvm_flush_remote_tlbs(vcpu->kvm);
1306
1307 for_each_sp(pages, sp, parents, i) {
1308 kvm_sync_page(vcpu, sp);
1309 mmu_pages_clear_parents(&parents);
1310 }
1311 cond_resched_lock(&vcpu->kvm->mmu_lock);
1312 kvm_mmu_pages_init(parent, &parents, &pages);
1313 }
1314 }
1315
1316 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1317 gfn_t gfn,
1318 gva_t gaddr,
1319 unsigned level,
1320 int direct,
1321 unsigned access,
1322 u64 *parent_pte)
1323 {
1324 union kvm_mmu_page_role role;
1325 unsigned index;
1326 unsigned quadrant;
1327 struct hlist_head *bucket;
1328 struct kvm_mmu_page *sp;
1329 struct hlist_node *node, *tmp;
1330
1331 role = vcpu->arch.mmu.base_role;
1332 role.level = level;
1333 role.direct = direct;
1334 role.access = access;
1335 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1336 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1337 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1338 role.quadrant = quadrant;
1339 }
1340 index = kvm_page_table_hashfn(gfn);
1341 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1342 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1343 if (sp->gfn == gfn) {
1344 if (sp->unsync)
1345 if (kvm_sync_page(vcpu, sp))
1346 continue;
1347
1348 if (sp->role.word != role.word)
1349 continue;
1350
1351 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1352 if (sp->unsync_children) {
1353 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1354 kvm_mmu_mark_parents_unsync(vcpu, sp);
1355 }
1356 trace_kvm_mmu_get_page(sp, false);
1357 return sp;
1358 }
1359 ++vcpu->kvm->stat.mmu_cache_miss;
1360 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1361 if (!sp)
1362 return sp;
1363 sp->gfn = gfn;
1364 sp->role = role;
1365 hlist_add_head(&sp->hash_link, bucket);
1366 if (!direct) {
1367 if (rmap_write_protect(vcpu->kvm, gfn))
1368 kvm_flush_remote_tlbs(vcpu->kvm);
1369 account_shadowed(vcpu->kvm, gfn);
1370 }
1371 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1372 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1373 else
1374 nonpaging_prefetch_page(vcpu, sp);
1375 trace_kvm_mmu_get_page(sp, true);
1376 return sp;
1377 }
1378
1379 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1380 struct kvm_vcpu *vcpu, u64 addr)
1381 {
1382 iterator->addr = addr;
1383 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1384 iterator->level = vcpu->arch.mmu.shadow_root_level;
1385 if (iterator->level == PT32E_ROOT_LEVEL) {
1386 iterator->shadow_addr
1387 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1388 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1389 --iterator->level;
1390 if (!iterator->shadow_addr)
1391 iterator->level = 0;
1392 }
1393 }
1394
1395 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1396 {
1397 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1398 return false;
1399
1400 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1401 if (is_large_pte(*iterator->sptep))
1402 return false;
1403
1404 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1405 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1406 return true;
1407 }
1408
1409 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1410 {
1411 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1412 --iterator->level;
1413 }
1414
1415 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1416 struct kvm_mmu_page *sp)
1417 {
1418 unsigned i;
1419 u64 *pt;
1420 u64 ent;
1421
1422 pt = sp->spt;
1423
1424 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1425 ent = pt[i];
1426
1427 if (is_shadow_present_pte(ent)) {
1428 if (!is_last_spte(ent, sp->role.level)) {
1429 ent &= PT64_BASE_ADDR_MASK;
1430 mmu_page_remove_parent_pte(page_header(ent),
1431 &pt[i]);
1432 } else {
1433 if (is_large_pte(ent))
1434 --kvm->stat.lpages;
1435 rmap_remove(kvm, &pt[i]);
1436 }
1437 }
1438 pt[i] = shadow_trap_nonpresent_pte;
1439 }
1440 }
1441
1442 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1443 {
1444 mmu_page_remove_parent_pte(sp, parent_pte);
1445 }
1446
1447 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1448 {
1449 int i;
1450 struct kvm_vcpu *vcpu;
1451
1452 kvm_for_each_vcpu(i, vcpu, kvm)
1453 vcpu->arch.last_pte_updated = NULL;
1454 }
1455
1456 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1457 {
1458 u64 *parent_pte;
1459
1460 while (sp->multimapped || sp->parent_pte) {
1461 if (!sp->multimapped)
1462 parent_pte = sp->parent_pte;
1463 else {
1464 struct kvm_pte_chain *chain;
1465
1466 chain = container_of(sp->parent_ptes.first,
1467 struct kvm_pte_chain, link);
1468 parent_pte = chain->parent_ptes[0];
1469 }
1470 BUG_ON(!parent_pte);
1471 kvm_mmu_put_page(sp, parent_pte);
1472 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1473 }
1474 }
1475
1476 static int mmu_zap_unsync_children(struct kvm *kvm,
1477 struct kvm_mmu_page *parent)
1478 {
1479 int i, zapped = 0;
1480 struct mmu_page_path parents;
1481 struct kvm_mmu_pages pages;
1482
1483 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1484 return 0;
1485
1486 kvm_mmu_pages_init(parent, &parents, &pages);
1487 while (mmu_unsync_walk(parent, &pages)) {
1488 struct kvm_mmu_page *sp;
1489
1490 for_each_sp(pages, sp, parents, i) {
1491 kvm_mmu_zap_page(kvm, sp);
1492 mmu_pages_clear_parents(&parents);
1493 zapped++;
1494 }
1495 kvm_mmu_pages_init(parent, &parents, &pages);
1496 }
1497
1498 return zapped;
1499 }
1500
1501 static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1502 {
1503 int ret;
1504
1505 trace_kvm_mmu_zap_page(sp);
1506 ++kvm->stat.mmu_shadow_zapped;
1507 ret = mmu_zap_unsync_children(kvm, sp);
1508 kvm_mmu_page_unlink_children(kvm, sp);
1509 kvm_mmu_unlink_parents(kvm, sp);
1510 kvm_flush_remote_tlbs(kvm);
1511 if (!sp->role.invalid && !sp->role.direct)
1512 unaccount_shadowed(kvm, sp->gfn);
1513 if (sp->unsync)
1514 kvm_unlink_unsync_page(kvm, sp);
1515 if (!sp->root_count) {
1516 hlist_del(&sp->hash_link);
1517 kvm_mmu_free_page(kvm, sp);
1518 } else {
1519 sp->role.invalid = 1;
1520 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1521 kvm_reload_remote_mmus(kvm);
1522 }
1523 kvm_mmu_reset_last_pte_updated(kvm);
1524 return ret;
1525 }
1526
1527 /*
1528 * Changing the number of mmu pages allocated to the vm
1529 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1530 */
1531 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1532 {
1533 int used_pages;
1534
1535 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1536 used_pages = max(0, used_pages);
1537
1538 /*
1539 * If we set the number of mmu pages to be smaller be than the
1540 * number of actived pages , we must to free some mmu pages before we
1541 * change the value
1542 */
1543
1544 if (used_pages > kvm_nr_mmu_pages) {
1545 while (used_pages > kvm_nr_mmu_pages &&
1546 !list_empty(&kvm->arch.active_mmu_pages)) {
1547 struct kvm_mmu_page *page;
1548
1549 page = container_of(kvm->arch.active_mmu_pages.prev,
1550 struct kvm_mmu_page, link);
1551 used_pages -= kvm_mmu_zap_page(kvm, page);
1552 used_pages--;
1553 }
1554 kvm_nr_mmu_pages = used_pages;
1555 kvm->arch.n_free_mmu_pages = 0;
1556 }
1557 else
1558 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1559 - kvm->arch.n_alloc_mmu_pages;
1560
1561 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
1562 }
1563
1564 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1565 {
1566 unsigned index;
1567 struct hlist_head *bucket;
1568 struct kvm_mmu_page *sp;
1569 struct hlist_node *node, *n;
1570 int r;
1571
1572 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1573 r = 0;
1574 index = kvm_page_table_hashfn(gfn);
1575 bucket = &kvm->arch.mmu_page_hash[index];
1576 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
1577 if (sp->gfn == gfn && !sp->role.direct) {
1578 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
1579 sp->role.word);
1580 r = 1;
1581 if (kvm_mmu_zap_page(kvm, sp))
1582 n = bucket->first;
1583 }
1584 return r;
1585 }
1586
1587 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1588 {
1589 unsigned index;
1590 struct hlist_head *bucket;
1591 struct kvm_mmu_page *sp;
1592 struct hlist_node *node, *nn;
1593
1594 index = kvm_page_table_hashfn(gfn);
1595 bucket = &kvm->arch.mmu_page_hash[index];
1596 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
1597 if (sp->gfn == gfn && !sp->role.direct
1598 && !sp->role.invalid) {
1599 pgprintk("%s: zap %lx %x\n",
1600 __func__, gfn, sp->role.word);
1601 if (kvm_mmu_zap_page(kvm, sp))
1602 nn = bucket->first;
1603 }
1604 }
1605 }
1606
1607 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1608 {
1609 int slot = memslot_id(kvm, gfn);
1610 struct kvm_mmu_page *sp = page_header(__pa(pte));
1611
1612 __set_bit(slot, sp->slot_bitmap);
1613 }
1614
1615 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1616 {
1617 int i;
1618 u64 *pt = sp->spt;
1619
1620 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1621 return;
1622
1623 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1624 if (pt[i] == shadow_notrap_nonpresent_pte)
1625 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1626 }
1627 }
1628
1629 struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1630 {
1631 struct page *page;
1632
1633 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
1634
1635 if (gpa == UNMAPPED_GVA)
1636 return NULL;
1637
1638 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
1639
1640 return page;
1641 }
1642
1643 /*
1644 * The function is based on mtrr_type_lookup() in
1645 * arch/x86/kernel/cpu/mtrr/generic.c
1646 */
1647 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1648 u64 start, u64 end)
1649 {
1650 int i;
1651 u64 base, mask;
1652 u8 prev_match, curr_match;
1653 int num_var_ranges = KVM_NR_VAR_MTRR;
1654
1655 if (!mtrr_state->enabled)
1656 return 0xFF;
1657
1658 /* Make end inclusive end, instead of exclusive */
1659 end--;
1660
1661 /* Look in fixed ranges. Just return the type as per start */
1662 if (mtrr_state->have_fixed && (start < 0x100000)) {
1663 int idx;
1664
1665 if (start < 0x80000) {
1666 idx = 0;
1667 idx += (start >> 16);
1668 return mtrr_state->fixed_ranges[idx];
1669 } else if (start < 0xC0000) {
1670 idx = 1 * 8;
1671 idx += ((start - 0x80000) >> 14);
1672 return mtrr_state->fixed_ranges[idx];
1673 } else if (start < 0x1000000) {
1674 idx = 3 * 8;
1675 idx += ((start - 0xC0000) >> 12);
1676 return mtrr_state->fixed_ranges[idx];
1677 }
1678 }
1679
1680 /*
1681 * Look in variable ranges
1682 * Look of multiple ranges matching this address and pick type
1683 * as per MTRR precedence
1684 */
1685 if (!(mtrr_state->enabled & 2))
1686 return mtrr_state->def_type;
1687
1688 prev_match = 0xFF;
1689 for (i = 0; i < num_var_ranges; ++i) {
1690 unsigned short start_state, end_state;
1691
1692 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1693 continue;
1694
1695 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1696 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1697 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1698 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1699
1700 start_state = ((start & mask) == (base & mask));
1701 end_state = ((end & mask) == (base & mask));
1702 if (start_state != end_state)
1703 return 0xFE;
1704
1705 if ((start & mask) != (base & mask))
1706 continue;
1707
1708 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1709 if (prev_match == 0xFF) {
1710 prev_match = curr_match;
1711 continue;
1712 }
1713
1714 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1715 curr_match == MTRR_TYPE_UNCACHABLE)
1716 return MTRR_TYPE_UNCACHABLE;
1717
1718 if ((prev_match == MTRR_TYPE_WRBACK &&
1719 curr_match == MTRR_TYPE_WRTHROUGH) ||
1720 (prev_match == MTRR_TYPE_WRTHROUGH &&
1721 curr_match == MTRR_TYPE_WRBACK)) {
1722 prev_match = MTRR_TYPE_WRTHROUGH;
1723 curr_match = MTRR_TYPE_WRTHROUGH;
1724 }
1725
1726 if (prev_match != curr_match)
1727 return MTRR_TYPE_UNCACHABLE;
1728 }
1729
1730 if (prev_match != 0xFF)
1731 return prev_match;
1732
1733 return mtrr_state->def_type;
1734 }
1735
1736 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1737 {
1738 u8 mtrr;
1739
1740 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1741 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1742 if (mtrr == 0xfe || mtrr == 0xff)
1743 mtrr = MTRR_TYPE_WRBACK;
1744 return mtrr;
1745 }
1746 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1747
1748 static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1749 {
1750 unsigned index;
1751 struct hlist_head *bucket;
1752 struct kvm_mmu_page *s;
1753 struct hlist_node *node, *n;
1754
1755 trace_kvm_mmu_unsync_page(sp);
1756 index = kvm_page_table_hashfn(sp->gfn);
1757 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1758 /* don't unsync if pagetable is shadowed with multiple roles */
1759 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
1760 if (s->gfn != sp->gfn || s->role.direct)
1761 continue;
1762 if (s->role.word != sp->role.word)
1763 return 1;
1764 }
1765 ++vcpu->kvm->stat.mmu_unsync;
1766 sp->unsync = 1;
1767
1768 kvm_mmu_mark_parents_unsync(vcpu, sp);
1769
1770 mmu_convert_notrap(sp);
1771 return 0;
1772 }
1773
1774 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1775 bool can_unsync)
1776 {
1777 struct kvm_mmu_page *shadow;
1778
1779 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1780 if (shadow) {
1781 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1782 return 1;
1783 if (shadow->unsync)
1784 return 0;
1785 if (can_unsync && oos_shadow)
1786 return kvm_unsync_page(vcpu, shadow);
1787 return 1;
1788 }
1789 return 0;
1790 }
1791
1792 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1793 unsigned pte_access, int user_fault,
1794 int write_fault, int dirty, int level,
1795 gfn_t gfn, pfn_t pfn, bool speculative,
1796 bool can_unsync, bool reset_host_protection)
1797 {
1798 u64 spte;
1799 int ret = 0;
1800
1801 /*
1802 * We don't set the accessed bit, since we sometimes want to see
1803 * whether the guest actually used the pte (in order to detect
1804 * demand paging).
1805 */
1806 spte = shadow_base_present_pte | shadow_dirty_mask;
1807 if (!speculative)
1808 spte |= shadow_accessed_mask;
1809 if (!dirty)
1810 pte_access &= ~ACC_WRITE_MASK;
1811 if (pte_access & ACC_EXEC_MASK)
1812 spte |= shadow_x_mask;
1813 else
1814 spte |= shadow_nx_mask;
1815 if (pte_access & ACC_USER_MASK)
1816 spte |= shadow_user_mask;
1817 if (level > PT_PAGE_TABLE_LEVEL)
1818 spte |= PT_PAGE_SIZE_MASK;
1819 if (tdp_enabled)
1820 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1821 kvm_is_mmio_pfn(pfn));
1822
1823 if (reset_host_protection)
1824 spte |= SPTE_HOST_WRITEABLE;
1825
1826 spte |= (u64)pfn << PAGE_SHIFT;
1827
1828 if ((pte_access & ACC_WRITE_MASK)
1829 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1830
1831 if (level > PT_PAGE_TABLE_LEVEL &&
1832 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1833 ret = 1;
1834 spte = shadow_trap_nonpresent_pte;
1835 goto set_pte;
1836 }
1837
1838 spte |= PT_WRITABLE_MASK;
1839
1840 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1841 spte &= ~PT_USER_MASK;
1842
1843 /*
1844 * Optimization: for pte sync, if spte was writable the hash
1845 * lookup is unnecessary (and expensive). Write protection
1846 * is responsibility of mmu_get_page / kvm_sync_page.
1847 * Same reasoning can be applied to dirty page accounting.
1848 */
1849 if (!can_unsync && is_writable_pte(*sptep))
1850 goto set_pte;
1851
1852 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1853 pgprintk("%s: found shadow page for %lx, marking ro\n",
1854 __func__, gfn);
1855 ret = 1;
1856 pte_access &= ~ACC_WRITE_MASK;
1857 if (is_writable_pte(spte))
1858 spte &= ~PT_WRITABLE_MASK;
1859 }
1860 }
1861
1862 if (pte_access & ACC_WRITE_MASK)
1863 mark_page_dirty(vcpu->kvm, gfn);
1864
1865 set_pte:
1866 __set_spte(sptep, spte);
1867 return ret;
1868 }
1869
1870 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1871 unsigned pt_access, unsigned pte_access,
1872 int user_fault, int write_fault, int dirty,
1873 int *ptwrite, int level, gfn_t gfn,
1874 pfn_t pfn, bool speculative,
1875 bool reset_host_protection)
1876 {
1877 int was_rmapped = 0;
1878 int was_writable = is_writable_pte(*sptep);
1879 int rmap_count;
1880
1881 pgprintk("%s: spte %llx access %x write_fault %d"
1882 " user_fault %d gfn %lx\n",
1883 __func__, *sptep, pt_access,
1884 write_fault, user_fault, gfn);
1885
1886 if (is_rmap_spte(*sptep)) {
1887 /*
1888 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1889 * the parent of the now unreachable PTE.
1890 */
1891 if (level > PT_PAGE_TABLE_LEVEL &&
1892 !is_large_pte(*sptep)) {
1893 struct kvm_mmu_page *child;
1894 u64 pte = *sptep;
1895
1896 child = page_header(pte & PT64_BASE_ADDR_MASK);
1897 mmu_page_remove_parent_pte(child, sptep);
1898 __set_spte(sptep, shadow_trap_nonpresent_pte);
1899 kvm_flush_remote_tlbs(vcpu->kvm);
1900 } else if (pfn != spte_to_pfn(*sptep)) {
1901 pgprintk("hfn old %lx new %lx\n",
1902 spte_to_pfn(*sptep), pfn);
1903 rmap_remove(vcpu->kvm, sptep);
1904 __set_spte(sptep, shadow_trap_nonpresent_pte);
1905 kvm_flush_remote_tlbs(vcpu->kvm);
1906 } else
1907 was_rmapped = 1;
1908 }
1909
1910 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1911 dirty, level, gfn, pfn, speculative, true,
1912 reset_host_protection)) {
1913 if (write_fault)
1914 *ptwrite = 1;
1915 kvm_x86_ops->tlb_flush(vcpu);
1916 }
1917
1918 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1919 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
1920 is_large_pte(*sptep)? "2MB" : "4kB",
1921 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1922 *sptep, sptep);
1923 if (!was_rmapped && is_large_pte(*sptep))
1924 ++vcpu->kvm->stat.lpages;
1925
1926 page_header_update_slot(vcpu->kvm, sptep, gfn);
1927 if (!was_rmapped) {
1928 rmap_count = rmap_add(vcpu, sptep, gfn);
1929 kvm_release_pfn_clean(pfn);
1930 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
1931 rmap_recycle(vcpu, sptep, gfn);
1932 } else {
1933 if (was_writable)
1934 kvm_release_pfn_dirty(pfn);
1935 else
1936 kvm_release_pfn_clean(pfn);
1937 }
1938 if (speculative) {
1939 vcpu->arch.last_pte_updated = sptep;
1940 vcpu->arch.last_pte_gfn = gfn;
1941 }
1942 }
1943
1944 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1945 {
1946 }
1947
1948 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
1949 int level, gfn_t gfn, pfn_t pfn)
1950 {
1951 struct kvm_shadow_walk_iterator iterator;
1952 struct kvm_mmu_page *sp;
1953 int pt_write = 0;
1954 gfn_t pseudo_gfn;
1955
1956 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
1957 if (iterator.level == level) {
1958 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1959 0, write, 1, &pt_write,
1960 level, gfn, pfn, false, true);
1961 ++vcpu->stat.pf_fixed;
1962 break;
1963 }
1964
1965 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1966 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1967 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1968 iterator.level - 1,
1969 1, ACC_ALL, iterator.sptep);
1970 if (!sp) {
1971 pgprintk("nonpaging_map: ENOMEM\n");
1972 kvm_release_pfn_clean(pfn);
1973 return -ENOMEM;
1974 }
1975
1976 __set_spte(iterator.sptep,
1977 __pa(sp->spt)
1978 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1979 | shadow_user_mask | shadow_x_mask);
1980 }
1981 }
1982 return pt_write;
1983 }
1984
1985 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1986 {
1987 int r;
1988 int level;
1989 pfn_t pfn;
1990 unsigned long mmu_seq;
1991
1992 level = mapping_level(vcpu, gfn);
1993
1994 /*
1995 * This path builds a PAE pagetable - so we can map 2mb pages at
1996 * maximum. Therefore check if the level is larger than that.
1997 */
1998 if (level > PT_DIRECTORY_LEVEL)
1999 level = PT_DIRECTORY_LEVEL;
2000
2001 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2002
2003 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2004 smp_rmb();
2005 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2006
2007 /* mmio */
2008 if (is_error_pfn(pfn)) {
2009 kvm_release_pfn_clean(pfn);
2010 return 1;
2011 }
2012
2013 spin_lock(&vcpu->kvm->mmu_lock);
2014 if (mmu_notifier_retry(vcpu, mmu_seq))
2015 goto out_unlock;
2016 kvm_mmu_free_some_pages(vcpu);
2017 r = __direct_map(vcpu, v, write, level, gfn, pfn);
2018 spin_unlock(&vcpu->kvm->mmu_lock);
2019
2020
2021 return r;
2022
2023 out_unlock:
2024 spin_unlock(&vcpu->kvm->mmu_lock);
2025 kvm_release_pfn_clean(pfn);
2026 return 0;
2027 }
2028
2029
2030 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2031 {
2032 int i;
2033 struct kvm_mmu_page *sp;
2034
2035 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2036 return;
2037 spin_lock(&vcpu->kvm->mmu_lock);
2038 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2039 hpa_t root = vcpu->arch.mmu.root_hpa;
2040
2041 sp = page_header(root);
2042 --sp->root_count;
2043 if (!sp->root_count && sp->role.invalid)
2044 kvm_mmu_zap_page(vcpu->kvm, sp);
2045 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2046 spin_unlock(&vcpu->kvm->mmu_lock);
2047 return;
2048 }
2049 for (i = 0; i < 4; ++i) {
2050 hpa_t root = vcpu->arch.mmu.pae_root[i];
2051
2052 if (root) {
2053 root &= PT64_BASE_ADDR_MASK;
2054 sp = page_header(root);
2055 --sp->root_count;
2056 if (!sp->root_count && sp->role.invalid)
2057 kvm_mmu_zap_page(vcpu->kvm, sp);
2058 }
2059 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2060 }
2061 spin_unlock(&vcpu->kvm->mmu_lock);
2062 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2063 }
2064
2065 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2066 {
2067 int ret = 0;
2068
2069 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2070 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2071 ret = 1;
2072 }
2073
2074 return ret;
2075 }
2076
2077 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2078 {
2079 int i;
2080 gfn_t root_gfn;
2081 struct kvm_mmu_page *sp;
2082 int direct = 0;
2083 u64 pdptr;
2084
2085 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
2086
2087 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2088 hpa_t root = vcpu->arch.mmu.root_hpa;
2089
2090 ASSERT(!VALID_PAGE(root));
2091 if (tdp_enabled)
2092 direct = 1;
2093 if (mmu_check_root(vcpu, root_gfn))
2094 return 1;
2095 spin_lock(&vcpu->kvm->mmu_lock);
2096 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
2097 PT64_ROOT_LEVEL, direct,
2098 ACC_ALL, NULL);
2099 root = __pa(sp->spt);
2100 ++sp->root_count;
2101 spin_unlock(&vcpu->kvm->mmu_lock);
2102 vcpu->arch.mmu.root_hpa = root;
2103 return 0;
2104 }
2105 direct = !is_paging(vcpu);
2106 if (tdp_enabled)
2107 direct = 1;
2108 for (i = 0; i < 4; ++i) {
2109 hpa_t root = vcpu->arch.mmu.pae_root[i];
2110
2111 ASSERT(!VALID_PAGE(root));
2112 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2113 pdptr = kvm_pdptr_read(vcpu, i);
2114 if (!is_present_gpte(pdptr)) {
2115 vcpu->arch.mmu.pae_root[i] = 0;
2116 continue;
2117 }
2118 root_gfn = pdptr >> PAGE_SHIFT;
2119 } else if (vcpu->arch.mmu.root_level == 0)
2120 root_gfn = 0;
2121 if (mmu_check_root(vcpu, root_gfn))
2122 return 1;
2123 spin_lock(&vcpu->kvm->mmu_lock);
2124 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2125 PT32_ROOT_LEVEL, direct,
2126 ACC_ALL, NULL);
2127 root = __pa(sp->spt);
2128 ++sp->root_count;
2129 spin_unlock(&vcpu->kvm->mmu_lock);
2130
2131 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2132 }
2133 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2134 return 0;
2135 }
2136
2137 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2138 {
2139 int i;
2140 struct kvm_mmu_page *sp;
2141
2142 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2143 return;
2144 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2145 hpa_t root = vcpu->arch.mmu.root_hpa;
2146 sp = page_header(root);
2147 mmu_sync_children(vcpu, sp);
2148 return;
2149 }
2150 for (i = 0; i < 4; ++i) {
2151 hpa_t root = vcpu->arch.mmu.pae_root[i];
2152
2153 if (root && VALID_PAGE(root)) {
2154 root &= PT64_BASE_ADDR_MASK;
2155 sp = page_header(root);
2156 mmu_sync_children(vcpu, sp);
2157 }
2158 }
2159 }
2160
2161 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2162 {
2163 spin_lock(&vcpu->kvm->mmu_lock);
2164 mmu_sync_roots(vcpu);
2165 spin_unlock(&vcpu->kvm->mmu_lock);
2166 }
2167
2168 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2169 u32 access, u32 *error)
2170 {
2171 if (error)
2172 *error = 0;
2173 return vaddr;
2174 }
2175
2176 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2177 u32 error_code)
2178 {
2179 gfn_t gfn;
2180 int r;
2181
2182 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2183 r = mmu_topup_memory_caches(vcpu);
2184 if (r)
2185 return r;
2186
2187 ASSERT(vcpu);
2188 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2189
2190 gfn = gva >> PAGE_SHIFT;
2191
2192 return nonpaging_map(vcpu, gva & PAGE_MASK,
2193 error_code & PFERR_WRITE_MASK, gfn);
2194 }
2195
2196 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2197 u32 error_code)
2198 {
2199 pfn_t pfn;
2200 int r;
2201 int level;
2202 gfn_t gfn = gpa >> PAGE_SHIFT;
2203 unsigned long mmu_seq;
2204
2205 ASSERT(vcpu);
2206 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2207
2208 r = mmu_topup_memory_caches(vcpu);
2209 if (r)
2210 return r;
2211
2212 level = mapping_level(vcpu, gfn);
2213
2214 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2215
2216 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2217 smp_rmb();
2218 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2219 if (is_error_pfn(pfn)) {
2220 kvm_release_pfn_clean(pfn);
2221 return 1;
2222 }
2223 spin_lock(&vcpu->kvm->mmu_lock);
2224 if (mmu_notifier_retry(vcpu, mmu_seq))
2225 goto out_unlock;
2226 kvm_mmu_free_some_pages(vcpu);
2227 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
2228 level, gfn, pfn);
2229 spin_unlock(&vcpu->kvm->mmu_lock);
2230
2231 return r;
2232
2233 out_unlock:
2234 spin_unlock(&vcpu->kvm->mmu_lock);
2235 kvm_release_pfn_clean(pfn);
2236 return 0;
2237 }
2238
2239 static void nonpaging_free(struct kvm_vcpu *vcpu)
2240 {
2241 mmu_free_roots(vcpu);
2242 }
2243
2244 static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2245 {
2246 struct kvm_mmu *context = &vcpu->arch.mmu;
2247
2248 context->new_cr3 = nonpaging_new_cr3;
2249 context->page_fault = nonpaging_page_fault;
2250 context->gva_to_gpa = nonpaging_gva_to_gpa;
2251 context->free = nonpaging_free;
2252 context->prefetch_page = nonpaging_prefetch_page;
2253 context->sync_page = nonpaging_sync_page;
2254 context->invlpg = nonpaging_invlpg;
2255 context->root_level = 0;
2256 context->shadow_root_level = PT32E_ROOT_LEVEL;
2257 context->root_hpa = INVALID_PAGE;
2258 return 0;
2259 }
2260
2261 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2262 {
2263 ++vcpu->stat.tlb_flush;
2264 kvm_x86_ops->tlb_flush(vcpu);
2265 }
2266
2267 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2268 {
2269 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
2270 mmu_free_roots(vcpu);
2271 }
2272
2273 static void inject_page_fault(struct kvm_vcpu *vcpu,
2274 u64 addr,
2275 u32 err_code)
2276 {
2277 kvm_inject_page_fault(vcpu, addr, err_code);
2278 }
2279
2280 static void paging_free(struct kvm_vcpu *vcpu)
2281 {
2282 nonpaging_free(vcpu);
2283 }
2284
2285 static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2286 {
2287 int bit7;
2288
2289 bit7 = (gpte >> 7) & 1;
2290 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2291 }
2292
2293 #define PTTYPE 64
2294 #include "paging_tmpl.h"
2295 #undef PTTYPE
2296
2297 #define PTTYPE 32
2298 #include "paging_tmpl.h"
2299 #undef PTTYPE
2300
2301 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2302 {
2303 struct kvm_mmu *context = &vcpu->arch.mmu;
2304 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2305 u64 exb_bit_rsvd = 0;
2306
2307 if (!is_nx(vcpu))
2308 exb_bit_rsvd = rsvd_bits(63, 63);
2309 switch (level) {
2310 case PT32_ROOT_LEVEL:
2311 /* no rsvd bits for 2 level 4K page table entries */
2312 context->rsvd_bits_mask[0][1] = 0;
2313 context->rsvd_bits_mask[0][0] = 0;
2314 if (is_cpuid_PSE36())
2315 /* 36bits PSE 4MB page */
2316 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2317 else
2318 /* 32 bits PSE 4MB page */
2319 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2320 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2321 break;
2322 case PT32E_ROOT_LEVEL:
2323 context->rsvd_bits_mask[0][2] =
2324 rsvd_bits(maxphyaddr, 63) |
2325 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2326 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2327 rsvd_bits(maxphyaddr, 62); /* PDE */
2328 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2329 rsvd_bits(maxphyaddr, 62); /* PTE */
2330 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2331 rsvd_bits(maxphyaddr, 62) |
2332 rsvd_bits(13, 20); /* large page */
2333 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2334 break;
2335 case PT64_ROOT_LEVEL:
2336 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2337 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2338 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2339 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2340 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2341 rsvd_bits(maxphyaddr, 51);
2342 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2343 rsvd_bits(maxphyaddr, 51);
2344 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2345 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2346 rsvd_bits(maxphyaddr, 51) |
2347 rsvd_bits(13, 29);
2348 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2349 rsvd_bits(maxphyaddr, 51) |
2350 rsvd_bits(13, 20); /* large page */
2351 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2352 break;
2353 }
2354 }
2355
2356 static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
2357 {
2358 struct kvm_mmu *context = &vcpu->arch.mmu;
2359
2360 ASSERT(is_pae(vcpu));
2361 context->new_cr3 = paging_new_cr3;
2362 context->page_fault = paging64_page_fault;
2363 context->gva_to_gpa = paging64_gva_to_gpa;
2364 context->prefetch_page = paging64_prefetch_page;
2365 context->sync_page = paging64_sync_page;
2366 context->invlpg = paging64_invlpg;
2367 context->free = paging_free;
2368 context->root_level = level;
2369 context->shadow_root_level = level;
2370 context->root_hpa = INVALID_PAGE;
2371 return 0;
2372 }
2373
2374 static int paging64_init_context(struct kvm_vcpu *vcpu)
2375 {
2376 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2377 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2378 }
2379
2380 static int paging32_init_context(struct kvm_vcpu *vcpu)
2381 {
2382 struct kvm_mmu *context = &vcpu->arch.mmu;
2383
2384 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2385 context->new_cr3 = paging_new_cr3;
2386 context->page_fault = paging32_page_fault;
2387 context->gva_to_gpa = paging32_gva_to_gpa;
2388 context->free = paging_free;
2389 context->prefetch_page = paging32_prefetch_page;
2390 context->sync_page = paging32_sync_page;
2391 context->invlpg = paging32_invlpg;
2392 context->root_level = PT32_ROOT_LEVEL;
2393 context->shadow_root_level = PT32E_ROOT_LEVEL;
2394 context->root_hpa = INVALID_PAGE;
2395 return 0;
2396 }
2397
2398 static int paging32E_init_context(struct kvm_vcpu *vcpu)
2399 {
2400 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2401 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
2402 }
2403
2404 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2405 {
2406 struct kvm_mmu *context = &vcpu->arch.mmu;
2407
2408 context->new_cr3 = nonpaging_new_cr3;
2409 context->page_fault = tdp_page_fault;
2410 context->free = nonpaging_free;
2411 context->prefetch_page = nonpaging_prefetch_page;
2412 context->sync_page = nonpaging_sync_page;
2413 context->invlpg = nonpaging_invlpg;
2414 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2415 context->root_hpa = INVALID_PAGE;
2416
2417 if (!is_paging(vcpu)) {
2418 context->gva_to_gpa = nonpaging_gva_to_gpa;
2419 context->root_level = 0;
2420 } else if (is_long_mode(vcpu)) {
2421 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2422 context->gva_to_gpa = paging64_gva_to_gpa;
2423 context->root_level = PT64_ROOT_LEVEL;
2424 } else if (is_pae(vcpu)) {
2425 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2426 context->gva_to_gpa = paging64_gva_to_gpa;
2427 context->root_level = PT32E_ROOT_LEVEL;
2428 } else {
2429 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2430 context->gva_to_gpa = paging32_gva_to_gpa;
2431 context->root_level = PT32_ROOT_LEVEL;
2432 }
2433
2434 return 0;
2435 }
2436
2437 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2438 {
2439 int r;
2440
2441 ASSERT(vcpu);
2442 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2443
2444 if (!is_paging(vcpu))
2445 r = nonpaging_init_context(vcpu);
2446 else if (is_long_mode(vcpu))
2447 r = paging64_init_context(vcpu);
2448 else if (is_pae(vcpu))
2449 r = paging32E_init_context(vcpu);
2450 else
2451 r = paging32_init_context(vcpu);
2452
2453 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2454 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2455
2456 return r;
2457 }
2458
2459 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2460 {
2461 vcpu->arch.update_pte.pfn = bad_pfn;
2462
2463 if (tdp_enabled)
2464 return init_kvm_tdp_mmu(vcpu);
2465 else
2466 return init_kvm_softmmu(vcpu);
2467 }
2468
2469 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2470 {
2471 ASSERT(vcpu);
2472 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2473 vcpu->arch.mmu.free(vcpu);
2474 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2475 }
2476 }
2477
2478 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
2479 {
2480 destroy_kvm_mmu(vcpu);
2481 return init_kvm_mmu(vcpu);
2482 }
2483 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
2484
2485 int kvm_mmu_load(struct kvm_vcpu *vcpu)
2486 {
2487 int r;
2488
2489 r = mmu_topup_memory_caches(vcpu);
2490 if (r)
2491 goto out;
2492 spin_lock(&vcpu->kvm->mmu_lock);
2493 kvm_mmu_free_some_pages(vcpu);
2494 spin_unlock(&vcpu->kvm->mmu_lock);
2495 r = mmu_alloc_roots(vcpu);
2496 spin_lock(&vcpu->kvm->mmu_lock);
2497 mmu_sync_roots(vcpu);
2498 spin_unlock(&vcpu->kvm->mmu_lock);
2499 if (r)
2500 goto out;
2501 /* set_cr3() should ensure TLB has been flushed */
2502 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
2503 out:
2504 return r;
2505 }
2506 EXPORT_SYMBOL_GPL(kvm_mmu_load);
2507
2508 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2509 {
2510 mmu_free_roots(vcpu);
2511 }
2512
2513 static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
2514 struct kvm_mmu_page *sp,
2515 u64 *spte)
2516 {
2517 u64 pte;
2518 struct kvm_mmu_page *child;
2519
2520 pte = *spte;
2521 if (is_shadow_present_pte(pte)) {
2522 if (is_last_spte(pte, sp->role.level))
2523 rmap_remove(vcpu->kvm, spte);
2524 else {
2525 child = page_header(pte & PT64_BASE_ADDR_MASK);
2526 mmu_page_remove_parent_pte(child, spte);
2527 }
2528 }
2529 __set_spte(spte, shadow_trap_nonpresent_pte);
2530 if (is_large_pte(pte))
2531 --vcpu->kvm->stat.lpages;
2532 }
2533
2534 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
2535 struct kvm_mmu_page *sp,
2536 u64 *spte,
2537 const void *new)
2538 {
2539 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
2540 ++vcpu->kvm->stat.mmu_pde_zapped;
2541 return;
2542 }
2543
2544 ++vcpu->kvm->stat.mmu_pte_updated;
2545 if (sp->role.glevels == PT32_ROOT_LEVEL)
2546 paging32_update_pte(vcpu, sp, spte, new);
2547 else
2548 paging64_update_pte(vcpu, sp, spte, new);
2549 }
2550
2551 static bool need_remote_flush(u64 old, u64 new)
2552 {
2553 if (!is_shadow_present_pte(old))
2554 return false;
2555 if (!is_shadow_present_pte(new))
2556 return true;
2557 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2558 return true;
2559 old ^= PT64_NX_MASK;
2560 new ^= PT64_NX_MASK;
2561 return (old & ~new & PT64_PERM_MASK) != 0;
2562 }
2563
2564 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2565 {
2566 if (need_remote_flush(old, new))
2567 kvm_flush_remote_tlbs(vcpu->kvm);
2568 else
2569 kvm_mmu_flush_tlb(vcpu);
2570 }
2571
2572 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2573 {
2574 u64 *spte = vcpu->arch.last_pte_updated;
2575
2576 return !!(spte && (*spte & shadow_accessed_mask));
2577 }
2578
2579 static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2580 const u8 *new, int bytes)
2581 {
2582 gfn_t gfn;
2583 int r;
2584 u64 gpte = 0;
2585 pfn_t pfn;
2586
2587 if (bytes != 4 && bytes != 8)
2588 return;
2589
2590 /*
2591 * Assume that the pte write on a page table of the same type
2592 * as the current vcpu paging mode. This is nearly always true
2593 * (might be false while changing modes). Note it is verified later
2594 * by update_pte().
2595 */
2596 if (is_pae(vcpu)) {
2597 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2598 if ((bytes == 4) && (gpa % 4 == 0)) {
2599 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2600 if (r)
2601 return;
2602 memcpy((void *)&gpte + (gpa % 8), new, 4);
2603 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2604 memcpy((void *)&gpte, new, 8);
2605 }
2606 } else {
2607 if ((bytes == 4) && (gpa % 4 == 0))
2608 memcpy((void *)&gpte, new, 4);
2609 }
2610 if (!is_present_gpte(gpte))
2611 return;
2612 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
2613
2614 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
2615 smp_rmb();
2616 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2617
2618 if (is_error_pfn(pfn)) {
2619 kvm_release_pfn_clean(pfn);
2620 return;
2621 }
2622 vcpu->arch.update_pte.gfn = gfn;
2623 vcpu->arch.update_pte.pfn = pfn;
2624 }
2625
2626 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2627 {
2628 u64 *spte = vcpu->arch.last_pte_updated;
2629
2630 if (spte
2631 && vcpu->arch.last_pte_gfn == gfn
2632 && shadow_accessed_mask
2633 && !(*spte & shadow_accessed_mask)
2634 && is_shadow_present_pte(*spte))
2635 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2636 }
2637
2638 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2639 const u8 *new, int bytes,
2640 bool guest_initiated)
2641 {
2642 gfn_t gfn = gpa >> PAGE_SHIFT;
2643 struct kvm_mmu_page *sp;
2644 struct hlist_node *node, *n;
2645 struct hlist_head *bucket;
2646 unsigned index;
2647 u64 entry, gentry;
2648 u64 *spte;
2649 unsigned offset = offset_in_page(gpa);
2650 unsigned pte_size;
2651 unsigned page_offset;
2652 unsigned misaligned;
2653 unsigned quadrant;
2654 int level;
2655 int flooded = 0;
2656 int npte;
2657 int r;
2658
2659 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
2660 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
2661 spin_lock(&vcpu->kvm->mmu_lock);
2662 kvm_mmu_access_page(vcpu, gfn);
2663 kvm_mmu_free_some_pages(vcpu);
2664 ++vcpu->kvm->stat.mmu_pte_write;
2665 kvm_mmu_audit(vcpu, "pre pte write");
2666 if (guest_initiated) {
2667 if (gfn == vcpu->arch.last_pt_write_gfn
2668 && !last_updated_pte_accessed(vcpu)) {
2669 ++vcpu->arch.last_pt_write_count;
2670 if (vcpu->arch.last_pt_write_count >= 3)
2671 flooded = 1;
2672 } else {
2673 vcpu->arch.last_pt_write_gfn = gfn;
2674 vcpu->arch.last_pt_write_count = 1;
2675 vcpu->arch.last_pte_updated = NULL;
2676 }
2677 }
2678 index = kvm_page_table_hashfn(gfn);
2679 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
2680 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
2681 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
2682 continue;
2683 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
2684 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
2685 misaligned |= bytes < 4;
2686 if (misaligned || flooded) {
2687 /*
2688 * Misaligned accesses are too much trouble to fix
2689 * up; also, they usually indicate a page is not used
2690 * as a page table.
2691 *
2692 * If we're seeing too many writes to a page,
2693 * it may no longer be a page table, or we may be
2694 * forking, in which case it is better to unmap the
2695 * page.
2696 */
2697 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
2698 gpa, bytes, sp->role.word);
2699 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2700 n = bucket->first;
2701 ++vcpu->kvm->stat.mmu_flooded;
2702 continue;
2703 }
2704 page_offset = offset;
2705 level = sp->role.level;
2706 npte = 1;
2707 if (sp->role.glevels == PT32_ROOT_LEVEL) {
2708 page_offset <<= 1; /* 32->64 */
2709 /*
2710 * A 32-bit pde maps 4MB while the shadow pdes map
2711 * only 2MB. So we need to double the offset again
2712 * and zap two pdes instead of one.
2713 */
2714 if (level == PT32_ROOT_LEVEL) {
2715 page_offset &= ~7; /* kill rounding error */
2716 page_offset <<= 1;
2717 npte = 2;
2718 }
2719 quadrant = page_offset >> PAGE_SHIFT;
2720 page_offset &= ~PAGE_MASK;
2721 if (quadrant != sp->role.quadrant)
2722 continue;
2723 }
2724 spte = &sp->spt[page_offset / sizeof(*spte)];
2725 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2726 gentry = 0;
2727 r = kvm_read_guest_atomic(vcpu->kvm,
2728 gpa & ~(u64)(pte_size - 1),
2729 &gentry, pte_size);
2730 new = (const void *)&gentry;
2731 if (r < 0)
2732 new = NULL;
2733 }
2734 while (npte--) {
2735 entry = *spte;
2736 mmu_pte_write_zap_pte(vcpu, sp, spte);
2737 if (new)
2738 mmu_pte_write_new_pte(vcpu, sp, spte, new);
2739 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
2740 ++spte;
2741 }
2742 }
2743 kvm_mmu_audit(vcpu, "post pte write");
2744 spin_unlock(&vcpu->kvm->mmu_lock);
2745 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2746 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2747 vcpu->arch.update_pte.pfn = bad_pfn;
2748 }
2749 }
2750
2751 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2752 {
2753 gpa_t gpa;
2754 int r;
2755
2756 if (tdp_enabled)
2757 return 0;
2758
2759 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2760
2761 spin_lock(&vcpu->kvm->mmu_lock);
2762 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2763 spin_unlock(&vcpu->kvm->mmu_lock);
2764 return r;
2765 }
2766 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
2767
2768 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
2769 {
2770 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2771 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
2772 struct kvm_mmu_page *sp;
2773
2774 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
2775 struct kvm_mmu_page, link);
2776 kvm_mmu_zap_page(vcpu->kvm, sp);
2777 ++vcpu->kvm->stat.mmu_recycled;
2778 }
2779 }
2780
2781 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2782 {
2783 int r;
2784 enum emulation_result er;
2785
2786 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
2787 if (r < 0)
2788 goto out;
2789
2790 if (!r) {
2791 r = 1;
2792 goto out;
2793 }
2794
2795 r = mmu_topup_memory_caches(vcpu);
2796 if (r)
2797 goto out;
2798
2799 er = emulate_instruction(vcpu, cr2, error_code, 0);
2800
2801 switch (er) {
2802 case EMULATE_DONE:
2803 return 1;
2804 case EMULATE_DO_MMIO:
2805 ++vcpu->stat.mmio_exits;
2806 return 0;
2807 case EMULATE_FAIL:
2808 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2809 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2810 vcpu->run->internal.ndata = 0;
2811 return 0;
2812 default:
2813 BUG();
2814 }
2815 out:
2816 return r;
2817 }
2818 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2819
2820 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2821 {
2822 vcpu->arch.mmu.invlpg(vcpu, gva);
2823 kvm_mmu_flush_tlb(vcpu);
2824 ++vcpu->stat.invlpg;
2825 }
2826 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2827
2828 void kvm_enable_tdp(void)
2829 {
2830 tdp_enabled = true;
2831 }
2832 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2833
2834 void kvm_disable_tdp(void)
2835 {
2836 tdp_enabled = false;
2837 }
2838 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2839
2840 static void free_mmu_pages(struct kvm_vcpu *vcpu)
2841 {
2842 free_page((unsigned long)vcpu->arch.mmu.pae_root);
2843 }
2844
2845 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2846 {
2847 struct page *page;
2848 int i;
2849
2850 ASSERT(vcpu);
2851
2852 /*
2853 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2854 * Therefore we need to allocate shadow page tables in the first
2855 * 4GB of memory, which happens to fit the DMA32 zone.
2856 */
2857 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2858 if (!page)
2859 return -ENOMEM;
2860
2861 vcpu->arch.mmu.pae_root = page_address(page);
2862 for (i = 0; i < 4; ++i)
2863 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2864
2865 return 0;
2866 }
2867
2868 int kvm_mmu_create(struct kvm_vcpu *vcpu)
2869 {
2870 ASSERT(vcpu);
2871 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2872
2873 return alloc_mmu_pages(vcpu);
2874 }
2875
2876 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2877 {
2878 ASSERT(vcpu);
2879 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2880
2881 return init_kvm_mmu(vcpu);
2882 }
2883
2884 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2885 {
2886 ASSERT(vcpu);
2887
2888 destroy_kvm_mmu(vcpu);
2889 free_mmu_pages(vcpu);
2890 mmu_free_memory_caches(vcpu);
2891 }
2892
2893 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
2894 {
2895 struct kvm_mmu_page *sp;
2896
2897 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
2898 int i;
2899 u64 *pt;
2900
2901 if (!test_bit(slot, sp->slot_bitmap))
2902 continue;
2903
2904 pt = sp->spt;
2905 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2906 /* avoid RMW */
2907 if (pt[i] & PT_WRITABLE_MASK)
2908 pt[i] &= ~PT_WRITABLE_MASK;
2909 }
2910 kvm_flush_remote_tlbs(kvm);
2911 }
2912
2913 void kvm_mmu_zap_all(struct kvm *kvm)
2914 {
2915 struct kvm_mmu_page *sp, *node;
2916
2917 spin_lock(&kvm->mmu_lock);
2918 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
2919 if (kvm_mmu_zap_page(kvm, sp))
2920 node = container_of(kvm->arch.active_mmu_pages.next,
2921 struct kvm_mmu_page, link);
2922 spin_unlock(&kvm->mmu_lock);
2923
2924 kvm_flush_remote_tlbs(kvm);
2925 }
2926
2927 static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
2928 {
2929 struct kvm_mmu_page *page;
2930
2931 page = container_of(kvm->arch.active_mmu_pages.prev,
2932 struct kvm_mmu_page, link);
2933 kvm_mmu_zap_page(kvm, page);
2934 }
2935
2936 static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2937 {
2938 struct kvm *kvm;
2939 struct kvm *kvm_freed = NULL;
2940 int cache_count = 0;
2941
2942 spin_lock(&kvm_lock);
2943
2944 list_for_each_entry(kvm, &vm_list, vm_list) {
2945 int npages, idx;
2946
2947 idx = srcu_read_lock(&kvm->srcu);
2948 spin_lock(&kvm->mmu_lock);
2949 npages = kvm->arch.n_alloc_mmu_pages -
2950 kvm->arch.n_free_mmu_pages;
2951 cache_count += npages;
2952 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2953 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2954 cache_count--;
2955 kvm_freed = kvm;
2956 }
2957 nr_to_scan--;
2958
2959 spin_unlock(&kvm->mmu_lock);
2960 srcu_read_unlock(&kvm->srcu, idx);
2961 }
2962 if (kvm_freed)
2963 list_move_tail(&kvm_freed->vm_list, &vm_list);
2964
2965 spin_unlock(&kvm_lock);
2966
2967 return cache_count;
2968 }
2969
2970 static struct shrinker mmu_shrinker = {
2971 .shrink = mmu_shrink,
2972 .seeks = DEFAULT_SEEKS * 10,
2973 };
2974
2975 static void mmu_destroy_caches(void)
2976 {
2977 if (pte_chain_cache)
2978 kmem_cache_destroy(pte_chain_cache);
2979 if (rmap_desc_cache)
2980 kmem_cache_destroy(rmap_desc_cache);
2981 if (mmu_page_header_cache)
2982 kmem_cache_destroy(mmu_page_header_cache);
2983 }
2984
2985 void kvm_mmu_module_exit(void)
2986 {
2987 mmu_destroy_caches();
2988 unregister_shrinker(&mmu_shrinker);
2989 }
2990
2991 int kvm_mmu_module_init(void)
2992 {
2993 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
2994 sizeof(struct kvm_pte_chain),
2995 0, 0, NULL);
2996 if (!pte_chain_cache)
2997 goto nomem;
2998 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
2999 sizeof(struct kvm_rmap_desc),
3000 0, 0, NULL);
3001 if (!rmap_desc_cache)
3002 goto nomem;
3003
3004 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3005 sizeof(struct kvm_mmu_page),
3006 0, 0, NULL);
3007 if (!mmu_page_header_cache)
3008 goto nomem;
3009
3010 register_shrinker(&mmu_shrinker);
3011
3012 return 0;
3013
3014 nomem:
3015 mmu_destroy_caches();
3016 return -ENOMEM;
3017 }
3018
3019 /*
3020 * Caculate mmu pages needed for kvm.
3021 */
3022 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3023 {
3024 int i;
3025 unsigned int nr_mmu_pages;
3026 unsigned int nr_pages = 0;
3027 struct kvm_memslots *slots;
3028
3029 slots = rcu_dereference(kvm->memslots);
3030 for (i = 0; i < slots->nmemslots; i++)
3031 nr_pages += slots->memslots[i].npages;
3032
3033 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3034 nr_mmu_pages = max(nr_mmu_pages,
3035 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3036
3037 return nr_mmu_pages;
3038 }
3039
3040 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3041 unsigned len)
3042 {
3043 if (len > buffer->len)
3044 return NULL;
3045 return buffer->ptr;
3046 }
3047
3048 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3049 unsigned len)
3050 {
3051 void *ret;
3052
3053 ret = pv_mmu_peek_buffer(buffer, len);
3054 if (!ret)
3055 return ret;
3056 buffer->ptr += len;
3057 buffer->len -= len;
3058 buffer->processed += len;
3059 return ret;
3060 }
3061
3062 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3063 gpa_t addr, gpa_t value)
3064 {
3065 int bytes = 8;
3066 int r;
3067
3068 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3069 bytes = 4;
3070
3071 r = mmu_topup_memory_caches(vcpu);
3072 if (r)
3073 return r;
3074
3075 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3076 return -EFAULT;
3077
3078 return 1;
3079 }
3080
3081 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3082 {
3083 kvm_set_cr3(vcpu, vcpu->arch.cr3);
3084 return 1;
3085 }
3086
3087 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3088 {
3089 spin_lock(&vcpu->kvm->mmu_lock);
3090 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3091 spin_unlock(&vcpu->kvm->mmu_lock);
3092 return 1;
3093 }
3094
3095 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3096 struct kvm_pv_mmu_op_buffer *buffer)
3097 {
3098 struct kvm_mmu_op_header *header;
3099
3100 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3101 if (!header)
3102 return 0;
3103 switch (header->op) {
3104 case KVM_MMU_OP_WRITE_PTE: {
3105 struct kvm_mmu_op_write_pte *wpte;
3106
3107 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3108 if (!wpte)
3109 return 0;
3110 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3111 wpte->pte_val);
3112 }
3113 case KVM_MMU_OP_FLUSH_TLB: {
3114 struct kvm_mmu_op_flush_tlb *ftlb;
3115
3116 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3117 if (!ftlb)
3118 return 0;
3119 return kvm_pv_mmu_flush_tlb(vcpu);
3120 }
3121 case KVM_MMU_OP_RELEASE_PT: {
3122 struct kvm_mmu_op_release_pt *rpt;
3123
3124 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3125 if (!rpt)
3126 return 0;
3127 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3128 }
3129 default: return 0;
3130 }
3131 }
3132
3133 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3134 gpa_t addr, unsigned long *ret)
3135 {
3136 int r;
3137 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3138
3139 buffer->ptr = buffer->buf;
3140 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3141 buffer->processed = 0;
3142
3143 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3144 if (r)
3145 goto out;
3146
3147 while (buffer->len) {
3148 r = kvm_pv_mmu_op_one(vcpu, buffer);
3149 if (r < 0)
3150 goto out;
3151 if (r == 0)
3152 break;
3153 }
3154
3155 r = 1;
3156 out:
3157 *ret = buffer->processed;
3158 return r;
3159 }
3160
3161 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3162 {
3163 struct kvm_shadow_walk_iterator iterator;
3164 int nr_sptes = 0;
3165
3166 spin_lock(&vcpu->kvm->mmu_lock);
3167 for_each_shadow_entry(vcpu, addr, iterator) {
3168 sptes[iterator.level-1] = *iterator.sptep;
3169 nr_sptes++;
3170 if (!is_shadow_present_pte(*iterator.sptep))
3171 break;
3172 }
3173 spin_unlock(&vcpu->kvm->mmu_lock);
3174
3175 return nr_sptes;
3176 }
3177 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3178
3179 #ifdef AUDIT
3180
3181 static const char *audit_msg;
3182
3183 static gva_t canonicalize(gva_t gva)
3184 {
3185 #ifdef CONFIG_X86_64
3186 gva = (long long)(gva << 16) >> 16;
3187 #endif
3188 return gva;
3189 }
3190
3191
3192 typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3193 u64 *sptep);
3194
3195 static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3196 inspect_spte_fn fn)
3197 {
3198 int i;
3199
3200 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3201 u64 ent = sp->spt[i];
3202
3203 if (is_shadow_present_pte(ent)) {
3204 if (!is_last_spte(ent, sp->role.level)) {
3205 struct kvm_mmu_page *child;
3206 child = page_header(ent & PT64_BASE_ADDR_MASK);
3207 __mmu_spte_walk(kvm, child, fn);
3208 } else
3209 fn(kvm, sp, &sp->spt[i]);
3210 }
3211 }
3212 }
3213
3214 static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3215 {
3216 int i;
3217 struct kvm_mmu_page *sp;
3218
3219 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3220 return;
3221 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3222 hpa_t root = vcpu->arch.mmu.root_hpa;
3223 sp = page_header(root);
3224 __mmu_spte_walk(vcpu->kvm, sp, fn);
3225 return;
3226 }
3227 for (i = 0; i < 4; ++i) {
3228 hpa_t root = vcpu->arch.mmu.pae_root[i];
3229
3230 if (root && VALID_PAGE(root)) {
3231 root &= PT64_BASE_ADDR_MASK;
3232 sp = page_header(root);
3233 __mmu_spte_walk(vcpu->kvm, sp, fn);
3234 }
3235 }
3236 return;
3237 }
3238
3239 static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3240 gva_t va, int level)
3241 {
3242 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3243 int i;
3244 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3245
3246 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3247 u64 ent = pt[i];
3248
3249 if (ent == shadow_trap_nonpresent_pte)
3250 continue;
3251
3252 va = canonicalize(va);
3253 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3254 audit_mappings_page(vcpu, ent, va, level - 1);
3255 else {
3256 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
3257 gfn_t gfn = gpa >> PAGE_SHIFT;
3258 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3259 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
3260
3261 if (is_error_pfn(pfn)) {
3262 kvm_release_pfn_clean(pfn);
3263 continue;
3264 }
3265
3266 if (is_shadow_present_pte(ent)
3267 && (ent & PT64_BASE_ADDR_MASK) != hpa)
3268 printk(KERN_ERR "xx audit error: (%s) levels %d"
3269 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
3270 audit_msg, vcpu->arch.mmu.root_level,
3271 va, gpa, hpa, ent,
3272 is_shadow_present_pte(ent));
3273 else if (ent == shadow_notrap_nonpresent_pte
3274 && !is_error_hpa(hpa))
3275 printk(KERN_ERR "audit: (%s) notrap shadow,"
3276 " valid guest gva %lx\n", audit_msg, va);
3277 kvm_release_pfn_clean(pfn);
3278
3279 }
3280 }
3281 }
3282
3283 static void audit_mappings(struct kvm_vcpu *vcpu)
3284 {
3285 unsigned i;
3286
3287 if (vcpu->arch.mmu.root_level == 4)
3288 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
3289 else
3290 for (i = 0; i < 4; ++i)
3291 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
3292 audit_mappings_page(vcpu,
3293 vcpu->arch.mmu.pae_root[i],
3294 i << 30,
3295 2);
3296 }
3297
3298 static int count_rmaps(struct kvm_vcpu *vcpu)
3299 {
3300 int nmaps = 0;
3301 int i, j, k, idx;
3302
3303 idx = srcu_read_lock(&kvm->srcu);
3304 slots = rcu_dereference(kvm->memslots);
3305 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3306 struct kvm_memory_slot *m = &slots->memslots[i];
3307 struct kvm_rmap_desc *d;
3308
3309 for (j = 0; j < m->npages; ++j) {
3310 unsigned long *rmapp = &m->rmap[j];
3311
3312 if (!*rmapp)
3313 continue;
3314 if (!(*rmapp & 1)) {
3315 ++nmaps;
3316 continue;
3317 }
3318 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
3319 while (d) {
3320 for (k = 0; k < RMAP_EXT; ++k)
3321 if (d->sptes[k])
3322 ++nmaps;
3323 else
3324 break;
3325 d = d->more;
3326 }
3327 }
3328 }
3329 srcu_read_unlock(&kvm->srcu, idx);
3330 return nmaps;
3331 }
3332
3333 void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3334 {
3335 unsigned long *rmapp;
3336 struct kvm_mmu_page *rev_sp;
3337 gfn_t gfn;
3338
3339 if (*sptep & PT_WRITABLE_MASK) {
3340 rev_sp = page_header(__pa(sptep));
3341 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3342
3343 if (!gfn_to_memslot(kvm, gfn)) {
3344 if (!printk_ratelimit())
3345 return;
3346 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3347 audit_msg, gfn);
3348 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3349 audit_msg, sptep - rev_sp->spt,
3350 rev_sp->gfn);
3351 dump_stack();
3352 return;
3353 }
3354
3355 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3356 is_large_pte(*sptep));
3357 if (!*rmapp) {
3358 if (!printk_ratelimit())
3359 return;
3360 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3361 audit_msg, *sptep);
3362 dump_stack();
3363 }
3364 }
3365
3366 }
3367
3368 void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3369 {
3370 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3371 }
3372
3373 static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
3374 {
3375 struct kvm_mmu_page *sp;
3376 int i;
3377
3378 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3379 u64 *pt = sp->spt;
3380
3381 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
3382 continue;
3383
3384 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3385 u64 ent = pt[i];
3386
3387 if (!(ent & PT_PRESENT_MASK))
3388 continue;
3389 if (!(ent & PT_WRITABLE_MASK))
3390 continue;
3391 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
3392 }
3393 }
3394 return;
3395 }
3396
3397 static void audit_rmap(struct kvm_vcpu *vcpu)
3398 {
3399 check_writable_mappings_rmap(vcpu);
3400 count_rmaps(vcpu);
3401 }
3402
3403 static void audit_write_protection(struct kvm_vcpu *vcpu)
3404 {
3405 struct kvm_mmu_page *sp;
3406 struct kvm_memory_slot *slot;
3407 unsigned long *rmapp;
3408 u64 *spte;
3409 gfn_t gfn;
3410
3411 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3412 if (sp->role.direct)
3413 continue;
3414 if (sp->unsync)
3415 continue;
3416
3417 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
3418 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
3419 rmapp = &slot->rmap[gfn - slot->base_gfn];
3420
3421 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3422 while (spte) {
3423 if (*spte & PT_WRITABLE_MASK)
3424 printk(KERN_ERR "%s: (%s) shadow page has "
3425 "writable mappings: gfn %lx role %x\n",
3426 __func__, audit_msg, sp->gfn,
3427 sp->role.word);
3428 spte = rmap_next(vcpu->kvm, rmapp, spte);
3429 }
3430 }
3431 }
3432
3433 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3434 {
3435 int olddbg = dbg;
3436
3437 dbg = 0;
3438 audit_msg = msg;
3439 audit_rmap(vcpu);
3440 audit_write_protection(vcpu);
3441 if (strcmp("pre pte write", audit_msg) != 0)
3442 audit_mappings(vcpu);
3443 audit_writable_sptes_have_rmaps(vcpu);
3444 dbg = olddbg;
3445 }
3446
3447 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree