percpu: add __percpu for sparse.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ixgbe / ixgbe_common.c
blob6621e172df3d79533e391777bb2cb0e78050e75a
1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/list.h>
32 #include <linux/netdevice.h>
34 #include "ixgbe.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 u16 count);
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
52 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
53 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
55 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
56 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
58 /**
59 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
60 * @hw: pointer to hardware structure
62 * Starts the hardware by filling the bus info structure and media type, clears
63 * all on chip counters, initializes receive address registers, multicast
64 * table, VLAN filter table, calls routine to set up link and flow control
65 * settings, and leaves transmit and receive units disabled and uninitialized
66 **/
67 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
69 u32 ctrl_ext;
71 /* Set the media type */
72 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
74 /* Identify the PHY */
75 hw->phy.ops.identify(hw);
77 /* Clear the VLAN filter table */
78 hw->mac.ops.clear_vfta(hw);
80 /* Clear statistics registers */
81 hw->mac.ops.clear_hw_cntrs(hw);
83 /* Set No Snoop Disable */
84 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
85 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
86 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
87 IXGBE_WRITE_FLUSH(hw);
89 /* Setup flow control */
90 ixgbe_setup_fc(hw, 0);
92 /* Clear adapter stopped flag */
93 hw->adapter_stopped = false;
95 return 0;
98 /**
99 * ixgbe_init_hw_generic - Generic hardware initialization
100 * @hw: pointer to hardware structure
102 * Initialize the hardware by resetting the hardware, filling the bus info
103 * structure and media type, clears all on chip counters, initializes receive
104 * address registers, multicast table, VLAN filter table, calls routine to set
105 * up link and flow control settings, and leaves transmit and receive units
106 * disabled and uninitialized
108 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
110 s32 status;
112 /* Reset the hardware */
113 status = hw->mac.ops.reset_hw(hw);
115 if (status == 0) {
116 /* Start the HW */
117 status = hw->mac.ops.start_hw(hw);
120 return status;
124 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
125 * @hw: pointer to hardware structure
127 * Clears all hardware statistics counters by reading them from the hardware
128 * Statistics counters are clear on read.
130 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
132 u16 i = 0;
134 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
135 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
136 IXGBE_READ_REG(hw, IXGBE_ERRBC);
137 IXGBE_READ_REG(hw, IXGBE_MSPDC);
138 for (i = 0; i < 8; i++)
139 IXGBE_READ_REG(hw, IXGBE_MPC(i));
141 IXGBE_READ_REG(hw, IXGBE_MLFC);
142 IXGBE_READ_REG(hw, IXGBE_MRFC);
143 IXGBE_READ_REG(hw, IXGBE_RLEC);
144 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
145 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
146 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
147 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
149 for (i = 0; i < 8; i++) {
150 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
152 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
153 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
156 IXGBE_READ_REG(hw, IXGBE_PRC64);
157 IXGBE_READ_REG(hw, IXGBE_PRC127);
158 IXGBE_READ_REG(hw, IXGBE_PRC255);
159 IXGBE_READ_REG(hw, IXGBE_PRC511);
160 IXGBE_READ_REG(hw, IXGBE_PRC1023);
161 IXGBE_READ_REG(hw, IXGBE_PRC1522);
162 IXGBE_READ_REG(hw, IXGBE_GPRC);
163 IXGBE_READ_REG(hw, IXGBE_BPRC);
164 IXGBE_READ_REG(hw, IXGBE_MPRC);
165 IXGBE_READ_REG(hw, IXGBE_GPTC);
166 IXGBE_READ_REG(hw, IXGBE_GORCL);
167 IXGBE_READ_REG(hw, IXGBE_GORCH);
168 IXGBE_READ_REG(hw, IXGBE_GOTCL);
169 IXGBE_READ_REG(hw, IXGBE_GOTCH);
170 for (i = 0; i < 8; i++)
171 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
172 IXGBE_READ_REG(hw, IXGBE_RUC);
173 IXGBE_READ_REG(hw, IXGBE_RFC);
174 IXGBE_READ_REG(hw, IXGBE_ROC);
175 IXGBE_READ_REG(hw, IXGBE_RJC);
176 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
177 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
178 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
179 IXGBE_READ_REG(hw, IXGBE_TORL);
180 IXGBE_READ_REG(hw, IXGBE_TORH);
181 IXGBE_READ_REG(hw, IXGBE_TPR);
182 IXGBE_READ_REG(hw, IXGBE_TPT);
183 IXGBE_READ_REG(hw, IXGBE_PTC64);
184 IXGBE_READ_REG(hw, IXGBE_PTC127);
185 IXGBE_READ_REG(hw, IXGBE_PTC255);
186 IXGBE_READ_REG(hw, IXGBE_PTC511);
187 IXGBE_READ_REG(hw, IXGBE_PTC1023);
188 IXGBE_READ_REG(hw, IXGBE_PTC1522);
189 IXGBE_READ_REG(hw, IXGBE_MPTC);
190 IXGBE_READ_REG(hw, IXGBE_BPTC);
191 for (i = 0; i < 16; i++) {
192 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
193 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
194 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
195 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
198 return 0;
202 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
203 * @hw: pointer to hardware structure
204 * @pba_num: stores the part number from the EEPROM
206 * Reads the part number from the EEPROM.
208 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
210 s32 ret_val;
211 u16 data;
213 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
214 if (ret_val) {
215 hw_dbg(hw, "NVM Read Error\n");
216 return ret_val;
218 *pba_num = (u32)(data << 16);
220 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
221 if (ret_val) {
222 hw_dbg(hw, "NVM Read Error\n");
223 return ret_val;
225 *pba_num |= data;
227 return 0;
231 * ixgbe_get_mac_addr_generic - Generic get MAC address
232 * @hw: pointer to hardware structure
233 * @mac_addr: Adapter MAC address
235 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
236 * A reset of the adapter must be performed prior to calling this function
237 * in order for the MAC address to have been loaded from the EEPROM into RAR0
239 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
241 u32 rar_high;
242 u32 rar_low;
243 u16 i;
245 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
246 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
248 for (i = 0; i < 4; i++)
249 mac_addr[i] = (u8)(rar_low >> (i*8));
251 for (i = 0; i < 2; i++)
252 mac_addr[i+4] = (u8)(rar_high >> (i*8));
254 return 0;
258 * ixgbe_get_bus_info_generic - Generic set PCI bus info
259 * @hw: pointer to hardware structure
261 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
263 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
265 struct ixgbe_adapter *adapter = hw->back;
266 struct ixgbe_mac_info *mac = &hw->mac;
267 u16 link_status;
269 hw->bus.type = ixgbe_bus_type_pci_express;
271 /* Get the negotiated link width and speed from PCI config space */
272 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
273 &link_status);
275 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
276 case IXGBE_PCI_LINK_WIDTH_1:
277 hw->bus.width = ixgbe_bus_width_pcie_x1;
278 break;
279 case IXGBE_PCI_LINK_WIDTH_2:
280 hw->bus.width = ixgbe_bus_width_pcie_x2;
281 break;
282 case IXGBE_PCI_LINK_WIDTH_4:
283 hw->bus.width = ixgbe_bus_width_pcie_x4;
284 break;
285 case IXGBE_PCI_LINK_WIDTH_8:
286 hw->bus.width = ixgbe_bus_width_pcie_x8;
287 break;
288 default:
289 hw->bus.width = ixgbe_bus_width_unknown;
290 break;
293 switch (link_status & IXGBE_PCI_LINK_SPEED) {
294 case IXGBE_PCI_LINK_SPEED_2500:
295 hw->bus.speed = ixgbe_bus_speed_2500;
296 break;
297 case IXGBE_PCI_LINK_SPEED_5000:
298 hw->bus.speed = ixgbe_bus_speed_5000;
299 break;
300 default:
301 hw->bus.speed = ixgbe_bus_speed_unknown;
302 break;
305 mac->ops.set_lan_id(hw);
307 return 0;
311 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
312 * @hw: pointer to the HW structure
314 * Determines the LAN function id by reading memory-mapped registers
315 * and swaps the port value if requested.
317 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
319 struct ixgbe_bus_info *bus = &hw->bus;
320 u32 reg;
322 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
323 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
324 bus->lan_id = bus->func;
326 /* check for a port swap */
327 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
328 if (reg & IXGBE_FACTPS_LFS)
329 bus->func ^= 0x1;
333 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
334 * @hw: pointer to hardware structure
336 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
337 * disables transmit and receive units. The adapter_stopped flag is used by
338 * the shared code and drivers to determine if the adapter is in a stopped
339 * state and should not touch the hardware.
341 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
343 u32 number_of_queues;
344 u32 reg_val;
345 u16 i;
348 * Set the adapter_stopped flag so other driver functions stop touching
349 * the hardware
351 hw->adapter_stopped = true;
353 /* Disable the receive unit */
354 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
355 reg_val &= ~(IXGBE_RXCTRL_RXEN);
356 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
357 IXGBE_WRITE_FLUSH(hw);
358 msleep(2);
360 /* Clear interrupt mask to stop from interrupts being generated */
361 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
363 /* Clear any pending interrupts */
364 IXGBE_READ_REG(hw, IXGBE_EICR);
366 /* Disable the transmit unit. Each queue must be disabled. */
367 number_of_queues = hw->mac.max_tx_queues;
368 for (i = 0; i < number_of_queues; i++) {
369 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
370 if (reg_val & IXGBE_TXDCTL_ENABLE) {
371 reg_val &= ~IXGBE_TXDCTL_ENABLE;
372 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
377 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
378 * access and verify no pending requests
380 if (ixgbe_disable_pcie_master(hw) != 0)
381 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
383 return 0;
387 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
388 * @hw: pointer to hardware structure
389 * @index: led number to turn on
391 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
393 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
395 /* To turn on the LED, set mode to ON. */
396 led_reg &= ~IXGBE_LED_MODE_MASK(index);
397 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
398 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
399 IXGBE_WRITE_FLUSH(hw);
401 return 0;
405 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
406 * @hw: pointer to hardware structure
407 * @index: led number to turn off
409 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
411 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
413 /* To turn off the LED, set mode to OFF. */
414 led_reg &= ~IXGBE_LED_MODE_MASK(index);
415 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
416 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
417 IXGBE_WRITE_FLUSH(hw);
419 return 0;
423 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
424 * @hw: pointer to hardware structure
426 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
427 * ixgbe_hw struct in order to set up EEPROM access.
429 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
431 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
432 u32 eec;
433 u16 eeprom_size;
435 if (eeprom->type == ixgbe_eeprom_uninitialized) {
436 eeprom->type = ixgbe_eeprom_none;
437 /* Set default semaphore delay to 10ms which is a well
438 * tested value */
439 eeprom->semaphore_delay = 10;
442 * Check for EEPROM present first.
443 * If not present leave as none
445 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
446 if (eec & IXGBE_EEC_PRES) {
447 eeprom->type = ixgbe_eeprom_spi;
450 * SPI EEPROM is assumed here. This code would need to
451 * change if a future EEPROM is not SPI.
453 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
454 IXGBE_EEC_SIZE_SHIFT);
455 eeprom->word_size = 1 << (eeprom_size +
456 IXGBE_EEPROM_WORD_SIZE_SHIFT);
459 if (eec & IXGBE_EEC_ADDR_SIZE)
460 eeprom->address_bits = 16;
461 else
462 eeprom->address_bits = 8;
463 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
464 "%d\n", eeprom->type, eeprom->word_size,
465 eeprom->address_bits);
468 return 0;
472 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
473 * @hw: pointer to hardware structure
474 * @offset: offset within the EEPROM to be written to
475 * @data: 16 bit word to be written to the EEPROM
477 * If ixgbe_eeprom_update_checksum is not called after this function, the
478 * EEPROM will most likely contain an invalid checksum.
480 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
482 s32 status;
483 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
485 hw->eeprom.ops.init_params(hw);
487 if (offset >= hw->eeprom.word_size) {
488 status = IXGBE_ERR_EEPROM;
489 goto out;
492 /* Prepare the EEPROM for writing */
493 status = ixgbe_acquire_eeprom(hw);
495 if (status == 0) {
496 if (ixgbe_ready_eeprom(hw) != 0) {
497 ixgbe_release_eeprom(hw);
498 status = IXGBE_ERR_EEPROM;
502 if (status == 0) {
503 ixgbe_standby_eeprom(hw);
505 /* Send the WRITE ENABLE command (8 bit opcode ) */
506 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
507 IXGBE_EEPROM_OPCODE_BITS);
509 ixgbe_standby_eeprom(hw);
512 * Some SPI eeproms use the 8th address bit embedded in the
513 * opcode
515 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
516 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
518 /* Send the Write command (8-bit opcode + addr) */
519 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
520 IXGBE_EEPROM_OPCODE_BITS);
521 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
522 hw->eeprom.address_bits);
524 /* Send the data */
525 data = (data >> 8) | (data << 8);
526 ixgbe_shift_out_eeprom_bits(hw, data, 16);
527 ixgbe_standby_eeprom(hw);
529 msleep(hw->eeprom.semaphore_delay);
530 /* Done with writing - release the EEPROM */
531 ixgbe_release_eeprom(hw);
534 out:
535 return status;
539 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
540 * @hw: pointer to hardware structure
541 * @offset: offset within the EEPROM to be read
542 * @data: read 16 bit value from EEPROM
544 * Reads 16 bit value from EEPROM through bit-bang method
546 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
547 u16 *data)
549 s32 status;
550 u16 word_in;
551 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
553 hw->eeprom.ops.init_params(hw);
555 if (offset >= hw->eeprom.word_size) {
556 status = IXGBE_ERR_EEPROM;
557 goto out;
560 /* Prepare the EEPROM for reading */
561 status = ixgbe_acquire_eeprom(hw);
563 if (status == 0) {
564 if (ixgbe_ready_eeprom(hw) != 0) {
565 ixgbe_release_eeprom(hw);
566 status = IXGBE_ERR_EEPROM;
570 if (status == 0) {
571 ixgbe_standby_eeprom(hw);
574 * Some SPI eeproms use the 8th address bit embedded in the
575 * opcode
577 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
578 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
580 /* Send the READ command (opcode + addr) */
581 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
582 IXGBE_EEPROM_OPCODE_BITS);
583 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
584 hw->eeprom.address_bits);
586 /* Read the data. */
587 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
588 *data = (word_in >> 8) | (word_in << 8);
590 /* End this read operation */
591 ixgbe_release_eeprom(hw);
594 out:
595 return status;
599 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
600 * @hw: pointer to hardware structure
601 * @offset: offset of word in the EEPROM to read
602 * @data: word read from the EEPROM
604 * Reads a 16 bit word from the EEPROM using the EERD register.
606 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
608 u32 eerd;
609 s32 status;
611 hw->eeprom.ops.init_params(hw);
613 if (offset >= hw->eeprom.word_size) {
614 status = IXGBE_ERR_EEPROM;
615 goto out;
618 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
619 IXGBE_EEPROM_READ_REG_START;
621 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
622 status = ixgbe_poll_eeprom_eerd_done(hw);
624 if (status == 0)
625 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
626 IXGBE_EEPROM_READ_REG_DATA);
627 else
628 hw_dbg(hw, "Eeprom read timed out\n");
630 out:
631 return status;
635 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
636 * @hw: pointer to hardware structure
638 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
640 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
642 u32 i;
643 u32 reg;
644 s32 status = IXGBE_ERR_EEPROM;
646 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
647 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
648 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
649 status = 0;
650 break;
652 udelay(5);
654 return status;
658 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
659 * @hw: pointer to hardware structure
661 * Prepares EEPROM for access using bit-bang method. This function should
662 * be called before issuing a command to the EEPROM.
664 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
666 s32 status = 0;
667 u32 eec = 0;
668 u32 i;
670 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
671 status = IXGBE_ERR_SWFW_SYNC;
673 if (status == 0) {
674 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
676 /* Request EEPROM Access */
677 eec |= IXGBE_EEC_REQ;
678 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
680 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
681 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
682 if (eec & IXGBE_EEC_GNT)
683 break;
684 udelay(5);
687 /* Release if grant not acquired */
688 if (!(eec & IXGBE_EEC_GNT)) {
689 eec &= ~IXGBE_EEC_REQ;
690 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
691 hw_dbg(hw, "Could not acquire EEPROM grant\n");
693 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
694 status = IXGBE_ERR_EEPROM;
698 /* Setup EEPROM for Read/Write */
699 if (status == 0) {
700 /* Clear CS and SK */
701 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
702 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
703 IXGBE_WRITE_FLUSH(hw);
704 udelay(1);
706 return status;
710 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
711 * @hw: pointer to hardware structure
713 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
715 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
717 s32 status = IXGBE_ERR_EEPROM;
718 u32 timeout;
719 u32 i;
720 u32 swsm;
722 /* Set timeout value based on size of EEPROM */
723 timeout = hw->eeprom.word_size + 1;
725 /* Get SMBI software semaphore between device drivers first */
726 for (i = 0; i < timeout; i++) {
728 * If the SMBI bit is 0 when we read it, then the bit will be
729 * set and we have the semaphore
731 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
732 if (!(swsm & IXGBE_SWSM_SMBI)) {
733 status = 0;
734 break;
736 msleep(1);
739 /* Now get the semaphore between SW/FW through the SWESMBI bit */
740 if (status == 0) {
741 for (i = 0; i < timeout; i++) {
742 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
744 /* Set the SW EEPROM semaphore bit to request access */
745 swsm |= IXGBE_SWSM_SWESMBI;
746 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
749 * If we set the bit successfully then we got the
750 * semaphore.
752 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
753 if (swsm & IXGBE_SWSM_SWESMBI)
754 break;
756 udelay(50);
760 * Release semaphores and return error if SW EEPROM semaphore
761 * was not granted because we don't have access to the EEPROM
763 if (i >= timeout) {
764 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
765 "not granted.\n");
766 ixgbe_release_eeprom_semaphore(hw);
767 status = IXGBE_ERR_EEPROM;
771 return status;
775 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
776 * @hw: pointer to hardware structure
778 * This function clears hardware semaphore bits.
780 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
782 u32 swsm;
784 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
786 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
787 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
788 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
789 IXGBE_WRITE_FLUSH(hw);
793 * ixgbe_ready_eeprom - Polls for EEPROM ready
794 * @hw: pointer to hardware structure
796 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
798 s32 status = 0;
799 u16 i;
800 u8 spi_stat_reg;
803 * Read "Status Register" repeatedly until the LSB is cleared. The
804 * EEPROM will signal that the command has been completed by clearing
805 * bit 0 of the internal status register. If it's not cleared within
806 * 5 milliseconds, then error out.
808 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
809 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
810 IXGBE_EEPROM_OPCODE_BITS);
811 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
812 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
813 break;
815 udelay(5);
816 ixgbe_standby_eeprom(hw);
820 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
821 * devices (and only 0-5mSec on 5V devices)
823 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
824 hw_dbg(hw, "SPI EEPROM Status error\n");
825 status = IXGBE_ERR_EEPROM;
828 return status;
832 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
833 * @hw: pointer to hardware structure
835 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
837 u32 eec;
839 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
841 /* Toggle CS to flush commands */
842 eec |= IXGBE_EEC_CS;
843 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
844 IXGBE_WRITE_FLUSH(hw);
845 udelay(1);
846 eec &= ~IXGBE_EEC_CS;
847 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
848 IXGBE_WRITE_FLUSH(hw);
849 udelay(1);
853 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
854 * @hw: pointer to hardware structure
855 * @data: data to send to the EEPROM
856 * @count: number of bits to shift out
858 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
859 u16 count)
861 u32 eec;
862 u32 mask;
863 u32 i;
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
868 * Mask is used to shift "count" bits of "data" out to the EEPROM
869 * one bit at a time. Determine the starting bit based on count
871 mask = 0x01 << (count - 1);
873 for (i = 0; i < count; i++) {
875 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
876 * "1", and then raising and then lowering the clock (the SK
877 * bit controls the clock input to the EEPROM). A "0" is
878 * shifted out to the EEPROM by setting "DI" to "0" and then
879 * raising and then lowering the clock.
881 if (data & mask)
882 eec |= IXGBE_EEC_DI;
883 else
884 eec &= ~IXGBE_EEC_DI;
886 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
887 IXGBE_WRITE_FLUSH(hw);
889 udelay(1);
891 ixgbe_raise_eeprom_clk(hw, &eec);
892 ixgbe_lower_eeprom_clk(hw, &eec);
895 * Shift mask to signify next bit of data to shift in to the
896 * EEPROM
898 mask = mask >> 1;
901 /* We leave the "DI" bit set to "0" when we leave this routine. */
902 eec &= ~IXGBE_EEC_DI;
903 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
904 IXGBE_WRITE_FLUSH(hw);
908 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
909 * @hw: pointer to hardware structure
911 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
913 u32 eec;
914 u32 i;
915 u16 data = 0;
918 * In order to read a register from the EEPROM, we need to shift
919 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
920 * the clock input to the EEPROM (setting the SK bit), and then reading
921 * the value of the "DO" bit. During this "shifting in" process the
922 * "DI" bit should always be clear.
924 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
926 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
928 for (i = 0; i < count; i++) {
929 data = data << 1;
930 ixgbe_raise_eeprom_clk(hw, &eec);
932 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
934 eec &= ~(IXGBE_EEC_DI);
935 if (eec & IXGBE_EEC_DO)
936 data |= 1;
938 ixgbe_lower_eeprom_clk(hw, &eec);
941 return data;
945 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
946 * @hw: pointer to hardware structure
947 * @eec: EEC register's current value
949 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
952 * Raise the clock input to the EEPROM
953 * (setting the SK bit), then delay
955 *eec = *eec | IXGBE_EEC_SK;
956 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
957 IXGBE_WRITE_FLUSH(hw);
958 udelay(1);
962 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
963 * @hw: pointer to hardware structure
964 * @eecd: EECD's current value
966 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
969 * Lower the clock input to the EEPROM (clearing the SK bit), then
970 * delay
972 *eec = *eec & ~IXGBE_EEC_SK;
973 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
974 IXGBE_WRITE_FLUSH(hw);
975 udelay(1);
979 * ixgbe_release_eeprom - Release EEPROM, release semaphores
980 * @hw: pointer to hardware structure
982 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
984 u32 eec;
986 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
988 eec |= IXGBE_EEC_CS; /* Pull CS high */
989 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
991 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
992 IXGBE_WRITE_FLUSH(hw);
994 udelay(1);
996 /* Stop requesting EEPROM access */
997 eec &= ~IXGBE_EEC_REQ;
998 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1000 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1004 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1005 * @hw: pointer to hardware structure
1007 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1009 u16 i;
1010 u16 j;
1011 u16 checksum = 0;
1012 u16 length = 0;
1013 u16 pointer = 0;
1014 u16 word = 0;
1016 /* Include 0x0-0x3F in the checksum */
1017 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1018 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1019 hw_dbg(hw, "EEPROM read failed\n");
1020 break;
1022 checksum += word;
1025 /* Include all data from pointers except for the fw pointer */
1026 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1027 hw->eeprom.ops.read(hw, i, &pointer);
1029 /* Make sure the pointer seems valid */
1030 if (pointer != 0xFFFF && pointer != 0) {
1031 hw->eeprom.ops.read(hw, pointer, &length);
1033 if (length != 0xFFFF && length != 0) {
1034 for (j = pointer+1; j <= pointer+length; j++) {
1035 hw->eeprom.ops.read(hw, j, &word);
1036 checksum += word;
1042 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1044 return checksum;
1048 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1049 * @hw: pointer to hardware structure
1050 * @checksum_val: calculated checksum
1052 * Performs checksum calculation and validates the EEPROM checksum. If the
1053 * caller does not need checksum_val, the value can be NULL.
1055 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1056 u16 *checksum_val)
1058 s32 status;
1059 u16 checksum;
1060 u16 read_checksum = 0;
1063 * Read the first word from the EEPROM. If this times out or fails, do
1064 * not continue or we could be in for a very long wait while every
1065 * EEPROM read fails
1067 status = hw->eeprom.ops.read(hw, 0, &checksum);
1069 if (status == 0) {
1070 checksum = ixgbe_calc_eeprom_checksum(hw);
1072 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1075 * Verify read checksum from EEPROM is the same as
1076 * calculated checksum
1078 if (read_checksum != checksum)
1079 status = IXGBE_ERR_EEPROM_CHECKSUM;
1081 /* If the user cares, return the calculated checksum */
1082 if (checksum_val)
1083 *checksum_val = checksum;
1084 } else {
1085 hw_dbg(hw, "EEPROM read failed\n");
1088 return status;
1092 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1093 * @hw: pointer to hardware structure
1095 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1097 s32 status;
1098 u16 checksum;
1101 * Read the first word from the EEPROM. If this times out or fails, do
1102 * not continue or we could be in for a very long wait while every
1103 * EEPROM read fails
1105 status = hw->eeprom.ops.read(hw, 0, &checksum);
1107 if (status == 0) {
1108 checksum = ixgbe_calc_eeprom_checksum(hw);
1109 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1110 checksum);
1111 } else {
1112 hw_dbg(hw, "EEPROM read failed\n");
1115 return status;
1119 * ixgbe_validate_mac_addr - Validate MAC address
1120 * @mac_addr: pointer to MAC address.
1122 * Tests a MAC address to ensure it is a valid Individual Address
1124 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1126 s32 status = 0;
1128 /* Make sure it is not a multicast address */
1129 if (IXGBE_IS_MULTICAST(mac_addr))
1130 status = IXGBE_ERR_INVALID_MAC_ADDR;
1131 /* Not a broadcast address */
1132 else if (IXGBE_IS_BROADCAST(mac_addr))
1133 status = IXGBE_ERR_INVALID_MAC_ADDR;
1134 /* Reject the zero address */
1135 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1136 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1137 status = IXGBE_ERR_INVALID_MAC_ADDR;
1139 return status;
1143 * ixgbe_set_rar_generic - Set Rx address register
1144 * @hw: pointer to hardware structure
1145 * @index: Receive address register to write
1146 * @addr: Address to put into receive address register
1147 * @vmdq: VMDq "set" or "pool" index
1148 * @enable_addr: set flag that address is active
1150 * Puts an ethernet address into a receive address register.
1152 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1153 u32 enable_addr)
1155 u32 rar_low, rar_high;
1156 u32 rar_entries = hw->mac.num_rar_entries;
1158 /* setup VMDq pool selection before this RAR gets enabled */
1159 hw->mac.ops.set_vmdq(hw, index, vmdq);
1161 /* Make sure we are using a valid rar index range */
1162 if (index < rar_entries) {
1164 * HW expects these in little endian so we reverse the byte
1165 * order from network order (big endian) to little endian
1167 rar_low = ((u32)addr[0] |
1168 ((u32)addr[1] << 8) |
1169 ((u32)addr[2] << 16) |
1170 ((u32)addr[3] << 24));
1172 * Some parts put the VMDq setting in the extra RAH bits,
1173 * so save everything except the lower 16 bits that hold part
1174 * of the address and the address valid bit.
1176 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1177 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1178 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1180 if (enable_addr != 0)
1181 rar_high |= IXGBE_RAH_AV;
1183 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1184 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1185 } else {
1186 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1189 return 0;
1193 * ixgbe_clear_rar_generic - Remove Rx address register
1194 * @hw: pointer to hardware structure
1195 * @index: Receive address register to write
1197 * Clears an ethernet address from a receive address register.
1199 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1201 u32 rar_high;
1202 u32 rar_entries = hw->mac.num_rar_entries;
1204 /* Make sure we are using a valid rar index range */
1205 if (index < rar_entries) {
1207 * Some parts put the VMDq setting in the extra RAH bits,
1208 * so save everything except the lower 16 bits that hold part
1209 * of the address and the address valid bit.
1211 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1212 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1214 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1215 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1216 } else {
1217 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1220 /* clear VMDq pool/queue selection for this RAR */
1221 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1223 return 0;
1227 * ixgbe_enable_rar - Enable Rx address register
1228 * @hw: pointer to hardware structure
1229 * @index: index into the RAR table
1231 * Enables the select receive address register.
1233 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1235 u32 rar_high;
1237 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1238 rar_high |= IXGBE_RAH_AV;
1239 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1243 * ixgbe_disable_rar - Disable Rx address register
1244 * @hw: pointer to hardware structure
1245 * @index: index into the RAR table
1247 * Disables the select receive address register.
1249 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1251 u32 rar_high;
1253 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1254 rar_high &= (~IXGBE_RAH_AV);
1255 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1259 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1260 * @hw: pointer to hardware structure
1262 * Places the MAC address in receive address register 0 and clears the rest
1263 * of the receive address registers. Clears the multicast table. Assumes
1264 * the receiver is in reset when the routine is called.
1266 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1268 u32 i;
1269 u32 rar_entries = hw->mac.num_rar_entries;
1272 * If the current mac address is valid, assume it is a software override
1273 * to the permanent address.
1274 * Otherwise, use the permanent address from the eeprom.
1276 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1277 IXGBE_ERR_INVALID_MAC_ADDR) {
1278 /* Get the MAC address from the RAR0 for later reference */
1279 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1281 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1282 hw->mac.addr[0], hw->mac.addr[1],
1283 hw->mac.addr[2]);
1284 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1285 hw->mac.addr[4], hw->mac.addr[5]);
1286 } else {
1287 /* Setup the receive address. */
1288 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1289 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1290 hw->mac.addr[0], hw->mac.addr[1],
1291 hw->mac.addr[2]);
1292 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1293 hw->mac.addr[4], hw->mac.addr[5]);
1295 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1297 hw->addr_ctrl.overflow_promisc = 0;
1299 hw->addr_ctrl.rar_used_count = 1;
1301 /* Zero out the other receive addresses. */
1302 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1303 for (i = 1; i < rar_entries; i++) {
1304 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1305 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1308 /* Clear the MTA */
1309 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1310 hw->addr_ctrl.mta_in_use = 0;
1311 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1313 hw_dbg(hw, " Clearing MTA\n");
1314 for (i = 0; i < hw->mac.mcft_size; i++)
1315 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1317 if (hw->mac.ops.init_uta_tables)
1318 hw->mac.ops.init_uta_tables(hw);
1320 return 0;
1324 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1325 * @hw: pointer to hardware structure
1326 * @addr: new address
1328 * Adds it to unused receive address register or goes into promiscuous mode.
1330 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1332 u32 rar_entries = hw->mac.num_rar_entries;
1333 u32 rar;
1335 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1336 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1339 * Place this address in the RAR if there is room,
1340 * else put the controller into promiscuous mode
1342 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1343 rar = hw->addr_ctrl.rar_used_count -
1344 hw->addr_ctrl.mc_addr_in_rar_count;
1345 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1346 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1347 hw->addr_ctrl.rar_used_count++;
1348 } else {
1349 hw->addr_ctrl.overflow_promisc++;
1352 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1356 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1357 * @hw: pointer to hardware structure
1358 * @addr_list: the list of new addresses
1359 * @addr_count: number of addresses
1360 * @next: iterator function to walk the address list
1362 * The given list replaces any existing list. Clears the secondary addrs from
1363 * receive address registers. Uses unused receive address registers for the
1364 * first secondary addresses, and falls back to promiscuous mode as needed.
1366 * Drivers using secondary unicast addresses must set user_set_promisc when
1367 * manually putting the device into promiscuous mode.
1369 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1370 struct list_head *uc_list)
1372 u32 i;
1373 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1374 u32 uc_addr_in_use;
1375 u32 fctrl;
1376 struct netdev_hw_addr *ha;
1379 * Clear accounting of old secondary address list,
1380 * don't count RAR[0]
1382 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1383 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1384 hw->addr_ctrl.overflow_promisc = 0;
1386 /* Zero out the other receive addresses */
1387 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
1388 for (i = 1; i <= uc_addr_in_use; i++) {
1389 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1390 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1393 /* Add the new addresses */
1394 list_for_each_entry(ha, uc_list, list) {
1395 hw_dbg(hw, " Adding the secondary addresses:\n");
1396 ixgbe_add_uc_addr(hw, ha->addr, 0);
1399 if (hw->addr_ctrl.overflow_promisc) {
1400 /* enable promisc if not already in overflow or set by user */
1401 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1402 hw_dbg(hw, " Entering address overflow promisc mode\n");
1403 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1404 fctrl |= IXGBE_FCTRL_UPE;
1405 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1407 } else {
1408 /* only disable if set by overflow, not by user */
1409 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1410 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1411 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1412 fctrl &= ~IXGBE_FCTRL_UPE;
1413 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1417 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1418 return 0;
1422 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1423 * @hw: pointer to hardware structure
1424 * @mc_addr: the multicast address
1426 * Extracts the 12 bits, from a multicast address, to determine which
1427 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1428 * incoming rx multicast addresses, to determine the bit-vector to check in
1429 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1430 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1431 * to mc_filter_type.
1433 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1435 u32 vector = 0;
1437 switch (hw->mac.mc_filter_type) {
1438 case 0: /* use bits [47:36] of the address */
1439 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1440 break;
1441 case 1: /* use bits [46:35] of the address */
1442 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1443 break;
1444 case 2: /* use bits [45:34] of the address */
1445 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1446 break;
1447 case 3: /* use bits [43:32] of the address */
1448 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1449 break;
1450 default: /* Invalid mc_filter_type */
1451 hw_dbg(hw, "MC filter type param set incorrectly\n");
1452 break;
1455 /* vector can only be 12-bits or boundary will be exceeded */
1456 vector &= 0xFFF;
1457 return vector;
1461 * ixgbe_set_mta - Set bit-vector in multicast table
1462 * @hw: pointer to hardware structure
1463 * @hash_value: Multicast address hash value
1465 * Sets the bit-vector in the multicast table.
1467 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1469 u32 vector;
1470 u32 vector_bit;
1471 u32 vector_reg;
1472 u32 mta_reg;
1474 hw->addr_ctrl.mta_in_use++;
1476 vector = ixgbe_mta_vector(hw, mc_addr);
1477 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1480 * The MTA is a register array of 128 32-bit registers. It is treated
1481 * like an array of 4096 bits. We want to set bit
1482 * BitArray[vector_value]. So we figure out what register the bit is
1483 * in, read it, OR in the new bit, then write back the new value. The
1484 * register is determined by the upper 7 bits of the vector value and
1485 * the bit within that register are determined by the lower 5 bits of
1486 * the value.
1488 vector_reg = (vector >> 5) & 0x7F;
1489 vector_bit = vector & 0x1F;
1490 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1491 mta_reg |= (1 << vector_bit);
1492 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1496 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1497 * @hw: pointer to hardware structure
1498 * @mc_addr_list: the list of new multicast addresses
1499 * @mc_addr_count: number of addresses
1500 * @next: iterator function to walk the multicast address list
1502 * The given list replaces any existing list. Clears the MC addrs from receive
1503 * address registers and the multicast table. Uses unused receive address
1504 * registers for the first multicast addresses, and hashes the rest into the
1505 * multicast table.
1507 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1508 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1510 u32 i;
1511 u32 vmdq;
1514 * Set the new number of MC addresses that we are being requested to
1515 * use.
1517 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1518 hw->addr_ctrl.mta_in_use = 0;
1520 /* Clear the MTA */
1521 hw_dbg(hw, " Clearing MTA\n");
1522 for (i = 0; i < hw->mac.mcft_size; i++)
1523 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1525 /* Add the new addresses */
1526 for (i = 0; i < mc_addr_count; i++) {
1527 hw_dbg(hw, " Adding the multicast addresses:\n");
1528 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1531 /* Enable mta */
1532 if (hw->addr_ctrl.mta_in_use > 0)
1533 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1534 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1536 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1537 return 0;
1541 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1542 * @hw: pointer to hardware structure
1544 * Enables multicast address in RAR and the use of the multicast hash table.
1546 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1548 u32 i;
1549 u32 rar_entries = hw->mac.num_rar_entries;
1550 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1552 if (a->mc_addr_in_rar_count > 0)
1553 for (i = (rar_entries - a->mc_addr_in_rar_count);
1554 i < rar_entries; i++)
1555 ixgbe_enable_rar(hw, i);
1557 if (a->mta_in_use > 0)
1558 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1559 hw->mac.mc_filter_type);
1561 return 0;
1565 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1566 * @hw: pointer to hardware structure
1568 * Disables multicast address in RAR and the use of the multicast hash table.
1570 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1572 u32 i;
1573 u32 rar_entries = hw->mac.num_rar_entries;
1574 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1576 if (a->mc_addr_in_rar_count > 0)
1577 for (i = (rar_entries - a->mc_addr_in_rar_count);
1578 i < rar_entries; i++)
1579 ixgbe_disable_rar(hw, i);
1581 if (a->mta_in_use > 0)
1582 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1584 return 0;
1588 * ixgbe_fc_enable_generic - Enable flow control
1589 * @hw: pointer to hardware structure
1590 * @packetbuf_num: packet buffer number (0-7)
1592 * Enable flow control according to the current settings.
1594 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1596 s32 ret_val = 0;
1597 u32 mflcn_reg, fccfg_reg;
1598 u32 reg;
1599 u32 rx_pba_size;
1601 #ifdef CONFIG_DCB
1602 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1603 goto out;
1605 #endif /* CONFIG_DCB */
1606 /* Negotiate the fc mode to use */
1607 ret_val = ixgbe_fc_autoneg(hw);
1608 if (ret_val)
1609 goto out;
1611 /* Disable any previous flow control settings */
1612 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1613 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1615 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1616 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1619 * The possible values of fc.current_mode are:
1620 * 0: Flow control is completely disabled
1621 * 1: Rx flow control is enabled (we can receive pause frames,
1622 * but not send pause frames).
1623 * 2: Tx flow control is enabled (we can send pause frames but
1624 * we do not support receiving pause frames).
1625 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1626 * 4: Priority Flow Control is enabled.
1627 * other: Invalid.
1629 switch (hw->fc.current_mode) {
1630 case ixgbe_fc_none:
1632 * Flow control is disabled by software override or autoneg.
1633 * The code below will actually disable it in the HW.
1635 break;
1636 case ixgbe_fc_rx_pause:
1638 * Rx Flow control is enabled and Tx Flow control is
1639 * disabled by software override. Since there really
1640 * isn't a way to advertise that we are capable of RX
1641 * Pause ONLY, we will advertise that we support both
1642 * symmetric and asymmetric Rx PAUSE. Later, we will
1643 * disable the adapter's ability to send PAUSE frames.
1645 mflcn_reg |= IXGBE_MFLCN_RFCE;
1646 break;
1647 case ixgbe_fc_tx_pause:
1649 * Tx Flow control is enabled, and Rx Flow control is
1650 * disabled by software override.
1652 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1653 break;
1654 case ixgbe_fc_full:
1655 /* Flow control (both Rx and Tx) is enabled by SW override. */
1656 mflcn_reg |= IXGBE_MFLCN_RFCE;
1657 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1658 break;
1659 #ifdef CONFIG_DCB
1660 case ixgbe_fc_pfc:
1661 goto out;
1662 break;
1663 #endif /* CONFIG_DCB */
1664 default:
1665 hw_dbg(hw, "Flow control param set incorrectly\n");
1666 ret_val = -IXGBE_ERR_CONFIG;
1667 goto out;
1668 break;
1671 /* Set 802.3x based flow control settings. */
1672 mflcn_reg |= IXGBE_MFLCN_DPF;
1673 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1674 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1676 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1677 /* Thresholds are different for link flow control when in DCB mode */
1678 if (reg & IXGBE_MTQC_RT_ENA) {
1679 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1681 /* Always disable XON for LFC when in DCB mode */
1682 reg = (rx_pba_size >> 5) & 0xFFE0;
1683 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1685 reg = (rx_pba_size >> 2) & 0xFFE0;
1686 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1687 reg |= IXGBE_FCRTH_FCEN;
1688 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1689 } else {
1691 * Set up and enable Rx high/low water mark thresholds,
1692 * enable XON.
1694 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1695 if (hw->fc.send_xon) {
1696 IXGBE_WRITE_REG(hw,
1697 IXGBE_FCRTL_82599(packetbuf_num),
1698 (hw->fc.low_water |
1699 IXGBE_FCRTL_XONE));
1700 } else {
1701 IXGBE_WRITE_REG(hw,
1702 IXGBE_FCRTL_82599(packetbuf_num),
1703 hw->fc.low_water);
1706 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1707 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1711 /* Configure pause time (2 TCs per register) */
1712 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1713 if ((packetbuf_num & 1) == 0)
1714 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1715 else
1716 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1717 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1719 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1721 out:
1722 return ret_val;
1726 * ixgbe_fc_autoneg - Configure flow control
1727 * @hw: pointer to hardware structure
1729 * Compares our advertised flow control capabilities to those advertised by
1730 * our link partner, and determines the proper flow control mode to use.
1732 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1734 s32 ret_val = 0;
1735 ixgbe_link_speed speed;
1736 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1737 bool link_up;
1740 * AN should have completed when the cable was plugged in.
1741 * Look for reasons to bail out. Bail out if:
1742 * - FC autoneg is disabled, or if
1743 * - we don't have multispeed fiber, or if
1744 * - we're not running at 1G, or if
1745 * - link is not up, or if
1746 * - link is up but AN did not complete, or if
1747 * - link is up and AN completed but timed out
1749 * Since we're being called from an LSC, link is already know to be up.
1750 * So use link_up_wait_to_complete=false.
1752 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1753 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1755 if (hw->fc.disable_fc_autoneg ||
1756 !hw->phy.multispeed_fiber ||
1757 (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
1758 !link_up ||
1759 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1760 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1761 hw->fc.fc_was_autonegged = false;
1762 hw->fc.current_mode = hw->fc.requested_mode;
1763 hw_dbg(hw, "Autoneg FC was skipped.\n");
1764 goto out;
1768 * Read the AN advertisement and LP ability registers and resolve
1769 * local flow control settings accordingly
1771 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1772 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1773 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1774 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1776 * Now we need to check if the user selected Rx ONLY
1777 * of pause frames. In this case, we had to advertise
1778 * FULL flow control because we could not advertise RX
1779 * ONLY. Hence, we must now check to see if we need to
1780 * turn OFF the TRANSMISSION of PAUSE frames.
1782 if (hw->fc.requested_mode == ixgbe_fc_full) {
1783 hw->fc.current_mode = ixgbe_fc_full;
1784 hw_dbg(hw, "Flow Control = FULL.\n");
1785 } else {
1786 hw->fc.current_mode = ixgbe_fc_rx_pause;
1787 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1789 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1790 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1791 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1792 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1793 hw->fc.current_mode = ixgbe_fc_tx_pause;
1794 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1795 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1796 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1797 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1798 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1799 hw->fc.current_mode = ixgbe_fc_rx_pause;
1800 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1801 } else {
1802 hw->fc.current_mode = ixgbe_fc_none;
1803 hw_dbg(hw, "Flow Control = NONE.\n");
1806 /* Record that current_mode is the result of a successful autoneg */
1807 hw->fc.fc_was_autonegged = true;
1809 out:
1810 return ret_val;
1814 * ixgbe_setup_fc - Set up flow control
1815 * @hw: pointer to hardware structure
1817 * Called at init time to set up flow control.
1819 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1821 s32 ret_val = 0;
1822 u32 reg;
1824 #ifdef CONFIG_DCB
1825 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1826 hw->fc.current_mode = hw->fc.requested_mode;
1827 goto out;
1830 #endif
1831 /* Validate the packetbuf configuration */
1832 if (packetbuf_num < 0 || packetbuf_num > 7) {
1833 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1834 "is 0-7\n", packetbuf_num);
1835 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1836 goto out;
1840 * Validate the water mark configuration. Zero water marks are invalid
1841 * because it causes the controller to just blast out fc packets.
1843 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1844 hw_dbg(hw, "Invalid water mark configuration\n");
1845 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1846 goto out;
1850 * Validate the requested mode. Strict IEEE mode does not allow
1851 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1853 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1854 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1855 "IEEE mode\n");
1856 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1857 goto out;
1861 * 10gig parts do not have a word in the EEPROM to determine the
1862 * default flow control setting, so we explicitly set it to full.
1864 if (hw->fc.requested_mode == ixgbe_fc_default)
1865 hw->fc.requested_mode = ixgbe_fc_full;
1868 * Set up the 1G flow control advertisement registers so the HW will be
1869 * able to do fc autoneg once the cable is plugged in. If we end up
1870 * using 10g instead, this is harmless.
1872 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1875 * The possible values of fc.requested_mode are:
1876 * 0: Flow control is completely disabled
1877 * 1: Rx flow control is enabled (we can receive pause frames,
1878 * but not send pause frames).
1879 * 2: Tx flow control is enabled (we can send pause frames but
1880 * we do not support receiving pause frames).
1881 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1882 #ifdef CONFIG_DCB
1883 * 4: Priority Flow Control is enabled.
1884 #endif
1885 * other: Invalid.
1887 switch (hw->fc.requested_mode) {
1888 case ixgbe_fc_none:
1889 /* Flow control completely disabled by software override. */
1890 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1891 break;
1892 case ixgbe_fc_rx_pause:
1894 * Rx Flow control is enabled and Tx Flow control is
1895 * disabled by software override. Since there really
1896 * isn't a way to advertise that we are capable of RX
1897 * Pause ONLY, we will advertise that we support both
1898 * symmetric and asymmetric Rx PAUSE. Later, we will
1899 * disable the adapter's ability to send PAUSE frames.
1901 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1902 break;
1903 case ixgbe_fc_tx_pause:
1905 * Tx Flow control is enabled, and Rx Flow control is
1906 * disabled by software override.
1908 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1909 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1910 break;
1911 case ixgbe_fc_full:
1912 /* Flow control (both Rx and Tx) is enabled by SW override. */
1913 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1914 break;
1915 #ifdef CONFIG_DCB
1916 case ixgbe_fc_pfc:
1917 goto out;
1918 break;
1919 #endif /* CONFIG_DCB */
1920 default:
1921 hw_dbg(hw, "Flow control param set incorrectly\n");
1922 ret_val = -IXGBE_ERR_CONFIG;
1923 goto out;
1924 break;
1927 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1928 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1930 /* Enable and restart autoneg to inform the link partner */
1931 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1933 /* Disable AN timeout */
1934 if (hw->fc.strict_ieee)
1935 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1937 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1938 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
1940 out:
1941 return ret_val;
1945 * ixgbe_disable_pcie_master - Disable PCI-express master access
1946 * @hw: pointer to hardware structure
1948 * Disables PCI-Express master access and verifies there are no pending
1949 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1950 * bit hasn't caused the master requests to be disabled, else 0
1951 * is returned signifying master requests disabled.
1953 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1955 u32 i;
1956 u32 reg_val;
1957 u32 number_of_queues;
1958 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1960 /* Disable the receive unit by stopping each queue */
1961 number_of_queues = hw->mac.max_rx_queues;
1962 for (i = 0; i < number_of_queues; i++) {
1963 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1964 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1965 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1966 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1970 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1971 reg_val |= IXGBE_CTRL_GIO_DIS;
1972 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
1974 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1975 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1976 status = 0;
1977 break;
1979 udelay(100);
1982 return status;
1987 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1988 * @hw: pointer to hardware structure
1989 * @mask: Mask to specify which semaphore to acquire
1991 * Acquires the SWFW semaphore thought the GSSR register for the specified
1992 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1994 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1996 u32 gssr;
1997 u32 swmask = mask;
1998 u32 fwmask = mask << 5;
1999 s32 timeout = 200;
2001 while (timeout) {
2002 if (ixgbe_get_eeprom_semaphore(hw))
2003 return -IXGBE_ERR_SWFW_SYNC;
2005 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2006 if (!(gssr & (fwmask | swmask)))
2007 break;
2010 * Firmware currently using resource (fwmask) or other software
2011 * thread currently using resource (swmask)
2013 ixgbe_release_eeprom_semaphore(hw);
2014 msleep(5);
2015 timeout--;
2018 if (!timeout) {
2019 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2020 return -IXGBE_ERR_SWFW_SYNC;
2023 gssr |= swmask;
2024 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2026 ixgbe_release_eeprom_semaphore(hw);
2027 return 0;
2031 * ixgbe_release_swfw_sync - Release SWFW semaphore
2032 * @hw: pointer to hardware structure
2033 * @mask: Mask to specify which semaphore to release
2035 * Releases the SWFW semaphore thought the GSSR register for the specified
2036 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2038 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2040 u32 gssr;
2041 u32 swmask = mask;
2043 ixgbe_get_eeprom_semaphore(hw);
2045 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2046 gssr &= ~swmask;
2047 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2049 ixgbe_release_eeprom_semaphore(hw);
2053 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2054 * @hw: pointer to hardware structure
2055 * @regval: register value to write to RXCTRL
2057 * Enables the Rx DMA unit
2059 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2061 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2063 return 0;
2067 * ixgbe_blink_led_start_generic - Blink LED based on index.
2068 * @hw: pointer to hardware structure
2069 * @index: led number to blink
2071 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2073 ixgbe_link_speed speed = 0;
2074 bool link_up = 0;
2075 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2076 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2079 * Link must be up to auto-blink the LEDs;
2080 * Force it if link is down.
2082 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2084 if (!link_up) {
2085 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2086 autoc_reg |= IXGBE_AUTOC_FLU;
2087 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2088 msleep(10);
2091 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2092 led_reg |= IXGBE_LED_BLINK(index);
2093 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2094 IXGBE_WRITE_FLUSH(hw);
2096 return 0;
2100 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2101 * @hw: pointer to hardware structure
2102 * @index: led number to stop blinking
2104 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2106 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2107 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2109 autoc_reg &= ~IXGBE_AUTOC_FLU;
2110 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2111 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2113 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2114 led_reg &= ~IXGBE_LED_BLINK(index);
2115 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2116 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2117 IXGBE_WRITE_FLUSH(hw);
2119 return 0;