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drm/i915: Wait for the clocks to stabilise before updating PLLs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob6ab195c0097f9bb78a8361863d71ddef0ed73a82
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static inline u32 /* units of 100MHz */
102 intel_fdi_link_freq(struct drm_device *dev)
103 {
104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
109 }
110
111 static const intel_limit_t intel_limits_i8xx_dvo = {
112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
122 .find_pll = intel_find_best_PLL,
123 };
124
125 static const intel_limit_t intel_limits_i8xx_lvds = {
126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
136 .find_pll = intel_find_best_PLL,
137 };
138
139 static const intel_limit_t intel_limits_i9xx_sdvo = {
140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
150 .find_pll = intel_find_best_PLL,
151 };
152
153 static const intel_limit_t intel_limits_i9xx_lvds = {
154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
164 .find_pll = intel_find_best_PLL,
165 };
166
167
168 static const intel_limit_t intel_limits_g4x_sdvo = {
169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
180 },
181 .find_pll = intel_g4x_find_best_PLL,
182 };
183
184 static const intel_limit_t intel_limits_g4x_hdmi = {
185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
195 .find_pll = intel_g4x_find_best_PLL,
196 };
197
198 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
209 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_display_port = {
229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 10, .p2_fast = 10 },
239 .find_pll = intel_find_pll_g4x_dp,
240 };
241
242 static const intel_limit_t intel_limits_pineview_sdvo = {
243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
245 /* Pineview's Ncounter is a ring counter */
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 /* Pineview only has one combined m divider, which we treat as m2. */
249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
255 .find_pll = intel_find_best_PLL,
256 };
257
258 static const intel_limit_t intel_limits_pineview_lvds = {
259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
269 .find_pll = intel_find_best_PLL,
270 };
271
272 /* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
277 static const intel_limit_t intel_limits_ironlake_dac = {
278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
288 .find_pll = intel_g4x_find_best_PLL,
289 };
290
291 static const intel_limit_t intel_limits_ironlake_single_lvds = {
292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
302 .find_pll = intel_g4x_find_best_PLL,
303 };
304
305 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
316 .find_pll = intel_g4x_find_best_PLL,
317 };
318
319 /* LVDS 100mhz refclk limits. */
320 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
342 .p1 = { .min = 2, .max = 6 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_ironlake_display_port = {
349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 10, .p2_fast = 10 },
359 .find_pll = intel_find_pll_ironlake_dp,
360 };
361
362 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363 {
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382 out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385 }
386
387 static void vlv_init_dpio(struct drm_device *dev)
388 {
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396 }
397
398 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399 {
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402 }
403
404 static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414 };
415
416 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418 {
419 unsigned int val;
420
421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
453 /* LVDS dual channel */
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
459 if (refclk == 100000)
460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
467 else
468 limit = &intel_limits_ironlake_dac;
469
470 return limit;
471 }
472
473 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474 {
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
480 if (is_dual_link_lvds(dev_priv, LVDS))
481 /* LVDS with dual channel */
482 limit = &intel_limits_g4x_dual_channel_lvds;
483 else
484 /* LVDS with dual channel */
485 limit = &intel_limits_g4x_single_channel_lvds;
486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
488 limit = &intel_limits_g4x_hdmi;
489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
490 limit = &intel_limits_g4x_sdvo;
491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
492 limit = &intel_limits_g4x_display_port;
493 } else /* The option is for other outputs */
494 limit = &intel_limits_i9xx_sdvo;
495
496 return limit;
497 }
498
499 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
500 {
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
504 if (HAS_PCH_SPLIT(dev))
505 limit = intel_ironlake_limit(crtc, refclk);
506 else if (IS_G4X(dev)) {
507 limit = intel_g4x_limit(crtc);
508 } else if (IS_PINEVIEW(dev)) {
509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_pineview_lvds;
511 else
512 limit = &intel_limits_pineview_sdvo;
513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_i8xx_lvds;
521 else
522 limit = &intel_limits_i8xx_dvo;
523 }
524 return limit;
525 }
526
527 /* m1 is reserved as 0 in Pineview, n is a ring counter */
528 static void pineview_clock(int refclk, intel_clock_t *clock)
529 {
530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534 }
535
536 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537 {
538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
540 return;
541 }
542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546 }
547
548 /**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
551 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
552 {
553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
562 }
563
564 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
565 /**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
570 static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
573 {
574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
575 INTELPllInvalid("p1 out of range\n");
576 if (clock->p < limit->p.min || limit->p.max < clock->p)
577 INTELPllInvalid("p out of range\n");
578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
579 INTELPllInvalid("m2 out of range\n");
580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
581 INTELPllInvalid("m1 out of range\n");
582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
583 INTELPllInvalid("m1 <= m2\n");
584 if (clock->m < limit->m.min || limit->m.max < clock->m)
585 INTELPllInvalid("m out of range\n");
586 if (clock->n < limit->n.min || limit->n.max < clock->n)
587 INTELPllInvalid("n out of range\n");
588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
589 INTELPllInvalid("vco out of range\n");
590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
594 INTELPllInvalid("dot out of range\n");
595
596 return true;
597 }
598
599 static bool
600 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
603
604 {
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
611 (I915_READ(LVDS)) != 0) {
612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
618 if (is_dual_link_lvds(dev_priv, LVDS))
619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
629 memset(best_clock, 0, sizeof(*best_clock));
630
631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
642 int this_err;
643
644 intel_clock(dev, refclk, &clock);
645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
647 continue;
648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663 }
664
665 static bool
666 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
680 int lvds_reg;
681
682 if (HAS_PCH_SPLIT(dev))
683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
700 /* based on hardware requirement, prefer smaller n to precision */
701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
702 /* based on hardware requirement, prefere larger m1,m2 */
703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
711 intel_clock(dev, refclk, &clock);
712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
714 continue;
715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
718
719 this_err = abs(clock.dot - target);
720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
730 return found;
731 }
732
733 static bool
734 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
737 {
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
740
741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757 }
758
759 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
760 static bool
761 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
785 }
786
787 /**
788 * intel_wait_for_vblank - wait for vblank on a given pipe
789 * @dev: drm device
790 * @pipe: pipe to wait for
791 *
792 * Wait for vblank to occur on a given pipe. Needed for various bits of
793 * mode setting code.
794 */
795 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
796 {
797 struct drm_i915_private *dev_priv = dev->dev_private;
798 int pipestat_reg = PIPESTAT(pipe);
799
800 /* Clear existing vblank status. Note this will clear any other
801 * sticky status fields as well.
802 *
803 * This races with i915_driver_irq_handler() with the result
804 * that either function could miss a vblank event. Here it is not
805 * fatal, as we will either wait upon the next vblank interrupt or
806 * timeout. Generally speaking intel_wait_for_vblank() is only
807 * called during modeset at which time the GPU should be idle and
808 * should *not* be performing page flips and thus not waiting on
809 * vblanks...
810 * Currently, the result of us stealing a vblank from the irq
811 * handler is that a single frame will be skipped during swapbuffers.
812 */
813 I915_WRITE(pipestat_reg,
814 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
815
816 /* Wait for vblank interrupt bit to set */
817 if (wait_for(I915_READ(pipestat_reg) &
818 PIPE_VBLANK_INTERRUPT_STATUS,
819 50))
820 DRM_DEBUG_KMS("vblank wait timed out\n");
821 }
822
823 /*
824 * intel_wait_for_pipe_off - wait for pipe to turn off
825 * @dev: drm device
826 * @pipe: pipe to wait for
827 *
828 * After disabling a pipe, we can't wait for vblank in the usual way,
829 * spinning on the vblank interrupt status bit, since we won't actually
830 * see an interrupt when the pipe is disabled.
831 *
832 * On Gen4 and above:
833 * wait for the pipe register state bit to turn off
834 *
835 * Otherwise:
836 * wait for the display line value to settle (it usually
837 * ends up stopping at the start of the next frame).
838 *
839 */
840 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
841 {
842 struct drm_i915_private *dev_priv = dev->dev_private;
843
844 if (INTEL_INFO(dev)->gen >= 4) {
845 int reg = PIPECONF(pipe);
846
847 /* Wait for the Pipe State to go off */
848 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
849 100))
850 DRM_DEBUG_KMS("pipe_off wait timed out\n");
851 } else {
852 u32 last_line;
853 int reg = PIPEDSL(pipe);
854 unsigned long timeout = jiffies + msecs_to_jiffies(100);
855
856 /* Wait for the display line to settle */
857 do {
858 last_line = I915_READ(reg) & DSL_LINEMASK;
859 mdelay(5);
860 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
861 time_after(timeout, jiffies));
862 if (time_after(jiffies, timeout))
863 DRM_DEBUG_KMS("pipe_off wait timed out\n");
864 }
865 }
866
867 static const char *state_string(bool enabled)
868 {
869 return enabled ? "on" : "off";
870 }
871
872 /* Only for pre-ILK configs */
873 static void assert_pll(struct drm_i915_private *dev_priv,
874 enum pipe pipe, bool state)
875 {
876 int reg;
877 u32 val;
878 bool cur_state;
879
880 reg = DPLL(pipe);
881 val = I915_READ(reg);
882 cur_state = !!(val & DPLL_VCO_ENABLE);
883 WARN(cur_state != state,
884 "PLL state assertion failure (expected %s, current %s)\n",
885 state_string(state), state_string(cur_state));
886 }
887 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
888 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
889
890 /* For ILK+ */
891 static void assert_pch_pll(struct drm_i915_private *dev_priv,
892 struct intel_crtc *intel_crtc, bool state)
893 {
894 int reg;
895 u32 val;
896 bool cur_state;
897
898 if (!intel_crtc->pch_pll) {
899 WARN(1, "asserting PCH PLL enabled with no PLL\n");
900 return;
901 }
902
903 if (HAS_PCH_CPT(dev_priv->dev)) {
904 u32 pch_dpll;
905
906 pch_dpll = I915_READ(PCH_DPLL_SEL);
907
908 /* Make sure the selected PLL is enabled to the transcoder */
909 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
910 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
911 }
912
913 reg = intel_crtc->pch_pll->pll_reg;
914 val = I915_READ(reg);
915 cur_state = !!(val & DPLL_VCO_ENABLE);
916 WARN(cur_state != state,
917 "PCH PLL state assertion failure (expected %s, current %s)\n",
918 state_string(state), state_string(cur_state));
919 }
920 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
921 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
922
923 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
924 enum pipe pipe, bool state)
925 {
926 int reg;
927 u32 val;
928 bool cur_state;
929
930 reg = FDI_TX_CTL(pipe);
931 val = I915_READ(reg);
932 cur_state = !!(val & FDI_TX_ENABLE);
933 WARN(cur_state != state,
934 "FDI TX state assertion failure (expected %s, current %s)\n",
935 state_string(state), state_string(cur_state));
936 }
937 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
938 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
939
940 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
941 enum pipe pipe, bool state)
942 {
943 int reg;
944 u32 val;
945 bool cur_state;
946
947 reg = FDI_RX_CTL(pipe);
948 val = I915_READ(reg);
949 cur_state = !!(val & FDI_RX_ENABLE);
950 WARN(cur_state != state,
951 "FDI RX state assertion failure (expected %s, current %s)\n",
952 state_string(state), state_string(cur_state));
953 }
954 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
955 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
956
957 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
958 enum pipe pipe)
959 {
960 int reg;
961 u32 val;
962
963 /* ILK FDI PLL is always enabled */
964 if (dev_priv->info->gen == 5)
965 return;
966
967 reg = FDI_TX_CTL(pipe);
968 val = I915_READ(reg);
969 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
970 }
971
972 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
973 enum pipe pipe)
974 {
975 int reg;
976 u32 val;
977
978 reg = FDI_RX_CTL(pipe);
979 val = I915_READ(reg);
980 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
981 }
982
983 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
984 enum pipe pipe)
985 {
986 int pp_reg, lvds_reg;
987 u32 val;
988 enum pipe panel_pipe = PIPE_A;
989 bool locked = true;
990
991 if (HAS_PCH_SPLIT(dev_priv->dev)) {
992 pp_reg = PCH_PP_CONTROL;
993 lvds_reg = PCH_LVDS;
994 } else {
995 pp_reg = PP_CONTROL;
996 lvds_reg = LVDS;
997 }
998
999 val = I915_READ(pp_reg);
1000 if (!(val & PANEL_POWER_ON) ||
1001 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1002 locked = false;
1003
1004 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1005 panel_pipe = PIPE_B;
1006
1007 WARN(panel_pipe == pipe && locked,
1008 "panel assertion failure, pipe %c regs locked\n",
1009 pipe_name(pipe));
1010 }
1011
1012 void assert_pipe(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 /* if we need the pipe A quirk it must be always on */
1020 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1021 state = true;
1022
1023 reg = PIPECONF(pipe);
1024 val = I915_READ(reg);
1025 cur_state = !!(val & PIPECONF_ENABLE);
1026 WARN(cur_state != state,
1027 "pipe %c assertion failure (expected %s, current %s)\n",
1028 pipe_name(pipe), state_string(state), state_string(cur_state));
1029 }
1030
1031 static void assert_plane(struct drm_i915_private *dev_priv,
1032 enum plane plane, bool state)
1033 {
1034 int reg;
1035 u32 val;
1036 bool cur_state;
1037
1038 reg = DSPCNTR(plane);
1039 val = I915_READ(reg);
1040 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1041 WARN(cur_state != state,
1042 "plane %c assertion failure (expected %s, current %s)\n",
1043 plane_name(plane), state_string(state), state_string(cur_state));
1044 }
1045
1046 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1047 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1048
1049 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1050 enum pipe pipe)
1051 {
1052 int reg, i;
1053 u32 val;
1054 int cur_pipe;
1055
1056 /* Planes are fixed to pipes on ILK+ */
1057 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058 reg = DSPCNTR(pipe);
1059 val = I915_READ(reg);
1060 WARN((val & DISPLAY_PLANE_ENABLE),
1061 "plane %c assertion failure, should be disabled but not\n",
1062 plane_name(pipe));
1063 return;
1064 }
1065
1066 /* Need to check both planes against the pipe */
1067 for (i = 0; i < 2; i++) {
1068 reg = DSPCNTR(i);
1069 val = I915_READ(reg);
1070 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1071 DISPPLANE_SEL_PIPE_SHIFT;
1072 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1073 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1074 plane_name(i), pipe_name(pipe));
1075 }
1076 }
1077
1078 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1079 {
1080 u32 val;
1081 bool enabled;
1082
1083 val = I915_READ(PCH_DREF_CONTROL);
1084 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1085 DREF_SUPERSPREAD_SOURCE_MASK));
1086 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1087 }
1088
1089 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1090 enum pipe pipe)
1091 {
1092 int reg;
1093 u32 val;
1094 bool enabled;
1095
1096 reg = TRANSCONF(pipe);
1097 val = I915_READ(reg);
1098 enabled = !!(val & TRANS_ENABLE);
1099 WARN(enabled,
1100 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1101 pipe_name(pipe));
1102 }
1103
1104 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1105 enum pipe pipe, u32 port_sel, u32 val)
1106 {
1107 if ((val & DP_PORT_EN) == 0)
1108 return false;
1109
1110 if (HAS_PCH_CPT(dev_priv->dev)) {
1111 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1112 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1113 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1114 return false;
1115 } else {
1116 if ((val & DP_PIPE_MASK) != (pipe << 30))
1117 return false;
1118 }
1119 return true;
1120 }
1121
1122 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, u32 val)
1124 {
1125 if ((val & PORT_ENABLE) == 0)
1126 return false;
1127
1128 if (HAS_PCH_CPT(dev_priv->dev)) {
1129 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1130 return false;
1131 } else {
1132 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1133 return false;
1134 }
1135 return true;
1136 }
1137
1138 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, u32 val)
1140 {
1141 if ((val & LVDS_PORT_EN) == 0)
1142 return false;
1143
1144 if (HAS_PCH_CPT(dev_priv->dev)) {
1145 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1146 return false;
1147 } else {
1148 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1149 return false;
1150 }
1151 return true;
1152 }
1153
1154 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe, u32 val)
1156 {
1157 if ((val & ADPA_DAC_ENABLE) == 0)
1158 return false;
1159 if (HAS_PCH_CPT(dev_priv->dev)) {
1160 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1161 return false;
1162 } else {
1163 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1164 return false;
1165 }
1166 return true;
1167 }
1168
1169 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, int reg, u32 port_sel)
1171 {
1172 u32 val = I915_READ(reg);
1173 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1174 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1175 reg, pipe_name(pipe));
1176 }
1177
1178 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, int reg)
1180 {
1181 u32 val = I915_READ(reg);
1182 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1183 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1184 reg, pipe_name(pipe));
1185 }
1186
1187 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1188 enum pipe pipe)
1189 {
1190 int reg;
1191 u32 val;
1192
1193 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1194 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1195 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1196
1197 reg = PCH_ADPA;
1198 val = I915_READ(reg);
1199 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1200 "PCH VGA enabled on transcoder %c, should be disabled\n",
1201 pipe_name(pipe));
1202
1203 reg = PCH_LVDS;
1204 val = I915_READ(reg);
1205 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1206 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1207 pipe_name(pipe));
1208
1209 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1210 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1211 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1212 }
1213
1214 /**
1215 * intel_enable_pll - enable a PLL
1216 * @dev_priv: i915 private structure
1217 * @pipe: pipe PLL to enable
1218 *
1219 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1220 * make sure the PLL reg is writable first though, since the panel write
1221 * protect mechanism may be enabled.
1222 *
1223 * Note! This is for pre-ILK only.
1224 */
1225 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1226 {
1227 int reg;
1228 u32 val;
1229
1230 /* No really, not for ILK+ */
1231 BUG_ON(dev_priv->info->gen >= 5);
1232
1233 /* PLL is protected by panel, make sure we can write it */
1234 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1235 assert_panel_unlocked(dev_priv, pipe);
1236
1237 reg = DPLL(pipe);
1238 val = I915_READ(reg);
1239 val |= DPLL_VCO_ENABLE;
1240
1241 /* We do this three times for luck */
1242 I915_WRITE(reg, val);
1243 POSTING_READ(reg);
1244 udelay(150); /* wait for warmup */
1245 I915_WRITE(reg, val);
1246 POSTING_READ(reg);
1247 udelay(150); /* wait for warmup */
1248 I915_WRITE(reg, val);
1249 POSTING_READ(reg);
1250 udelay(150); /* wait for warmup */
1251 }
1252
1253 /**
1254 * intel_disable_pll - disable a PLL
1255 * @dev_priv: i915 private structure
1256 * @pipe: pipe PLL to disable
1257 *
1258 * Disable the PLL for @pipe, making sure the pipe is off first.
1259 *
1260 * Note! This is for pre-ILK only.
1261 */
1262 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1263 {
1264 int reg;
1265 u32 val;
1266
1267 /* Don't disable pipe A or pipe A PLLs if needed */
1268 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1269 return;
1270
1271 /* Make sure the pipe isn't still relying on us */
1272 assert_pipe_disabled(dev_priv, pipe);
1273
1274 reg = DPLL(pipe);
1275 val = I915_READ(reg);
1276 val &= ~DPLL_VCO_ENABLE;
1277 I915_WRITE(reg, val);
1278 POSTING_READ(reg);
1279 }
1280
1281 /**
1282 * intel_enable_pch_pll - enable PCH PLL
1283 * @dev_priv: i915 private structure
1284 * @pipe: pipe PLL to enable
1285 *
1286 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1287 * drives the transcoder clock.
1288 */
1289 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1290 {
1291 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1292 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1293 int reg;
1294 u32 val;
1295
1296 /* PCH only available on ILK+ */
1297 BUG_ON(dev_priv->info->gen < 5);
1298 BUG_ON(pll == NULL);
1299 BUG_ON(pll->refcount == 0);
1300
1301 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1302 pll->pll_reg, pll->active, pll->on,
1303 intel_crtc->base.base.id);
1304
1305 /* PCH refclock must be enabled first */
1306 assert_pch_refclk_enabled(dev_priv);
1307
1308 if (pll->active++ && pll->on) {
1309 assert_pch_pll_enabled(dev_priv, intel_crtc);
1310 return;
1311 }
1312
1313 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1314
1315 reg = pll->pll_reg;
1316 val = I915_READ(reg);
1317 val |= DPLL_VCO_ENABLE;
1318 I915_WRITE(reg, val);
1319 POSTING_READ(reg);
1320 udelay(200);
1321
1322 pll->on = true;
1323 }
1324
1325 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1326 {
1327 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1328 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1329 int reg;
1330 u32 val;
1331
1332 /* PCH only available on ILK+ */
1333 BUG_ON(dev_priv->info->gen < 5);
1334 if (pll == NULL)
1335 return;
1336
1337 BUG_ON(pll->refcount == 0);
1338
1339 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1340 pll->pll_reg, pll->active, pll->on,
1341 intel_crtc->base.base.id);
1342
1343 BUG_ON(pll->active == 0);
1344 if (--pll->active) {
1345 assert_pch_pll_enabled(dev_priv, intel_crtc);
1346 return;
1347 }
1348
1349 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1350
1351 /* Make sure transcoder isn't still depending on us */
1352 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1353
1354 reg = pll->pll_reg;
1355 val = I915_READ(reg);
1356 val &= ~DPLL_VCO_ENABLE;
1357 I915_WRITE(reg, val);
1358 POSTING_READ(reg);
1359 udelay(200);
1360
1361 pll->on = false;
1362 }
1363
1364 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 int reg;
1368 u32 val, pipeconf_val;
1369 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1370
1371 /* PCH only available on ILK+ */
1372 BUG_ON(dev_priv->info->gen < 5);
1373
1374 /* Make sure PCH DPLL is enabled */
1375 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
1376
1377 /* FDI must be feeding us bits for PCH ports */
1378 assert_fdi_tx_enabled(dev_priv, pipe);
1379 assert_fdi_rx_enabled(dev_priv, pipe);
1380
1381 reg = TRANSCONF(pipe);
1382 val = I915_READ(reg);
1383 pipeconf_val = I915_READ(PIPECONF(pipe));
1384
1385 if (HAS_PCH_IBX(dev_priv->dev)) {
1386 /*
1387 * make the BPC in transcoder be consistent with
1388 * that in pipeconf reg.
1389 */
1390 val &= ~PIPE_BPC_MASK;
1391 val |= pipeconf_val & PIPE_BPC_MASK;
1392 }
1393
1394 val &= ~TRANS_INTERLACE_MASK;
1395 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1396 if (HAS_PCH_IBX(dev_priv->dev) &&
1397 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1398 val |= TRANS_LEGACY_INTERLACED_ILK;
1399 else
1400 val |= TRANS_INTERLACED;
1401 else
1402 val |= TRANS_PROGRESSIVE;
1403
1404 I915_WRITE(reg, val | TRANS_ENABLE);
1405 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1406 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1407 }
1408
1409 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1410 enum pipe pipe)
1411 {
1412 int reg;
1413 u32 val;
1414
1415 /* FDI relies on the transcoder */
1416 assert_fdi_tx_disabled(dev_priv, pipe);
1417 assert_fdi_rx_disabled(dev_priv, pipe);
1418
1419 /* Ports must be off as well */
1420 assert_pch_ports_disabled(dev_priv, pipe);
1421
1422 reg = TRANSCONF(pipe);
1423 val = I915_READ(reg);
1424 val &= ~TRANS_ENABLE;
1425 I915_WRITE(reg, val);
1426 /* wait for PCH transcoder off, transcoder state */
1427 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1428 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1429 }
1430
1431 /**
1432 * intel_enable_pipe - enable a pipe, asserting requirements
1433 * @dev_priv: i915 private structure
1434 * @pipe: pipe to enable
1435 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1436 *
1437 * Enable @pipe, making sure that various hardware specific requirements
1438 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1439 *
1440 * @pipe should be %PIPE_A or %PIPE_B.
1441 *
1442 * Will wait until the pipe is actually running (i.e. first vblank) before
1443 * returning.
1444 */
1445 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1446 bool pch_port)
1447 {
1448 int reg;
1449 u32 val;
1450
1451 /*
1452 * A pipe without a PLL won't actually be able to drive bits from
1453 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1454 * need the check.
1455 */
1456 if (!HAS_PCH_SPLIT(dev_priv->dev))
1457 assert_pll_enabled(dev_priv, pipe);
1458 else {
1459 if (pch_port) {
1460 /* if driving the PCH, we need FDI enabled */
1461 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1462 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1463 }
1464 /* FIXME: assert CPU port conditions for SNB+ */
1465 }
1466
1467 reg = PIPECONF(pipe);
1468 val = I915_READ(reg);
1469 if (val & PIPECONF_ENABLE)
1470 return;
1471
1472 I915_WRITE(reg, val | PIPECONF_ENABLE);
1473 intel_wait_for_vblank(dev_priv->dev, pipe);
1474 }
1475
1476 /**
1477 * intel_disable_pipe - disable a pipe, asserting requirements
1478 * @dev_priv: i915 private structure
1479 * @pipe: pipe to disable
1480 *
1481 * Disable @pipe, making sure that various hardware specific requirements
1482 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1483 *
1484 * @pipe should be %PIPE_A or %PIPE_B.
1485 *
1486 * Will wait until the pipe has shut down before returning.
1487 */
1488 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1489 enum pipe pipe)
1490 {
1491 int reg;
1492 u32 val;
1493
1494 /*
1495 * Make sure planes won't keep trying to pump pixels to us,
1496 * or we might hang the display.
1497 */
1498 assert_planes_disabled(dev_priv, pipe);
1499
1500 /* Don't disable pipe A or pipe A PLLs if needed */
1501 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1502 return;
1503
1504 reg = PIPECONF(pipe);
1505 val = I915_READ(reg);
1506 if ((val & PIPECONF_ENABLE) == 0)
1507 return;
1508
1509 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1510 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1511 }
1512
1513 /*
1514 * Plane regs are double buffered, going from enabled->disabled needs a
1515 * trigger in order to latch. The display address reg provides this.
1516 */
1517 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1518 enum plane plane)
1519 {
1520 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1521 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1522 }
1523
1524 /**
1525 * intel_enable_plane - enable a display plane on a given pipe
1526 * @dev_priv: i915 private structure
1527 * @plane: plane to enable
1528 * @pipe: pipe being fed
1529 *
1530 * Enable @plane on @pipe, making sure that @pipe is running first.
1531 */
1532 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1533 enum plane plane, enum pipe pipe)
1534 {
1535 int reg;
1536 u32 val;
1537
1538 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1539 assert_pipe_enabled(dev_priv, pipe);
1540
1541 reg = DSPCNTR(plane);
1542 val = I915_READ(reg);
1543 if (val & DISPLAY_PLANE_ENABLE)
1544 return;
1545
1546 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1547 intel_flush_display_plane(dev_priv, plane);
1548 intel_wait_for_vblank(dev_priv->dev, pipe);
1549 }
1550
1551 /**
1552 * intel_disable_plane - disable a display plane
1553 * @dev_priv: i915 private structure
1554 * @plane: plane to disable
1555 * @pipe: pipe consuming the data
1556 *
1557 * Disable @plane; should be an independent operation.
1558 */
1559 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1560 enum plane plane, enum pipe pipe)
1561 {
1562 int reg;
1563 u32 val;
1564
1565 reg = DSPCNTR(plane);
1566 val = I915_READ(reg);
1567 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1568 return;
1569
1570 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1571 intel_flush_display_plane(dev_priv, plane);
1572 intel_wait_for_vblank(dev_priv->dev, pipe);
1573 }
1574
1575 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1576 enum pipe pipe, int reg, u32 port_sel)
1577 {
1578 u32 val = I915_READ(reg);
1579 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1580 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1581 I915_WRITE(reg, val & ~DP_PORT_EN);
1582 }
1583 }
1584
1585 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1586 enum pipe pipe, int reg)
1587 {
1588 u32 val = I915_READ(reg);
1589 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1590 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1591 reg, pipe);
1592 I915_WRITE(reg, val & ~PORT_ENABLE);
1593 }
1594 }
1595
1596 /* Disable any ports connected to this transcoder */
1597 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1598 enum pipe pipe)
1599 {
1600 u32 reg, val;
1601
1602 val = I915_READ(PCH_PP_CONTROL);
1603 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1604
1605 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1606 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1607 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1608
1609 reg = PCH_ADPA;
1610 val = I915_READ(reg);
1611 if (adpa_pipe_enabled(dev_priv, val, pipe))
1612 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1613
1614 reg = PCH_LVDS;
1615 val = I915_READ(reg);
1616 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1617 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1618 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1619 POSTING_READ(reg);
1620 udelay(100);
1621 }
1622
1623 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1624 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1625 disable_pch_hdmi(dev_priv, pipe, HDMID);
1626 }
1627
1628 int
1629 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1630 struct drm_i915_gem_object *obj,
1631 struct intel_ring_buffer *pipelined)
1632 {
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 u32 alignment;
1635 int ret;
1636
1637 switch (obj->tiling_mode) {
1638 case I915_TILING_NONE:
1639 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1640 alignment = 128 * 1024;
1641 else if (INTEL_INFO(dev)->gen >= 4)
1642 alignment = 4 * 1024;
1643 else
1644 alignment = 64 * 1024;
1645 break;
1646 case I915_TILING_X:
1647 /* pin() will align the object as required by fence */
1648 alignment = 0;
1649 break;
1650 case I915_TILING_Y:
1651 /* FIXME: Is this true? */
1652 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1653 return -EINVAL;
1654 default:
1655 BUG();
1656 }
1657
1658 dev_priv->mm.interruptible = false;
1659 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1660 if (ret)
1661 goto err_interruptible;
1662
1663 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1664 * fence, whereas 965+ only requires a fence if using
1665 * framebuffer compression. For simplicity, we always install
1666 * a fence as the cost is not that onerous.
1667 */
1668 ret = i915_gem_object_get_fence(obj);
1669 if (ret)
1670 goto err_unpin;
1671
1672 i915_gem_object_pin_fence(obj);
1673
1674 dev_priv->mm.interruptible = true;
1675 return 0;
1676
1677 err_unpin:
1678 i915_gem_object_unpin(obj);
1679 err_interruptible:
1680 dev_priv->mm.interruptible = true;
1681 return ret;
1682 }
1683
1684 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1685 {
1686 i915_gem_object_unpin_fence(obj);
1687 i915_gem_object_unpin(obj);
1688 }
1689
1690 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1691 int x, int y)
1692 {
1693 struct drm_device *dev = crtc->dev;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1696 struct intel_framebuffer *intel_fb;
1697 struct drm_i915_gem_object *obj;
1698 int plane = intel_crtc->plane;
1699 unsigned long Start, Offset;
1700 u32 dspcntr;
1701 u32 reg;
1702
1703 switch (plane) {
1704 case 0:
1705 case 1:
1706 break;
1707 default:
1708 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1709 return -EINVAL;
1710 }
1711
1712 intel_fb = to_intel_framebuffer(fb);
1713 obj = intel_fb->obj;
1714
1715 reg = DSPCNTR(plane);
1716 dspcntr = I915_READ(reg);
1717 /* Mask out pixel format bits in case we change it */
1718 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1719 switch (fb->bits_per_pixel) {
1720 case 8:
1721 dspcntr |= DISPPLANE_8BPP;
1722 break;
1723 case 16:
1724 if (fb->depth == 15)
1725 dspcntr |= DISPPLANE_15_16BPP;
1726 else
1727 dspcntr |= DISPPLANE_16BPP;
1728 break;
1729 case 24:
1730 case 32:
1731 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1732 break;
1733 default:
1734 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1735 return -EINVAL;
1736 }
1737 if (INTEL_INFO(dev)->gen >= 4) {
1738 if (obj->tiling_mode != I915_TILING_NONE)
1739 dspcntr |= DISPPLANE_TILED;
1740 else
1741 dspcntr &= ~DISPPLANE_TILED;
1742 }
1743
1744 I915_WRITE(reg, dspcntr);
1745
1746 Start = obj->gtt_offset;
1747 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1748
1749 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1750 Start, Offset, x, y, fb->pitches[0]);
1751 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1752 if (INTEL_INFO(dev)->gen >= 4) {
1753 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1755 I915_WRITE(DSPADDR(plane), Offset);
1756 } else
1757 I915_WRITE(DSPADDR(plane), Start + Offset);
1758 POSTING_READ(reg);
1759
1760 return 0;
1761 }
1762
1763 static int ironlake_update_plane(struct drm_crtc *crtc,
1764 struct drm_framebuffer *fb, int x, int y)
1765 {
1766 struct drm_device *dev = crtc->dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1769 struct intel_framebuffer *intel_fb;
1770 struct drm_i915_gem_object *obj;
1771 int plane = intel_crtc->plane;
1772 unsigned long Start, Offset;
1773 u32 dspcntr;
1774 u32 reg;
1775
1776 switch (plane) {
1777 case 0:
1778 case 1:
1779 case 2:
1780 break;
1781 default:
1782 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1783 return -EINVAL;
1784 }
1785
1786 intel_fb = to_intel_framebuffer(fb);
1787 obj = intel_fb->obj;
1788
1789 reg = DSPCNTR(plane);
1790 dspcntr = I915_READ(reg);
1791 /* Mask out pixel format bits in case we change it */
1792 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1793 switch (fb->bits_per_pixel) {
1794 case 8:
1795 dspcntr |= DISPPLANE_8BPP;
1796 break;
1797 case 16:
1798 if (fb->depth != 16)
1799 return -EINVAL;
1800
1801 dspcntr |= DISPPLANE_16BPP;
1802 break;
1803 case 24:
1804 case 32:
1805 if (fb->depth == 24)
1806 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1807 else if (fb->depth == 30)
1808 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1809 else
1810 return -EINVAL;
1811 break;
1812 default:
1813 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1814 return -EINVAL;
1815 }
1816
1817 if (obj->tiling_mode != I915_TILING_NONE)
1818 dspcntr |= DISPPLANE_TILED;
1819 else
1820 dspcntr &= ~DISPPLANE_TILED;
1821
1822 /* must disable */
1823 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1824
1825 I915_WRITE(reg, dspcntr);
1826
1827 Start = obj->gtt_offset;
1828 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1829
1830 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1831 Start, Offset, x, y, fb->pitches[0]);
1832 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1833 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
1834 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1835 I915_WRITE(DSPADDR(plane), Offset);
1836 POSTING_READ(reg);
1837
1838 return 0;
1839 }
1840
1841 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1842 static int
1843 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1844 int x, int y, enum mode_set_atomic state)
1845 {
1846 struct drm_device *dev = crtc->dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848
1849 if (dev_priv->display.disable_fbc)
1850 dev_priv->display.disable_fbc(dev);
1851 intel_increase_pllclock(crtc);
1852
1853 return dev_priv->display.update_plane(crtc, fb, x, y);
1854 }
1855
1856 static int
1857 intel_finish_fb(struct drm_framebuffer *old_fb)
1858 {
1859 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1860 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1861 bool was_interruptible = dev_priv->mm.interruptible;
1862 int ret;
1863
1864 wait_event(dev_priv->pending_flip_queue,
1865 atomic_read(&dev_priv->mm.wedged) ||
1866 atomic_read(&obj->pending_flip) == 0);
1867
1868 /* Big Hammer, we also need to ensure that any pending
1869 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1870 * current scanout is retired before unpinning the old
1871 * framebuffer.
1872 *
1873 * This should only fail upon a hung GPU, in which case we
1874 * can safely continue.
1875 */
1876 dev_priv->mm.interruptible = false;
1877 ret = i915_gem_object_finish_gpu(obj);
1878 dev_priv->mm.interruptible = was_interruptible;
1879
1880 return ret;
1881 }
1882
1883 static int
1884 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1885 struct drm_framebuffer *old_fb)
1886 {
1887 struct drm_device *dev = crtc->dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct drm_i915_master_private *master_priv;
1890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1891 int ret;
1892
1893 /* no fb bound */
1894 if (!crtc->fb) {
1895 DRM_ERROR("No FB bound\n");
1896 return 0;
1897 }
1898
1899 switch (intel_crtc->plane) {
1900 case 0:
1901 case 1:
1902 break;
1903 case 2:
1904 if (IS_IVYBRIDGE(dev))
1905 break;
1906 /* fall through otherwise */
1907 default:
1908 DRM_ERROR("no plane for crtc\n");
1909 return -EINVAL;
1910 }
1911
1912 mutex_lock(&dev->struct_mutex);
1913 ret = intel_pin_and_fence_fb_obj(dev,
1914 to_intel_framebuffer(crtc->fb)->obj,
1915 NULL);
1916 if (ret != 0) {
1917 mutex_unlock(&dev->struct_mutex);
1918 DRM_ERROR("pin & fence failed\n");
1919 return ret;
1920 }
1921
1922 if (old_fb)
1923 intel_finish_fb(old_fb);
1924
1925 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
1926 if (ret) {
1927 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1928 mutex_unlock(&dev->struct_mutex);
1929 DRM_ERROR("failed to update base address\n");
1930 return ret;
1931 }
1932
1933 if (old_fb) {
1934 intel_wait_for_vblank(dev, intel_crtc->pipe);
1935 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1936 }
1937
1938 intel_update_fbc(dev);
1939 mutex_unlock(&dev->struct_mutex);
1940
1941 if (!dev->primary->master)
1942 return 0;
1943
1944 master_priv = dev->primary->master->driver_priv;
1945 if (!master_priv->sarea_priv)
1946 return 0;
1947
1948 if (intel_crtc->pipe) {
1949 master_priv->sarea_priv->pipeB_x = x;
1950 master_priv->sarea_priv->pipeB_y = y;
1951 } else {
1952 master_priv->sarea_priv->pipeA_x = x;
1953 master_priv->sarea_priv->pipeA_y = y;
1954 }
1955
1956 return 0;
1957 }
1958
1959 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1960 {
1961 struct drm_device *dev = crtc->dev;
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 u32 dpa_ctl;
1964
1965 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1966 dpa_ctl = I915_READ(DP_A);
1967 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1968
1969 if (clock < 200000) {
1970 u32 temp;
1971 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1972 /* workaround for 160Mhz:
1973 1) program 0x4600c bits 15:0 = 0x8124
1974 2) program 0x46010 bit 0 = 1
1975 3) program 0x46034 bit 24 = 1
1976 4) program 0x64000 bit 14 = 1
1977 */
1978 temp = I915_READ(0x4600c);
1979 temp &= 0xffff0000;
1980 I915_WRITE(0x4600c, temp | 0x8124);
1981
1982 temp = I915_READ(0x46010);
1983 I915_WRITE(0x46010, temp | 1);
1984
1985 temp = I915_READ(0x46034);
1986 I915_WRITE(0x46034, temp | (1 << 24));
1987 } else {
1988 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1989 }
1990 I915_WRITE(DP_A, dpa_ctl);
1991
1992 POSTING_READ(DP_A);
1993 udelay(500);
1994 }
1995
1996 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1997 {
1998 struct drm_device *dev = crtc->dev;
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2001 int pipe = intel_crtc->pipe;
2002 u32 reg, temp;
2003
2004 /* enable normal train */
2005 reg = FDI_TX_CTL(pipe);
2006 temp = I915_READ(reg);
2007 if (IS_IVYBRIDGE(dev)) {
2008 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2009 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2010 } else {
2011 temp &= ~FDI_LINK_TRAIN_NONE;
2012 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2013 }
2014 I915_WRITE(reg, temp);
2015
2016 reg = FDI_RX_CTL(pipe);
2017 temp = I915_READ(reg);
2018 if (HAS_PCH_CPT(dev)) {
2019 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2020 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2021 } else {
2022 temp &= ~FDI_LINK_TRAIN_NONE;
2023 temp |= FDI_LINK_TRAIN_NONE;
2024 }
2025 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2026
2027 /* wait one idle pattern time */
2028 POSTING_READ(reg);
2029 udelay(1000);
2030
2031 /* IVB wants error correction enabled */
2032 if (IS_IVYBRIDGE(dev))
2033 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2034 FDI_FE_ERRC_ENABLE);
2035 }
2036
2037 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2038 {
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 u32 flags = I915_READ(SOUTH_CHICKEN1);
2041
2042 flags |= FDI_PHASE_SYNC_OVR(pipe);
2043 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2044 flags |= FDI_PHASE_SYNC_EN(pipe);
2045 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2046 POSTING_READ(SOUTH_CHICKEN1);
2047 }
2048
2049 /* The FDI link training functions for ILK/Ibexpeak. */
2050 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2051 {
2052 struct drm_device *dev = crtc->dev;
2053 struct drm_i915_private *dev_priv = dev->dev_private;
2054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2055 int pipe = intel_crtc->pipe;
2056 int plane = intel_crtc->plane;
2057 u32 reg, temp, tries;
2058
2059 /* FDI needs bits from pipe & plane first */
2060 assert_pipe_enabled(dev_priv, pipe);
2061 assert_plane_enabled(dev_priv, plane);
2062
2063 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2064 for train result */
2065 reg = FDI_RX_IMR(pipe);
2066 temp = I915_READ(reg);
2067 temp &= ~FDI_RX_SYMBOL_LOCK;
2068 temp &= ~FDI_RX_BIT_LOCK;
2069 I915_WRITE(reg, temp);
2070 I915_READ(reg);
2071 udelay(150);
2072
2073 /* enable CPU FDI TX and PCH FDI RX */
2074 reg = FDI_TX_CTL(pipe);
2075 temp = I915_READ(reg);
2076 temp &= ~(7 << 19);
2077 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2078 temp &= ~FDI_LINK_TRAIN_NONE;
2079 temp |= FDI_LINK_TRAIN_PATTERN_1;
2080 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2081
2082 reg = FDI_RX_CTL(pipe);
2083 temp = I915_READ(reg);
2084 temp &= ~FDI_LINK_TRAIN_NONE;
2085 temp |= FDI_LINK_TRAIN_PATTERN_1;
2086 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2087
2088 POSTING_READ(reg);
2089 udelay(150);
2090
2091 /* Ironlake workaround, enable clock pointer after FDI enable*/
2092 if (HAS_PCH_IBX(dev)) {
2093 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2094 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2095 FDI_RX_PHASE_SYNC_POINTER_EN);
2096 }
2097
2098 reg = FDI_RX_IIR(pipe);
2099 for (tries = 0; tries < 5; tries++) {
2100 temp = I915_READ(reg);
2101 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2102
2103 if ((temp & FDI_RX_BIT_LOCK)) {
2104 DRM_DEBUG_KMS("FDI train 1 done.\n");
2105 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2106 break;
2107 }
2108 }
2109 if (tries == 5)
2110 DRM_ERROR("FDI train 1 fail!\n");
2111
2112 /* Train 2 */
2113 reg = FDI_TX_CTL(pipe);
2114 temp = I915_READ(reg);
2115 temp &= ~FDI_LINK_TRAIN_NONE;
2116 temp |= FDI_LINK_TRAIN_PATTERN_2;
2117 I915_WRITE(reg, temp);
2118
2119 reg = FDI_RX_CTL(pipe);
2120 temp = I915_READ(reg);
2121 temp &= ~FDI_LINK_TRAIN_NONE;
2122 temp |= FDI_LINK_TRAIN_PATTERN_2;
2123 I915_WRITE(reg, temp);
2124
2125 POSTING_READ(reg);
2126 udelay(150);
2127
2128 reg = FDI_RX_IIR(pipe);
2129 for (tries = 0; tries < 5; tries++) {
2130 temp = I915_READ(reg);
2131 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2132
2133 if (temp & FDI_RX_SYMBOL_LOCK) {
2134 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2135 DRM_DEBUG_KMS("FDI train 2 done.\n");
2136 break;
2137 }
2138 }
2139 if (tries == 5)
2140 DRM_ERROR("FDI train 2 fail!\n");
2141
2142 DRM_DEBUG_KMS("FDI train done\n");
2143
2144 }
2145
2146 static const int snb_b_fdi_train_param[] = {
2147 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2148 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2149 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2150 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2151 };
2152
2153 /* The FDI link training functions for SNB/Cougarpoint. */
2154 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2155 {
2156 struct drm_device *dev = crtc->dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2159 int pipe = intel_crtc->pipe;
2160 u32 reg, temp, i, retry;
2161
2162 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2163 for train result */
2164 reg = FDI_RX_IMR(pipe);
2165 temp = I915_READ(reg);
2166 temp &= ~FDI_RX_SYMBOL_LOCK;
2167 temp &= ~FDI_RX_BIT_LOCK;
2168 I915_WRITE(reg, temp);
2169
2170 POSTING_READ(reg);
2171 udelay(150);
2172
2173 /* enable CPU FDI TX and PCH FDI RX */
2174 reg = FDI_TX_CTL(pipe);
2175 temp = I915_READ(reg);
2176 temp &= ~(7 << 19);
2177 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2178 temp &= ~FDI_LINK_TRAIN_NONE;
2179 temp |= FDI_LINK_TRAIN_PATTERN_1;
2180 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2181 /* SNB-B */
2182 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2183 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2184
2185 reg = FDI_RX_CTL(pipe);
2186 temp = I915_READ(reg);
2187 if (HAS_PCH_CPT(dev)) {
2188 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2189 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2190 } else {
2191 temp &= ~FDI_LINK_TRAIN_NONE;
2192 temp |= FDI_LINK_TRAIN_PATTERN_1;
2193 }
2194 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2195
2196 POSTING_READ(reg);
2197 udelay(150);
2198
2199 if (HAS_PCH_CPT(dev))
2200 cpt_phase_pointer_enable(dev, pipe);
2201
2202 for (i = 0; i < 4; i++) {
2203 reg = FDI_TX_CTL(pipe);
2204 temp = I915_READ(reg);
2205 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2206 temp |= snb_b_fdi_train_param[i];
2207 I915_WRITE(reg, temp);
2208
2209 POSTING_READ(reg);
2210 udelay(500);
2211
2212 for (retry = 0; retry < 5; retry++) {
2213 reg = FDI_RX_IIR(pipe);
2214 temp = I915_READ(reg);
2215 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2216 if (temp & FDI_RX_BIT_LOCK) {
2217 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2218 DRM_DEBUG_KMS("FDI train 1 done.\n");
2219 break;
2220 }
2221 udelay(50);
2222 }
2223 if (retry < 5)
2224 break;
2225 }
2226 if (i == 4)
2227 DRM_ERROR("FDI train 1 fail!\n");
2228
2229 /* Train 2 */
2230 reg = FDI_TX_CTL(pipe);
2231 temp = I915_READ(reg);
2232 temp &= ~FDI_LINK_TRAIN_NONE;
2233 temp |= FDI_LINK_TRAIN_PATTERN_2;
2234 if (IS_GEN6(dev)) {
2235 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2236 /* SNB-B */
2237 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2238 }
2239 I915_WRITE(reg, temp);
2240
2241 reg = FDI_RX_CTL(pipe);
2242 temp = I915_READ(reg);
2243 if (HAS_PCH_CPT(dev)) {
2244 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2245 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2246 } else {
2247 temp &= ~FDI_LINK_TRAIN_NONE;
2248 temp |= FDI_LINK_TRAIN_PATTERN_2;
2249 }
2250 I915_WRITE(reg, temp);
2251
2252 POSTING_READ(reg);
2253 udelay(150);
2254
2255 for (i = 0; i < 4; i++) {
2256 reg = FDI_TX_CTL(pipe);
2257 temp = I915_READ(reg);
2258 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2259 temp |= snb_b_fdi_train_param[i];
2260 I915_WRITE(reg, temp);
2261
2262 POSTING_READ(reg);
2263 udelay(500);
2264
2265 for (retry = 0; retry < 5; retry++) {
2266 reg = FDI_RX_IIR(pipe);
2267 temp = I915_READ(reg);
2268 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2269 if (temp & FDI_RX_SYMBOL_LOCK) {
2270 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2271 DRM_DEBUG_KMS("FDI train 2 done.\n");
2272 break;
2273 }
2274 udelay(50);
2275 }
2276 if (retry < 5)
2277 break;
2278 }
2279 if (i == 4)
2280 DRM_ERROR("FDI train 2 fail!\n");
2281
2282 DRM_DEBUG_KMS("FDI train done.\n");
2283 }
2284
2285 /* Manual link training for Ivy Bridge A0 parts */
2286 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2287 {
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
2292 u32 reg, temp, i;
2293
2294 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2295 for train result */
2296 reg = FDI_RX_IMR(pipe);
2297 temp = I915_READ(reg);
2298 temp &= ~FDI_RX_SYMBOL_LOCK;
2299 temp &= ~FDI_RX_BIT_LOCK;
2300 I915_WRITE(reg, temp);
2301
2302 POSTING_READ(reg);
2303 udelay(150);
2304
2305 /* enable CPU FDI TX and PCH FDI RX */
2306 reg = FDI_TX_CTL(pipe);
2307 temp = I915_READ(reg);
2308 temp &= ~(7 << 19);
2309 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2310 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2311 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2312 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2313 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2314 temp |= FDI_COMPOSITE_SYNC;
2315 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2316
2317 reg = FDI_RX_CTL(pipe);
2318 temp = I915_READ(reg);
2319 temp &= ~FDI_LINK_TRAIN_AUTO;
2320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2322 temp |= FDI_COMPOSITE_SYNC;
2323 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2324
2325 POSTING_READ(reg);
2326 udelay(150);
2327
2328 if (HAS_PCH_CPT(dev))
2329 cpt_phase_pointer_enable(dev, pipe);
2330
2331 for (i = 0; i < 4; i++) {
2332 reg = FDI_TX_CTL(pipe);
2333 temp = I915_READ(reg);
2334 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2335 temp |= snb_b_fdi_train_param[i];
2336 I915_WRITE(reg, temp);
2337
2338 POSTING_READ(reg);
2339 udelay(500);
2340
2341 reg = FDI_RX_IIR(pipe);
2342 temp = I915_READ(reg);
2343 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2344
2345 if (temp & FDI_RX_BIT_LOCK ||
2346 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2347 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2348 DRM_DEBUG_KMS("FDI train 1 done.\n");
2349 break;
2350 }
2351 }
2352 if (i == 4)
2353 DRM_ERROR("FDI train 1 fail!\n");
2354
2355 /* Train 2 */
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2359 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2360 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2361 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2362 I915_WRITE(reg, temp);
2363
2364 reg = FDI_RX_CTL(pipe);
2365 temp = I915_READ(reg);
2366 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2367 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2368 I915_WRITE(reg, temp);
2369
2370 POSTING_READ(reg);
2371 udelay(150);
2372
2373 for (i = 0; i < 4; i++) {
2374 reg = FDI_TX_CTL(pipe);
2375 temp = I915_READ(reg);
2376 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2377 temp |= snb_b_fdi_train_param[i];
2378 I915_WRITE(reg, temp);
2379
2380 POSTING_READ(reg);
2381 udelay(500);
2382
2383 reg = FDI_RX_IIR(pipe);
2384 temp = I915_READ(reg);
2385 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2386
2387 if (temp & FDI_RX_SYMBOL_LOCK) {
2388 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2389 DRM_DEBUG_KMS("FDI train 2 done.\n");
2390 break;
2391 }
2392 }
2393 if (i == 4)
2394 DRM_ERROR("FDI train 2 fail!\n");
2395
2396 DRM_DEBUG_KMS("FDI train done.\n");
2397 }
2398
2399 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2400 {
2401 struct drm_device *dev = crtc->dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2404 int pipe = intel_crtc->pipe;
2405 u32 reg, temp;
2406
2407 /* Write the TU size bits so error detection works */
2408 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2409 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2410
2411 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2412 reg = FDI_RX_CTL(pipe);
2413 temp = I915_READ(reg);
2414 temp &= ~((0x7 << 19) | (0x7 << 16));
2415 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2416 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2417 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2418
2419 POSTING_READ(reg);
2420 udelay(200);
2421
2422 /* Switch from Rawclk to PCDclk */
2423 temp = I915_READ(reg);
2424 I915_WRITE(reg, temp | FDI_PCDCLK);
2425
2426 POSTING_READ(reg);
2427 udelay(200);
2428
2429 /* Enable CPU FDI TX PLL, always on for Ironlake */
2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2433 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2434
2435 POSTING_READ(reg);
2436 udelay(100);
2437 }
2438 }
2439
2440 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2441 {
2442 struct drm_i915_private *dev_priv = dev->dev_private;
2443 u32 flags = I915_READ(SOUTH_CHICKEN1);
2444
2445 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2446 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2447 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2448 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2449 POSTING_READ(SOUTH_CHICKEN1);
2450 }
2451 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2452 {
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
2457 u32 reg, temp;
2458
2459 /* disable CPU FDI tx and PCH FDI rx */
2460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
2462 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2463 POSTING_READ(reg);
2464
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~(0x7 << 16);
2468 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2469 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2470
2471 POSTING_READ(reg);
2472 udelay(100);
2473
2474 /* Ironlake workaround, disable clock pointer after downing FDI */
2475 if (HAS_PCH_IBX(dev)) {
2476 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2477 I915_WRITE(FDI_RX_CHICKEN(pipe),
2478 I915_READ(FDI_RX_CHICKEN(pipe) &
2479 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2480 } else if (HAS_PCH_CPT(dev)) {
2481 cpt_phase_pointer_disable(dev, pipe);
2482 }
2483
2484 /* still set train pattern 1 */
2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_1;
2489 I915_WRITE(reg, temp);
2490
2491 reg = FDI_RX_CTL(pipe);
2492 temp = I915_READ(reg);
2493 if (HAS_PCH_CPT(dev)) {
2494 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2496 } else {
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 }
2500 /* BPC in FDI rx is consistent with that in PIPECONF */
2501 temp &= ~(0x07 << 16);
2502 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2503 I915_WRITE(reg, temp);
2504
2505 POSTING_READ(reg);
2506 udelay(100);
2507 }
2508
2509 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2510 {
2511 struct drm_device *dev = crtc->dev;
2512
2513 if (crtc->fb == NULL)
2514 return;
2515
2516 mutex_lock(&dev->struct_mutex);
2517 intel_finish_fb(crtc->fb);
2518 mutex_unlock(&dev->struct_mutex);
2519 }
2520
2521 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2522 {
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_mode_config *mode_config = &dev->mode_config;
2525 struct intel_encoder *encoder;
2526
2527 /*
2528 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2529 * must be driven by its own crtc; no sharing is possible.
2530 */
2531 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2532 if (encoder->base.crtc != crtc)
2533 continue;
2534
2535 switch (encoder->type) {
2536 case INTEL_OUTPUT_EDP:
2537 if (!intel_encoder_is_pch_edp(&encoder->base))
2538 return false;
2539 continue;
2540 }
2541 }
2542
2543 return true;
2544 }
2545
2546 /*
2547 * Enable PCH resources required for PCH ports:
2548 * - PCH PLLs
2549 * - FDI training & RX/TX
2550 * - update transcoder timings
2551 * - DP transcoding bits
2552 * - transcoder
2553 */
2554 static void ironlake_pch_enable(struct drm_crtc *crtc)
2555 {
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_i915_private *dev_priv = dev->dev_private;
2558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2559 int pipe = intel_crtc->pipe;
2560 u32 reg, temp;
2561
2562 /* For PCH output, training FDI link */
2563 dev_priv->display.fdi_link_train(crtc);
2564
2565 intel_enable_pch_pll(intel_crtc);
2566
2567 if (HAS_PCH_CPT(dev)) {
2568 u32 sel;
2569
2570 temp = I915_READ(PCH_DPLL_SEL);
2571 switch (pipe) {
2572 default:
2573 case 0:
2574 temp |= TRANSA_DPLL_ENABLE;
2575 sel = TRANSA_DPLLB_SEL;
2576 break;
2577 case 1:
2578 temp |= TRANSB_DPLL_ENABLE;
2579 sel = TRANSB_DPLLB_SEL;
2580 break;
2581 case 2:
2582 temp |= TRANSC_DPLL_ENABLE;
2583 sel = TRANSC_DPLLB_SEL;
2584 break;
2585 }
2586 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2587 temp |= sel;
2588 else
2589 temp &= ~sel;
2590 I915_WRITE(PCH_DPLL_SEL, temp);
2591 }
2592
2593 /* set transcoder timing, panel must allow it */
2594 assert_panel_unlocked(dev_priv, pipe);
2595 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2596 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2597 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2598
2599 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2600 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2601 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2602 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2603
2604 intel_fdi_normal_train(crtc);
2605
2606 /* For PCH DP, enable TRANS_DP_CTL */
2607 if (HAS_PCH_CPT(dev) &&
2608 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2609 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2610 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2611 reg = TRANS_DP_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2614 TRANS_DP_SYNC_MASK |
2615 TRANS_DP_BPC_MASK);
2616 temp |= (TRANS_DP_OUTPUT_ENABLE |
2617 TRANS_DP_ENH_FRAMING);
2618 temp |= bpc << 9; /* same format but at 11:9 */
2619
2620 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2621 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2622 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2623 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2624
2625 switch (intel_trans_dp_port_sel(crtc)) {
2626 case PCH_DP_B:
2627 temp |= TRANS_DP_PORT_SEL_B;
2628 break;
2629 case PCH_DP_C:
2630 temp |= TRANS_DP_PORT_SEL_C;
2631 break;
2632 case PCH_DP_D:
2633 temp |= TRANS_DP_PORT_SEL_D;
2634 break;
2635 default:
2636 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2637 temp |= TRANS_DP_PORT_SEL_B;
2638 break;
2639 }
2640
2641 I915_WRITE(reg, temp);
2642 }
2643
2644 intel_enable_transcoder(dev_priv, pipe);
2645 }
2646
2647 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2648 {
2649 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2650
2651 if (pll == NULL)
2652 return;
2653
2654 if (pll->refcount == 0) {
2655 WARN(1, "bad PCH PLL refcount\n");
2656 return;
2657 }
2658
2659 --pll->refcount;
2660 intel_crtc->pch_pll = NULL;
2661 }
2662
2663 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2664 {
2665 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2666 struct intel_pch_pll *pll;
2667 int i;
2668
2669 pll = intel_crtc->pch_pll;
2670 if (pll) {
2671 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2672 intel_crtc->base.base.id, pll->pll_reg);
2673 goto prepare;
2674 }
2675
2676 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2677 pll = &dev_priv->pch_plls[i];
2678
2679 /* Only want to check enabled timings first */
2680 if (pll->refcount == 0)
2681 continue;
2682
2683 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2684 fp == I915_READ(pll->fp0_reg)) {
2685 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2686 intel_crtc->base.base.id,
2687 pll->pll_reg, pll->refcount, pll->active);
2688
2689 goto found;
2690 }
2691 }
2692
2693 /* Ok no matching timings, maybe there's a free one? */
2694 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2695 pll = &dev_priv->pch_plls[i];
2696 if (pll->refcount == 0) {
2697 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2698 intel_crtc->base.base.id, pll->pll_reg);
2699 goto found;
2700 }
2701 }
2702
2703 return NULL;
2704
2705 found:
2706 intel_crtc->pch_pll = pll;
2707 pll->refcount++;
2708 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2709 prepare: /* separate function? */
2710 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
2711
2712 /* Wait for the clocks to stabilize before rewriting the regs */
2713 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2714 POSTING_READ(pll->pll_reg);
2715 udelay(150);
2716
2717 I915_WRITE(pll->fp0_reg, fp);
2718 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
2719 pll->on = false;
2720 return pll;
2721 }
2722
2723 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2724 {
2725 struct drm_i915_private *dev_priv = dev->dev_private;
2726 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2727 u32 temp;
2728
2729 temp = I915_READ(dslreg);
2730 udelay(500);
2731 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2732 /* Without this, mode sets may fail silently on FDI */
2733 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2734 udelay(250);
2735 I915_WRITE(tc2reg, 0);
2736 if (wait_for(I915_READ(dslreg) != temp, 5))
2737 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2738 }
2739 }
2740
2741 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2742 {
2743 struct drm_device *dev = crtc->dev;
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2746 int pipe = intel_crtc->pipe;
2747 int plane = intel_crtc->plane;
2748 u32 temp;
2749 bool is_pch_port;
2750
2751 if (intel_crtc->active)
2752 return;
2753
2754 intel_crtc->active = true;
2755 intel_update_watermarks(dev);
2756
2757 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2758 temp = I915_READ(PCH_LVDS);
2759 if ((temp & LVDS_PORT_EN) == 0)
2760 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2761 }
2762
2763 is_pch_port = intel_crtc_driving_pch(crtc);
2764
2765 if (is_pch_port)
2766 ironlake_fdi_pll_enable(crtc);
2767 else
2768 ironlake_fdi_disable(crtc);
2769
2770 /* Enable panel fitting for LVDS */
2771 if (dev_priv->pch_pf_size &&
2772 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2773 /* Force use of hard-coded filter coefficients
2774 * as some pre-programmed values are broken,
2775 * e.g. x201.
2776 */
2777 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2778 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2779 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2780 }
2781
2782 /*
2783 * On ILK+ LUT must be loaded before the pipe is running but with
2784 * clocks enabled
2785 */
2786 intel_crtc_load_lut(crtc);
2787
2788 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2789 intel_enable_plane(dev_priv, plane, pipe);
2790
2791 if (is_pch_port)
2792 ironlake_pch_enable(crtc);
2793
2794 mutex_lock(&dev->struct_mutex);
2795 intel_update_fbc(dev);
2796 mutex_unlock(&dev->struct_mutex);
2797
2798 intel_crtc_update_cursor(crtc, true);
2799 }
2800
2801 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2802 {
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806 int pipe = intel_crtc->pipe;
2807 int plane = intel_crtc->plane;
2808 u32 reg, temp;
2809
2810 if (!intel_crtc->active)
2811 return;
2812
2813 intel_crtc_wait_for_pending_flips(crtc);
2814 drm_vblank_off(dev, pipe);
2815 intel_crtc_update_cursor(crtc, false);
2816
2817 intel_disable_plane(dev_priv, plane, pipe);
2818
2819 if (dev_priv->cfb_plane == plane)
2820 intel_disable_fbc(dev);
2821
2822 intel_disable_pipe(dev_priv, pipe);
2823
2824 /* Disable PF */
2825 I915_WRITE(PF_CTL(pipe), 0);
2826 I915_WRITE(PF_WIN_SZ(pipe), 0);
2827
2828 ironlake_fdi_disable(crtc);
2829
2830 /* This is a horrible layering violation; we should be doing this in
2831 * the connector/encoder ->prepare instead, but we don't always have
2832 * enough information there about the config to know whether it will
2833 * actually be necessary or just cause undesired flicker.
2834 */
2835 intel_disable_pch_ports(dev_priv, pipe);
2836
2837 intel_disable_transcoder(dev_priv, pipe);
2838
2839 if (HAS_PCH_CPT(dev)) {
2840 /* disable TRANS_DP_CTL */
2841 reg = TRANS_DP_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2844 temp |= TRANS_DP_PORT_SEL_NONE;
2845 I915_WRITE(reg, temp);
2846
2847 /* disable DPLL_SEL */
2848 temp = I915_READ(PCH_DPLL_SEL);
2849 switch (pipe) {
2850 case 0:
2851 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2852 break;
2853 case 1:
2854 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2855 break;
2856 case 2:
2857 /* C shares PLL A or B */
2858 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2859 break;
2860 default:
2861 BUG(); /* wtf */
2862 }
2863 I915_WRITE(PCH_DPLL_SEL, temp);
2864 }
2865
2866 /* disable PCH DPLL */
2867 intel_disable_pch_pll(intel_crtc);
2868
2869 /* Switch from PCDclk to Rawclk */
2870 reg = FDI_RX_CTL(pipe);
2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2873
2874 /* Disable CPU FDI TX PLL */
2875 reg = FDI_TX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2878
2879 POSTING_READ(reg);
2880 udelay(100);
2881
2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2885
2886 /* Wait for the clocks to turn off. */
2887 POSTING_READ(reg);
2888 udelay(100);
2889
2890 intel_crtc->active = false;
2891 intel_update_watermarks(dev);
2892
2893 mutex_lock(&dev->struct_mutex);
2894 intel_update_fbc(dev);
2895 mutex_unlock(&dev->struct_mutex);
2896 }
2897
2898 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2899 {
2900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2901 int pipe = intel_crtc->pipe;
2902 int plane = intel_crtc->plane;
2903
2904 /* XXX: When our outputs are all unaware of DPMS modes other than off
2905 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2906 */
2907 switch (mode) {
2908 case DRM_MODE_DPMS_ON:
2909 case DRM_MODE_DPMS_STANDBY:
2910 case DRM_MODE_DPMS_SUSPEND:
2911 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2912 ironlake_crtc_enable(crtc);
2913 break;
2914
2915 case DRM_MODE_DPMS_OFF:
2916 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2917 ironlake_crtc_disable(crtc);
2918 break;
2919 }
2920 }
2921
2922 static void ironlake_crtc_off(struct drm_crtc *crtc)
2923 {
2924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2925 intel_put_pch_pll(intel_crtc);
2926 }
2927
2928 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2929 {
2930 if (!enable && intel_crtc->overlay) {
2931 struct drm_device *dev = intel_crtc->base.dev;
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933
2934 mutex_lock(&dev->struct_mutex);
2935 dev_priv->mm.interruptible = false;
2936 (void) intel_overlay_switch_off(intel_crtc->overlay);
2937 dev_priv->mm.interruptible = true;
2938 mutex_unlock(&dev->struct_mutex);
2939 }
2940
2941 /* Let userspace switch the overlay on again. In most cases userspace
2942 * has to recompute where to put it anyway.
2943 */
2944 }
2945
2946 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2947 {
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
2952 int plane = intel_crtc->plane;
2953
2954 if (intel_crtc->active)
2955 return;
2956
2957 intel_crtc->active = true;
2958 intel_update_watermarks(dev);
2959
2960 intel_enable_pll(dev_priv, pipe);
2961 intel_enable_pipe(dev_priv, pipe, false);
2962 intel_enable_plane(dev_priv, plane, pipe);
2963
2964 intel_crtc_load_lut(crtc);
2965 intel_update_fbc(dev);
2966
2967 /* Give the overlay scaler a chance to enable if it's on this pipe */
2968 intel_crtc_dpms_overlay(intel_crtc, true);
2969 intel_crtc_update_cursor(crtc, true);
2970 }
2971
2972 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2973 {
2974 struct drm_device *dev = crtc->dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2977 int pipe = intel_crtc->pipe;
2978 int plane = intel_crtc->plane;
2979
2980 if (!intel_crtc->active)
2981 return;
2982
2983 /* Give the overlay scaler a chance to disable if it's on this pipe */
2984 intel_crtc_wait_for_pending_flips(crtc);
2985 drm_vblank_off(dev, pipe);
2986 intel_crtc_dpms_overlay(intel_crtc, false);
2987 intel_crtc_update_cursor(crtc, false);
2988
2989 if (dev_priv->cfb_plane == plane)
2990 intel_disable_fbc(dev);
2991
2992 intel_disable_plane(dev_priv, plane, pipe);
2993 intel_disable_pipe(dev_priv, pipe);
2994 intel_disable_pll(dev_priv, pipe);
2995
2996 intel_crtc->active = false;
2997 intel_update_fbc(dev);
2998 intel_update_watermarks(dev);
2999 }
3000
3001 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3002 {
3003 /* XXX: When our outputs are all unaware of DPMS modes other than off
3004 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3005 */
3006 switch (mode) {
3007 case DRM_MODE_DPMS_ON:
3008 case DRM_MODE_DPMS_STANDBY:
3009 case DRM_MODE_DPMS_SUSPEND:
3010 i9xx_crtc_enable(crtc);
3011 break;
3012 case DRM_MODE_DPMS_OFF:
3013 i9xx_crtc_disable(crtc);
3014 break;
3015 }
3016 }
3017
3018 static void i9xx_crtc_off(struct drm_crtc *crtc)
3019 {
3020 }
3021
3022 /**
3023 * Sets the power management mode of the pipe and plane.
3024 */
3025 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3026 {
3027 struct drm_device *dev = crtc->dev;
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct drm_i915_master_private *master_priv;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
3032 bool enabled;
3033
3034 if (intel_crtc->dpms_mode == mode)
3035 return;
3036
3037 intel_crtc->dpms_mode = mode;
3038
3039 dev_priv->display.dpms(crtc, mode);
3040
3041 if (!dev->primary->master)
3042 return;
3043
3044 master_priv = dev->primary->master->driver_priv;
3045 if (!master_priv->sarea_priv)
3046 return;
3047
3048 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3049
3050 switch (pipe) {
3051 case 0:
3052 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3053 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3054 break;
3055 case 1:
3056 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3057 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3058 break;
3059 default:
3060 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3061 break;
3062 }
3063 }
3064
3065 static void intel_crtc_disable(struct drm_crtc *crtc)
3066 {
3067 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070
3071 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3072 dev_priv->display.off(crtc);
3073
3074 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3075 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3076
3077 if (crtc->fb) {
3078 mutex_lock(&dev->struct_mutex);
3079 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3080 mutex_unlock(&dev->struct_mutex);
3081 }
3082 }
3083
3084 /* Prepare for a mode set.
3085 *
3086 * Note we could be a lot smarter here. We need to figure out which outputs
3087 * will be enabled, which disabled (in short, how the config will changes)
3088 * and perform the minimum necessary steps to accomplish that, e.g. updating
3089 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3090 * panel fitting is in the proper state, etc.
3091 */
3092 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3093 {
3094 i9xx_crtc_disable(crtc);
3095 }
3096
3097 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3098 {
3099 i9xx_crtc_enable(crtc);
3100 }
3101
3102 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3103 {
3104 ironlake_crtc_disable(crtc);
3105 }
3106
3107 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3108 {
3109 ironlake_crtc_enable(crtc);
3110 }
3111
3112 void intel_encoder_prepare(struct drm_encoder *encoder)
3113 {
3114 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3115 /* lvds has its own version of prepare see intel_lvds_prepare */
3116 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3117 }
3118
3119 void intel_encoder_commit(struct drm_encoder *encoder)
3120 {
3121 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3122 struct drm_device *dev = encoder->dev;
3123 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3124 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3125
3126 /* lvds has its own version of commit see intel_lvds_commit */
3127 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3128
3129 if (HAS_PCH_CPT(dev))
3130 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3131 }
3132
3133 void intel_encoder_destroy(struct drm_encoder *encoder)
3134 {
3135 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3136
3137 drm_encoder_cleanup(encoder);
3138 kfree(intel_encoder);
3139 }
3140
3141 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3142 struct drm_display_mode *mode,
3143 struct drm_display_mode *adjusted_mode)
3144 {
3145 struct drm_device *dev = crtc->dev;
3146
3147 if (HAS_PCH_SPLIT(dev)) {
3148 /* FDI link clock is fixed at 2.7G */
3149 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3150 return false;
3151 }
3152
3153 /* All interlaced capable intel hw wants timings in frames. */
3154 drm_mode_set_crtcinfo(adjusted_mode, 0);
3155
3156 return true;
3157 }
3158
3159 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3160 {
3161 return 400000; /* FIXME */
3162 }
3163
3164 static int i945_get_display_clock_speed(struct drm_device *dev)
3165 {
3166 return 400000;
3167 }
3168
3169 static int i915_get_display_clock_speed(struct drm_device *dev)
3170 {
3171 return 333000;
3172 }
3173
3174 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3175 {
3176 return 200000;
3177 }
3178
3179 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3180 {
3181 u16 gcfgc = 0;
3182
3183 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3184
3185 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3186 return 133000;
3187 else {
3188 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3189 case GC_DISPLAY_CLOCK_333_MHZ:
3190 return 333000;
3191 default:
3192 case GC_DISPLAY_CLOCK_190_200_MHZ:
3193 return 190000;
3194 }
3195 }
3196 }
3197
3198 static int i865_get_display_clock_speed(struct drm_device *dev)
3199 {
3200 return 266000;
3201 }
3202
3203 static int i855_get_display_clock_speed(struct drm_device *dev)
3204 {
3205 u16 hpllcc = 0;
3206 /* Assume that the hardware is in the high speed state. This
3207 * should be the default.
3208 */
3209 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3210 case GC_CLOCK_133_200:
3211 case GC_CLOCK_100_200:
3212 return 200000;
3213 case GC_CLOCK_166_250:
3214 return 250000;
3215 case GC_CLOCK_100_133:
3216 return 133000;
3217 }
3218
3219 /* Shouldn't happen */
3220 return 0;
3221 }
3222
3223 static int i830_get_display_clock_speed(struct drm_device *dev)
3224 {
3225 return 133000;
3226 }
3227
3228 struct fdi_m_n {
3229 u32 tu;
3230 u32 gmch_m;
3231 u32 gmch_n;
3232 u32 link_m;
3233 u32 link_n;
3234 };
3235
3236 static void
3237 fdi_reduce_ratio(u32 *num, u32 *den)
3238 {
3239 while (*num > 0xffffff || *den > 0xffffff) {
3240 *num >>= 1;
3241 *den >>= 1;
3242 }
3243 }
3244
3245 static void
3246 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3247 int link_clock, struct fdi_m_n *m_n)
3248 {
3249 m_n->tu = 64; /* default size */
3250
3251 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3252 m_n->gmch_m = bits_per_pixel * pixel_clock;
3253 m_n->gmch_n = link_clock * nlanes * 8;
3254 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3255
3256 m_n->link_m = pixel_clock;
3257 m_n->link_n = link_clock;
3258 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3259 }
3260
3261 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3262 {
3263 if (i915_panel_use_ssc >= 0)
3264 return i915_panel_use_ssc != 0;
3265 return dev_priv->lvds_use_ssc
3266 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3267 }
3268
3269 /**
3270 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3271 * @crtc: CRTC structure
3272 * @mode: requested mode
3273 *
3274 * A pipe may be connected to one or more outputs. Based on the depth of the
3275 * attached framebuffer, choose a good color depth to use on the pipe.
3276 *
3277 * If possible, match the pipe depth to the fb depth. In some cases, this
3278 * isn't ideal, because the connected output supports a lesser or restricted
3279 * set of depths. Resolve that here:
3280 * LVDS typically supports only 6bpc, so clamp down in that case
3281 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3282 * Displays may support a restricted set as well, check EDID and clamp as
3283 * appropriate.
3284 * DP may want to dither down to 6bpc to fit larger modes
3285 *
3286 * RETURNS:
3287 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3288 * true if they don't match).
3289 */
3290 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3291 unsigned int *pipe_bpp,
3292 struct drm_display_mode *mode)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 struct drm_encoder *encoder;
3297 struct drm_connector *connector;
3298 unsigned int display_bpc = UINT_MAX, bpc;
3299
3300 /* Walk the encoders & connectors on this crtc, get min bpc */
3301 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3302 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3303
3304 if (encoder->crtc != crtc)
3305 continue;
3306
3307 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3308 unsigned int lvds_bpc;
3309
3310 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3311 LVDS_A3_POWER_UP)
3312 lvds_bpc = 8;
3313 else
3314 lvds_bpc = 6;
3315
3316 if (lvds_bpc < display_bpc) {
3317 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3318 display_bpc = lvds_bpc;
3319 }
3320 continue;
3321 }
3322
3323 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3324 /* Use VBT settings if we have an eDP panel */
3325 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3326
3327 if (edp_bpc < display_bpc) {
3328 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3329 display_bpc = edp_bpc;
3330 }
3331 continue;
3332 }
3333
3334 /* Not one of the known troublemakers, check the EDID */
3335 list_for_each_entry(connector, &dev->mode_config.connector_list,
3336 head) {
3337 if (connector->encoder != encoder)
3338 continue;
3339
3340 /* Don't use an invalid EDID bpc value */
3341 if (connector->display_info.bpc &&
3342 connector->display_info.bpc < display_bpc) {
3343 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3344 display_bpc = connector->display_info.bpc;
3345 }
3346 }
3347
3348 /*
3349 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3350 * through, clamp it down. (Note: >12bpc will be caught below.)
3351 */
3352 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3353 if (display_bpc > 8 && display_bpc < 12) {
3354 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3355 display_bpc = 12;
3356 } else {
3357 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3358 display_bpc = 8;
3359 }
3360 }
3361 }
3362
3363 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3364 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3365 display_bpc = 6;
3366 }
3367
3368 /*
3369 * We could just drive the pipe at the highest bpc all the time and
3370 * enable dithering as needed, but that costs bandwidth. So choose
3371 * the minimum value that expresses the full color range of the fb but
3372 * also stays within the max display bpc discovered above.
3373 */
3374
3375 switch (crtc->fb->depth) {
3376 case 8:
3377 bpc = 8; /* since we go through a colormap */
3378 break;
3379 case 15:
3380 case 16:
3381 bpc = 6; /* min is 18bpp */
3382 break;
3383 case 24:
3384 bpc = 8;
3385 break;
3386 case 30:
3387 bpc = 10;
3388 break;
3389 case 48:
3390 bpc = 12;
3391 break;
3392 default:
3393 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3394 bpc = min((unsigned int)8, display_bpc);
3395 break;
3396 }
3397
3398 display_bpc = min(display_bpc, bpc);
3399
3400 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3401 bpc, display_bpc);
3402
3403 *pipe_bpp = display_bpc * 3;
3404
3405 return display_bpc != bpc;
3406 }
3407
3408 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3409 {
3410 struct drm_device *dev = crtc->dev;
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 int refclk;
3413
3414 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3415 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3416 refclk = dev_priv->lvds_ssc_freq * 1000;
3417 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3418 refclk / 1000);
3419 } else if (!IS_GEN2(dev)) {
3420 refclk = 96000;
3421 } else {
3422 refclk = 48000;
3423 }
3424
3425 return refclk;
3426 }
3427
3428 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3429 intel_clock_t *clock)
3430 {
3431 /* SDVO TV has fixed PLL values depend on its clock range,
3432 this mirrors vbios setting. */
3433 if (adjusted_mode->clock >= 100000
3434 && adjusted_mode->clock < 140500) {
3435 clock->p1 = 2;
3436 clock->p2 = 10;
3437 clock->n = 3;
3438 clock->m1 = 16;
3439 clock->m2 = 8;
3440 } else if (adjusted_mode->clock >= 140500
3441 && adjusted_mode->clock <= 200000) {
3442 clock->p1 = 1;
3443 clock->p2 = 10;
3444 clock->n = 6;
3445 clock->m1 = 12;
3446 clock->m2 = 8;
3447 }
3448 }
3449
3450 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3451 intel_clock_t *clock,
3452 intel_clock_t *reduced_clock)
3453 {
3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457 int pipe = intel_crtc->pipe;
3458 u32 fp, fp2 = 0;
3459
3460 if (IS_PINEVIEW(dev)) {
3461 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3462 if (reduced_clock)
3463 fp2 = (1 << reduced_clock->n) << 16 |
3464 reduced_clock->m1 << 8 | reduced_clock->m2;
3465 } else {
3466 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3467 if (reduced_clock)
3468 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3469 reduced_clock->m2;
3470 }
3471
3472 I915_WRITE(FP0(pipe), fp);
3473
3474 intel_crtc->lowfreq_avail = false;
3475 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3476 reduced_clock && i915_powersave) {
3477 I915_WRITE(FP1(pipe), fp2);
3478 intel_crtc->lowfreq_avail = true;
3479 } else {
3480 I915_WRITE(FP1(pipe), fp);
3481 }
3482 }
3483
3484 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3485 struct drm_display_mode *adjusted_mode)
3486 {
3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3490 int pipe = intel_crtc->pipe;
3491 u32 temp;
3492
3493 temp = I915_READ(LVDS);
3494 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3495 if (pipe == 1) {
3496 temp |= LVDS_PIPEB_SELECT;
3497 } else {
3498 temp &= ~LVDS_PIPEB_SELECT;
3499 }
3500 /* set the corresponsding LVDS_BORDER bit */
3501 temp |= dev_priv->lvds_border_bits;
3502 /* Set the B0-B3 data pairs corresponding to whether we're going to
3503 * set the DPLLs for dual-channel mode or not.
3504 */
3505 if (clock->p2 == 7)
3506 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3507 else
3508 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3509
3510 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3511 * appropriately here, but we need to look more thoroughly into how
3512 * panels behave in the two modes.
3513 */
3514 /* set the dithering flag on LVDS as needed */
3515 if (INTEL_INFO(dev)->gen >= 4) {
3516 if (dev_priv->lvds_dither)
3517 temp |= LVDS_ENABLE_DITHER;
3518 else
3519 temp &= ~LVDS_ENABLE_DITHER;
3520 }
3521 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3522 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3523 temp |= LVDS_HSYNC_POLARITY;
3524 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3525 temp |= LVDS_VSYNC_POLARITY;
3526 I915_WRITE(LVDS, temp);
3527 }
3528
3529 static void i9xx_update_pll(struct drm_crtc *crtc,
3530 struct drm_display_mode *mode,
3531 struct drm_display_mode *adjusted_mode,
3532 intel_clock_t *clock, intel_clock_t *reduced_clock,
3533 int num_connectors)
3534 {
3535 struct drm_device *dev = crtc->dev;
3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3538 int pipe = intel_crtc->pipe;
3539 u32 dpll;
3540 bool is_sdvo;
3541
3542 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3543 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3544
3545 dpll = DPLL_VGA_MODE_DIS;
3546
3547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3548 dpll |= DPLLB_MODE_LVDS;
3549 else
3550 dpll |= DPLLB_MODE_DAC_SERIAL;
3551 if (is_sdvo) {
3552 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3553 if (pixel_multiplier > 1) {
3554 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3555 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3556 }
3557 dpll |= DPLL_DVO_HIGH_SPEED;
3558 }
3559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3560 dpll |= DPLL_DVO_HIGH_SPEED;
3561
3562 /* compute bitmask from p1 value */
3563 if (IS_PINEVIEW(dev))
3564 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3565 else {
3566 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3567 if (IS_G4X(dev) && reduced_clock)
3568 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3569 }
3570 switch (clock->p2) {
3571 case 5:
3572 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3573 break;
3574 case 7:
3575 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3576 break;
3577 case 10:
3578 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3579 break;
3580 case 14:
3581 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3582 break;
3583 }
3584 if (INTEL_INFO(dev)->gen >= 4)
3585 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3586
3587 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3588 dpll |= PLL_REF_INPUT_TVCLKINBC;
3589 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3590 /* XXX: just matching BIOS for now */
3591 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3592 dpll |= 3;
3593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3594 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3595 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3596 else
3597 dpll |= PLL_REF_INPUT_DREFCLK;
3598
3599 dpll |= DPLL_VCO_ENABLE;
3600 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3601 POSTING_READ(DPLL(pipe));
3602 udelay(150);
3603
3604 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3605 * This is an exception to the general rule that mode_set doesn't turn
3606 * things on.
3607 */
3608 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3609 intel_update_lvds(crtc, clock, adjusted_mode);
3610
3611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3612 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3613
3614 I915_WRITE(DPLL(pipe), dpll);
3615
3616 /* Wait for the clocks to stabilize. */
3617 POSTING_READ(DPLL(pipe));
3618 udelay(150);
3619
3620 if (INTEL_INFO(dev)->gen >= 4) {
3621 u32 temp = 0;
3622 if (is_sdvo) {
3623 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3624 if (temp > 1)
3625 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3626 else
3627 temp = 0;
3628 }
3629 I915_WRITE(DPLL_MD(pipe), temp);
3630 } else {
3631 /* The pixel multiplier can only be updated once the
3632 * DPLL is enabled and the clocks are stable.
3633 *
3634 * So write it again.
3635 */
3636 I915_WRITE(DPLL(pipe), dpll);
3637 }
3638 }
3639
3640 static void i8xx_update_pll(struct drm_crtc *crtc,
3641 struct drm_display_mode *adjusted_mode,
3642 intel_clock_t *clock,
3643 int num_connectors)
3644 {
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3648 int pipe = intel_crtc->pipe;
3649 u32 dpll;
3650
3651 dpll = DPLL_VGA_MODE_DIS;
3652
3653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3654 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3655 } else {
3656 if (clock->p1 == 2)
3657 dpll |= PLL_P1_DIVIDE_BY_TWO;
3658 else
3659 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3660 if (clock->p2 == 4)
3661 dpll |= PLL_P2_DIVIDE_BY_4;
3662 }
3663
3664 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3665 /* XXX: just matching BIOS for now */
3666 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3667 dpll |= 3;
3668 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3669 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3670 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3671 else
3672 dpll |= PLL_REF_INPUT_DREFCLK;
3673
3674 dpll |= DPLL_VCO_ENABLE;
3675 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3676 POSTING_READ(DPLL(pipe));
3677 udelay(150);
3678
3679 I915_WRITE(DPLL(pipe), dpll);
3680
3681 /* Wait for the clocks to stabilize. */
3682 POSTING_READ(DPLL(pipe));
3683 udelay(150);
3684
3685 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3686 * This is an exception to the general rule that mode_set doesn't turn
3687 * things on.
3688 */
3689 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3690 intel_update_lvds(crtc, clock, adjusted_mode);
3691
3692 /* The pixel multiplier can only be updated once the
3693 * DPLL is enabled and the clocks are stable.
3694 *
3695 * So write it again.
3696 */
3697 I915_WRITE(DPLL(pipe), dpll);
3698 }
3699
3700 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3701 struct drm_display_mode *mode,
3702 struct drm_display_mode *adjusted_mode,
3703 int x, int y,
3704 struct drm_framebuffer *old_fb)
3705 {
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3709 int pipe = intel_crtc->pipe;
3710 int plane = intel_crtc->plane;
3711 int refclk, num_connectors = 0;
3712 intel_clock_t clock, reduced_clock;
3713 u32 dspcntr, pipeconf, vsyncshift;
3714 bool ok, has_reduced_clock = false, is_sdvo = false;
3715 bool is_lvds = false, is_tv = false, is_dp = false;
3716 struct drm_mode_config *mode_config = &dev->mode_config;
3717 struct intel_encoder *encoder;
3718 const intel_limit_t *limit;
3719 int ret;
3720
3721 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3722 if (encoder->base.crtc != crtc)
3723 continue;
3724
3725 switch (encoder->type) {
3726 case INTEL_OUTPUT_LVDS:
3727 is_lvds = true;
3728 break;
3729 case INTEL_OUTPUT_SDVO:
3730 case INTEL_OUTPUT_HDMI:
3731 is_sdvo = true;
3732 if (encoder->needs_tv_clock)
3733 is_tv = true;
3734 break;
3735 case INTEL_OUTPUT_TVOUT:
3736 is_tv = true;
3737 break;
3738 case INTEL_OUTPUT_DISPLAYPORT:
3739 is_dp = true;
3740 break;
3741 }
3742
3743 num_connectors++;
3744 }
3745
3746 refclk = i9xx_get_refclk(crtc, num_connectors);
3747
3748 /*
3749 * Returns a set of divisors for the desired target clock with the given
3750 * refclk, or FALSE. The returned values represent the clock equation:
3751 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3752 */
3753 limit = intel_limit(crtc, refclk);
3754 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3755 &clock);
3756 if (!ok) {
3757 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3758 return -EINVAL;
3759 }
3760
3761 /* Ensure that the cursor is valid for the new mode before changing... */
3762 intel_crtc_update_cursor(crtc, true);
3763
3764 if (is_lvds && dev_priv->lvds_downclock_avail) {
3765 /*
3766 * Ensure we match the reduced clock's P to the target clock.
3767 * If the clocks don't match, we can't switch the display clock
3768 * by using the FP0/FP1. In such case we will disable the LVDS
3769 * downclock feature.
3770 */
3771 has_reduced_clock = limit->find_pll(limit, crtc,
3772 dev_priv->lvds_downclock,
3773 refclk,
3774 &clock,
3775 &reduced_clock);
3776 }
3777
3778 if (is_sdvo && is_tv)
3779 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3780
3781 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3782 &reduced_clock : NULL);
3783
3784 if (IS_GEN2(dev))
3785 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
3786 else
3787 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
3788 has_reduced_clock ? &reduced_clock : NULL,
3789 num_connectors);
3790
3791 /* setup pipeconf */
3792 pipeconf = I915_READ(PIPECONF(pipe));
3793
3794 /* Set up the display plane register */
3795 dspcntr = DISPPLANE_GAMMA_ENABLE;
3796
3797 if (pipe == 0)
3798 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3799 else
3800 dspcntr |= DISPPLANE_SEL_PIPE_B;
3801
3802 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3803 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3804 * core speed.
3805 *
3806 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3807 * pipe == 0 check?
3808 */
3809 if (mode->clock >
3810 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3811 pipeconf |= PIPECONF_DOUBLE_WIDE;
3812 else
3813 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3814 }
3815
3816 /* default to 8bpc */
3817 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3818 if (is_dp) {
3819 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3820 pipeconf |= PIPECONF_BPP_6 |
3821 PIPECONF_DITHER_EN |
3822 PIPECONF_DITHER_TYPE_SP;
3823 }
3824 }
3825
3826 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3827 drm_mode_debug_printmodeline(mode);
3828
3829 if (HAS_PIPE_CXSR(dev)) {
3830 if (intel_crtc->lowfreq_avail) {
3831 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3832 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3833 } else {
3834 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3835 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3836 }
3837 }
3838
3839 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3840 if (!IS_GEN2(dev) &&
3841 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3842 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3843 /* the chip adds 2 halflines automatically */
3844 adjusted_mode->crtc_vtotal -= 1;
3845 adjusted_mode->crtc_vblank_end -= 1;
3846 vsyncshift = adjusted_mode->crtc_hsync_start
3847 - adjusted_mode->crtc_htotal/2;
3848 } else {
3849 pipeconf |= PIPECONF_PROGRESSIVE;
3850 vsyncshift = 0;
3851 }
3852
3853 if (!IS_GEN3(dev))
3854 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3855
3856 I915_WRITE(HTOTAL(pipe),
3857 (adjusted_mode->crtc_hdisplay - 1) |
3858 ((adjusted_mode->crtc_htotal - 1) << 16));
3859 I915_WRITE(HBLANK(pipe),
3860 (adjusted_mode->crtc_hblank_start - 1) |
3861 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3862 I915_WRITE(HSYNC(pipe),
3863 (adjusted_mode->crtc_hsync_start - 1) |
3864 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3865
3866 I915_WRITE(VTOTAL(pipe),
3867 (adjusted_mode->crtc_vdisplay - 1) |
3868 ((adjusted_mode->crtc_vtotal - 1) << 16));
3869 I915_WRITE(VBLANK(pipe),
3870 (adjusted_mode->crtc_vblank_start - 1) |
3871 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3872 I915_WRITE(VSYNC(pipe),
3873 (adjusted_mode->crtc_vsync_start - 1) |
3874 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3875
3876 /* pipesrc and dspsize control the size that is scaled from,
3877 * which should always be the user's requested size.
3878 */
3879 I915_WRITE(DSPSIZE(plane),
3880 ((mode->vdisplay - 1) << 16) |
3881 (mode->hdisplay - 1));
3882 I915_WRITE(DSPPOS(plane), 0);
3883 I915_WRITE(PIPESRC(pipe),
3884 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3885
3886 I915_WRITE(PIPECONF(pipe), pipeconf);
3887 POSTING_READ(PIPECONF(pipe));
3888 intel_enable_pipe(dev_priv, pipe, false);
3889
3890 intel_wait_for_vblank(dev, pipe);
3891
3892 I915_WRITE(DSPCNTR(plane), dspcntr);
3893 POSTING_READ(DSPCNTR(plane));
3894
3895 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3896
3897 intel_update_watermarks(dev);
3898
3899 return ret;
3900 }
3901
3902 /*
3903 * Initialize reference clocks when the driver loads
3904 */
3905 void ironlake_init_pch_refclk(struct drm_device *dev)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct drm_mode_config *mode_config = &dev->mode_config;
3909 struct intel_encoder *encoder;
3910 u32 temp;
3911 bool has_lvds = false;
3912 bool has_cpu_edp = false;
3913 bool has_pch_edp = false;
3914 bool has_panel = false;
3915 bool has_ck505 = false;
3916 bool can_ssc = false;
3917
3918 /* We need to take the global config into account */
3919 list_for_each_entry(encoder, &mode_config->encoder_list,
3920 base.head) {
3921 switch (encoder->type) {
3922 case INTEL_OUTPUT_LVDS:
3923 has_panel = true;
3924 has_lvds = true;
3925 break;
3926 case INTEL_OUTPUT_EDP:
3927 has_panel = true;
3928 if (intel_encoder_is_pch_edp(&encoder->base))
3929 has_pch_edp = true;
3930 else
3931 has_cpu_edp = true;
3932 break;
3933 }
3934 }
3935
3936 if (HAS_PCH_IBX(dev)) {
3937 has_ck505 = dev_priv->display_clock_mode;
3938 can_ssc = has_ck505;
3939 } else {
3940 has_ck505 = false;
3941 can_ssc = true;
3942 }
3943
3944 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3945 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3946 has_ck505);
3947
3948 /* Ironlake: try to setup display ref clock before DPLL
3949 * enabling. This is only under driver's control after
3950 * PCH B stepping, previous chipset stepping should be
3951 * ignoring this setting.
3952 */
3953 temp = I915_READ(PCH_DREF_CONTROL);
3954 /* Always enable nonspread source */
3955 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3956
3957 if (has_ck505)
3958 temp |= DREF_NONSPREAD_CK505_ENABLE;
3959 else
3960 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3961
3962 if (has_panel) {
3963 temp &= ~DREF_SSC_SOURCE_MASK;
3964 temp |= DREF_SSC_SOURCE_ENABLE;
3965
3966 /* SSC must be turned on before enabling the CPU output */
3967 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3968 DRM_DEBUG_KMS("Using SSC on panel\n");
3969 temp |= DREF_SSC1_ENABLE;
3970 } else
3971 temp &= ~DREF_SSC1_ENABLE;
3972
3973 /* Get SSC going before enabling the outputs */
3974 I915_WRITE(PCH_DREF_CONTROL, temp);
3975 POSTING_READ(PCH_DREF_CONTROL);
3976 udelay(200);
3977
3978 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3979
3980 /* Enable CPU source on CPU attached eDP */
3981 if (has_cpu_edp) {
3982 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3983 DRM_DEBUG_KMS("Using SSC on eDP\n");
3984 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3985 }
3986 else
3987 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3988 } else
3989 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3990
3991 I915_WRITE(PCH_DREF_CONTROL, temp);
3992 POSTING_READ(PCH_DREF_CONTROL);
3993 udelay(200);
3994 } else {
3995 DRM_DEBUG_KMS("Disabling SSC entirely\n");
3996
3997 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3998
3999 /* Turn off CPU output */
4000 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4001
4002 I915_WRITE(PCH_DREF_CONTROL, temp);
4003 POSTING_READ(PCH_DREF_CONTROL);
4004 udelay(200);
4005
4006 /* Turn off the SSC source */
4007 temp &= ~DREF_SSC_SOURCE_MASK;
4008 temp |= DREF_SSC_SOURCE_DISABLE;
4009
4010 /* Turn off SSC1 */
4011 temp &= ~ DREF_SSC1_ENABLE;
4012
4013 I915_WRITE(PCH_DREF_CONTROL, temp);
4014 POSTING_READ(PCH_DREF_CONTROL);
4015 udelay(200);
4016 }
4017 }
4018
4019 static int ironlake_get_refclk(struct drm_crtc *crtc)
4020 {
4021 struct drm_device *dev = crtc->dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 struct intel_encoder *encoder;
4024 struct drm_mode_config *mode_config = &dev->mode_config;
4025 struct intel_encoder *edp_encoder = NULL;
4026 int num_connectors = 0;
4027 bool is_lvds = false;
4028
4029 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4030 if (encoder->base.crtc != crtc)
4031 continue;
4032
4033 switch (encoder->type) {
4034 case INTEL_OUTPUT_LVDS:
4035 is_lvds = true;
4036 break;
4037 case INTEL_OUTPUT_EDP:
4038 edp_encoder = encoder;
4039 break;
4040 }
4041 num_connectors++;
4042 }
4043
4044 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4045 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4046 dev_priv->lvds_ssc_freq);
4047 return dev_priv->lvds_ssc_freq * 1000;
4048 }
4049
4050 return 120000;
4051 }
4052
4053 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4054 struct drm_display_mode *mode,
4055 struct drm_display_mode *adjusted_mode,
4056 int x, int y,
4057 struct drm_framebuffer *old_fb)
4058 {
4059 struct drm_device *dev = crtc->dev;
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4062 int pipe = intel_crtc->pipe;
4063 int plane = intel_crtc->plane;
4064 int refclk, num_connectors = 0;
4065 intel_clock_t clock, reduced_clock;
4066 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4067 bool ok, has_reduced_clock = false, is_sdvo = false;
4068 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4069 struct drm_mode_config *mode_config = &dev->mode_config;
4070 struct intel_encoder *encoder, *edp_encoder = NULL;
4071 const intel_limit_t *limit;
4072 int ret;
4073 struct fdi_m_n m_n = {0};
4074 u32 temp;
4075 int target_clock, pixel_multiplier, lane, link_bw, factor;
4076 unsigned int pipe_bpp;
4077 bool dither;
4078 bool is_cpu_edp = false, is_pch_edp = false;
4079
4080 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4081 if (encoder->base.crtc != crtc)
4082 continue;
4083
4084 switch (encoder->type) {
4085 case INTEL_OUTPUT_LVDS:
4086 is_lvds = true;
4087 break;
4088 case INTEL_OUTPUT_SDVO:
4089 case INTEL_OUTPUT_HDMI:
4090 is_sdvo = true;
4091 if (encoder->needs_tv_clock)
4092 is_tv = true;
4093 break;
4094 case INTEL_OUTPUT_TVOUT:
4095 is_tv = true;
4096 break;
4097 case INTEL_OUTPUT_ANALOG:
4098 is_crt = true;
4099 break;
4100 case INTEL_OUTPUT_DISPLAYPORT:
4101 is_dp = true;
4102 break;
4103 case INTEL_OUTPUT_EDP:
4104 is_dp = true;
4105 if (intel_encoder_is_pch_edp(&encoder->base))
4106 is_pch_edp = true;
4107 else
4108 is_cpu_edp = true;
4109 edp_encoder = encoder;
4110 break;
4111 }
4112
4113 num_connectors++;
4114 }
4115
4116 refclk = ironlake_get_refclk(crtc);
4117
4118 /*
4119 * Returns a set of divisors for the desired target clock with the given
4120 * refclk, or FALSE. The returned values represent the clock equation:
4121 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4122 */
4123 limit = intel_limit(crtc, refclk);
4124 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4125 &clock);
4126 if (!ok) {
4127 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4128 return -EINVAL;
4129 }
4130
4131 /* Ensure that the cursor is valid for the new mode before changing... */
4132 intel_crtc_update_cursor(crtc, true);
4133
4134 if (is_lvds && dev_priv->lvds_downclock_avail) {
4135 /*
4136 * Ensure we match the reduced clock's P to the target clock.
4137 * If the clocks don't match, we can't switch the display clock
4138 * by using the FP0/FP1. In such case we will disable the LVDS
4139 * downclock feature.
4140 */
4141 has_reduced_clock = limit->find_pll(limit, crtc,
4142 dev_priv->lvds_downclock,
4143 refclk,
4144 &clock,
4145 &reduced_clock);
4146 }
4147 /* SDVO TV has fixed PLL values depend on its clock range,
4148 this mirrors vbios setting. */
4149 if (is_sdvo && is_tv) {
4150 if (adjusted_mode->clock >= 100000
4151 && adjusted_mode->clock < 140500) {
4152 clock.p1 = 2;
4153 clock.p2 = 10;
4154 clock.n = 3;
4155 clock.m1 = 16;
4156 clock.m2 = 8;
4157 } else if (adjusted_mode->clock >= 140500
4158 && adjusted_mode->clock <= 200000) {
4159 clock.p1 = 1;
4160 clock.p2 = 10;
4161 clock.n = 6;
4162 clock.m1 = 12;
4163 clock.m2 = 8;
4164 }
4165 }
4166
4167 /* FDI link */
4168 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4169 lane = 0;
4170 /* CPU eDP doesn't require FDI link, so just set DP M/N
4171 according to current link config */
4172 if (is_cpu_edp) {
4173 target_clock = mode->clock;
4174 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4175 } else {
4176 /* [e]DP over FDI requires target mode clock
4177 instead of link clock */
4178 if (is_dp)
4179 target_clock = mode->clock;
4180 else
4181 target_clock = adjusted_mode->clock;
4182
4183 /* FDI is a binary signal running at ~2.7GHz, encoding
4184 * each output octet as 10 bits. The actual frequency
4185 * is stored as a divider into a 100MHz clock, and the
4186 * mode pixel clock is stored in units of 1KHz.
4187 * Hence the bw of each lane in terms of the mode signal
4188 * is:
4189 */
4190 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4191 }
4192
4193 /* determine panel color depth */
4194 temp = I915_READ(PIPECONF(pipe));
4195 temp &= ~PIPE_BPC_MASK;
4196 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4197 switch (pipe_bpp) {
4198 case 18:
4199 temp |= PIPE_6BPC;
4200 break;
4201 case 24:
4202 temp |= PIPE_8BPC;
4203 break;
4204 case 30:
4205 temp |= PIPE_10BPC;
4206 break;
4207 case 36:
4208 temp |= PIPE_12BPC;
4209 break;
4210 default:
4211 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4212 pipe_bpp);
4213 temp |= PIPE_8BPC;
4214 pipe_bpp = 24;
4215 break;
4216 }
4217
4218 intel_crtc->bpp = pipe_bpp;
4219 I915_WRITE(PIPECONF(pipe), temp);
4220
4221 if (!lane) {
4222 /*
4223 * Account for spread spectrum to avoid
4224 * oversubscribing the link. Max center spread
4225 * is 2.5%; use 5% for safety's sake.
4226 */
4227 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4228 lane = bps / (link_bw * 8) + 1;
4229 }
4230
4231 intel_crtc->fdi_lanes = lane;
4232
4233 if (pixel_multiplier > 1)
4234 link_bw *= pixel_multiplier;
4235 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4236 &m_n);
4237
4238 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4239 if (has_reduced_clock)
4240 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4241 reduced_clock.m2;
4242
4243 /* Enable autotuning of the PLL clock (if permissible) */
4244 factor = 21;
4245 if (is_lvds) {
4246 if ((intel_panel_use_ssc(dev_priv) &&
4247 dev_priv->lvds_ssc_freq == 100) ||
4248 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4249 factor = 25;
4250 } else if (is_sdvo && is_tv)
4251 factor = 20;
4252
4253 if (clock.m < factor * clock.n)
4254 fp |= FP_CB_TUNE;
4255
4256 dpll = 0;
4257
4258 if (is_lvds)
4259 dpll |= DPLLB_MODE_LVDS;
4260 else
4261 dpll |= DPLLB_MODE_DAC_SERIAL;
4262 if (is_sdvo) {
4263 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4264 if (pixel_multiplier > 1) {
4265 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4266 }
4267 dpll |= DPLL_DVO_HIGH_SPEED;
4268 }
4269 if (is_dp && !is_cpu_edp)
4270 dpll |= DPLL_DVO_HIGH_SPEED;
4271
4272 /* compute bitmask from p1 value */
4273 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4274 /* also FPA1 */
4275 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4276
4277 switch (clock.p2) {
4278 case 5:
4279 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4280 break;
4281 case 7:
4282 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4283 break;
4284 case 10:
4285 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4286 break;
4287 case 14:
4288 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4289 break;
4290 }
4291
4292 if (is_sdvo && is_tv)
4293 dpll |= PLL_REF_INPUT_TVCLKINBC;
4294 else if (is_tv)
4295 /* XXX: just matching BIOS for now */
4296 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4297 dpll |= 3;
4298 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4299 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4300 else
4301 dpll |= PLL_REF_INPUT_DREFCLK;
4302
4303 /* setup pipeconf */
4304 pipeconf = I915_READ(PIPECONF(pipe));
4305
4306 /* Set up the display plane register */
4307 dspcntr = DISPPLANE_GAMMA_ENABLE;
4308
4309 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4310 drm_mode_debug_printmodeline(mode);
4311
4312 /* CPU eDP is the only output that doesn't need a PCH PLL of its own */
4313 if (!is_cpu_edp) {
4314 struct intel_pch_pll *pll;
4315
4316 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4317 if (pll == NULL) {
4318 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4319 pipe);
4320 return -EINVAL;
4321 }
4322 } else
4323 intel_put_pch_pll(intel_crtc);
4324
4325 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4326 * This is an exception to the general rule that mode_set doesn't turn
4327 * things on.
4328 */
4329 if (is_lvds) {
4330 temp = I915_READ(PCH_LVDS);
4331 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4332 if (HAS_PCH_CPT(dev)) {
4333 temp &= ~PORT_TRANS_SEL_MASK;
4334 temp |= PORT_TRANS_SEL_CPT(pipe);
4335 } else {
4336 if (pipe == 1)
4337 temp |= LVDS_PIPEB_SELECT;
4338 else
4339 temp &= ~LVDS_PIPEB_SELECT;
4340 }
4341
4342 /* set the corresponsding LVDS_BORDER bit */
4343 temp |= dev_priv->lvds_border_bits;
4344 /* Set the B0-B3 data pairs corresponding to whether we're going to
4345 * set the DPLLs for dual-channel mode or not.
4346 */
4347 if (clock.p2 == 7)
4348 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4349 else
4350 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4351
4352 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4353 * appropriately here, but we need to look more thoroughly into how
4354 * panels behave in the two modes.
4355 */
4356 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4357 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4358 temp |= LVDS_HSYNC_POLARITY;
4359 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4360 temp |= LVDS_VSYNC_POLARITY;
4361 I915_WRITE(PCH_LVDS, temp);
4362 }
4363
4364 pipeconf &= ~PIPECONF_DITHER_EN;
4365 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4366 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4367 pipeconf |= PIPECONF_DITHER_EN;
4368 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4369 }
4370 if (is_dp && !is_cpu_edp) {
4371 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4372 } else {
4373 /* For non-DP output, clear any trans DP clock recovery setting.*/
4374 I915_WRITE(TRANSDATA_M1(pipe), 0);
4375 I915_WRITE(TRANSDATA_N1(pipe), 0);
4376 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4377 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4378 }
4379
4380 if (intel_crtc->pch_pll) {
4381 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4382
4383 /* Wait for the clocks to stabilize. */
4384 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4385 udelay(150);
4386
4387 /* The pixel multiplier can only be updated once the
4388 * DPLL is enabled and the clocks are stable.
4389 *
4390 * So write it again.
4391 */
4392 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4393 }
4394
4395 intel_crtc->lowfreq_avail = false;
4396 if (intel_crtc->pch_pll) {
4397 if (is_lvds && has_reduced_clock && i915_powersave) {
4398 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4399 intel_crtc->lowfreq_avail = true;
4400 if (HAS_PIPE_CXSR(dev)) {
4401 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4402 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4403 }
4404 } else {
4405 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4406 if (HAS_PIPE_CXSR(dev)) {
4407 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4408 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4409 }
4410 }
4411 }
4412
4413 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4414 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4415 pipeconf |= PIPECONF_INTERLACED_ILK;
4416 /* the chip adds 2 halflines automatically */
4417 adjusted_mode->crtc_vtotal -= 1;
4418 adjusted_mode->crtc_vblank_end -= 1;
4419 I915_WRITE(VSYNCSHIFT(pipe),
4420 adjusted_mode->crtc_hsync_start
4421 - adjusted_mode->crtc_htotal/2);
4422 } else {
4423 pipeconf |= PIPECONF_PROGRESSIVE;
4424 I915_WRITE(VSYNCSHIFT(pipe), 0);
4425 }
4426
4427 I915_WRITE(HTOTAL(pipe),
4428 (adjusted_mode->crtc_hdisplay - 1) |
4429 ((adjusted_mode->crtc_htotal - 1) << 16));
4430 I915_WRITE(HBLANK(pipe),
4431 (adjusted_mode->crtc_hblank_start - 1) |
4432 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4433 I915_WRITE(HSYNC(pipe),
4434 (adjusted_mode->crtc_hsync_start - 1) |
4435 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4436
4437 I915_WRITE(VTOTAL(pipe),
4438 (adjusted_mode->crtc_vdisplay - 1) |
4439 ((adjusted_mode->crtc_vtotal - 1) << 16));
4440 I915_WRITE(VBLANK(pipe),
4441 (adjusted_mode->crtc_vblank_start - 1) |
4442 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4443 I915_WRITE(VSYNC(pipe),
4444 (adjusted_mode->crtc_vsync_start - 1) |
4445 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4446
4447 /* pipesrc controls the size that is scaled from, which should
4448 * always be the user's requested size.
4449 */
4450 I915_WRITE(PIPESRC(pipe),
4451 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4452
4453 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4454 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4455 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4456 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4457
4458 if (is_cpu_edp)
4459 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4460
4461 I915_WRITE(PIPECONF(pipe), pipeconf);
4462 POSTING_READ(PIPECONF(pipe));
4463
4464 intel_wait_for_vblank(dev, pipe);
4465
4466 I915_WRITE(DSPCNTR(plane), dspcntr);
4467 POSTING_READ(DSPCNTR(plane));
4468
4469 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4470
4471 intel_update_watermarks(dev);
4472
4473 return ret;
4474 }
4475
4476 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4477 struct drm_display_mode *mode,
4478 struct drm_display_mode *adjusted_mode,
4479 int x, int y,
4480 struct drm_framebuffer *old_fb)
4481 {
4482 struct drm_device *dev = crtc->dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4485 int pipe = intel_crtc->pipe;
4486 int ret;
4487
4488 drm_vblank_pre_modeset(dev, pipe);
4489
4490 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4491 x, y, old_fb);
4492 drm_vblank_post_modeset(dev, pipe);
4493
4494 if (ret)
4495 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4496 else
4497 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4498
4499 return ret;
4500 }
4501
4502 static bool intel_eld_uptodate(struct drm_connector *connector,
4503 int reg_eldv, uint32_t bits_eldv,
4504 int reg_elda, uint32_t bits_elda,
4505 int reg_edid)
4506 {
4507 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4508 uint8_t *eld = connector->eld;
4509 uint32_t i;
4510
4511 i = I915_READ(reg_eldv);
4512 i &= bits_eldv;
4513
4514 if (!eld[0])
4515 return !i;
4516
4517 if (!i)
4518 return false;
4519
4520 i = I915_READ(reg_elda);
4521 i &= ~bits_elda;
4522 I915_WRITE(reg_elda, i);
4523
4524 for (i = 0; i < eld[2]; i++)
4525 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4526 return false;
4527
4528 return true;
4529 }
4530
4531 static void g4x_write_eld(struct drm_connector *connector,
4532 struct drm_crtc *crtc)
4533 {
4534 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4535 uint8_t *eld = connector->eld;
4536 uint32_t eldv;
4537 uint32_t len;
4538 uint32_t i;
4539
4540 i = I915_READ(G4X_AUD_VID_DID);
4541
4542 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4543 eldv = G4X_ELDV_DEVCL_DEVBLC;
4544 else
4545 eldv = G4X_ELDV_DEVCTG;
4546
4547 if (intel_eld_uptodate(connector,
4548 G4X_AUD_CNTL_ST, eldv,
4549 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4550 G4X_HDMIW_HDMIEDID))
4551 return;
4552
4553 i = I915_READ(G4X_AUD_CNTL_ST);
4554 i &= ~(eldv | G4X_ELD_ADDR);
4555 len = (i >> 9) & 0x1f; /* ELD buffer size */
4556 I915_WRITE(G4X_AUD_CNTL_ST, i);
4557
4558 if (!eld[0])
4559 return;
4560
4561 len = min_t(uint8_t, eld[2], len);
4562 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4563 for (i = 0; i < len; i++)
4564 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4565
4566 i = I915_READ(G4X_AUD_CNTL_ST);
4567 i |= eldv;
4568 I915_WRITE(G4X_AUD_CNTL_ST, i);
4569 }
4570
4571 static void ironlake_write_eld(struct drm_connector *connector,
4572 struct drm_crtc *crtc)
4573 {
4574 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4575 uint8_t *eld = connector->eld;
4576 uint32_t eldv;
4577 uint32_t i;
4578 int len;
4579 int hdmiw_hdmiedid;
4580 int aud_config;
4581 int aud_cntl_st;
4582 int aud_cntrl_st2;
4583
4584 if (HAS_PCH_IBX(connector->dev)) {
4585 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4586 aud_config = IBX_AUD_CONFIG_A;
4587 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4588 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4589 } else {
4590 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4591 aud_config = CPT_AUD_CONFIG_A;
4592 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4593 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4594 }
4595
4596 i = to_intel_crtc(crtc)->pipe;
4597 hdmiw_hdmiedid += i * 0x100;
4598 aud_cntl_st += i * 0x100;
4599 aud_config += i * 0x100;
4600
4601 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4602
4603 i = I915_READ(aud_cntl_st);
4604 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4605 if (!i) {
4606 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4607 /* operate blindly on all ports */
4608 eldv = IBX_ELD_VALIDB;
4609 eldv |= IBX_ELD_VALIDB << 4;
4610 eldv |= IBX_ELD_VALIDB << 8;
4611 } else {
4612 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
4613 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4614 }
4615
4616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4617 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4618 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4619 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4620 } else
4621 I915_WRITE(aud_config, 0);
4622
4623 if (intel_eld_uptodate(connector,
4624 aud_cntrl_st2, eldv,
4625 aud_cntl_st, IBX_ELD_ADDRESS,
4626 hdmiw_hdmiedid))
4627 return;
4628
4629 i = I915_READ(aud_cntrl_st2);
4630 i &= ~eldv;
4631 I915_WRITE(aud_cntrl_st2, i);
4632
4633 if (!eld[0])
4634 return;
4635
4636 i = I915_READ(aud_cntl_st);
4637 i &= ~IBX_ELD_ADDRESS;
4638 I915_WRITE(aud_cntl_st, i);
4639
4640 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4641 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4642 for (i = 0; i < len; i++)
4643 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4644
4645 i = I915_READ(aud_cntrl_st2);
4646 i |= eldv;
4647 I915_WRITE(aud_cntrl_st2, i);
4648 }
4649
4650 void intel_write_eld(struct drm_encoder *encoder,
4651 struct drm_display_mode *mode)
4652 {
4653 struct drm_crtc *crtc = encoder->crtc;
4654 struct drm_connector *connector;
4655 struct drm_device *dev = encoder->dev;
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4657
4658 connector = drm_select_eld(encoder, mode);
4659 if (!connector)
4660 return;
4661
4662 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4663 connector->base.id,
4664 drm_get_connector_name(connector),
4665 connector->encoder->base.id,
4666 drm_get_encoder_name(connector->encoder));
4667
4668 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4669
4670 if (dev_priv->display.write_eld)
4671 dev_priv->display.write_eld(connector, crtc);
4672 }
4673
4674 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4675 void intel_crtc_load_lut(struct drm_crtc *crtc)
4676 {
4677 struct drm_device *dev = crtc->dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4680 int palreg = PALETTE(intel_crtc->pipe);
4681 int i;
4682
4683 /* The clocks have to be on to load the palette. */
4684 if (!crtc->enabled || !intel_crtc->active)
4685 return;
4686
4687 /* use legacy palette for Ironlake */
4688 if (HAS_PCH_SPLIT(dev))
4689 palreg = LGC_PALETTE(intel_crtc->pipe);
4690
4691 for (i = 0; i < 256; i++) {
4692 I915_WRITE(palreg + 4 * i,
4693 (intel_crtc->lut_r[i] << 16) |
4694 (intel_crtc->lut_g[i] << 8) |
4695 intel_crtc->lut_b[i]);
4696 }
4697 }
4698
4699 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4700 {
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 bool visible = base != 0;
4705 u32 cntl;
4706
4707 if (intel_crtc->cursor_visible == visible)
4708 return;
4709
4710 cntl = I915_READ(_CURACNTR);
4711 if (visible) {
4712 /* On these chipsets we can only modify the base whilst
4713 * the cursor is disabled.
4714 */
4715 I915_WRITE(_CURABASE, base);
4716
4717 cntl &= ~(CURSOR_FORMAT_MASK);
4718 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4719 cntl |= CURSOR_ENABLE |
4720 CURSOR_GAMMA_ENABLE |
4721 CURSOR_FORMAT_ARGB;
4722 } else
4723 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4724 I915_WRITE(_CURACNTR, cntl);
4725
4726 intel_crtc->cursor_visible = visible;
4727 }
4728
4729 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4730 {
4731 struct drm_device *dev = crtc->dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 int pipe = intel_crtc->pipe;
4735 bool visible = base != 0;
4736
4737 if (intel_crtc->cursor_visible != visible) {
4738 uint32_t cntl = I915_READ(CURCNTR(pipe));
4739 if (base) {
4740 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4741 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4742 cntl |= pipe << 28; /* Connect to correct pipe */
4743 } else {
4744 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4745 cntl |= CURSOR_MODE_DISABLE;
4746 }
4747 I915_WRITE(CURCNTR(pipe), cntl);
4748
4749 intel_crtc->cursor_visible = visible;
4750 }
4751 /* and commit changes on next vblank */
4752 I915_WRITE(CURBASE(pipe), base);
4753 }
4754
4755 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4756 {
4757 struct drm_device *dev = crtc->dev;
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4760 int pipe = intel_crtc->pipe;
4761 bool visible = base != 0;
4762
4763 if (intel_crtc->cursor_visible != visible) {
4764 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4765 if (base) {
4766 cntl &= ~CURSOR_MODE;
4767 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4768 } else {
4769 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4770 cntl |= CURSOR_MODE_DISABLE;
4771 }
4772 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4773
4774 intel_crtc->cursor_visible = visible;
4775 }
4776 /* and commit changes on next vblank */
4777 I915_WRITE(CURBASE_IVB(pipe), base);
4778 }
4779
4780 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4781 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4782 bool on)
4783 {
4784 struct drm_device *dev = crtc->dev;
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4787 int pipe = intel_crtc->pipe;
4788 int x = intel_crtc->cursor_x;
4789 int y = intel_crtc->cursor_y;
4790 u32 base, pos;
4791 bool visible;
4792
4793 pos = 0;
4794
4795 if (on && crtc->enabled && crtc->fb) {
4796 base = intel_crtc->cursor_addr;
4797 if (x > (int) crtc->fb->width)
4798 base = 0;
4799
4800 if (y > (int) crtc->fb->height)
4801 base = 0;
4802 } else
4803 base = 0;
4804
4805 if (x < 0) {
4806 if (x + intel_crtc->cursor_width < 0)
4807 base = 0;
4808
4809 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4810 x = -x;
4811 }
4812 pos |= x << CURSOR_X_SHIFT;
4813
4814 if (y < 0) {
4815 if (y + intel_crtc->cursor_height < 0)
4816 base = 0;
4817
4818 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4819 y = -y;
4820 }
4821 pos |= y << CURSOR_Y_SHIFT;
4822
4823 visible = base != 0;
4824 if (!visible && !intel_crtc->cursor_visible)
4825 return;
4826
4827 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4828 I915_WRITE(CURPOS_IVB(pipe), pos);
4829 ivb_update_cursor(crtc, base);
4830 } else {
4831 I915_WRITE(CURPOS(pipe), pos);
4832 if (IS_845G(dev) || IS_I865G(dev))
4833 i845_update_cursor(crtc, base);
4834 else
4835 i9xx_update_cursor(crtc, base);
4836 }
4837
4838 if (visible)
4839 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4840 }
4841
4842 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4843 struct drm_file *file,
4844 uint32_t handle,
4845 uint32_t width, uint32_t height)
4846 {
4847 struct drm_device *dev = crtc->dev;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850 struct drm_i915_gem_object *obj;
4851 uint32_t addr;
4852 int ret;
4853
4854 DRM_DEBUG_KMS("\n");
4855
4856 /* if we want to turn off the cursor ignore width and height */
4857 if (!handle) {
4858 DRM_DEBUG_KMS("cursor off\n");
4859 addr = 0;
4860 obj = NULL;
4861 mutex_lock(&dev->struct_mutex);
4862 goto finish;
4863 }
4864
4865 /* Currently we only support 64x64 cursors */
4866 if (width != 64 || height != 64) {
4867 DRM_ERROR("we currently only support 64x64 cursors\n");
4868 return -EINVAL;
4869 }
4870
4871 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4872 if (&obj->base == NULL)
4873 return -ENOENT;
4874
4875 if (obj->base.size < width * height * 4) {
4876 DRM_ERROR("buffer is to small\n");
4877 ret = -ENOMEM;
4878 goto fail;
4879 }
4880
4881 /* we only need to pin inside GTT if cursor is non-phy */
4882 mutex_lock(&dev->struct_mutex);
4883 if (!dev_priv->info->cursor_needs_physical) {
4884 if (obj->tiling_mode) {
4885 DRM_ERROR("cursor cannot be tiled\n");
4886 ret = -EINVAL;
4887 goto fail_locked;
4888 }
4889
4890 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4891 if (ret) {
4892 DRM_ERROR("failed to move cursor bo into the GTT\n");
4893 goto fail_locked;
4894 }
4895
4896 ret = i915_gem_object_put_fence(obj);
4897 if (ret) {
4898 DRM_ERROR("failed to release fence for cursor");
4899 goto fail_unpin;
4900 }
4901
4902 addr = obj->gtt_offset;
4903 } else {
4904 int align = IS_I830(dev) ? 16 * 1024 : 256;
4905 ret = i915_gem_attach_phys_object(dev, obj,
4906 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4907 align);
4908 if (ret) {
4909 DRM_ERROR("failed to attach phys object\n");
4910 goto fail_locked;
4911 }
4912 addr = obj->phys_obj->handle->busaddr;
4913 }
4914
4915 if (IS_GEN2(dev))
4916 I915_WRITE(CURSIZE, (height << 12) | width);
4917
4918 finish:
4919 if (intel_crtc->cursor_bo) {
4920 if (dev_priv->info->cursor_needs_physical) {
4921 if (intel_crtc->cursor_bo != obj)
4922 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4923 } else
4924 i915_gem_object_unpin(intel_crtc->cursor_bo);
4925 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4926 }
4927
4928 mutex_unlock(&dev->struct_mutex);
4929
4930 intel_crtc->cursor_addr = addr;
4931 intel_crtc->cursor_bo = obj;
4932 intel_crtc->cursor_width = width;
4933 intel_crtc->cursor_height = height;
4934
4935 intel_crtc_update_cursor(crtc, true);
4936
4937 return 0;
4938 fail_unpin:
4939 i915_gem_object_unpin(obj);
4940 fail_locked:
4941 mutex_unlock(&dev->struct_mutex);
4942 fail:
4943 drm_gem_object_unreference_unlocked(&obj->base);
4944 return ret;
4945 }
4946
4947 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4948 {
4949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4950
4951 intel_crtc->cursor_x = x;
4952 intel_crtc->cursor_y = y;
4953
4954 intel_crtc_update_cursor(crtc, true);
4955
4956 return 0;
4957 }
4958
4959 /** Sets the color ramps on behalf of RandR */
4960 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4961 u16 blue, int regno)
4962 {
4963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964
4965 intel_crtc->lut_r[regno] = red >> 8;
4966 intel_crtc->lut_g[regno] = green >> 8;
4967 intel_crtc->lut_b[regno] = blue >> 8;
4968 }
4969
4970 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4971 u16 *blue, int regno)
4972 {
4973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974
4975 *red = intel_crtc->lut_r[regno] << 8;
4976 *green = intel_crtc->lut_g[regno] << 8;
4977 *blue = intel_crtc->lut_b[regno] << 8;
4978 }
4979
4980 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4981 u16 *blue, uint32_t start, uint32_t size)
4982 {
4983 int end = (start + size > 256) ? 256 : start + size, i;
4984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4985
4986 for (i = start; i < end; i++) {
4987 intel_crtc->lut_r[i] = red[i] >> 8;
4988 intel_crtc->lut_g[i] = green[i] >> 8;
4989 intel_crtc->lut_b[i] = blue[i] >> 8;
4990 }
4991
4992 intel_crtc_load_lut(crtc);
4993 }
4994
4995 /**
4996 * Get a pipe with a simple mode set on it for doing load-based monitor
4997 * detection.
4998 *
4999 * It will be up to the load-detect code to adjust the pipe as appropriate for
5000 * its requirements. The pipe will be connected to no other encoders.
5001 *
5002 * Currently this code will only succeed if there is a pipe with no encoders
5003 * configured for it. In the future, it could choose to temporarily disable
5004 * some outputs to free up a pipe for its use.
5005 *
5006 * \return crtc, or NULL if no pipes are available.
5007 */
5008
5009 /* VESA 640x480x72Hz mode to set on the pipe */
5010 static struct drm_display_mode load_detect_mode = {
5011 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5012 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5013 };
5014
5015 static struct drm_framebuffer *
5016 intel_framebuffer_create(struct drm_device *dev,
5017 struct drm_mode_fb_cmd2 *mode_cmd,
5018 struct drm_i915_gem_object *obj)
5019 {
5020 struct intel_framebuffer *intel_fb;
5021 int ret;
5022
5023 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5024 if (!intel_fb) {
5025 drm_gem_object_unreference_unlocked(&obj->base);
5026 return ERR_PTR(-ENOMEM);
5027 }
5028
5029 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5030 if (ret) {
5031 drm_gem_object_unreference_unlocked(&obj->base);
5032 kfree(intel_fb);
5033 return ERR_PTR(ret);
5034 }
5035
5036 return &intel_fb->base;
5037 }
5038
5039 static u32
5040 intel_framebuffer_pitch_for_width(int width, int bpp)
5041 {
5042 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5043 return ALIGN(pitch, 64);
5044 }
5045
5046 static u32
5047 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5048 {
5049 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5050 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5051 }
5052
5053 static struct drm_framebuffer *
5054 intel_framebuffer_create_for_mode(struct drm_device *dev,
5055 struct drm_display_mode *mode,
5056 int depth, int bpp)
5057 {
5058 struct drm_i915_gem_object *obj;
5059 struct drm_mode_fb_cmd2 mode_cmd;
5060
5061 obj = i915_gem_alloc_object(dev,
5062 intel_framebuffer_size_for_mode(mode, bpp));
5063 if (obj == NULL)
5064 return ERR_PTR(-ENOMEM);
5065
5066 mode_cmd.width = mode->hdisplay;
5067 mode_cmd.height = mode->vdisplay;
5068 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5069 bpp);
5070 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5071
5072 return intel_framebuffer_create(dev, &mode_cmd, obj);
5073 }
5074
5075 static struct drm_framebuffer *
5076 mode_fits_in_fbdev(struct drm_device *dev,
5077 struct drm_display_mode *mode)
5078 {
5079 struct drm_i915_private *dev_priv = dev->dev_private;
5080 struct drm_i915_gem_object *obj;
5081 struct drm_framebuffer *fb;
5082
5083 if (dev_priv->fbdev == NULL)
5084 return NULL;
5085
5086 obj = dev_priv->fbdev->ifb.obj;
5087 if (obj == NULL)
5088 return NULL;
5089
5090 fb = &dev_priv->fbdev->ifb.base;
5091 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5092 fb->bits_per_pixel))
5093 return NULL;
5094
5095 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5096 return NULL;
5097
5098 return fb;
5099 }
5100
5101 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5102 struct drm_connector *connector,
5103 struct drm_display_mode *mode,
5104 struct intel_load_detect_pipe *old)
5105 {
5106 struct intel_crtc *intel_crtc;
5107 struct drm_crtc *possible_crtc;
5108 struct drm_encoder *encoder = &intel_encoder->base;
5109 struct drm_crtc *crtc = NULL;
5110 struct drm_device *dev = encoder->dev;
5111 struct drm_framebuffer *old_fb;
5112 int i = -1;
5113
5114 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5115 connector->base.id, drm_get_connector_name(connector),
5116 encoder->base.id, drm_get_encoder_name(encoder));
5117
5118 /*
5119 * Algorithm gets a little messy:
5120 *
5121 * - if the connector already has an assigned crtc, use it (but make
5122 * sure it's on first)
5123 *
5124 * - try to find the first unused crtc that can drive this connector,
5125 * and use that if we find one
5126 */
5127
5128 /* See if we already have a CRTC for this connector */
5129 if (encoder->crtc) {
5130 crtc = encoder->crtc;
5131
5132 intel_crtc = to_intel_crtc(crtc);
5133 old->dpms_mode = intel_crtc->dpms_mode;
5134 old->load_detect_temp = false;
5135
5136 /* Make sure the crtc and connector are running */
5137 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5138 struct drm_encoder_helper_funcs *encoder_funcs;
5139 struct drm_crtc_helper_funcs *crtc_funcs;
5140
5141 crtc_funcs = crtc->helper_private;
5142 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5143
5144 encoder_funcs = encoder->helper_private;
5145 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5146 }
5147
5148 return true;
5149 }
5150
5151 /* Find an unused one (if possible) */
5152 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5153 i++;
5154 if (!(encoder->possible_crtcs & (1 << i)))
5155 continue;
5156 if (!possible_crtc->enabled) {
5157 crtc = possible_crtc;
5158 break;
5159 }
5160 }
5161
5162 /*
5163 * If we didn't find an unused CRTC, don't use any.
5164 */
5165 if (!crtc) {
5166 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5167 return false;
5168 }
5169
5170 encoder->crtc = crtc;
5171 connector->encoder = encoder;
5172
5173 intel_crtc = to_intel_crtc(crtc);
5174 old->dpms_mode = intel_crtc->dpms_mode;
5175 old->load_detect_temp = true;
5176 old->release_fb = NULL;
5177
5178 if (!mode)
5179 mode = &load_detect_mode;
5180
5181 old_fb = crtc->fb;
5182
5183 /* We need a framebuffer large enough to accommodate all accesses
5184 * that the plane may generate whilst we perform load detection.
5185 * We can not rely on the fbcon either being present (we get called
5186 * during its initialisation to detect all boot displays, or it may
5187 * not even exist) or that it is large enough to satisfy the
5188 * requested mode.
5189 */
5190 crtc->fb = mode_fits_in_fbdev(dev, mode);
5191 if (crtc->fb == NULL) {
5192 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5193 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5194 old->release_fb = crtc->fb;
5195 } else
5196 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5197 if (IS_ERR(crtc->fb)) {
5198 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5199 crtc->fb = old_fb;
5200 return false;
5201 }
5202
5203 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5204 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5205 if (old->release_fb)
5206 old->release_fb->funcs->destroy(old->release_fb);
5207 crtc->fb = old_fb;
5208 return false;
5209 }
5210
5211 /* let the connector get through one full cycle before testing */
5212 intel_wait_for_vblank(dev, intel_crtc->pipe);
5213
5214 return true;
5215 }
5216
5217 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5218 struct drm_connector *connector,
5219 struct intel_load_detect_pipe *old)
5220 {
5221 struct drm_encoder *encoder = &intel_encoder->base;
5222 struct drm_device *dev = encoder->dev;
5223 struct drm_crtc *crtc = encoder->crtc;
5224 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5225 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5226
5227 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5228 connector->base.id, drm_get_connector_name(connector),
5229 encoder->base.id, drm_get_encoder_name(encoder));
5230
5231 if (old->load_detect_temp) {
5232 connector->encoder = NULL;
5233 drm_helper_disable_unused_functions(dev);
5234
5235 if (old->release_fb)
5236 old->release_fb->funcs->destroy(old->release_fb);
5237
5238 return;
5239 }
5240
5241 /* Switch crtc and encoder back off if necessary */
5242 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5243 encoder_funcs->dpms(encoder, old->dpms_mode);
5244 crtc_funcs->dpms(crtc, old->dpms_mode);
5245 }
5246 }
5247
5248 /* Returns the clock of the currently programmed mode of the given pipe. */
5249 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5250 {
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5253 int pipe = intel_crtc->pipe;
5254 u32 dpll = I915_READ(DPLL(pipe));
5255 u32 fp;
5256 intel_clock_t clock;
5257
5258 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5259 fp = I915_READ(FP0(pipe));
5260 else
5261 fp = I915_READ(FP1(pipe));
5262
5263 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5264 if (IS_PINEVIEW(dev)) {
5265 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5266 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5267 } else {
5268 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5269 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5270 }
5271
5272 if (!IS_GEN2(dev)) {
5273 if (IS_PINEVIEW(dev))
5274 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5275 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5276 else
5277 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5278 DPLL_FPA01_P1_POST_DIV_SHIFT);
5279
5280 switch (dpll & DPLL_MODE_MASK) {
5281 case DPLLB_MODE_DAC_SERIAL:
5282 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5283 5 : 10;
5284 break;
5285 case DPLLB_MODE_LVDS:
5286 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5287 7 : 14;
5288 break;
5289 default:
5290 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5291 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5292 return 0;
5293 }
5294
5295 /* XXX: Handle the 100Mhz refclk */
5296 intel_clock(dev, 96000, &clock);
5297 } else {
5298 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5299
5300 if (is_lvds) {
5301 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5302 DPLL_FPA01_P1_POST_DIV_SHIFT);
5303 clock.p2 = 14;
5304
5305 if ((dpll & PLL_REF_INPUT_MASK) ==
5306 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5307 /* XXX: might not be 66MHz */
5308 intel_clock(dev, 66000, &clock);
5309 } else
5310 intel_clock(dev, 48000, &clock);
5311 } else {
5312 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5313 clock.p1 = 2;
5314 else {
5315 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5316 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5317 }
5318 if (dpll & PLL_P2_DIVIDE_BY_4)
5319 clock.p2 = 4;
5320 else
5321 clock.p2 = 2;
5322
5323 intel_clock(dev, 48000, &clock);
5324 }
5325 }
5326
5327 /* XXX: It would be nice to validate the clocks, but we can't reuse
5328 * i830PllIsValid() because it relies on the xf86_config connector
5329 * configuration being accurate, which it isn't necessarily.
5330 */
5331
5332 return clock.dot;
5333 }
5334
5335 /** Returns the currently programmed mode of the given pipe. */
5336 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5337 struct drm_crtc *crtc)
5338 {
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5341 int pipe = intel_crtc->pipe;
5342 struct drm_display_mode *mode;
5343 int htot = I915_READ(HTOTAL(pipe));
5344 int hsync = I915_READ(HSYNC(pipe));
5345 int vtot = I915_READ(VTOTAL(pipe));
5346 int vsync = I915_READ(VSYNC(pipe));
5347
5348 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5349 if (!mode)
5350 return NULL;
5351
5352 mode->clock = intel_crtc_clock_get(dev, crtc);
5353 mode->hdisplay = (htot & 0xffff) + 1;
5354 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5355 mode->hsync_start = (hsync & 0xffff) + 1;
5356 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5357 mode->vdisplay = (vtot & 0xffff) + 1;
5358 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5359 mode->vsync_start = (vsync & 0xffff) + 1;
5360 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5361
5362 drm_mode_set_name(mode);
5363 drm_mode_set_crtcinfo(mode, 0);
5364
5365 return mode;
5366 }
5367
5368 #define GPU_IDLE_TIMEOUT 500 /* ms */
5369
5370 /* When this timer fires, we've been idle for awhile */
5371 static void intel_gpu_idle_timer(unsigned long arg)
5372 {
5373 struct drm_device *dev = (struct drm_device *)arg;
5374 drm_i915_private_t *dev_priv = dev->dev_private;
5375
5376 if (!list_empty(&dev_priv->mm.active_list)) {
5377 /* Still processing requests, so just re-arm the timer. */
5378 mod_timer(&dev_priv->idle_timer, jiffies +
5379 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5380 return;
5381 }
5382
5383 dev_priv->busy = false;
5384 queue_work(dev_priv->wq, &dev_priv->idle_work);
5385 }
5386
5387 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5388
5389 static void intel_crtc_idle_timer(unsigned long arg)
5390 {
5391 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5392 struct drm_crtc *crtc = &intel_crtc->base;
5393 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5394 struct intel_framebuffer *intel_fb;
5395
5396 intel_fb = to_intel_framebuffer(crtc->fb);
5397 if (intel_fb && intel_fb->obj->active) {
5398 /* The framebuffer is still being accessed by the GPU. */
5399 mod_timer(&intel_crtc->idle_timer, jiffies +
5400 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5401 return;
5402 }
5403
5404 intel_crtc->busy = false;
5405 queue_work(dev_priv->wq, &dev_priv->idle_work);
5406 }
5407
5408 static void intel_increase_pllclock(struct drm_crtc *crtc)
5409 {
5410 struct drm_device *dev = crtc->dev;
5411 drm_i915_private_t *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 int pipe = intel_crtc->pipe;
5414 int dpll_reg = DPLL(pipe);
5415 int dpll;
5416
5417 if (HAS_PCH_SPLIT(dev))
5418 return;
5419
5420 if (!dev_priv->lvds_downclock_avail)
5421 return;
5422
5423 dpll = I915_READ(dpll_reg);
5424 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5425 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5426
5427 assert_panel_unlocked(dev_priv, pipe);
5428
5429 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5430 I915_WRITE(dpll_reg, dpll);
5431 intel_wait_for_vblank(dev, pipe);
5432
5433 dpll = I915_READ(dpll_reg);
5434 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5435 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5436 }
5437
5438 /* Schedule downclock */
5439 mod_timer(&intel_crtc->idle_timer, jiffies +
5440 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5441 }
5442
5443 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5444 {
5445 struct drm_device *dev = crtc->dev;
5446 drm_i915_private_t *dev_priv = dev->dev_private;
5447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5448 int pipe = intel_crtc->pipe;
5449 int dpll_reg = DPLL(pipe);
5450 int dpll = I915_READ(dpll_reg);
5451
5452 if (HAS_PCH_SPLIT(dev))
5453 return;
5454
5455 if (!dev_priv->lvds_downclock_avail)
5456 return;
5457
5458 /*
5459 * Since this is called by a timer, we should never get here in
5460 * the manual case.
5461 */
5462 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5463 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5464
5465 assert_panel_unlocked(dev_priv, pipe);
5466
5467 dpll |= DISPLAY_RATE_SELECT_FPA1;
5468 I915_WRITE(dpll_reg, dpll);
5469 intel_wait_for_vblank(dev, pipe);
5470 dpll = I915_READ(dpll_reg);
5471 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5472 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5473 }
5474
5475 }
5476
5477 /**
5478 * intel_idle_update - adjust clocks for idleness
5479 * @work: work struct
5480 *
5481 * Either the GPU or display (or both) went idle. Check the busy status
5482 * here and adjust the CRTC and GPU clocks as necessary.
5483 */
5484 static void intel_idle_update(struct work_struct *work)
5485 {
5486 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5487 idle_work);
5488 struct drm_device *dev = dev_priv->dev;
5489 struct drm_crtc *crtc;
5490 struct intel_crtc *intel_crtc;
5491
5492 if (!i915_powersave)
5493 return;
5494
5495 mutex_lock(&dev->struct_mutex);
5496
5497 i915_update_gfx_val(dev_priv);
5498
5499 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5500 /* Skip inactive CRTCs */
5501 if (!crtc->fb)
5502 continue;
5503
5504 intel_crtc = to_intel_crtc(crtc);
5505 if (!intel_crtc->busy)
5506 intel_decrease_pllclock(crtc);
5507 }
5508
5509
5510 mutex_unlock(&dev->struct_mutex);
5511 }
5512
5513 /**
5514 * intel_mark_busy - mark the GPU and possibly the display busy
5515 * @dev: drm device
5516 * @obj: object we're operating on
5517 *
5518 * Callers can use this function to indicate that the GPU is busy processing
5519 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5520 * buffer), we'll also mark the display as busy, so we know to increase its
5521 * clock frequency.
5522 */
5523 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5524 {
5525 drm_i915_private_t *dev_priv = dev->dev_private;
5526 struct drm_crtc *crtc = NULL;
5527 struct intel_framebuffer *intel_fb;
5528 struct intel_crtc *intel_crtc;
5529
5530 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5531 return;
5532
5533 if (!dev_priv->busy)
5534 dev_priv->busy = true;
5535 else
5536 mod_timer(&dev_priv->idle_timer, jiffies +
5537 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5538
5539 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5540 if (!crtc->fb)
5541 continue;
5542
5543 intel_crtc = to_intel_crtc(crtc);
5544 intel_fb = to_intel_framebuffer(crtc->fb);
5545 if (intel_fb->obj == obj) {
5546 if (!intel_crtc->busy) {
5547 /* Non-busy -> busy, upclock */
5548 intel_increase_pllclock(crtc);
5549 intel_crtc->busy = true;
5550 } else {
5551 /* Busy -> busy, put off timer */
5552 mod_timer(&intel_crtc->idle_timer, jiffies +
5553 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5554 }
5555 }
5556 }
5557 }
5558
5559 static void intel_crtc_destroy(struct drm_crtc *crtc)
5560 {
5561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5562 struct drm_device *dev = crtc->dev;
5563 struct intel_unpin_work *work;
5564 unsigned long flags;
5565
5566 spin_lock_irqsave(&dev->event_lock, flags);
5567 work = intel_crtc->unpin_work;
5568 intel_crtc->unpin_work = NULL;
5569 spin_unlock_irqrestore(&dev->event_lock, flags);
5570
5571 if (work) {
5572 cancel_work_sync(&work->work);
5573 kfree(work);
5574 }
5575
5576 drm_crtc_cleanup(crtc);
5577
5578 kfree(intel_crtc);
5579 }
5580
5581 static void intel_unpin_work_fn(struct work_struct *__work)
5582 {
5583 struct intel_unpin_work *work =
5584 container_of(__work, struct intel_unpin_work, work);
5585
5586 mutex_lock(&work->dev->struct_mutex);
5587 intel_unpin_fb_obj(work->old_fb_obj);
5588 drm_gem_object_unreference(&work->pending_flip_obj->base);
5589 drm_gem_object_unreference(&work->old_fb_obj->base);
5590
5591 intel_update_fbc(work->dev);
5592 mutex_unlock(&work->dev->struct_mutex);
5593 kfree(work);
5594 }
5595
5596 static void do_intel_finish_page_flip(struct drm_device *dev,
5597 struct drm_crtc *crtc)
5598 {
5599 drm_i915_private_t *dev_priv = dev->dev_private;
5600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601 struct intel_unpin_work *work;
5602 struct drm_i915_gem_object *obj;
5603 struct drm_pending_vblank_event *e;
5604 struct timeval tnow, tvbl;
5605 unsigned long flags;
5606
5607 /* Ignore early vblank irqs */
5608 if (intel_crtc == NULL)
5609 return;
5610
5611 do_gettimeofday(&tnow);
5612
5613 spin_lock_irqsave(&dev->event_lock, flags);
5614 work = intel_crtc->unpin_work;
5615 if (work == NULL || !work->pending) {
5616 spin_unlock_irqrestore(&dev->event_lock, flags);
5617 return;
5618 }
5619
5620 intel_crtc->unpin_work = NULL;
5621
5622 if (work->event) {
5623 e = work->event;
5624 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5625
5626 /* Called before vblank count and timestamps have
5627 * been updated for the vblank interval of flip
5628 * completion? Need to increment vblank count and
5629 * add one videorefresh duration to returned timestamp
5630 * to account for this. We assume this happened if we
5631 * get called over 0.9 frame durations after the last
5632 * timestamped vblank.
5633 *
5634 * This calculation can not be used with vrefresh rates
5635 * below 5Hz (10Hz to be on the safe side) without
5636 * promoting to 64 integers.
5637 */
5638 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5639 9 * crtc->framedur_ns) {
5640 e->event.sequence++;
5641 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5642 crtc->framedur_ns);
5643 }
5644
5645 e->event.tv_sec = tvbl.tv_sec;
5646 e->event.tv_usec = tvbl.tv_usec;
5647
5648 list_add_tail(&e->base.link,
5649 &e->base.file_priv->event_list);
5650 wake_up_interruptible(&e->base.file_priv->event_wait);
5651 }
5652
5653 drm_vblank_put(dev, intel_crtc->pipe);
5654
5655 spin_unlock_irqrestore(&dev->event_lock, flags);
5656
5657 obj = work->old_fb_obj;
5658
5659 atomic_clear_mask(1 << intel_crtc->plane,
5660 &obj->pending_flip.counter);
5661 if (atomic_read(&obj->pending_flip) == 0)
5662 wake_up(&dev_priv->pending_flip_queue);
5663
5664 schedule_work(&work->work);
5665
5666 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5667 }
5668
5669 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5670 {
5671 drm_i915_private_t *dev_priv = dev->dev_private;
5672 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5673
5674 do_intel_finish_page_flip(dev, crtc);
5675 }
5676
5677 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5678 {
5679 drm_i915_private_t *dev_priv = dev->dev_private;
5680 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5681
5682 do_intel_finish_page_flip(dev, crtc);
5683 }
5684
5685 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5686 {
5687 drm_i915_private_t *dev_priv = dev->dev_private;
5688 struct intel_crtc *intel_crtc =
5689 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5690 unsigned long flags;
5691
5692 spin_lock_irqsave(&dev->event_lock, flags);
5693 if (intel_crtc->unpin_work) {
5694 if ((++intel_crtc->unpin_work->pending) > 1)
5695 DRM_ERROR("Prepared flip multiple times\n");
5696 } else {
5697 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5698 }
5699 spin_unlock_irqrestore(&dev->event_lock, flags);
5700 }
5701
5702 static int intel_gen2_queue_flip(struct drm_device *dev,
5703 struct drm_crtc *crtc,
5704 struct drm_framebuffer *fb,
5705 struct drm_i915_gem_object *obj)
5706 {
5707 struct drm_i915_private *dev_priv = dev->dev_private;
5708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5709 unsigned long offset;
5710 u32 flip_mask;
5711 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5712 int ret;
5713
5714 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5715 if (ret)
5716 goto err;
5717
5718 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5719 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5720
5721 ret = intel_ring_begin(ring, 6);
5722 if (ret)
5723 goto err_unpin;
5724
5725 /* Can't queue multiple flips, so wait for the previous
5726 * one to finish before executing the next.
5727 */
5728 if (intel_crtc->plane)
5729 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5730 else
5731 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5732 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5733 intel_ring_emit(ring, MI_NOOP);
5734 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5735 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5736 intel_ring_emit(ring, fb->pitches[0]);
5737 intel_ring_emit(ring, obj->gtt_offset + offset);
5738 intel_ring_emit(ring, 0); /* aux display base address, unused */
5739 intel_ring_advance(ring);
5740 return 0;
5741
5742 err_unpin:
5743 intel_unpin_fb_obj(obj);
5744 err:
5745 return ret;
5746 }
5747
5748 static int intel_gen3_queue_flip(struct drm_device *dev,
5749 struct drm_crtc *crtc,
5750 struct drm_framebuffer *fb,
5751 struct drm_i915_gem_object *obj)
5752 {
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5755 unsigned long offset;
5756 u32 flip_mask;
5757 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5758 int ret;
5759
5760 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5761 if (ret)
5762 goto err;
5763
5764 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5765 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5766
5767 ret = intel_ring_begin(ring, 6);
5768 if (ret)
5769 goto err_unpin;
5770
5771 if (intel_crtc->plane)
5772 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5773 else
5774 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5775 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5776 intel_ring_emit(ring, MI_NOOP);
5777 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
5778 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5779 intel_ring_emit(ring, fb->pitches[0]);
5780 intel_ring_emit(ring, obj->gtt_offset + offset);
5781 intel_ring_emit(ring, MI_NOOP);
5782
5783 intel_ring_advance(ring);
5784 return 0;
5785
5786 err_unpin:
5787 intel_unpin_fb_obj(obj);
5788 err:
5789 return ret;
5790 }
5791
5792 static int intel_gen4_queue_flip(struct drm_device *dev,
5793 struct drm_crtc *crtc,
5794 struct drm_framebuffer *fb,
5795 struct drm_i915_gem_object *obj)
5796 {
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799 uint32_t pf, pipesrc;
5800 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5801 int ret;
5802
5803 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5804 if (ret)
5805 goto err;
5806
5807 ret = intel_ring_begin(ring, 4);
5808 if (ret)
5809 goto err_unpin;
5810
5811 /* i965+ uses the linear or tiled offsets from the
5812 * Display Registers (which do not change across a page-flip)
5813 * so we need only reprogram the base address.
5814 */
5815 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5816 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5817 intel_ring_emit(ring, fb->pitches[0]);
5818 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
5819
5820 /* XXX Enabling the panel-fitter across page-flip is so far
5821 * untested on non-native modes, so ignore it for now.
5822 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5823 */
5824 pf = 0;
5825 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5826 intel_ring_emit(ring, pf | pipesrc);
5827 intel_ring_advance(ring);
5828 return 0;
5829
5830 err_unpin:
5831 intel_unpin_fb_obj(obj);
5832 err:
5833 return ret;
5834 }
5835
5836 static int intel_gen6_queue_flip(struct drm_device *dev,
5837 struct drm_crtc *crtc,
5838 struct drm_framebuffer *fb,
5839 struct drm_i915_gem_object *obj)
5840 {
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5843 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5844 uint32_t pf, pipesrc;
5845 int ret;
5846
5847 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5848 if (ret)
5849 goto err;
5850
5851 ret = intel_ring_begin(ring, 4);
5852 if (ret)
5853 goto err_unpin;
5854
5855 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5856 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5857 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
5858 intel_ring_emit(ring, obj->gtt_offset);
5859
5860 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5861 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5862 intel_ring_emit(ring, pf | pipesrc);
5863 intel_ring_advance(ring);
5864 return 0;
5865
5866 err_unpin:
5867 intel_unpin_fb_obj(obj);
5868 err:
5869 return ret;
5870 }
5871
5872 /*
5873 * On gen7 we currently use the blit ring because (in early silicon at least)
5874 * the render ring doesn't give us interrpts for page flip completion, which
5875 * means clients will hang after the first flip is queued. Fortunately the
5876 * blit ring generates interrupts properly, so use it instead.
5877 */
5878 static int intel_gen7_queue_flip(struct drm_device *dev,
5879 struct drm_crtc *crtc,
5880 struct drm_framebuffer *fb,
5881 struct drm_i915_gem_object *obj)
5882 {
5883 struct drm_i915_private *dev_priv = dev->dev_private;
5884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5886 int ret;
5887
5888 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5889 if (ret)
5890 goto err;
5891
5892 ret = intel_ring_begin(ring, 4);
5893 if (ret)
5894 goto err_unpin;
5895
5896 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5897 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5898 intel_ring_emit(ring, (obj->gtt_offset));
5899 intel_ring_emit(ring, (MI_NOOP));
5900 intel_ring_advance(ring);
5901 return 0;
5902
5903 err_unpin:
5904 intel_unpin_fb_obj(obj);
5905 err:
5906 return ret;
5907 }
5908
5909 static int intel_default_queue_flip(struct drm_device *dev,
5910 struct drm_crtc *crtc,
5911 struct drm_framebuffer *fb,
5912 struct drm_i915_gem_object *obj)
5913 {
5914 return -ENODEV;
5915 }
5916
5917 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5918 struct drm_framebuffer *fb,
5919 struct drm_pending_vblank_event *event)
5920 {
5921 struct drm_device *dev = crtc->dev;
5922 struct drm_i915_private *dev_priv = dev->dev_private;
5923 struct intel_framebuffer *intel_fb;
5924 struct drm_i915_gem_object *obj;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5926 struct intel_unpin_work *work;
5927 unsigned long flags;
5928 int ret;
5929
5930 work = kzalloc(sizeof *work, GFP_KERNEL);
5931 if (work == NULL)
5932 return -ENOMEM;
5933
5934 work->event = event;
5935 work->dev = crtc->dev;
5936 intel_fb = to_intel_framebuffer(crtc->fb);
5937 work->old_fb_obj = intel_fb->obj;
5938 INIT_WORK(&work->work, intel_unpin_work_fn);
5939
5940 ret = drm_vblank_get(dev, intel_crtc->pipe);
5941 if (ret)
5942 goto free_work;
5943
5944 /* We borrow the event spin lock for protecting unpin_work */
5945 spin_lock_irqsave(&dev->event_lock, flags);
5946 if (intel_crtc->unpin_work) {
5947 spin_unlock_irqrestore(&dev->event_lock, flags);
5948 kfree(work);
5949 drm_vblank_put(dev, intel_crtc->pipe);
5950
5951 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5952 return -EBUSY;
5953 }
5954 intel_crtc->unpin_work = work;
5955 spin_unlock_irqrestore(&dev->event_lock, flags);
5956
5957 intel_fb = to_intel_framebuffer(fb);
5958 obj = intel_fb->obj;
5959
5960 mutex_lock(&dev->struct_mutex);
5961
5962 /* Reference the objects for the scheduled work. */
5963 drm_gem_object_reference(&work->old_fb_obj->base);
5964 drm_gem_object_reference(&obj->base);
5965
5966 crtc->fb = fb;
5967
5968 work->pending_flip_obj = obj;
5969
5970 work->enable_stall_check = true;
5971
5972 /* Block clients from rendering to the new back buffer until
5973 * the flip occurs and the object is no longer visible.
5974 */
5975 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5976
5977 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5978 if (ret)
5979 goto cleanup_pending;
5980
5981 intel_disable_fbc(dev);
5982 mutex_unlock(&dev->struct_mutex);
5983
5984 trace_i915_flip_request(intel_crtc->plane, obj);
5985
5986 return 0;
5987
5988 cleanup_pending:
5989 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5990 drm_gem_object_unreference(&work->old_fb_obj->base);
5991 drm_gem_object_unreference(&obj->base);
5992 mutex_unlock(&dev->struct_mutex);
5993
5994 spin_lock_irqsave(&dev->event_lock, flags);
5995 intel_crtc->unpin_work = NULL;
5996 spin_unlock_irqrestore(&dev->event_lock, flags);
5997
5998 drm_vblank_put(dev, intel_crtc->pipe);
5999 free_work:
6000 kfree(work);
6001
6002 return ret;
6003 }
6004
6005 static void intel_sanitize_modesetting(struct drm_device *dev,
6006 int pipe, int plane)
6007 {
6008 struct drm_i915_private *dev_priv = dev->dev_private;
6009 u32 reg, val;
6010
6011 /* Clear any frame start delays used for debugging left by the BIOS */
6012 for_each_pipe(pipe) {
6013 reg = PIPECONF(pipe);
6014 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6015 }
6016
6017 if (HAS_PCH_SPLIT(dev))
6018 return;
6019
6020 /* Who knows what state these registers were left in by the BIOS or
6021 * grub?
6022 *
6023 * If we leave the registers in a conflicting state (e.g. with the
6024 * display plane reading from the other pipe than the one we intend
6025 * to use) then when we attempt to teardown the active mode, we will
6026 * not disable the pipes and planes in the correct order -- leaving
6027 * a plane reading from a disabled pipe and possibly leading to
6028 * undefined behaviour.
6029 */
6030
6031 reg = DSPCNTR(plane);
6032 val = I915_READ(reg);
6033
6034 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6035 return;
6036 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6037 return;
6038
6039 /* This display plane is active and attached to the other CPU pipe. */
6040 pipe = !pipe;
6041
6042 /* Disable the plane and wait for it to stop reading from the pipe. */
6043 intel_disable_plane(dev_priv, plane, pipe);
6044 intel_disable_pipe(dev_priv, pipe);
6045 }
6046
6047 static void intel_crtc_reset(struct drm_crtc *crtc)
6048 {
6049 struct drm_device *dev = crtc->dev;
6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6051
6052 /* Reset flags back to the 'unknown' status so that they
6053 * will be correctly set on the initial modeset.
6054 */
6055 intel_crtc->dpms_mode = -1;
6056
6057 /* We need to fix up any BIOS configuration that conflicts with
6058 * our expectations.
6059 */
6060 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6061 }
6062
6063 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6064 .dpms = intel_crtc_dpms,
6065 .mode_fixup = intel_crtc_mode_fixup,
6066 .mode_set = intel_crtc_mode_set,
6067 .mode_set_base = intel_pipe_set_base,
6068 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6069 .load_lut = intel_crtc_load_lut,
6070 .disable = intel_crtc_disable,
6071 };
6072
6073 static const struct drm_crtc_funcs intel_crtc_funcs = {
6074 .reset = intel_crtc_reset,
6075 .cursor_set = intel_crtc_cursor_set,
6076 .cursor_move = intel_crtc_cursor_move,
6077 .gamma_set = intel_crtc_gamma_set,
6078 .set_config = drm_crtc_helper_set_config,
6079 .destroy = intel_crtc_destroy,
6080 .page_flip = intel_crtc_page_flip,
6081 };
6082
6083 static void intel_pch_pll_init(struct drm_device *dev)
6084 {
6085 drm_i915_private_t *dev_priv = dev->dev_private;
6086 int i;
6087
6088 if (dev_priv->num_pch_pll == 0) {
6089 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6090 return;
6091 }
6092
6093 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6094 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6095 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6096 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6097 }
6098 }
6099
6100 static void intel_crtc_init(struct drm_device *dev, int pipe)
6101 {
6102 drm_i915_private_t *dev_priv = dev->dev_private;
6103 struct intel_crtc *intel_crtc;
6104 int i;
6105
6106 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6107 if (intel_crtc == NULL)
6108 return;
6109
6110 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6111
6112 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6113 for (i = 0; i < 256; i++) {
6114 intel_crtc->lut_r[i] = i;
6115 intel_crtc->lut_g[i] = i;
6116 intel_crtc->lut_b[i] = i;
6117 }
6118
6119 /* Swap pipes & planes for FBC on pre-965 */
6120 intel_crtc->pipe = pipe;
6121 intel_crtc->plane = pipe;
6122 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6123 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6124 intel_crtc->plane = !pipe;
6125 }
6126
6127 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6128 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6129 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6130 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6131
6132 intel_crtc_reset(&intel_crtc->base);
6133 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6134 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6135
6136 if (HAS_PCH_SPLIT(dev)) {
6137 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6138 intel_helper_funcs.commit = ironlake_crtc_commit;
6139 } else {
6140 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6141 intel_helper_funcs.commit = i9xx_crtc_commit;
6142 }
6143
6144 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6145
6146 intel_crtc->busy = false;
6147
6148 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6149 (unsigned long)intel_crtc);
6150 }
6151
6152 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6153 struct drm_file *file)
6154 {
6155 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6156 struct drm_mode_object *drmmode_obj;
6157 struct intel_crtc *crtc;
6158
6159 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6160 return -ENODEV;
6161
6162 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6163 DRM_MODE_OBJECT_CRTC);
6164
6165 if (!drmmode_obj) {
6166 DRM_ERROR("no such CRTC id\n");
6167 return -EINVAL;
6168 }
6169
6170 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6171 pipe_from_crtc_id->pipe = crtc->pipe;
6172
6173 return 0;
6174 }
6175
6176 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6177 {
6178 struct intel_encoder *encoder;
6179 int index_mask = 0;
6180 int entry = 0;
6181
6182 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6183 if (type_mask & encoder->clone_mask)
6184 index_mask |= (1 << entry);
6185 entry++;
6186 }
6187
6188 return index_mask;
6189 }
6190
6191 static bool has_edp_a(struct drm_device *dev)
6192 {
6193 struct drm_i915_private *dev_priv = dev->dev_private;
6194
6195 if (!IS_MOBILE(dev))
6196 return false;
6197
6198 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6199 return false;
6200
6201 if (IS_GEN5(dev) &&
6202 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6203 return false;
6204
6205 return true;
6206 }
6207
6208 static void intel_setup_outputs(struct drm_device *dev)
6209 {
6210 struct drm_i915_private *dev_priv = dev->dev_private;
6211 struct intel_encoder *encoder;
6212 bool dpd_is_edp = false;
6213 bool has_lvds;
6214
6215 has_lvds = intel_lvds_init(dev);
6216 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6217 /* disable the panel fitter on everything but LVDS */
6218 I915_WRITE(PFIT_CONTROL, 0);
6219 }
6220
6221 if (HAS_PCH_SPLIT(dev)) {
6222 dpd_is_edp = intel_dpd_is_edp(dev);
6223
6224 if (has_edp_a(dev))
6225 intel_dp_init(dev, DP_A);
6226
6227 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6228 intel_dp_init(dev, PCH_DP_D);
6229 }
6230
6231 intel_crt_init(dev);
6232
6233 if (HAS_PCH_SPLIT(dev)) {
6234 int found;
6235
6236 if (I915_READ(HDMIB) & PORT_DETECTED) {
6237 /* PCH SDVOB multiplex with HDMIB */
6238 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6239 if (!found)
6240 intel_hdmi_init(dev, HDMIB);
6241 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6242 intel_dp_init(dev, PCH_DP_B);
6243 }
6244
6245 if (I915_READ(HDMIC) & PORT_DETECTED)
6246 intel_hdmi_init(dev, HDMIC);
6247
6248 if (I915_READ(HDMID) & PORT_DETECTED)
6249 intel_hdmi_init(dev, HDMID);
6250
6251 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6252 intel_dp_init(dev, PCH_DP_C);
6253
6254 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6255 intel_dp_init(dev, PCH_DP_D);
6256
6257 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6258 bool found = false;
6259
6260 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6261 DRM_DEBUG_KMS("probing SDVOB\n");
6262 found = intel_sdvo_init(dev, SDVOB, true);
6263 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6264 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6265 intel_hdmi_init(dev, SDVOB);
6266 }
6267
6268 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6269 DRM_DEBUG_KMS("probing DP_B\n");
6270 intel_dp_init(dev, DP_B);
6271 }
6272 }
6273
6274 /* Before G4X SDVOC doesn't have its own detect register */
6275
6276 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6277 DRM_DEBUG_KMS("probing SDVOC\n");
6278 found = intel_sdvo_init(dev, SDVOC, false);
6279 }
6280
6281 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6282
6283 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6284 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6285 intel_hdmi_init(dev, SDVOC);
6286 }
6287 if (SUPPORTS_INTEGRATED_DP(dev)) {
6288 DRM_DEBUG_KMS("probing DP_C\n");
6289 intel_dp_init(dev, DP_C);
6290 }
6291 }
6292
6293 if (SUPPORTS_INTEGRATED_DP(dev) &&
6294 (I915_READ(DP_D) & DP_DETECTED)) {
6295 DRM_DEBUG_KMS("probing DP_D\n");
6296 intel_dp_init(dev, DP_D);
6297 }
6298 } else if (IS_GEN2(dev))
6299 intel_dvo_init(dev);
6300
6301 if (SUPPORTS_TV(dev))
6302 intel_tv_init(dev);
6303
6304 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6305 encoder->base.possible_crtcs = encoder->crtc_mask;
6306 encoder->base.possible_clones =
6307 intel_encoder_clones(dev, encoder->clone_mask);
6308 }
6309
6310 /* disable all the possible outputs/crtcs before entering KMS mode */
6311 drm_helper_disable_unused_functions(dev);
6312
6313 if (HAS_PCH_SPLIT(dev))
6314 ironlake_init_pch_refclk(dev);
6315 }
6316
6317 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6318 {
6319 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6320
6321 drm_framebuffer_cleanup(fb);
6322 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6323
6324 kfree(intel_fb);
6325 }
6326
6327 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6328 struct drm_file *file,
6329 unsigned int *handle)
6330 {
6331 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6332 struct drm_i915_gem_object *obj = intel_fb->obj;
6333
6334 return drm_gem_handle_create(file, &obj->base, handle);
6335 }
6336
6337 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6338 .destroy = intel_user_framebuffer_destroy,
6339 .create_handle = intel_user_framebuffer_create_handle,
6340 };
6341
6342 int intel_framebuffer_init(struct drm_device *dev,
6343 struct intel_framebuffer *intel_fb,
6344 struct drm_mode_fb_cmd2 *mode_cmd,
6345 struct drm_i915_gem_object *obj)
6346 {
6347 int ret;
6348
6349 if (obj->tiling_mode == I915_TILING_Y)
6350 return -EINVAL;
6351
6352 if (mode_cmd->pitches[0] & 63)
6353 return -EINVAL;
6354
6355 switch (mode_cmd->pixel_format) {
6356 case DRM_FORMAT_RGB332:
6357 case DRM_FORMAT_RGB565:
6358 case DRM_FORMAT_XRGB8888:
6359 case DRM_FORMAT_XBGR8888:
6360 case DRM_FORMAT_ARGB8888:
6361 case DRM_FORMAT_XRGB2101010:
6362 case DRM_FORMAT_ARGB2101010:
6363 /* RGB formats are common across chipsets */
6364 break;
6365 case DRM_FORMAT_YUYV:
6366 case DRM_FORMAT_UYVY:
6367 case DRM_FORMAT_YVYU:
6368 case DRM_FORMAT_VYUY:
6369 break;
6370 default:
6371 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6372 mode_cmd->pixel_format);
6373 return -EINVAL;
6374 }
6375
6376 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6377 if (ret) {
6378 DRM_ERROR("framebuffer init failed %d\n", ret);
6379 return ret;
6380 }
6381
6382 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6383 intel_fb->obj = obj;
6384 return 0;
6385 }
6386
6387 static struct drm_framebuffer *
6388 intel_user_framebuffer_create(struct drm_device *dev,
6389 struct drm_file *filp,
6390 struct drm_mode_fb_cmd2 *mode_cmd)
6391 {
6392 struct drm_i915_gem_object *obj;
6393
6394 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6395 mode_cmd->handles[0]));
6396 if (&obj->base == NULL)
6397 return ERR_PTR(-ENOENT);
6398
6399 return intel_framebuffer_create(dev, mode_cmd, obj);
6400 }
6401
6402 static const struct drm_mode_config_funcs intel_mode_funcs = {
6403 .fb_create = intel_user_framebuffer_create,
6404 .output_poll_changed = intel_fb_output_poll_changed,
6405 };
6406
6407 /* Set up chip specific display functions */
6408 static void intel_init_display(struct drm_device *dev)
6409 {
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411
6412 /* We always want a DPMS function */
6413 if (HAS_PCH_SPLIT(dev)) {
6414 dev_priv->display.dpms = ironlake_crtc_dpms;
6415 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6416 dev_priv->display.off = ironlake_crtc_off;
6417 dev_priv->display.update_plane = ironlake_update_plane;
6418 } else {
6419 dev_priv->display.dpms = i9xx_crtc_dpms;
6420 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6421 dev_priv->display.off = i9xx_crtc_off;
6422 dev_priv->display.update_plane = i9xx_update_plane;
6423 }
6424
6425 /* Returns the core display clock speed */
6426 if (IS_VALLEYVIEW(dev))
6427 dev_priv->display.get_display_clock_speed =
6428 valleyview_get_display_clock_speed;
6429 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6430 dev_priv->display.get_display_clock_speed =
6431 i945_get_display_clock_speed;
6432 else if (IS_I915G(dev))
6433 dev_priv->display.get_display_clock_speed =
6434 i915_get_display_clock_speed;
6435 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6436 dev_priv->display.get_display_clock_speed =
6437 i9xx_misc_get_display_clock_speed;
6438 else if (IS_I915GM(dev))
6439 dev_priv->display.get_display_clock_speed =
6440 i915gm_get_display_clock_speed;
6441 else if (IS_I865G(dev))
6442 dev_priv->display.get_display_clock_speed =
6443 i865_get_display_clock_speed;
6444 else if (IS_I85X(dev))
6445 dev_priv->display.get_display_clock_speed =
6446 i855_get_display_clock_speed;
6447 else /* 852, 830 */
6448 dev_priv->display.get_display_clock_speed =
6449 i830_get_display_clock_speed;
6450
6451 if (HAS_PCH_SPLIT(dev)) {
6452 if (IS_GEN5(dev)) {
6453 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6454 dev_priv->display.write_eld = ironlake_write_eld;
6455 } else if (IS_GEN6(dev)) {
6456 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6457 dev_priv->display.write_eld = ironlake_write_eld;
6458 } else if (IS_IVYBRIDGE(dev)) {
6459 /* FIXME: detect B0+ stepping and use auto training */
6460 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6461 dev_priv->display.write_eld = ironlake_write_eld;
6462 } else
6463 dev_priv->display.update_wm = NULL;
6464 } else if (IS_VALLEYVIEW(dev)) {
6465 dev_priv->display.force_wake_get = vlv_force_wake_get;
6466 dev_priv->display.force_wake_put = vlv_force_wake_put;
6467 } else if (IS_G4X(dev)) {
6468 dev_priv->display.write_eld = g4x_write_eld;
6469 }
6470
6471 /* Default just returns -ENODEV to indicate unsupported */
6472 dev_priv->display.queue_flip = intel_default_queue_flip;
6473
6474 switch (INTEL_INFO(dev)->gen) {
6475 case 2:
6476 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6477 break;
6478
6479 case 3:
6480 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6481 break;
6482
6483 case 4:
6484 case 5:
6485 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6486 break;
6487
6488 case 6:
6489 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6490 break;
6491 case 7:
6492 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6493 break;
6494 }
6495 }
6496
6497 /*
6498 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6499 * resume, or other times. This quirk makes sure that's the case for
6500 * affected systems.
6501 */
6502 static void quirk_pipea_force(struct drm_device *dev)
6503 {
6504 struct drm_i915_private *dev_priv = dev->dev_private;
6505
6506 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6507 DRM_INFO("applying pipe a force quirk\n");
6508 }
6509
6510 /*
6511 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6512 */
6513 static void quirk_ssc_force_disable(struct drm_device *dev)
6514 {
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6517 DRM_INFO("applying lvds SSC disable quirk\n");
6518 }
6519
6520 /*
6521 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6522 * brightness value
6523 */
6524 static void quirk_invert_brightness(struct drm_device *dev)
6525 {
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
6528 DRM_INFO("applying inverted panel brightness quirk\n");
6529 }
6530
6531 struct intel_quirk {
6532 int device;
6533 int subsystem_vendor;
6534 int subsystem_device;
6535 void (*hook)(struct drm_device *dev);
6536 };
6537
6538 static struct intel_quirk intel_quirks[] = {
6539 /* HP Mini needs pipe A force quirk (LP: #322104) */
6540 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6541
6542 /* Thinkpad R31 needs pipe A force quirk */
6543 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6544 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6545 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6546
6547 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6548 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6549 /* ThinkPad X40 needs pipe A force quirk */
6550
6551 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6552 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6553
6554 /* 855 & before need to leave pipe A & dpll A up */
6555 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6556 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6557
6558 /* Lenovo U160 cannot use SSC on LVDS */
6559 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6560
6561 /* Sony Vaio Y cannot use SSC on LVDS */
6562 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6563
6564 /* Acer Aspire 5734Z must invert backlight brightness */
6565 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
6566 };
6567
6568 static void intel_init_quirks(struct drm_device *dev)
6569 {
6570 struct pci_dev *d = dev->pdev;
6571 int i;
6572
6573 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6574 struct intel_quirk *q = &intel_quirks[i];
6575
6576 if (d->device == q->device &&
6577 (d->subsystem_vendor == q->subsystem_vendor ||
6578 q->subsystem_vendor == PCI_ANY_ID) &&
6579 (d->subsystem_device == q->subsystem_device ||
6580 q->subsystem_device == PCI_ANY_ID))
6581 q->hook(dev);
6582 }
6583 }
6584
6585 /* Disable the VGA plane that we never use */
6586 static void i915_disable_vga(struct drm_device *dev)
6587 {
6588 struct drm_i915_private *dev_priv = dev->dev_private;
6589 u8 sr1;
6590 u32 vga_reg;
6591
6592 if (HAS_PCH_SPLIT(dev))
6593 vga_reg = CPU_VGACNTRL;
6594 else
6595 vga_reg = VGACNTRL;
6596
6597 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6598 outb(SR01, VGA_SR_INDEX);
6599 sr1 = inb(VGA_SR_DATA);
6600 outb(sr1 | 1<<5, VGA_SR_DATA);
6601 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6602 udelay(300);
6603
6604 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6605 POSTING_READ(vga_reg);
6606 }
6607
6608 static void ivb_pch_pwm_override(struct drm_device *dev)
6609 {
6610 struct drm_i915_private *dev_priv = dev->dev_private;
6611
6612 /*
6613 * IVB has CPU eDP backlight regs too, set things up to let the
6614 * PCH regs control the backlight
6615 */
6616 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6617 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6618 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6619 }
6620
6621 void intel_modeset_init_hw(struct drm_device *dev)
6622 {
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624
6625 intel_init_clock_gating(dev);
6626
6627 if (IS_IRONLAKE_M(dev)) {
6628 ironlake_enable_drps(dev);
6629 intel_init_emon(dev);
6630 }
6631
6632 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
6633 gen6_enable_rps(dev_priv);
6634 gen6_update_ring_freq(dev_priv);
6635 }
6636
6637 if (IS_IVYBRIDGE(dev))
6638 ivb_pch_pwm_override(dev);
6639 }
6640
6641 void intel_modeset_init(struct drm_device *dev)
6642 {
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 int i, ret;
6645
6646 drm_mode_config_init(dev);
6647
6648 dev->mode_config.min_width = 0;
6649 dev->mode_config.min_height = 0;
6650
6651 dev->mode_config.preferred_depth = 24;
6652 dev->mode_config.prefer_shadow = 1;
6653
6654 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6655
6656 intel_init_quirks(dev);
6657
6658 intel_init_pm(dev);
6659
6660 intel_init_display(dev);
6661
6662 if (IS_GEN2(dev)) {
6663 dev->mode_config.max_width = 2048;
6664 dev->mode_config.max_height = 2048;
6665 } else if (IS_GEN3(dev)) {
6666 dev->mode_config.max_width = 4096;
6667 dev->mode_config.max_height = 4096;
6668 } else {
6669 dev->mode_config.max_width = 8192;
6670 dev->mode_config.max_height = 8192;
6671 }
6672 dev->mode_config.fb_base = dev->agp->base;
6673
6674 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6675 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6676
6677 for (i = 0; i < dev_priv->num_pipe; i++) {
6678 intel_crtc_init(dev, i);
6679 ret = intel_plane_init(dev, i);
6680 if (ret)
6681 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6682 }
6683
6684 intel_pch_pll_init(dev);
6685
6686 /* Just disable it once at startup */
6687 i915_disable_vga(dev);
6688 intel_setup_outputs(dev);
6689
6690 intel_modeset_init_hw(dev);
6691
6692 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6693 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6694 (unsigned long)dev);
6695 }
6696
6697 void intel_modeset_gem_init(struct drm_device *dev)
6698 {
6699 if (IS_IRONLAKE_M(dev))
6700 ironlake_enable_rc6(dev);
6701
6702 intel_setup_overlay(dev);
6703 }
6704
6705 void intel_modeset_cleanup(struct drm_device *dev)
6706 {
6707 struct drm_i915_private *dev_priv = dev->dev_private;
6708 struct drm_crtc *crtc;
6709 struct intel_crtc *intel_crtc;
6710
6711 drm_kms_helper_poll_fini(dev);
6712 mutex_lock(&dev->struct_mutex);
6713
6714 intel_unregister_dsm_handler();
6715
6716
6717 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6718 /* Skip inactive CRTCs */
6719 if (!crtc->fb)
6720 continue;
6721
6722 intel_crtc = to_intel_crtc(crtc);
6723 intel_increase_pllclock(crtc);
6724 }
6725
6726 intel_disable_fbc(dev);
6727
6728 if (IS_IRONLAKE_M(dev))
6729 ironlake_disable_drps(dev);
6730 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
6731 gen6_disable_rps(dev);
6732
6733 if (IS_IRONLAKE_M(dev))
6734 ironlake_disable_rc6(dev);
6735
6736 if (IS_VALLEYVIEW(dev))
6737 vlv_init_dpio(dev);
6738
6739 mutex_unlock(&dev->struct_mutex);
6740
6741 /* Disable the irq before mode object teardown, for the irq might
6742 * enqueue unpin/hotplug work. */
6743 drm_irq_uninstall(dev);
6744 cancel_work_sync(&dev_priv->hotplug_work);
6745 cancel_work_sync(&dev_priv->rps_work);
6746
6747 /* flush any delayed tasks or pending work */
6748 flush_scheduled_work();
6749
6750 /* Shut off idle work before the crtcs get freed. */
6751 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6752 intel_crtc = to_intel_crtc(crtc);
6753 del_timer_sync(&intel_crtc->idle_timer);
6754 }
6755 del_timer_sync(&dev_priv->idle_timer);
6756 cancel_work_sync(&dev_priv->idle_work);
6757
6758 drm_mode_config_cleanup(dev);
6759 }
6760
6761 /*
6762 * Return which encoder is currently attached for connector.
6763 */
6764 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6765 {
6766 return &intel_attached_encoder(connector)->base;
6767 }
6768
6769 void intel_connector_attach_encoder(struct intel_connector *connector,
6770 struct intel_encoder *encoder)
6771 {
6772 connector->encoder = encoder;
6773 drm_mode_connector_attach_encoder(&connector->base,
6774 &encoder->base);
6775 }
6776
6777 /*
6778 * set vga decode state - true == enable VGA decode
6779 */
6780 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6781 {
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783 u16 gmch_ctrl;
6784
6785 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6786 if (state)
6787 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6788 else
6789 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6790 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6791 return 0;
6792 }
6793
6794 #ifdef CONFIG_DEBUG_FS
6795 #include <linux/seq_file.h>
6796
6797 struct intel_display_error_state {
6798 struct intel_cursor_error_state {
6799 u32 control;
6800 u32 position;
6801 u32 base;
6802 u32 size;
6803 } cursor[2];
6804
6805 struct intel_pipe_error_state {
6806 u32 conf;
6807 u32 source;
6808
6809 u32 htotal;
6810 u32 hblank;
6811 u32 hsync;
6812 u32 vtotal;
6813 u32 vblank;
6814 u32 vsync;
6815 } pipe[2];
6816
6817 struct intel_plane_error_state {
6818 u32 control;
6819 u32 stride;
6820 u32 size;
6821 u32 pos;
6822 u32 addr;
6823 u32 surface;
6824 u32 tile_offset;
6825 } plane[2];
6826 };
6827
6828 struct intel_display_error_state *
6829 intel_display_capture_error_state(struct drm_device *dev)
6830 {
6831 drm_i915_private_t *dev_priv = dev->dev_private;
6832 struct intel_display_error_state *error;
6833 int i;
6834
6835 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6836 if (error == NULL)
6837 return NULL;
6838
6839 for (i = 0; i < 2; i++) {
6840 error->cursor[i].control = I915_READ(CURCNTR(i));
6841 error->cursor[i].position = I915_READ(CURPOS(i));
6842 error->cursor[i].base = I915_READ(CURBASE(i));
6843
6844 error->plane[i].control = I915_READ(DSPCNTR(i));
6845 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6846 error->plane[i].size = I915_READ(DSPSIZE(i));
6847 error->plane[i].pos = I915_READ(DSPPOS(i));
6848 error->plane[i].addr = I915_READ(DSPADDR(i));
6849 if (INTEL_INFO(dev)->gen >= 4) {
6850 error->plane[i].surface = I915_READ(DSPSURF(i));
6851 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6852 }
6853
6854 error->pipe[i].conf = I915_READ(PIPECONF(i));
6855 error->pipe[i].source = I915_READ(PIPESRC(i));
6856 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6857 error->pipe[i].hblank = I915_READ(HBLANK(i));
6858 error->pipe[i].hsync = I915_READ(HSYNC(i));
6859 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6860 error->pipe[i].vblank = I915_READ(VBLANK(i));
6861 error->pipe[i].vsync = I915_READ(VSYNC(i));
6862 }
6863
6864 return error;
6865 }
6866
6867 void
6868 intel_display_print_error_state(struct seq_file *m,
6869 struct drm_device *dev,
6870 struct intel_display_error_state *error)
6871 {
6872 int i;
6873
6874 for (i = 0; i < 2; i++) {
6875 seq_printf(m, "Pipe [%d]:\n", i);
6876 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6877 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6878 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6879 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6880 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6881 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6882 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6883 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6884
6885 seq_printf(m, "Plane [%d]:\n", i);
6886 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6887 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6888 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6889 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6890 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6891 if (INTEL_INFO(dev)->gen >= 4) {
6892 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6893 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6894 }
6895
6896 seq_printf(m, "Cursor [%d]:\n", i);
6897 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6898 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6899 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6900 }
6901 }
6902 #endif
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