1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 #include "drm_crtc_helper.h"
34 #include "drm_fb_helper.h"
35 #include "intel_drv.h"
38 #include "i915_trace.h"
39 #include <linux/pci.h>
40 #include <linux/vgaarb.h>
41 #include <linux/acpi.h>
42 #include <linux/pnp.h>
43 #include <linux/vga_switcheroo.h>
44 #include <linux/slab.h>
45 #include <acpi/video.h>
48 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
50 #define BEGIN_LP_RING(n) \
51 intel_ring_begin(LP_RING(dev_priv), (n))
54 intel_ring_emit(LP_RING(dev_priv), x)
56 #define ADVANCE_LP_RING() \
57 intel_ring_advance(LP_RING(dev_priv))
60 * Lock test for when it's just for synchronization of ring access.
62 * In that case, we don't need to do it when GEM is initialized as nobody else
63 * has access to the ring.
65 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
66 if (LP_RING(dev->dev_private)->obj == NULL) \
67 LOCK_TEST_WITH_RETURN(dev, file); \
71 intel_read_legacy_status_page(struct drm_i915_private
*dev_priv
, int reg
)
73 if (I915_NEED_GFX_HWS(dev_priv
->dev
))
74 return ioread32(dev_priv
->dri1
.gfx_hws_cpu_addr
+ reg
);
76 return intel_read_status_page(LP_RING(dev_priv
), reg
);
79 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
80 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
81 #define I915_BREADCRUMB_INDEX 0x21
83 void i915_update_dri1_breadcrumb(struct drm_device
*dev
)
85 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
86 struct drm_i915_master_private
*master_priv
;
88 if (dev
->primary
->master
) {
89 master_priv
= dev
->primary
->master
->driver_priv
;
90 if (master_priv
->sarea_priv
)
91 master_priv
->sarea_priv
->last_dispatch
=
92 READ_BREADCRUMB(dev_priv
);
96 static void i915_write_hws_pga(struct drm_device
*dev
)
98 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
101 addr
= dev_priv
->status_page_dmah
->busaddr
;
102 if (INTEL_INFO(dev
)->gen
>= 4)
103 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
104 I915_WRITE(HWS_PGA
, addr
);
108 * Sets up the hardware status page for devices that need a physical address
111 static int i915_init_phys_hws(struct drm_device
*dev
)
113 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
115 /* Program Hardware Status Page */
116 dev_priv
->status_page_dmah
=
117 drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
);
119 if (!dev_priv
->status_page_dmah
) {
120 DRM_ERROR("Can not allocate hardware status page\n");
124 memset_io((void __force __iomem
*)dev_priv
->status_page_dmah
->vaddr
,
127 i915_write_hws_pga(dev
);
129 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
134 * Frees the hardware status page, whether it's a physical address or a virtual
135 * address set up by the X Server.
137 static void i915_free_hws(struct drm_device
*dev
)
139 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
140 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
142 if (dev_priv
->status_page_dmah
) {
143 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
144 dev_priv
->status_page_dmah
= NULL
;
147 if (ring
->status_page
.gfx_addr
) {
148 ring
->status_page
.gfx_addr
= 0;
149 iounmap(dev_priv
->dri1
.gfx_hws_cpu_addr
);
152 /* Need to rewrite hardware status page */
153 I915_WRITE(HWS_PGA
, 0x1ffff000);
156 void i915_kernel_lost_context(struct drm_device
* dev
)
158 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
159 struct drm_i915_master_private
*master_priv
;
160 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
163 * We should never lose context on the ring with modesetting
164 * as we don't expose it to userspace
166 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
169 ring
->head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
170 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
171 ring
->space
= ring
->head
- (ring
->tail
+ 8);
173 ring
->space
+= ring
->size
;
175 if (!dev
->primary
->master
)
178 master_priv
= dev
->primary
->master
->driver_priv
;
179 if (ring
->head
== ring
->tail
&& master_priv
->sarea_priv
)
180 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
183 static int i915_dma_cleanup(struct drm_device
* dev
)
185 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
188 /* Make sure interrupts are disabled here because the uninstall ioctl
189 * may not have been called from userspace and after dev_private
190 * is freed, it's too late.
192 if (dev
->irq_enabled
)
193 drm_irq_uninstall(dev
);
195 mutex_lock(&dev
->struct_mutex
);
196 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
197 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
198 mutex_unlock(&dev
->struct_mutex
);
200 /* Clear the HWS virtual address at teardown */
201 if (I915_NEED_GFX_HWS(dev
))
207 static int i915_initialize(struct drm_device
* dev
, drm_i915_init_t
* init
)
209 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
210 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
213 master_priv
->sarea
= drm_getsarea(dev
);
214 if (master_priv
->sarea
) {
215 master_priv
->sarea_priv
= (drm_i915_sarea_t
*)
216 ((u8
*)master_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
218 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
221 if (init
->ring_size
!= 0) {
222 if (LP_RING(dev_priv
)->obj
!= NULL
) {
223 i915_dma_cleanup(dev
);
224 DRM_ERROR("Client tried to initialize ringbuffer in "
229 ret
= intel_render_ring_init_dri(dev
,
233 i915_dma_cleanup(dev
);
238 dev_priv
->cpp
= init
->cpp
;
239 dev_priv
->back_offset
= init
->back_offset
;
240 dev_priv
->front_offset
= init
->front_offset
;
241 dev_priv
->current_page
= 0;
242 if (master_priv
->sarea_priv
)
243 master_priv
->sarea_priv
->pf_current_page
= 0;
245 /* Allow hardware batchbuffers unless told otherwise.
247 dev_priv
->dri1
.allow_batchbuffer
= 1;
252 static int i915_dma_resume(struct drm_device
* dev
)
254 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
255 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
257 DRM_DEBUG_DRIVER("%s\n", __func__
);
259 if (ring
->virtual_start
== NULL
) {
260 DRM_ERROR("can not ioremap virtual address for"
265 /* Program Hardware Status Page */
266 if (!ring
->status_page
.page_addr
) {
267 DRM_ERROR("Can not find hardware status page\n");
270 DRM_DEBUG_DRIVER("hw status page @ %p\n",
271 ring
->status_page
.page_addr
);
272 if (ring
->status_page
.gfx_addr
!= 0)
273 intel_ring_setup_status_page(ring
);
275 i915_write_hws_pga(dev
);
277 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
282 static int i915_dma_init(struct drm_device
*dev
, void *data
,
283 struct drm_file
*file_priv
)
285 drm_i915_init_t
*init
= data
;
288 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
291 switch (init
->func
) {
293 retcode
= i915_initialize(dev
, init
);
295 case I915_CLEANUP_DMA
:
296 retcode
= i915_dma_cleanup(dev
);
298 case I915_RESUME_DMA
:
299 retcode
= i915_dma_resume(dev
);
309 /* Implement basically the same security restrictions as hardware does
310 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
312 * Most of the calculations below involve calculating the size of a
313 * particular instruction. It's important to get the size right as
314 * that tells us where the next instruction to check is. Any illegal
315 * instruction detected will be given a size of zero, which is a
316 * signal to abort the rest of the buffer.
318 static int validate_cmd(int cmd
)
320 switch (((cmd
>> 29) & 0x7)) {
322 switch ((cmd
>> 23) & 0x3f) {
324 return 1; /* MI_NOOP */
326 return 1; /* MI_FLUSH */
328 return 0; /* disallow everything else */
332 return 0; /* reserved */
334 return (cmd
& 0xff) + 2; /* 2d commands */
336 if (((cmd
>> 24) & 0x1f) <= 0x18)
339 switch ((cmd
>> 24) & 0x1f) {
343 switch ((cmd
>> 16) & 0xff) {
345 return (cmd
& 0x1f) + 2;
347 return (cmd
& 0xf) + 2;
349 return (cmd
& 0xffff) + 2;
353 return (cmd
& 0xffff) + 1;
357 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
358 return (cmd
& 0x1ffff) + 2;
359 else if (cmd
& (1 << 17)) /* indirect random */
360 if ((cmd
& 0xffff) == 0)
361 return 0; /* unknown length, too hard */
363 return (((cmd
& 0xffff) + 1) / 2) + 1;
365 return 2; /* indirect sequential */
376 static int i915_emit_cmds(struct drm_device
* dev
, int *buffer
, int dwords
)
378 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
381 if ((dwords
+1) * sizeof(int) >= LP_RING(dev_priv
)->size
- 8)
384 for (i
= 0; i
< dwords
;) {
385 int sz
= validate_cmd(buffer
[i
]);
386 if (sz
== 0 || i
+ sz
> dwords
)
391 ret
= BEGIN_LP_RING((dwords
+1)&~1);
395 for (i
= 0; i
< dwords
; i
++)
406 i915_emit_box(struct drm_device
*dev
,
407 struct drm_clip_rect
*box
,
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
413 if (box
->y2
<= box
->y1
|| box
->x2
<= box
->x1
||
414 box
->y2
<= 0 || box
->x2
<= 0) {
415 DRM_ERROR("Bad box %d,%d..%d,%d\n",
416 box
->x1
, box
->y1
, box
->x2
, box
->y2
);
420 if (INTEL_INFO(dev
)->gen
>= 4) {
421 ret
= BEGIN_LP_RING(4);
425 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
426 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
427 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
430 ret
= BEGIN_LP_RING(6);
434 OUT_RING(GFX_OP_DRAWRECT_INFO
);
436 OUT_RING((box
->x1
& 0xffff) | (box
->y1
<< 16));
437 OUT_RING(((box
->x2
- 1) & 0xffff) | ((box
->y2
- 1) << 16));
446 /* XXX: Emitting the counter should really be moved to part of the IRQ
447 * emit. For now, do it in both places:
450 static void i915_emit_breadcrumb(struct drm_device
*dev
)
452 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
453 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
456 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
457 dev_priv
->counter
= 0;
458 if (master_priv
->sarea_priv
)
459 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
461 if (BEGIN_LP_RING(4) == 0) {
462 OUT_RING(MI_STORE_DWORD_INDEX
);
463 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
464 OUT_RING(dev_priv
->counter
);
470 static int i915_dispatch_cmdbuffer(struct drm_device
* dev
,
471 drm_i915_cmdbuffer_t
*cmd
,
472 struct drm_clip_rect
*cliprects
,
475 int nbox
= cmd
->num_cliprects
;
476 int i
= 0, count
, ret
;
479 DRM_ERROR("alignment");
483 i915_kernel_lost_context(dev
);
485 count
= nbox
? nbox
: 1;
487 for (i
= 0; i
< count
; i
++) {
489 ret
= i915_emit_box(dev
, &cliprects
[i
],
495 ret
= i915_emit_cmds(dev
, cmdbuf
, cmd
->sz
/ 4);
500 i915_emit_breadcrumb(dev
);
504 static int i915_dispatch_batchbuffer(struct drm_device
* dev
,
505 drm_i915_batchbuffer_t
* batch
,
506 struct drm_clip_rect
*cliprects
)
508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
509 int nbox
= batch
->num_cliprects
;
512 if ((batch
->start
| batch
->used
) & 0x7) {
513 DRM_ERROR("alignment");
517 i915_kernel_lost_context(dev
);
519 count
= nbox
? nbox
: 1;
520 for (i
= 0; i
< count
; i
++) {
522 ret
= i915_emit_box(dev
, &cliprects
[i
],
523 batch
->DR1
, batch
->DR4
);
528 if (!IS_I830(dev
) && !IS_845G(dev
)) {
529 ret
= BEGIN_LP_RING(2);
533 if (INTEL_INFO(dev
)->gen
>= 4) {
534 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6) | MI_BATCH_NON_SECURE_I965
);
535 OUT_RING(batch
->start
);
537 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
538 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
541 ret
= BEGIN_LP_RING(4);
545 OUT_RING(MI_BATCH_BUFFER
);
546 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
547 OUT_RING(batch
->start
+ batch
->used
- 4);
554 if (IS_G4X(dev
) || IS_GEN5(dev
)) {
555 if (BEGIN_LP_RING(2) == 0) {
556 OUT_RING(MI_FLUSH
| MI_NO_WRITE_FLUSH
| MI_INVALIDATE_ISP
);
562 i915_emit_breadcrumb(dev
);
566 static int i915_dispatch_flip(struct drm_device
* dev
)
568 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
569 struct drm_i915_master_private
*master_priv
=
570 dev
->primary
->master
->driver_priv
;
573 if (!master_priv
->sarea_priv
)
576 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
578 dev_priv
->current_page
,
579 master_priv
->sarea_priv
->pf_current_page
);
581 i915_kernel_lost_context(dev
);
583 ret
= BEGIN_LP_RING(10);
587 OUT_RING(MI_FLUSH
| MI_READ_FLUSH
);
590 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
592 if (dev_priv
->current_page
== 0) {
593 OUT_RING(dev_priv
->back_offset
);
594 dev_priv
->current_page
= 1;
596 OUT_RING(dev_priv
->front_offset
);
597 dev_priv
->current_page
= 0;
601 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
606 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
608 if (BEGIN_LP_RING(4) == 0) {
609 OUT_RING(MI_STORE_DWORD_INDEX
);
610 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
611 OUT_RING(dev_priv
->counter
);
616 master_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
620 static int i915_quiescent(struct drm_device
*dev
)
622 struct intel_ring_buffer
*ring
= LP_RING(dev
->dev_private
);
624 i915_kernel_lost_context(dev
);
625 return intel_wait_ring_idle(ring
);
628 static int i915_flush_ioctl(struct drm_device
*dev
, void *data
,
629 struct drm_file
*file_priv
)
633 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
636 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
638 mutex_lock(&dev
->struct_mutex
);
639 ret
= i915_quiescent(dev
);
640 mutex_unlock(&dev
->struct_mutex
);
645 static int i915_batchbuffer(struct drm_device
*dev
, void *data
,
646 struct drm_file
*file_priv
)
648 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
649 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
650 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
651 master_priv
->sarea_priv
;
652 drm_i915_batchbuffer_t
*batch
= data
;
654 struct drm_clip_rect
*cliprects
= NULL
;
656 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
659 if (!dev_priv
->dri1
.allow_batchbuffer
) {
660 DRM_ERROR("Batchbuffer ioctl disabled\n");
664 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
665 batch
->start
, batch
->used
, batch
->num_cliprects
);
667 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
669 if (batch
->num_cliprects
< 0)
672 if (batch
->num_cliprects
) {
673 cliprects
= kcalloc(batch
->num_cliprects
,
674 sizeof(struct drm_clip_rect
),
676 if (cliprects
== NULL
)
679 ret
= copy_from_user(cliprects
, batch
->cliprects
,
680 batch
->num_cliprects
*
681 sizeof(struct drm_clip_rect
));
688 mutex_lock(&dev
->struct_mutex
);
689 ret
= i915_dispatch_batchbuffer(dev
, batch
, cliprects
);
690 mutex_unlock(&dev
->struct_mutex
);
693 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
701 static int i915_cmdbuffer(struct drm_device
*dev
, void *data
,
702 struct drm_file
*file_priv
)
704 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
705 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
706 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
707 master_priv
->sarea_priv
;
708 drm_i915_cmdbuffer_t
*cmdbuf
= data
;
709 struct drm_clip_rect
*cliprects
= NULL
;
713 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
714 cmdbuf
->buf
, cmdbuf
->sz
, cmdbuf
->num_cliprects
);
716 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
719 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
721 if (cmdbuf
->num_cliprects
< 0)
724 batch_data
= kmalloc(cmdbuf
->sz
, GFP_KERNEL
);
725 if (batch_data
== NULL
)
728 ret
= copy_from_user(batch_data
, cmdbuf
->buf
, cmdbuf
->sz
);
731 goto fail_batch_free
;
734 if (cmdbuf
->num_cliprects
) {
735 cliprects
= kcalloc(cmdbuf
->num_cliprects
,
736 sizeof(struct drm_clip_rect
), GFP_KERNEL
);
737 if (cliprects
== NULL
) {
739 goto fail_batch_free
;
742 ret
= copy_from_user(cliprects
, cmdbuf
->cliprects
,
743 cmdbuf
->num_cliprects
*
744 sizeof(struct drm_clip_rect
));
751 mutex_lock(&dev
->struct_mutex
);
752 ret
= i915_dispatch_cmdbuffer(dev
, cmdbuf
, cliprects
, batch_data
);
753 mutex_unlock(&dev
->struct_mutex
);
755 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
760 sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
770 static int i915_emit_irq(struct drm_device
* dev
)
772 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
773 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
775 i915_kernel_lost_context(dev
);
777 DRM_DEBUG_DRIVER("\n");
780 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
781 dev_priv
->counter
= 1;
782 if (master_priv
->sarea_priv
)
783 master_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
;
785 if (BEGIN_LP_RING(4) == 0) {
786 OUT_RING(MI_STORE_DWORD_INDEX
);
787 OUT_RING(I915_BREADCRUMB_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
788 OUT_RING(dev_priv
->counter
);
789 OUT_RING(MI_USER_INTERRUPT
);
793 return dev_priv
->counter
;
796 static int i915_wait_irq(struct drm_device
* dev
, int irq_nr
)
798 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
799 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
801 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
803 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr
,
804 READ_BREADCRUMB(dev_priv
));
806 if (READ_BREADCRUMB(dev_priv
) >= irq_nr
) {
807 if (master_priv
->sarea_priv
)
808 master_priv
->sarea_priv
->last_dispatch
= READ_BREADCRUMB(dev_priv
);
812 if (master_priv
->sarea_priv
)
813 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
815 if (ring
->irq_get(ring
)) {
816 DRM_WAIT_ON(ret
, ring
->irq_queue
, 3 * DRM_HZ
,
817 READ_BREADCRUMB(dev_priv
) >= irq_nr
);
819 } else if (wait_for(READ_BREADCRUMB(dev_priv
) >= irq_nr
, 3000))
823 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
824 READ_BREADCRUMB(dev_priv
), (int)dev_priv
->counter
);
830 /* Needs the lock as it touches the ring.
832 static int i915_irq_emit(struct drm_device
*dev
, void *data
,
833 struct drm_file
*file_priv
)
835 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
836 drm_i915_irq_emit_t
*emit
= data
;
839 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
842 if (!dev_priv
|| !LP_RING(dev_priv
)->virtual_start
) {
843 DRM_ERROR("called with no initialization\n");
847 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
849 mutex_lock(&dev
->struct_mutex
);
850 result
= i915_emit_irq(dev
);
851 mutex_unlock(&dev
->struct_mutex
);
853 if (DRM_COPY_TO_USER(emit
->irq_seq
, &result
, sizeof(int))) {
854 DRM_ERROR("copy_to_user\n");
861 /* Doesn't need the hardware lock.
863 static int i915_irq_wait(struct drm_device
*dev
, void *data
,
864 struct drm_file
*file_priv
)
866 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
867 drm_i915_irq_wait_t
*irqwait
= data
;
869 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
873 DRM_ERROR("called with no initialization\n");
877 return i915_wait_irq(dev
, irqwait
->irq_seq
);
880 static int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
881 struct drm_file
*file_priv
)
883 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
884 drm_i915_vblank_pipe_t
*pipe
= data
;
886 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
890 DRM_ERROR("called with no initialization\n");
894 pipe
->pipe
= DRM_I915_VBLANK_PIPE_A
| DRM_I915_VBLANK_PIPE_B
;
900 * Schedule buffer swap at given vertical blank.
902 static int i915_vblank_swap(struct drm_device
*dev
, void *data
,
903 struct drm_file
*file_priv
)
905 /* The delayed swap mechanism was fundamentally racy, and has been
906 * removed. The model was that the client requested a delayed flip/swap
907 * from the kernel, then waited for vblank before continuing to perform
908 * rendering. The problem was that the kernel might wake the client
909 * up before it dispatched the vblank swap (since the lock has to be
910 * held while touching the ringbuffer), in which case the client would
911 * clear and start the next frame before the swap occurred, and
912 * flicker would occur in addition to likely missing the vblank.
914 * In the absence of this ioctl, userland falls back to a correct path
915 * of waiting for a vblank, then dispatching the swap on its own.
916 * Context switching to userland and back is plenty fast enough for
917 * meeting the requirements of vblank swapping.
922 static int i915_flip_bufs(struct drm_device
*dev
, void *data
,
923 struct drm_file
*file_priv
)
927 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
930 DRM_DEBUG_DRIVER("%s\n", __func__
);
932 RING_LOCK_TEST_WITH_RETURN(dev
, file_priv
);
934 mutex_lock(&dev
->struct_mutex
);
935 ret
= i915_dispatch_flip(dev
);
936 mutex_unlock(&dev
->struct_mutex
);
941 static int i915_getparam(struct drm_device
*dev
, void *data
,
942 struct drm_file
*file_priv
)
944 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
945 drm_i915_getparam_t
*param
= data
;
949 DRM_ERROR("called with no initialization\n");
953 switch (param
->param
) {
954 case I915_PARAM_IRQ_ACTIVE
:
955 value
= dev
->pdev
->irq
? 1 : 0;
957 case I915_PARAM_ALLOW_BATCHBUFFER
:
958 value
= dev_priv
->dri1
.allow_batchbuffer
? 1 : 0;
960 case I915_PARAM_LAST_DISPATCH
:
961 value
= READ_BREADCRUMB(dev_priv
);
963 case I915_PARAM_CHIPSET_ID
:
964 value
= dev
->pci_device
;
966 case I915_PARAM_HAS_GEM
:
969 case I915_PARAM_NUM_FENCES_AVAIL
:
970 value
= dev_priv
->num_fence_regs
- dev_priv
->fence_reg_start
;
972 case I915_PARAM_HAS_OVERLAY
:
973 value
= dev_priv
->overlay
? 1 : 0;
975 case I915_PARAM_HAS_PAGEFLIPPING
:
978 case I915_PARAM_HAS_EXECBUF2
:
982 case I915_PARAM_HAS_BSD
:
983 value
= HAS_BSD(dev
);
985 case I915_PARAM_HAS_BLT
:
986 value
= HAS_BLT(dev
);
988 case I915_PARAM_HAS_RELAXED_FENCING
:
991 case I915_PARAM_HAS_COHERENT_RINGS
:
994 case I915_PARAM_HAS_EXEC_CONSTANTS
:
995 value
= INTEL_INFO(dev
)->gen
>= 4;
997 case I915_PARAM_HAS_RELAXED_DELTA
:
1000 case I915_PARAM_HAS_GEN7_SOL_RESET
:
1003 case I915_PARAM_HAS_LLC
:
1004 value
= HAS_LLC(dev
);
1006 case I915_PARAM_HAS_ALIASING_PPGTT
:
1007 value
= dev_priv
->mm
.aliasing_ppgtt
? 1 : 0;
1010 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1015 if (DRM_COPY_TO_USER(param
->value
, &value
, sizeof(int))) {
1016 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1023 static int i915_setparam(struct drm_device
*dev
, void *data
,
1024 struct drm_file
*file_priv
)
1026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1027 drm_i915_setparam_t
*param
= data
;
1030 DRM_ERROR("called with no initialization\n");
1034 switch (param
->param
) {
1035 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
1037 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
1039 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
1040 dev_priv
->dri1
.allow_batchbuffer
= param
->value
? 1 : 0;
1042 case I915_SETPARAM_NUM_USED_FENCES
:
1043 if (param
->value
> dev_priv
->num_fence_regs
||
1046 /* Userspace can use first N regs */
1047 dev_priv
->fence_reg_start
= param
->value
;
1050 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1058 static int i915_set_status_page(struct drm_device
*dev
, void *data
,
1059 struct drm_file
*file_priv
)
1061 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1062 drm_i915_hws_addr_t
*hws
= data
;
1063 struct intel_ring_buffer
*ring
= LP_RING(dev_priv
);
1065 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
1068 if (!I915_NEED_GFX_HWS(dev
))
1072 DRM_ERROR("called with no initialization\n");
1076 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1077 WARN(1, "tried to set status page when mode setting active\n");
1081 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32
)hws
->addr
);
1083 ring
->status_page
.gfx_addr
= hws
->addr
& (0x1ffff<<12);
1085 dev_priv
->dri1
.gfx_hws_cpu_addr
= ioremap_wc(dev
->agp
->base
+ hws
->addr
,
1087 if (dev_priv
->dri1
.gfx_hws_cpu_addr
== NULL
) {
1088 i915_dma_cleanup(dev
);
1089 ring
->status_page
.gfx_addr
= 0;
1090 DRM_ERROR("can not ioremap virtual address for"
1091 " G33 hw status page\n");
1095 memset_io(dev_priv
->dri1
.gfx_hws_cpu_addr
, 0, PAGE_SIZE
);
1096 I915_WRITE(HWS_PGA
, ring
->status_page
.gfx_addr
);
1098 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1099 ring
->status_page
.gfx_addr
);
1100 DRM_DEBUG_DRIVER("load hws at %p\n",
1101 ring
->status_page
.page_addr
);
1105 static int i915_get_bridge_dev(struct drm_device
*dev
)
1107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1109 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1110 if (!dev_priv
->bridge_dev
) {
1111 DRM_ERROR("bridge device not found\n");
1117 #define MCHBAR_I915 0x44
1118 #define MCHBAR_I965 0x48
1119 #define MCHBAR_SIZE (4*4096)
1121 #define DEVEN_REG 0x54
1122 #define DEVEN_MCHBAR_EN (1 << 28)
1124 /* Allocate space for the MCH regs if needed, return nonzero on error */
1126 intel_alloc_mchbar_resource(struct drm_device
*dev
)
1128 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1129 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1130 u32 temp_lo
, temp_hi
= 0;
1134 if (INTEL_INFO(dev
)->gen
>= 4)
1135 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
1136 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
1137 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
1139 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1142 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
1146 /* Get some space for it */
1147 dev_priv
->mch_res
.name
= "i915 MCHBAR";
1148 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
1149 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
1151 MCHBAR_SIZE
, MCHBAR_SIZE
,
1153 0, pcibios_align_resource
,
1154 dev_priv
->bridge_dev
);
1156 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
1157 dev_priv
->mch_res
.start
= 0;
1161 if (INTEL_INFO(dev
)->gen
>= 4)
1162 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
1163 upper_32_bits(dev_priv
->mch_res
.start
));
1165 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
1166 lower_32_bits(dev_priv
->mch_res
.start
));
1170 /* Setup MCHBAR if possible, return true if we should disable it again */
1172 intel_setup_mchbar(struct drm_device
*dev
)
1174 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1175 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1179 dev_priv
->mchbar_need_disable
= false;
1181 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1182 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1183 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
1185 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1189 /* If it's already enabled, don't have to do anything */
1193 if (intel_alloc_mchbar_resource(dev
))
1196 dev_priv
->mchbar_need_disable
= true;
1198 /* Space is allocated or reserved, so enable it. */
1199 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1200 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
1201 temp
| DEVEN_MCHBAR_EN
);
1203 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1204 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
1209 intel_teardown_mchbar(struct drm_device
*dev
)
1211 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1212 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
1215 if (dev_priv
->mchbar_need_disable
) {
1216 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
1217 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
1218 temp
&= ~DEVEN_MCHBAR_EN
;
1219 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
1221 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
1223 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
1227 if (dev_priv
->mch_res
.start
)
1228 release_resource(&dev_priv
->mch_res
);
1231 /* true = enable decode, false = disable decoder */
1232 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
1234 struct drm_device
*dev
= cookie
;
1236 intel_modeset_vga_set_state(dev
, state
);
1238 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
1239 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1241 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
1244 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
1246 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1247 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
1248 if (state
== VGA_SWITCHEROO_ON
) {
1249 pr_info("switched on\n");
1250 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1251 /* i915 resume handler doesn't set to D0 */
1252 pci_set_power_state(dev
->pdev
, PCI_D0
);
1254 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
1256 pr_err("switched off\n");
1257 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
1258 i915_suspend(dev
, pmm
);
1259 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
1263 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
1265 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1268 spin_lock(&dev
->count_lock
);
1269 can_switch
= (dev
->open_count
== 0);
1270 spin_unlock(&dev
->count_lock
);
1274 static int i915_load_modeset_init(struct drm_device
*dev
)
1276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1279 ret
= intel_parse_bios(dev
);
1281 DRM_INFO("failed to find VBIOS tables\n");
1283 /* If we have > 1 VGA cards, then we need to arbitrate access
1284 * to the common VGA resources.
1286 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1287 * then we do not take part in VGA arbitration and the
1288 * vga_client_register() fails with -ENODEV.
1290 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
1291 if (ret
&& ret
!= -ENODEV
)
1294 intel_register_dsm_handler();
1296 ret
= vga_switcheroo_register_client(dev
->pdev
,
1297 i915_switcheroo_set_state
,
1299 i915_switcheroo_can_switch
);
1301 goto cleanup_vga_client
;
1303 /* Initialise stolen first so that we may reserve preallocated
1304 * objects for the BIOS to KMS transition.
1306 ret
= i915_gem_init_stolen(dev
);
1308 goto cleanup_vga_switcheroo
;
1310 intel_modeset_init(dev
);
1312 ret
= i915_gem_init(dev
);
1314 goto cleanup_gem_stolen
;
1316 intel_modeset_gem_init(dev
);
1318 ret
= drm_irq_install(dev
);
1322 /* Always safe in the mode setting case. */
1323 /* FIXME: do pre/post-mode set stuff in core KMS code */
1324 dev
->vblank_disable_allowed
= 1;
1326 ret
= intel_fbdev_init(dev
);
1330 drm_kms_helper_poll_init(dev
);
1332 /* We're off and running w/KMS */
1333 dev_priv
->mm
.suspended
= 0;
1338 drm_irq_uninstall(dev
);
1340 mutex_lock(&dev
->struct_mutex
);
1341 i915_gem_cleanup_ringbuffer(dev
);
1342 mutex_unlock(&dev
->struct_mutex
);
1343 i915_gem_cleanup_aliasing_ppgtt(dev
);
1345 i915_gem_cleanup_stolen(dev
);
1346 cleanup_vga_switcheroo
:
1347 vga_switcheroo_unregister_client(dev
->pdev
);
1349 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1354 int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
)
1356 struct drm_i915_master_private
*master_priv
;
1358 master_priv
= kzalloc(sizeof(*master_priv
), GFP_KERNEL
);
1362 master
->driver_priv
= master_priv
;
1366 void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
)
1368 struct drm_i915_master_private
*master_priv
= master
->driver_priv
;
1375 master
->driver_priv
= NULL
;
1379 i915_mtrr_setup(struct drm_i915_private
*dev_priv
, unsigned long base
,
1382 dev_priv
->mm
.gtt_mtrr
= -1;
1384 #if defined(CONFIG_X86_PAT)
1389 /* Set up a WC MTRR for non-PAT systems. This is more common than
1390 * one would think, because the kernel disables PAT on first
1391 * generation Core chips because WC PAT gets overridden by a UC
1392 * MTRR if present. Even if a UC MTRR isn't present.
1394 dev_priv
->mm
.gtt_mtrr
= mtrr_add(base
, size
, MTRR_TYPE_WRCOMB
, 1);
1395 if (dev_priv
->mm
.gtt_mtrr
< 0) {
1396 DRM_INFO("MTRR allocation failed. Graphics "
1397 "performance may suffer.\n");
1402 * i915_driver_load - setup chip and create an initial config
1404 * @flags: startup flags
1406 * The driver load routine has to do several things:
1407 * - drive output discovery via intel_modeset_init()
1408 * - initialize the memory manager
1409 * - allocate initial config memory
1410 * - setup the DRM framebuffer with the allocated memory
1412 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
1414 struct drm_i915_private
*dev_priv
;
1415 struct intel_device_info
*info
;
1416 int ret
= 0, mmio_bar
;
1417 uint32_t aperture_size
;
1419 info
= (struct intel_device_info
*) flags
;
1421 /* Refuse to load on gen6+ without kms enabled. */
1422 if (info
->gen
>= 6 && !drm_core_check_feature(dev
, DRIVER_MODESET
))
1426 /* i915 has 4 more counters */
1428 dev
->types
[6] = _DRM_STAT_IRQ
;
1429 dev
->types
[7] = _DRM_STAT_PRIMARY
;
1430 dev
->types
[8] = _DRM_STAT_SECONDARY
;
1431 dev
->types
[9] = _DRM_STAT_DMA
;
1433 dev_priv
= kzalloc(sizeof(drm_i915_private_t
), GFP_KERNEL
);
1434 if (dev_priv
== NULL
)
1437 dev
->dev_private
= (void *)dev_priv
;
1438 dev_priv
->dev
= dev
;
1439 dev_priv
->info
= info
;
1441 if (i915_get_bridge_dev(dev
)) {
1446 pci_set_master(dev
->pdev
);
1448 /* overlay on gen2 is broken and can't address above 1G */
1450 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
1452 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1453 * using 32bit addressing, overwriting memory if HWS is located
1456 * The documentation also mentions an issue with undefined
1457 * behaviour if any general state is accessed within a page above 4GB,
1458 * which also needs to be handled carefully.
1460 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1461 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
1463 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
1464 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, 0);
1465 if (!dev_priv
->regs
) {
1466 DRM_ERROR("failed to map registers\n");
1471 dev_priv
->mm
.gtt
= intel_gtt_get();
1472 if (!dev_priv
->mm
.gtt
) {
1473 DRM_ERROR("Failed to initialize GTT\n");
1478 aperture_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
1480 dev_priv
->mm
.gtt_mapping
=
1481 io_mapping_create_wc(dev
->agp
->base
, aperture_size
);
1482 if (dev_priv
->mm
.gtt_mapping
== NULL
) {
1487 i915_mtrr_setup(dev_priv
, dev
->agp
->base
, aperture_size
);
1489 /* The i915 workqueue is primarily used for batched retirement of
1490 * requests (and thus managing bo) once the task has been completed
1491 * by the GPU. i915_gem_retire_requests() is called directly when we
1492 * need high-priority retirement, such as waiting for an explicit
1495 * It is also used for periodic low-priority events, such as
1496 * idle-timers and recording error state.
1498 * All tasks on the workqueue are expected to acquire the dev mutex
1499 * so there is no point in running more than one instance of the
1500 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1502 dev_priv
->wq
= alloc_workqueue("i915",
1503 WQ_UNBOUND
| WQ_NON_REENTRANT
,
1505 if (dev_priv
->wq
== NULL
) {
1506 DRM_ERROR("Failed to create our workqueue.\n");
1511 intel_irq_init(dev
);
1513 /* Try to make sure MCHBAR is enabled before poking at it */
1514 intel_setup_mchbar(dev
);
1515 intel_setup_gmbus(dev
);
1516 intel_opregion_setup(dev
);
1518 /* Make sure the bios did its job and set up vital registers */
1519 intel_setup_bios(dev
);
1524 if (!I915_NEED_GFX_HWS(dev
)) {
1525 ret
= i915_init_phys_hws(dev
);
1527 goto out_gem_unload
;
1530 /* On the 945G/GM, the chipset reports the MSI capability on the
1531 * integrated graphics even though the support isn't actually there
1532 * according to the published specs. It doesn't appear to function
1533 * correctly in testing on 945G.
1534 * This may be a side effect of MSI having been made available for PEG
1535 * and the registers being closely associated.
1537 * According to chipset errata, on the 965GM, MSI interrupts may
1538 * be lost or delayed, but we use them anyways to avoid
1539 * stuck interrupts on some machines.
1541 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1542 pci_enable_msi(dev
->pdev
);
1544 spin_lock_init(&dev_priv
->gt_lock
);
1545 spin_lock_init(&dev_priv
->irq_lock
);
1546 spin_lock_init(&dev_priv
->error_lock
);
1547 spin_lock_init(&dev_priv
->rps_lock
);
1549 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1550 dev_priv
->num_pipe
= 3;
1551 else if (IS_MOBILE(dev
) || !IS_GEN2(dev
))
1552 dev_priv
->num_pipe
= 2;
1554 dev_priv
->num_pipe
= 1;
1556 ret
= drm_vblank_init(dev
, dev_priv
->num_pipe
);
1558 goto out_gem_unload
;
1560 /* Start out suspended */
1561 dev_priv
->mm
.suspended
= 1;
1563 intel_detect_pch(dev
);
1565 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1566 ret
= i915_load_modeset_init(dev
);
1568 DRM_ERROR("failed to init modeset\n");
1569 goto out_gem_unload
;
1573 i915_setup_sysfs(dev
);
1575 /* Must be done after probing outputs */
1576 intel_opregion_init(dev
);
1577 acpi_video_register();
1579 setup_timer(&dev_priv
->hangcheck_timer
, i915_hangcheck_elapsed
,
1580 (unsigned long) dev
);
1583 intel_gpu_ips_init(dev_priv
);
1588 if (dev_priv
->mm
.inactive_shrinker
.shrink
)
1589 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1591 if (dev
->pdev
->msi_enabled
)
1592 pci_disable_msi(dev
->pdev
);
1594 intel_teardown_gmbus(dev
);
1595 intel_teardown_mchbar(dev
);
1596 destroy_workqueue(dev_priv
->wq
);
1598 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1599 mtrr_del(dev_priv
->mm
.gtt_mtrr
, dev
->agp
->base
,
1600 dev
->agp
->agp_info
.aper_size
* 1024 * 1024);
1601 dev_priv
->mm
.gtt_mtrr
= -1;
1603 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1605 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1607 pci_dev_put(dev_priv
->bridge_dev
);
1613 int i915_driver_unload(struct drm_device
*dev
)
1615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1618 intel_gpu_ips_teardown();
1620 i915_teardown_sysfs(dev
);
1622 if (dev_priv
->mm
.inactive_shrinker
.shrink
)
1623 unregister_shrinker(&dev_priv
->mm
.inactive_shrinker
);
1625 mutex_lock(&dev
->struct_mutex
);
1626 ret
= i915_gpu_idle(dev
);
1628 DRM_ERROR("failed to idle hardware: %d\n", ret
);
1629 i915_gem_retire_requests(dev
);
1630 mutex_unlock(&dev
->struct_mutex
);
1632 /* Cancel the retire work handler, which should be idle now. */
1633 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
1635 io_mapping_free(dev_priv
->mm
.gtt_mapping
);
1636 if (dev_priv
->mm
.gtt_mtrr
>= 0) {
1637 mtrr_del(dev_priv
->mm
.gtt_mtrr
, dev
->agp
->base
,
1638 dev
->agp
->agp_info
.aper_size
* 1024 * 1024);
1639 dev_priv
->mm
.gtt_mtrr
= -1;
1642 acpi_video_unregister();
1644 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1645 intel_fbdev_fini(dev
);
1646 intel_modeset_cleanup(dev
);
1649 * free the memory space allocated for the child device
1650 * config parsed from VBT
1652 if (dev_priv
->child_dev
&& dev_priv
->child_dev_num
) {
1653 kfree(dev_priv
->child_dev
);
1654 dev_priv
->child_dev
= NULL
;
1655 dev_priv
->child_dev_num
= 0;
1658 vga_switcheroo_unregister_client(dev
->pdev
);
1659 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1662 /* Free error state after interrupts are fully disabled. */
1663 del_timer_sync(&dev_priv
->hangcheck_timer
);
1664 cancel_work_sync(&dev_priv
->error_work
);
1665 i915_destroy_error_state(dev
);
1667 if (dev
->pdev
->msi_enabled
)
1668 pci_disable_msi(dev
->pdev
);
1670 intel_opregion_fini(dev
);
1672 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1673 /* Flush any outstanding unpin_work. */
1674 flush_workqueue(dev_priv
->wq
);
1676 mutex_lock(&dev
->struct_mutex
);
1677 i915_gem_free_all_phys_object(dev
);
1678 i915_gem_cleanup_ringbuffer(dev
);
1679 mutex_unlock(&dev
->struct_mutex
);
1680 i915_gem_cleanup_aliasing_ppgtt(dev
);
1681 i915_gem_cleanup_stolen(dev
);
1682 drm_mm_takedown(&dev_priv
->mm
.stolen
);
1684 intel_cleanup_overlay(dev
);
1686 if (!I915_NEED_GFX_HWS(dev
))
1690 if (dev_priv
->regs
!= NULL
)
1691 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1693 intel_teardown_gmbus(dev
);
1694 intel_teardown_mchbar(dev
);
1696 destroy_workqueue(dev_priv
->wq
);
1698 pci_dev_put(dev_priv
->bridge_dev
);
1699 kfree(dev
->dev_private
);
1704 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1706 struct drm_i915_file_private
*file_priv
;
1708 DRM_DEBUG_DRIVER("\n");
1709 file_priv
= kmalloc(sizeof(*file_priv
), GFP_KERNEL
);
1713 file
->driver_priv
= file_priv
;
1715 spin_lock_init(&file_priv
->mm
.lock
);
1716 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
1722 * i915_driver_lastclose - clean up after all DRM clients have exited
1725 * Take care of cleaning up after all DRM clients have exited. In the
1726 * mode setting case, we want to restore the kernel's initial mode (just
1727 * in case the last client left us in a bad state).
1729 * Additionally, in the non-mode setting case, we'll tear down the GTT
1730 * and DMA structures, since the kernel won't be using them, and clea
1733 void i915_driver_lastclose(struct drm_device
* dev
)
1735 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1737 if (!dev_priv
|| drm_core_check_feature(dev
, DRIVER_MODESET
)) {
1738 intel_fb_restore_mode(dev
);
1739 vga_switcheroo_process_delayed_switch();
1743 i915_gem_lastclose(dev
);
1745 i915_dma_cleanup(dev
);
1748 void i915_driver_preclose(struct drm_device
* dev
, struct drm_file
*file_priv
)
1750 i915_gem_release(dev
, file_priv
);
1753 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1755 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1760 struct drm_ioctl_desc i915_ioctls
[] = {
1761 DRM_IOCTL_DEF_DRV(I915_INIT
, i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1762 DRM_IOCTL_DEF_DRV(I915_FLUSH
, i915_flush_ioctl
, DRM_AUTH
),
1763 DRM_IOCTL_DEF_DRV(I915_FLIP
, i915_flip_bufs
, DRM_AUTH
),
1764 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, i915_batchbuffer
, DRM_AUTH
),
1765 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, i915_irq_emit
, DRM_AUTH
),
1766 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, i915_irq_wait
, DRM_AUTH
),
1767 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
),
1768 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1769 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1770 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1771 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1772 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, i915_cmdbuffer
, DRM_AUTH
),
1773 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1774 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1775 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, i915_vblank_pipe_get
, DRM_AUTH
),
1776 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, i915_vblank_swap
, DRM_AUTH
),
1777 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, i915_set_status_page
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1778 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, i915_gem_init_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1779 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1780 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
),
1781 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1782 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_unpin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1783 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
1784 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
),
1785 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, i915_gem_entervt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1786 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, i915_gem_leavevt_ioctl
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1787 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
),
1788 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
),
1789 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
),
1790 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
),
1791 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
),
1792 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
),
1793 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
),
1794 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
),
1795 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
),
1796 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
),
1797 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1798 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
),
1799 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1800 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1801 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1802 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, intel_sprite_get_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1805 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
1808 * This is really ugly: Because old userspace abused the linux agp interface to
1809 * manage the gtt, we need to claim that all intel devices are agp. For
1810 * otherwise the drm core refuses to initialize the agp support code.
1812 int i915_driver_device_is_agp(struct drm_device
* dev
)