2 * linux/drivers/clocksource/acpi_pm.c
4 * This file contains the ACPI PM based clocksource.
6 * This code was largely moved from the i386 timer_pm.c file
7 * which was (C) Dominik Brodowski <linux@brodo.de> 2003
8 * and contained the following comments:
10 * Driver to use the Power Management Timer (PMTMR) available in some
11 * southbridges as primary timing source for the Linux kernel.
13 * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
14 * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
16 * This file is licensed under the GPL v2.
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clocksource.h>
21 #include <linux/timex.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
29 * The I/O port the PMTMR resides at.
30 * The location is detected during setup_arch(),
31 * in arch/i386/kernel/acpi/boot.c
33 u32 pmtmr_ioport __read_mostly
;
35 static inline u32
read_pmtmr(void)
37 /* mask the output to 24 bits */
38 return inl(pmtmr_ioport
) & ACPI_PM_MASK
;
41 u32
acpi_pm_read_verified(void)
43 u32 v1
= 0, v2
= 0, v3
= 0;
46 * It has been reported that because of various broken
47 * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
48 * source is not latched, you must read it multiple
49 * times to ensure a safe value is read:
55 } while (unlikely((v1
> v2
&& v1
< v3
) || (v2
> v3
&& v2
< v1
)
56 || (v3
> v1
&& v3
< v2
)));
61 static cycle_t
acpi_pm_read(struct clocksource
*cs
)
63 return (cycle_t
)read_pmtmr();
66 static struct clocksource clocksource_acpi_pm
= {
70 .mask
= (cycle_t
)ACPI_PM_MASK
,
71 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
76 static int __devinitdata acpi_pm_good
;
77 static int __init
acpi_pm_good_setup(char *__str
)
82 __setup("acpi_pm_good", acpi_pm_good_setup
);
84 static cycle_t
acpi_pm_read_slow(struct clocksource
*cs
)
86 return (cycle_t
)acpi_pm_read_verified();
89 static inline void acpi_pm_need_workaround(void)
91 clocksource_acpi_pm
.read
= acpi_pm_read_slow
;
92 clocksource_acpi_pm
.rating
= 120;
98 * The power management timer may return improper results when read.
99 * Although the timer value settles properly after incrementing,
100 * while incrementing there is a 3 ns window every 69.8 ns where the
101 * timer value is indeterminate (a 4.2% chance that the data will be
102 * incorrect when read). As a result, the ACPI free running count up
103 * timer specification is violated due to erroneous reads.
105 static void __devinit
acpi_pm_check_blacklist(struct pci_dev
*dev
)
110 /* the bug has been fixed in PIIX4M */
111 if (dev
->revision
< 3) {
112 printk(KERN_WARNING
"* Found PM-Timer Bug on the chipset."
113 " Due to workarounds for a bug,\n"
114 "* this clock source is slow. Consider trying"
115 " other clock sources\n");
117 acpi_pm_need_workaround();
120 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
,
121 acpi_pm_check_blacklist
);
123 static void __devinit
acpi_pm_check_graylist(struct pci_dev
*dev
)
128 printk(KERN_WARNING
"* The chipset may have PM-Timer Bug. Due to"
129 " workarounds for a bug,\n"
130 "* this clock source is slow. If you are sure your timer"
132 "* this bug, please use \"acpi_pm_good\" to disable the"
135 acpi_pm_need_workaround();
137 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
,
138 acpi_pm_check_graylist
);
139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_LE
,
140 acpi_pm_check_graylist
);
143 #ifndef CONFIG_X86_64
144 #include <asm/mach_timer.h>
145 #define PMTMR_EXPECTED_RATE \
146 ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
148 * Some boards have the PMTMR running way too fast. We check
149 * the PMTMR rate against PIT channel 2 to catch these cases.
151 static int verify_pmtmr_rate(void)
153 cycle_t value1
, value2
;
154 unsigned long count
, delta
;
156 mach_prepare_counter();
157 value1
= clocksource_acpi_pm
.read(&clocksource_acpi_pm
);
158 mach_countup(&count
);
159 value2
= clocksource_acpi_pm
.read(&clocksource_acpi_pm
);
160 delta
= (value2
- value1
) & ACPI_PM_MASK
;
162 /* Check that the PMTMR delta is within 5% of what we expect */
163 if (delta
< (PMTMR_EXPECTED_RATE
* 19) / 20 ||
164 delta
> (PMTMR_EXPECTED_RATE
* 21) / 20) {
165 printk(KERN_INFO
"PM-Timer running at invalid rate: %lu%% "
166 "of normal - aborting.\n",
167 100UL * delta
/ PMTMR_EXPECTED_RATE
);
174 #define verify_pmtmr_rate() (0)
177 /* Number of monotonicity checks to perform during initialization */
178 #define ACPI_PM_MONOTONICITY_CHECKS 10
179 /* Number of reads we try to get two different values */
180 #define ACPI_PM_READ_CHECKS 10000
182 static int __init
init_acpi_pm_clocksource(void)
184 cycle_t value1
, value2
;
185 unsigned int i
, j
= 0;
190 /* "verify" this timing source: */
191 for (j
= 0; j
< ACPI_PM_MONOTONICITY_CHECKS
; j
++) {
193 value1
= clocksource_acpi_pm
.read(&clocksource_acpi_pm
);
194 for (i
= 0; i
< ACPI_PM_READ_CHECKS
; i
++) {
195 value2
= clocksource_acpi_pm
.read(&clocksource_acpi_pm
);
196 if (value2
== value1
)
200 if ((value2
< value1
) && ((value2
) < 0xFFF))
202 printk(KERN_INFO
"PM-Timer had inconsistent results:"
203 " 0x%#llx, 0x%#llx - aborting.\n",
208 if (i
== ACPI_PM_READ_CHECKS
) {
209 printk(KERN_INFO
"PM-Timer failed consistency check "
210 " (0x%#llx) - aborting.\n", value1
);
216 if (verify_pmtmr_rate() != 0){
221 return clocksource_register_hz(&clocksource_acpi_pm
,
222 PMTMR_TICKS_PER_SEC
);
225 /* We use fs_initcall because we want the PCI fixups to have run
226 * but we still need to load before device_initcall
228 fs_initcall(init_acpi_pm_clocksource
);
231 * Allow an override of the IOPort. Stupid BIOSes do not tell us about
232 * the PMTimer, but we might know where it is.
234 static int __init
parse_pmtmr(char *arg
)
238 if (strict_strtoul(arg
, 16, &base
))
244 printk(KERN_INFO
"PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
250 __setup("pmtmr=", parse_pmtmr
);