2 * Debug Store (DS) support
4 * This provides a low-level interface to the hardware's Debug Store
5 * feature that is used for last branch recording (LBR) and
6 * precise-event based sampling (PEBS).
8 * Different architectures use a different DS layout/pointer size.
9 * The below functions therefore work on a void*.
12 * Since there is no user for PEBS, yet, only LBR (or branch
13 * trace store, BTS) is supported.
16 * Copyright (C) 2007 Intel Corporation.
17 * Markus Metzger <markus.t.metzger@intel.com>, Dec 2007
23 #include <linux/types.h>
24 #include <linux/init.h>
29 /* a branch trace record entry
31 * In order to unify the interface between various processor versions,
32 * we use the below data structure for all processors.
49 /* BTS_TASK_ARRIVES or
55 /* Overflow handling mechanisms */
56 #define DS_O_SIGNAL 1 /* send overflow signal */
57 #define DS_O_WRAP 2 /* wrap around */
59 extern int ds_allocate(void **, size_t);
60 extern int ds_free(void **);
61 extern int ds_get_bts_size(void *);
62 extern int ds_get_bts_end(void *);
63 extern int ds_get_bts_index(void *);
64 extern int ds_set_overflow(void *, int);
65 extern int ds_get_overflow(void *);
66 extern int ds_clear(void *);
67 extern int ds_read_bts(void *, int, struct bts_struct
*);
68 extern int ds_write_bts(void *, const struct bts_struct
*);
69 extern unsigned long ds_debugctl_mask(void);
70 extern void __cpuinit
ds_init_intel(struct cpuinfo_x86
*c
);
72 #endif /* _ASM_X86_DS_H */