arch/arm/mach-davinci/irq.c

   1 /*
   2  * Interrupt handler for DaVinci boards.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/hardware.h>
  28 #include <mach/cputype.h>
  29 #include <asm/mach/irq.h>
  30
  31 #define IRQ_BIT(irq)            ((irq) & 0x1f)
  32
  33 #define FIQ_REG0_OFFSET         0x0000
  34 #define FIQ_REG1_OFFSET         0x0004
  35 #define IRQ_REG0_OFFSET         0x0008
  36 #define IRQ_REG1_OFFSET         0x000C
  37 #define IRQ_ENT_REG0_OFFSET     0x0018
  38 #define IRQ_ENT_REG1_OFFSET     0x001C
  39 #define IRQ_INCTL_REG_OFFSET    0x0020
  40 #define IRQ_EABASE_REG_OFFSET   0x0024
  41 #define IRQ_INTPRI0_REG_OFFSET  0x0030
  42 #define IRQ_INTPRI7_REG_OFFSET  0x004C
  43
  44 const u8 *davinci_def_priorities;
  45
  46 #define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
  47
  48 static inline unsigned int davinci_irq_readl(int offset)
  49 {
  50         return __raw_readl(INTC_BASE + offset);
  51 }
  52
  53 static inline void davinci_irq_writel(unsigned long value, int offset)
  54 {
  55         __raw_writel(value, INTC_BASE + offset);
  56 }
  57
  58 /* Disable interrupt */
  59 static void davinci_mask_irq(unsigned int irq)
  60 {
  61         unsigned int mask;
  62         u32 l;
  63
  64         mask = 1 << IRQ_BIT(irq);
  65
  66         if (irq > 31) {
  67                 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
  68                 l &= ~mask;
  69                 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
  70         } else {
  71                 l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
  72                 l &= ~mask;
  73                 davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
  74         }
  75 }
  76
  77 /* Enable interrupt */
  78 static void davinci_unmask_irq(unsigned int irq)
  79 {
  80         unsigned int mask;
  81         u32 l;
  82
  83         mask = 1 << IRQ_BIT(irq);
  84
  85         if (irq > 31) {
  86                 l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
  87                 l |= mask;
  88                 davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
  89         } else {
  90                 l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
  91                 l |= mask;
  92                 davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
  93         }
  94 }
  95
  96 /* EOI interrupt */
  97 static void davinci_ack_irq(unsigned int irq)
  98 {
  99         unsigned int mask;
 100
 101         mask = 1 << IRQ_BIT(irq);
 102
 103         if (irq > 31)
 104                 davinci_irq_writel(mask, IRQ_REG1_OFFSET);
 105         else
 106                 davinci_irq_writel(mask, IRQ_REG0_OFFSET);
 107 }
 108
 109 static struct irq_chip davinci_irq_chip_0 = {
 110         .name   = "AINTC",
 111         .ack    = davinci_ack_irq,
 112         .mask   = davinci_mask_irq,
 113         .unmask = davinci_unmask_irq,
 114 };
 115
 116 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 117 static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
 118         [IRQ_VDINT0]            = 2,
 119         [IRQ_VDINT1]            = 6,
 120         [IRQ_VDINT2]            = 6,
 121         [IRQ_HISTINT]           = 6,
 122         [IRQ_H3AINT]            = 6,
 123         [IRQ_PRVUINT]           = 6,
 124         [IRQ_RSZINT]            = 6,
 125         [7]                     = 7,
 126         [IRQ_VENCINT]           = 6,
 127         [IRQ_ASQINT]            = 6,
 128         [IRQ_IMXINT]            = 6,
 129         [IRQ_VLCDINT]           = 6,
 130         [IRQ_USBINT]            = 4,
 131         [IRQ_EMACINT]           = 4,
 132         [14]                    = 7,
 133         [15]                    = 7,
 134         [IRQ_CCINT0]            = 5,    /* dma */
 135         [IRQ_CCERRINT]          = 5,    /* dma */
 136         [IRQ_TCERRINT0]         = 5,    /* dma */
 137         [IRQ_TCERRINT]          = 5,    /* dma */
 138         [IRQ_PSCIN]             = 7,
 139         [21]                    = 7,
 140         [IRQ_IDE]               = 4,
 141         [23]                    = 7,
 142         [IRQ_MBXINT]            = 7,
 143         [IRQ_MBRINT]            = 7,
 144         [IRQ_MMCINT]            = 7,
 145         [IRQ_SDIOINT]           = 7,
 146         [28]                    = 7,
 147         [IRQ_DDRINT]            = 7,
 148         [IRQ_AEMIFINT]          = 7,
 149         [IRQ_VLQINT]            = 4,
 150         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 151         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 152         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 153         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 154         [IRQ_PWMINT0]           = 7,
 155         [IRQ_PWMINT1]           = 7,
 156         [IRQ_PWMINT2]           = 7,
 157         [IRQ_I2C]               = 3,
 158         [IRQ_UARTINT0]          = 3,
 159         [IRQ_UARTINT1]          = 3,
 160         [IRQ_UARTINT2]          = 3,
 161         [IRQ_SPINT0]            = 3,
 162         [IRQ_SPINT1]            = 3,
 163         [45]                    = 7,
 164         [IRQ_DSP2ARM0]          = 4,
 165         [IRQ_DSP2ARM1]          = 4,
 166         [IRQ_GPIO0]             = 7,
 167         [IRQ_GPIO1]             = 7,
 168         [IRQ_GPIO2]             = 7,
 169         [IRQ_GPIO3]             = 7,
 170         [IRQ_GPIO4]             = 7,
 171         [IRQ_GPIO5]             = 7,
 172         [IRQ_GPIO6]             = 7,
 173         [IRQ_GPIO7]             = 7,
 174         [IRQ_GPIOBNK0]          = 7,
 175         [IRQ_GPIOBNK1]          = 7,
 176         [IRQ_GPIOBNK2]          = 7,
 177         [IRQ_GPIOBNK3]          = 7,
 178         [IRQ_GPIOBNK4]          = 7,
 179         [IRQ_COMMTX]            = 7,
 180         [IRQ_COMMRX]            = 7,
 181         [IRQ_EMUINT]            = 7,
 182 };
 183
 184 static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 185         [IRQ_DM646X_VP_VERTINT0]        = 7,
 186         [IRQ_DM646X_VP_VERTINT1]        = 7,
 187         [IRQ_DM646X_VP_VERTINT2]        = 7,
 188         [IRQ_DM646X_VP_VERTINT3]        = 7,
 189         [IRQ_DM646X_VP_ERRINT]          = 7,
 190         [IRQ_DM646X_RESERVED_1]         = 7,
 191         [IRQ_DM646X_RESERVED_2]         = 7,
 192         [IRQ_DM646X_WDINT]              = 7,
 193         [IRQ_DM646X_CRGENINT0]          = 7,
 194         [IRQ_DM646X_CRGENINT1]          = 7,
 195         [IRQ_DM646X_TSIFINT0]           = 7,
 196         [IRQ_DM646X_TSIFINT1]           = 7,
 197         [IRQ_DM646X_VDCEINT]            = 7,
 198         [IRQ_DM646X_USBINT]             = 7,
 199         [IRQ_DM646X_USBDMAINT]          = 7,
 200         [IRQ_DM646X_PCIINT]             = 7,
 201         [IRQ_CCINT0]                    = 7,    /* dma */
 202         [IRQ_CCERRINT]                  = 7,    /* dma */
 203         [IRQ_TCERRINT0]                 = 7,    /* dma */
 204         [IRQ_TCERRINT]                  = 7,    /* dma */
 205         [IRQ_DM646X_TCERRINT2]          = 7,
 206         [IRQ_DM646X_TCERRINT3]          = 7,
 207         [IRQ_DM646X_IDE]                = 7,
 208         [IRQ_DM646X_HPIINT]             = 7,
 209         [IRQ_DM646X_EMACRXTHINT]        = 7,
 210         [IRQ_DM646X_EMACRXINT]          = 7,
 211         [IRQ_DM646X_EMACTXINT]          = 7,
 212         [IRQ_DM646X_EMACMISCINT]        = 7,
 213         [IRQ_DM646X_MCASP0TXINT]        = 7,
 214         [IRQ_DM646X_MCASP0RXINT]        = 7,
 215         [IRQ_AEMIFINT]                  = 7,
 216         [IRQ_DM646X_RESERVED_3]         = 7,
 217         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 218         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 219         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 220         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 221         [IRQ_PWMINT0]                   = 7,
 222         [IRQ_PWMINT1]                   = 7,
 223         [IRQ_DM646X_VLQINT]             = 7,
 224         [IRQ_I2C]                       = 7,
 225         [IRQ_UARTINT0]                  = 7,
 226         [IRQ_UARTINT1]                  = 7,
 227         [IRQ_DM646X_UARTINT2]           = 7,
 228         [IRQ_DM646X_SPINT0]             = 7,
 229         [IRQ_DM646X_SPINT1]             = 7,
 230         [IRQ_DM646X_DSP2ARMINT]         = 7,
 231         [IRQ_DM646X_RESERVED_4]         = 7,
 232         [IRQ_DM646X_PSCINT]             = 7,
 233         [IRQ_DM646X_GPIO0]              = 7,
 234         [IRQ_DM646X_GPIO1]              = 7,
 235         [IRQ_DM646X_GPIO2]              = 7,
 236         [IRQ_DM646X_GPIO3]              = 7,
 237         [IRQ_DM646X_GPIO4]              = 7,
 238         [IRQ_DM646X_GPIO5]              = 7,
 239         [IRQ_DM646X_GPIO6]              = 7,
 240         [IRQ_DM646X_GPIO7]              = 7,
 241         [IRQ_DM646X_GPIOBNK0]           = 7,
 242         [IRQ_DM646X_GPIOBNK1]           = 7,
 243         [IRQ_DM646X_GPIOBNK2]           = 7,
 244         [IRQ_DM646X_DDRINT]             = 7,
 245         [IRQ_DM646X_AEMIFINT]           = 7,
 246         [IRQ_COMMTX]                    = 7,
 247         [IRQ_COMMRX]                    = 7,
 248         [IRQ_EMUINT]                    = 7,
 249 };
 250
 251 static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 252         [IRQ_DM355_CCDC_VDINT0]         = 2,
 253         [IRQ_DM355_CCDC_VDINT1]         = 6,
 254         [IRQ_DM355_CCDC_VDINT2]         = 6,
 255         [IRQ_DM355_IPIPE_HST]           = 6,
 256         [IRQ_DM355_H3AINT]              = 6,
 257         [IRQ_DM355_IPIPE_SDR]           = 6,
 258         [IRQ_DM355_IPIPEIFINT]          = 6,
 259         [IRQ_DM355_OSDINT]              = 7,
 260         [IRQ_DM355_VENCINT]             = 6,
 261         [IRQ_ASQINT]                    = 6,
 262         [IRQ_IMXINT]                    = 6,
 263         [IRQ_USBINT]                    = 4,
 264         [IRQ_DM355_RTOINT]              = 4,
 265         [IRQ_DM355_UARTINT2]            = 7,
 266         [IRQ_DM355_TINT6]               = 7,
 267         [IRQ_CCINT0]                    = 5,    /* dma */
 268         [IRQ_CCERRINT]                  = 5,    /* dma */
 269         [IRQ_TCERRINT0]                 = 5,    /* dma */
 270         [IRQ_TCERRINT]                  = 5,    /* dma */
 271         [IRQ_DM355_SPINT2_1]            = 7,
 272         [IRQ_DM355_TINT7]               = 4,
 273         [IRQ_DM355_SDIOINT0]            = 7,
 274         [IRQ_MBXINT]                    = 7,
 275         [IRQ_MBRINT]                    = 7,
 276         [IRQ_MMCINT]                    = 7,
 277         [IRQ_DM355_MMCINT1]             = 7,
 278         [IRQ_DM355_PWMINT3]             = 7,
 279         [IRQ_DDRINT]                    = 7,
 280         [IRQ_AEMIFINT]                  = 7,
 281         [IRQ_DM355_SDIOINT1]            = 4,
 282         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 283         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 284         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 285         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 286         [IRQ_PWMINT0]                   = 7,
 287         [IRQ_PWMINT1]                   = 7,
 288         [IRQ_PWMINT2]                   = 7,
 289         [IRQ_I2C]                       = 3,
 290         [IRQ_UARTINT0]                  = 3,
 291         [IRQ_UARTINT1]                  = 3,
 292         [IRQ_DM355_SPINT0_0]            = 3,
 293         [IRQ_DM355_SPINT0_1]            = 3,
 294         [IRQ_DM355_GPIO0]               = 3,
 295         [IRQ_DM355_GPIO1]               = 7,
 296         [IRQ_DM355_GPIO2]               = 4,
 297         [IRQ_DM355_GPIO3]               = 4,
 298         [IRQ_DM355_GPIO4]               = 7,
 299         [IRQ_DM355_GPIO5]               = 7,
 300         [IRQ_DM355_GPIO6]               = 7,
 301         [IRQ_DM355_GPIO7]               = 7,
 302         [IRQ_DM355_GPIO8]               = 7,
 303         [IRQ_DM355_GPIO9]               = 7,
 304         [IRQ_DM355_GPIOBNK0]            = 7,
 305         [IRQ_DM355_GPIOBNK1]            = 7,
 306         [IRQ_DM355_GPIOBNK2]            = 7,
 307         [IRQ_DM355_GPIOBNK3]            = 7,
 308         [IRQ_DM355_GPIOBNK4]            = 7,
 309         [IRQ_DM355_GPIOBNK5]            = 7,
 310         [IRQ_DM355_GPIOBNK6]            = 7,
 311         [IRQ_COMMTX]                    = 7,
 312         [IRQ_COMMRX]                    = 7,
 313         [IRQ_EMUINT]                    = 7,
 314 };
 315
 316 /* ARM Interrupt Controller Initialization */
 317 void __init davinci_irq_init(void)
 318 {
 319         unsigned i;
 320
 321         if (cpu_is_davinci_dm644x())
 322                 davinci_def_priorities = dm644x_default_priorities;
 323         else if (cpu_is_davinci_dm646x())
 324                 davinci_def_priorities = dm646x_default_priorities;
 325         else if (cpu_is_davinci_dm355())
 326                 davinci_def_priorities = dm355_default_priorities;
 327
 328         /* Clear all interrupt requests */
 329         davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 330         davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
 331         davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
 332         davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 333
 334         /* Disable all interrupts */
 335         davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
 336         davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
 337
 338         /* Interrupts disabled immediately, IRQ entry reflects all */
 339         davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
 340
 341         /* we don't use the hardware vector table, just its entry addresses */
 342         davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
 343
 344         /* Clear all interrupt requests */
 345         davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 346         davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
 347         davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
 348         davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 349
 350         for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
 351                 unsigned        j;
 352                 u32             pri;
 353
 354                 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
 355                         pri |= (*davinci_def_priorities & 0x07) << j;
 356                 davinci_irq_writel(pri, i);
 357         }
 358
 359         /* set up genirq dispatch for ARM INTC */
 360         for (i = 0; i < DAVINCI_N_AINTC_IRQ; i++) {
 361                 set_irq_chip(i, &davinci_irq_chip_0);
 362                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 363                 if (i != IRQ_TINT1_TINT34)
 364                         set_irq_handler(i, handle_edge_irq);
 365                 else
 366                         set_irq_handler(i, handle_level_irq);
 367         }
 368 }