arch/arm/mach-davinci/gpio.c

   1 /*
   2  * TI DaVinci GPIO Support
   3  *
   4  * Copyright (c) 2006-2007 David Brownell
   5  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/list.h>
  16 #include <linux/module.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/bitops.h>
  22
  23 #include <mach/cputype.h>
  24 #include <mach/irqs.h>
  25 #include <mach/hardware.h>
  26 #include <mach/gpio.h>
  27
  28 #include <asm/mach/irq.h>
  29
  30
  31 static DEFINE_SPINLOCK(gpio_lock);
  32
  33 struct davinci_gpio {
  34         struct gpio_chip        chip;
  35         struct gpio_controller  *__iomem regs;
  36 };
  37
  38 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
  39
  40 static unsigned __initdata ngpio;
  41
  42 /* create a non-inlined version */
  43 static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
  44 {
  45         return __gpio_to_controller(gpio);
  46 }
  47
  48
  49 /*--------------------------------------------------------------------------*/
  50
  51 /*
  52  * board setup code *MUST* set PINMUX0 and PINMUX1 as
  53  * needed, and enable the GPIO clock.
  54  */
  55
  56 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
  57 {
  58         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  59         struct gpio_controller *__iomem g = d->regs;
  60         u32 temp;
  61
  62         spin_lock(&gpio_lock);
  63         temp = __raw_readl(&g->dir);
  64         temp |= (1 << offset);
  65         __raw_writel(temp, &g->dir);
  66         spin_unlock(&gpio_lock);
  67
  68         return 0;
  69 }
  70
  71 /*
  72  * Read the pin's value (works even if it's set up as output);
  73  * returns zero/nonzero.
  74  *
  75  * Note that changes are synched to the GPIO clock, so reading values back
  76  * right after you've set them may give old values.
  77  */
  78 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
  79 {
  80         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  81         struct gpio_controller *__iomem g = d->regs;
  82
  83         return (1 << offset) & __raw_readl(&g->in_data);
  84 }
  85
  86 static int
  87 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
  88 {
  89         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
  90         struct gpio_controller *__iomem g = d->regs;
  91         u32 temp;
  92         u32 mask = 1 << offset;
  93
  94         spin_lock(&gpio_lock);
  95         temp = __raw_readl(&g->dir);
  96         temp &= ~mask;
  97         __raw_writel(mask, value ? &g->set_data : &g->clr_data);
  98         __raw_writel(temp, &g->dir);
  99         spin_unlock(&gpio_lock);
 100         return 0;
 101 }
 102
 103 /*
 104  * Assuming the pin is muxed as a gpio output, set its output value.
 105  */
 106 static void
 107 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 108 {
 109         struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
 110         struct gpio_controller *__iomem g = d->regs;
 111
 112         __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 113 }
 114
 115 static int __init davinci_gpio_setup(void)
 116 {
 117         int i, base;
 118
 119         /* The gpio banks conceptually expose a segmented bitmap,
 120          * and "ngpio" is one more than the largest zero-based
 121          * bit index that's valid.
 122          */
 123         if (cpu_is_davinci_dm355()) {           /* or dm335() */
 124                 ngpio = 104;
 125         } else if (cpu_is_davinci_dm644x()) {   /* or dm337() */
 126                 ngpio = 71;
 127         } else if (cpu_is_davinci_dm646x()) {
 128                 /* NOTE:  each bank has several "reserved" bits,
 129                  * unusable as GPIOs.  Only 33 of the GPIO numbers
 130                  * are usable, and we're not rejecting the others.
 131                  */
 132                 ngpio = 43;
 133         } else {
 134                 /* if cpu_is_davinci_dm643x() ngpio = 111 */
 135                 pr_err("GPIO setup:  how many GPIOs?\n");
 136                 return -EINVAL;
 137         }
 138
 139         if (WARN_ON(DAVINCI_N_GPIO < ngpio))
 140                 ngpio = DAVINCI_N_GPIO;
 141
 142         for (i = 0, base = 0; base < ngpio; i++, base += 32) {
 143                 chips[i].chip.label = "DaVinci";
 144
 145                 chips[i].chip.direction_input = davinci_direction_in;
 146                 chips[i].chip.get = davinci_gpio_get;
 147                 chips[i].chip.direction_output = davinci_direction_out;
 148                 chips[i].chip.set = davinci_gpio_set;
 149
 150                 chips[i].chip.base = base;
 151                 chips[i].chip.ngpio = ngpio - base;
 152                 if (chips[i].chip.ngpio > 32)
 153                         chips[i].chip.ngpio = 32;
 154
 155                 chips[i].regs = gpio2controller(base);
 156
 157                 gpiochip_add(&chips[i].chip);
 158         }
 159
 160         return 0;
 161 }
 162 pure_initcall(davinci_gpio_setup);
 163
 164 /*--------------------------------------------------------------------------*/
 165 /*
 166  * We expect irqs will normally be set up as input pins, but they can also be
 167  * used as output pins ... which is convenient for testing.
 168  *
 169  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 170  * to their GPIOBNK0 irq, with a bit less overhead but less flexibility
 171  * on triggering (e.g. no edge options).  We don't try to use those.
 172  *
 173  * All those INTC hookups (direct, plus several IRQ banks) can also
 174  * serve as EDMA event triggers.
 175  */
 176
 177 static void gpio_irq_disable(unsigned irq)
 178 {
 179         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 180         u32 mask = __gpio_mask(irq_to_gpio(irq));
 181
 182         __raw_writel(mask, &g->clr_falling);
 183         __raw_writel(mask, &g->clr_rising);
 184 }
 185
 186 static void gpio_irq_enable(unsigned irq)
 187 {
 188         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 189         u32 mask = __gpio_mask(irq_to_gpio(irq));
 190
 191         if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
 192                 __raw_writel(mask, &g->set_falling);
 193         if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
 194                 __raw_writel(mask, &g->set_rising);
 195 }
 196
 197 static int gpio_irq_type(unsigned irq, unsigned trigger)
 198 {
 199         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 200         u32 mask = __gpio_mask(irq_to_gpio(irq));
 201
 202         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 203                 return -EINVAL;
 204
 205         irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 206         irq_desc[irq].status |= trigger;
 207
 208         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
 209                      ? &g->set_falling : &g->clr_falling);
 210         __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
 211                      ? &g->set_rising : &g->clr_rising);
 212         return 0;
 213 }
 214
 215 static struct irq_chip gpio_irqchip = {
 216         .name           = "GPIO",
 217         .enable         = gpio_irq_enable,
 218         .disable        = gpio_irq_disable,
 219         .set_type       = gpio_irq_type,
 220 };
 221
 222 static void
 223 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 224 {
 225         struct gpio_controller *__iomem g = get_irq_chip_data(irq);
 226         u32 mask = 0xffff;
 227
 228         /* we only care about one bank */
 229         if (irq & 1)
 230                 mask <<= 16;
 231
 232         /* temporarily mask (level sensitive) parent IRQ */
 233         desc->chip->ack(irq);
 234         while (1) {
 235                 u32             status;
 236                 int             n;
 237                 int             res;
 238
 239                 /* ack any irqs */
 240                 status = __raw_readl(&g->intstat) & mask;
 241                 if (!status)
 242                         break;
 243                 __raw_writel(status, &g->intstat);
 244                 if (irq & 1)
 245                         status >>= 16;
 246
 247                 /* now demux them to the right lowlevel handler */
 248                 n = (int)get_irq_data(irq);
 249                 while (status) {
 250                         res = ffs(status);
 251                         n += res;
 252                         generic_handle_irq(n - 1);
 253                         status >>= res;
 254                 }
 255         }
 256         desc->chip->unmask(irq);
 257         /* now it may re-trigger */
 258 }
 259
 260 /*
 261  * NOTE:  for suspend/resume, probably best to make a platform_device with
 262  * suspend_late/resume_resume calls hooking into results of the set_wake()
 263  * calls ... so if no gpios are wakeup events the clock can be disabled,
 264  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 265  * (dm6446) can be set appropriately for GPIOV33 pins.
 266  */
 267
 268 static int __init davinci_gpio_irq_setup(void)
 269 {
 270         unsigned        gpio, irq, bank;
 271         unsigned        bank_irq;
 272         struct clk      *clk;
 273         u32             binten = 0;
 274
 275         if (cpu_is_davinci_dm355()) {           /* or dm335() */
 276                 bank_irq = IRQ_DM355_GPIOBNK0;
 277         } else if (cpu_is_davinci_dm644x()) {
 278                 bank_irq = IRQ_GPIOBNK0;
 279         } else if (cpu_is_davinci_dm646x()) {
 280                 bank_irq = IRQ_DM646X_GPIOBNK0;
 281         } else {
 282                 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
 283                 return -EINVAL;
 284         }
 285
 286         clk = clk_get(NULL, "gpio");
 287         if (IS_ERR(clk)) {
 288                 printk(KERN_ERR "Error %ld getting gpio clock?\n",
 289                        PTR_ERR(clk));
 290                 return PTR_ERR(clk);
 291         }
 292         clk_enable(clk);
 293
 294         for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
 295                         gpio < ngpio;
 296                         bank++, bank_irq++) {
 297                 struct gpio_controller  *__iomem g = gpio2controller(gpio);
 298                 unsigned                i;
 299
 300                 __raw_writel(~0, &g->clr_falling);
 301                 __raw_writel(~0, &g->clr_rising);
 302
 303                 /* set up all irqs in this bank */
 304                 set_irq_chained_handler(bank_irq, gpio_irq_handler);
 305                 set_irq_chip_data(bank_irq, g);
 306                 set_irq_data(bank_irq, (void *)irq);
 307
 308                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 309                         set_irq_chip(irq, &gpio_irqchip);
 310                         set_irq_chip_data(irq, g);
 311                         set_irq_handler(irq, handle_simple_irq);
 312                         set_irq_flags(irq, IRQF_VALID);
 313                 }
 314
 315                 binten |= BIT(bank);
 316         }
 317
 318         /* BINTEN -- per-bank interrupt enable. genirq would also let these
 319          * bits be set/cleared dynamically.
 320          */
 321         __raw_writel(binten, (void *__iomem)
 322                      IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
 323
 324         printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
 325
 326         return 0;
 327 }
 328 arch_initcall(davinci_gpio_irq_setup);