2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * Intel D82875P Memory Controller kernel module
6 * (C) 2003 Linux Networx (http://lnxi.com)
8 * This file may be distributed under the terms of the
9 * GNU General Public License.
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/edac.h>
17 #include "edac_core.h"
19 #define I3000_REVISION "1.1"
21 #define EDAC_MOD_STR "i3000_edac"
24 #define I3000_RANKS_PER_CHANNEL 4
25 #define I3000_CHANNELS 2
27 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
29 #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
30 #define I3000_MCHBAR_MASK 0xffffc000
31 #define I3000_MMR_WINDOW_SIZE 16384
33 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
38 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
44 #define I3000_DEAP_GRAIN (1 << 7)
47 * Helper functions to decode the DEAP/EDEAP hardware registers.
49 * The type promotion here is deliberate; we're deriving an
50 * unsigned long pfn and offset from hardware regs which are u8/u32.
53 static inline unsigned long deap_pfn(u8 edeap
, u32 deap
)
56 deap
|= (edeap
& 1) << (32 - PAGE_SHIFT
);
60 static inline unsigned long deap_offset(u32 deap
)
62 return deap
& ~(I3000_DEAP_GRAIN
- 1) & ~PAGE_MASK
;
65 static inline int deap_channel(u32 deap
)
70 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
72 * 7:0 DRAM ECC Syndrome
75 #define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
78 * 11 MCH Thermal Sensor Event
81 * 9 LOCK to non-DRAM Memory Flag (LCKF)
82 * 8 Received Refresh Timeout Flag (RRTOF)
84 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
85 * 0 Single-bit DRAM ECC Error Flag (DSERR)
87 #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
88 #define I3000_ERRSTS_UE 0x0002
89 #define I3000_ERRSTS_CE 0x0001
91 #define I3000_ERRCMD 0xca /* Error Command (16b)
94 * 11 SERR on MCH Thermal Sensor Event
97 * 9 SERR on LOCK to non-DRAM Memory
99 * 8 SERR on DRAM Refresh Timeout
102 * 1 SERR Multi-Bit DRAM ECC Error
104 * 0 SERR on Single-Bit ECC Error
108 /* Intel MMIO register space - device 0 function 0 - MMR space */
110 #define I3000_DRB_SHIFT 25 /* 32MiB grain */
112 #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
114 * 7:0 Channel 0 DRAM Rank Boundary Address
116 #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
118 * 7:0 Channel 1 DRAM Rank Boundary Address
121 #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
124 * 6:4 DRAM odd Rank Attribute
126 * 2:0 DRAM even Rank Attribute
128 * Each attribute defines the page
129 * size of the corresponding rank:
137 #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
139 static inline unsigned char odd_rank_attrib(unsigned char dra
)
141 return (dra
& 0x70) >> 4;
144 static inline unsigned char even_rank_attrib(unsigned char dra
)
149 #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
152 * 29 Initialization Complete (IC)
154 * 10:8 Refresh Mode Select (RMS)
156 * 6:4 Mode Select (SMS)
161 #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
163 * 31 Enhanced Addressing Enable (ENHADE)
171 struct i3000_dev_info
{
172 const char *ctl_name
;
175 struct i3000_error_info
{
183 static const struct i3000_dev_info i3000_devs
[] = {
185 .ctl_name
= "i3000"},
188 static struct pci_dev
*mci_pdev
;
189 static int i3000_registered
= 1;
190 static struct edac_pci_ctl_info
*i3000_pci
;
192 static void i3000_get_error_info(struct mem_ctl_info
*mci
,
193 struct i3000_error_info
*info
)
195 struct pci_dev
*pdev
;
197 pdev
= to_pci_dev(mci
->dev
);
200 * This is a mess because there is no atomic way to read all the
201 * registers at once and the registers can transition from CE being
204 pci_read_config_word(pdev
, I3000_ERRSTS
, &info
->errsts
);
205 if (!(info
->errsts
& I3000_ERRSTS_BITS
))
207 pci_read_config_byte(pdev
, I3000_EDEAP
, &info
->edeap
);
208 pci_read_config_dword(pdev
, I3000_DEAP
, &info
->deap
);
209 pci_read_config_byte(pdev
, I3000_DERRSYN
, &info
->derrsyn
);
210 pci_read_config_word(pdev
, I3000_ERRSTS
, &info
->errsts2
);
213 * If the error is the same for both reads then the first set
214 * of reads is valid. If there is a change then there is a CE
215 * with no info and the second set of reads is valid and
218 if ((info
->errsts
^ info
->errsts2
) & I3000_ERRSTS_BITS
) {
219 pci_read_config_byte(pdev
, I3000_EDEAP
, &info
->edeap
);
220 pci_read_config_dword(pdev
, I3000_DEAP
, &info
->deap
);
221 pci_read_config_byte(pdev
, I3000_DERRSYN
, &info
->derrsyn
);
225 * Clear any error bits.
226 * (Yes, we really clear bits by writing 1 to them.)
228 pci_write_bits16(pdev
, I3000_ERRSTS
, I3000_ERRSTS_BITS
,
232 static int i3000_process_error_info(struct mem_ctl_info
*mci
,
233 struct i3000_error_info
*info
,
236 int row
, multi_chan
, channel
;
237 unsigned long pfn
, offset
;
239 multi_chan
= mci
->csrows
[0].nr_channels
- 1;
241 if (!(info
->errsts
& I3000_ERRSTS_BITS
))
247 if ((info
->errsts
^ info
->errsts2
) & I3000_ERRSTS_BITS
) {
248 edac_mc_handle_ce_no_info(mci
, "UE overwrote CE");
249 info
->errsts
= info
->errsts2
;
252 pfn
= deap_pfn(info
->edeap
, info
->deap
);
253 offset
= deap_offset(info
->deap
);
254 channel
= deap_channel(info
->deap
);
256 row
= edac_mc_find_csrow_by_page(mci
, pfn
);
258 if (info
->errsts
& I3000_ERRSTS_UE
)
259 edac_mc_handle_ue(mci
, pfn
, offset
, row
, "i3000 UE");
261 edac_mc_handle_ce(mci
, pfn
, offset
, info
->derrsyn
, row
,
262 multi_chan
? channel
: 0, "i3000 CE");
267 static void i3000_check(struct mem_ctl_info
*mci
)
269 struct i3000_error_info info
;
271 debugf1("MC%d: %s()\n", mci
->mc_idx
, __func__
);
272 i3000_get_error_info(mci
, &info
);
273 i3000_process_error_info(mci
, &info
, 1);
276 static int i3000_is_interleaved(const unsigned char *c0dra
,
277 const unsigned char *c1dra
,
278 const unsigned char *c0drb
,
279 const unsigned char *c1drb
)
284 * If the channels aren't populated identically then
285 * we're not interleaved.
287 for (i
= 0; i
< I3000_RANKS_PER_CHANNEL
/ 2; i
++)
288 if (odd_rank_attrib(c0dra
[i
]) != odd_rank_attrib(c1dra
[i
]) ||
289 even_rank_attrib(c0dra
[i
]) !=
290 even_rank_attrib(c1dra
[i
]))
294 * If the rank boundaries for the two channels are different
295 * then we're not interleaved.
297 for (i
= 0; i
< I3000_RANKS_PER_CHANNEL
; i
++)
298 if (c0drb
[i
] != c1drb
[i
])
304 static int i3000_probe1(struct pci_dev
*pdev
, int dev_idx
)
308 struct mem_ctl_info
*mci
= NULL
;
309 unsigned long last_cumul_size
;
310 int interleaved
, nr_channels
;
311 unsigned char dra
[I3000_RANKS
/ 2], drb
[I3000_RANKS
];
312 unsigned char *c0dra
= dra
, *c1dra
= &dra
[I3000_RANKS_PER_CHANNEL
/ 2];
313 unsigned char *c0drb
= drb
, *c1drb
= &drb
[I3000_RANKS_PER_CHANNEL
];
314 unsigned long mchbar
;
315 void __iomem
*window
;
317 debugf0("MC: %s()\n", __func__
);
319 pci_read_config_dword(pdev
, I3000_MCHBAR
, (u32
*) & mchbar
);
320 mchbar
&= I3000_MCHBAR_MASK
;
321 window
= ioremap_nocache(mchbar
, I3000_MMR_WINDOW_SIZE
);
323 printk(KERN_ERR
"i3000: cannot map mmio space at 0x%lx\n",
328 c0dra
[0] = readb(window
+ I3000_C0DRA
+ 0); /* ranks 0,1 */
329 c0dra
[1] = readb(window
+ I3000_C0DRA
+ 1); /* ranks 2,3 */
330 c1dra
[0] = readb(window
+ I3000_C1DRA
+ 0); /* ranks 0,1 */
331 c1dra
[1] = readb(window
+ I3000_C1DRA
+ 1); /* ranks 2,3 */
333 for (i
= 0; i
< I3000_RANKS_PER_CHANNEL
; i
++) {
334 c0drb
[i
] = readb(window
+ I3000_C0DRB
+ i
);
335 c1drb
[i
] = readb(window
+ I3000_C1DRB
+ i
);
341 * Figure out how many channels we have.
343 * If we have what the datasheet calls "asymmetric channels"
344 * (essentially the same as what was called "virtual single
345 * channel mode" in the i82875) then it's a single channel as
346 * far as EDAC is concerned.
348 interleaved
= i3000_is_interleaved(c0dra
, c1dra
, c0drb
, c1drb
);
349 nr_channels
= interleaved
? 2 : 1;
350 mci
= edac_mc_alloc(0, I3000_RANKS
/ nr_channels
, nr_channels
, 0);
354 debugf3("MC: %s(): init mci\n", __func__
);
356 mci
->dev
= &pdev
->dev
;
357 mci
->mtype_cap
= MEM_FLAG_DDR2
;
359 mci
->edac_ctl_cap
= EDAC_FLAG_SECDED
;
360 mci
->edac_cap
= EDAC_FLAG_SECDED
;
362 mci
->mod_name
= EDAC_MOD_STR
;
363 mci
->mod_ver
= I3000_REVISION
;
364 mci
->ctl_name
= i3000_devs
[dev_idx
].ctl_name
;
365 mci
->dev_name
= pci_name(pdev
);
366 mci
->edac_check
= i3000_check
;
367 mci
->ctl_page_to_phys
= NULL
;
370 * The dram rank boundary (DRB) reg values are boundary addresses
371 * for each DRAM rank with a granularity of 32MB. DRB regs are
372 * cumulative; the last one will contain the total memory
373 * contained in all ranks.
375 * If we're in interleaved mode then we're only walking through
376 * the ranks of controller 0, so we double all the values we see.
378 for (last_cumul_size
= i
= 0; i
< mci
->nr_csrows
; i
++) {
381 struct csrow_info
*csrow
= &mci
->csrows
[i
];
384 cumul_size
= value
<< (I3000_DRB_SHIFT
- PAGE_SHIFT
);
387 debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
388 __func__
, i
, cumul_size
);
389 if (cumul_size
== last_cumul_size
) {
390 csrow
->mtype
= MEM_EMPTY
;
394 csrow
->first_page
= last_cumul_size
;
395 csrow
->last_page
= cumul_size
- 1;
396 csrow
->nr_pages
= cumul_size
- last_cumul_size
;
397 last_cumul_size
= cumul_size
;
398 csrow
->grain
= I3000_DEAP_GRAIN
;
399 csrow
->mtype
= MEM_DDR2
;
400 csrow
->dtype
= DEV_UNKNOWN
;
401 csrow
->edac_mode
= EDAC_UNKNOWN
;
405 * Clear any error bits.
406 * (Yes, we really clear bits by writing 1 to them.)
408 pci_write_bits16(pdev
, I3000_ERRSTS
, I3000_ERRSTS_BITS
,
412 if (edac_mc_add_mc(mci
)) {
413 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__
);
417 /* allocating generic PCI control info */
418 i3000_pci
= edac_pci_create_generic_ctl(&pdev
->dev
, EDAC_MOD_STR
);
421 "%s(): Unable to create PCI control\n",
424 "%s(): PCI error report via EDAC not setup\n",
428 /* get this far and it's successful */
429 debugf3("MC: %s(): success\n", __func__
);
439 /* returns count (>= 0), or negative on error */
440 static int __devinit
i3000_init_one(struct pci_dev
*pdev
,
441 const struct pci_device_id
*ent
)
445 debugf0("MC: %s()\n", __func__
);
447 if (pci_enable_device(pdev
) < 0)
450 rc
= i3000_probe1(pdev
, ent
->driver_data
);
452 mci_pdev
= pci_dev_get(pdev
);
457 static void __devexit
i3000_remove_one(struct pci_dev
*pdev
)
459 struct mem_ctl_info
*mci
;
461 debugf0("%s()\n", __func__
);
464 edac_pci_release_generic_ctl(i3000_pci
);
466 mci
= edac_mc_del_mc(&pdev
->dev
);
473 static const struct pci_device_id i3000_pci_tbl
[] __devinitdata
= {
475 PCI_VEND_DEV(INTEL
, 3000_HB
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
479 } /* 0 terminated list. */
482 MODULE_DEVICE_TABLE(pci
, i3000_pci_tbl
);
484 static struct pci_driver i3000_driver
= {
485 .name
= EDAC_MOD_STR
,
486 .probe
= i3000_init_one
,
487 .remove
= __devexit_p(i3000_remove_one
),
488 .id_table
= i3000_pci_tbl
,
491 static int __init
i3000_init(void)
495 debugf3("MC: %s()\n", __func__
);
497 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
500 pci_rc
= pci_register_driver(&i3000_driver
);
505 i3000_registered
= 0;
506 mci_pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
507 PCI_DEVICE_ID_INTEL_3000_HB
, NULL
);
509 debugf0("i3000 pci_get_device fail\n");
514 pci_rc
= i3000_init_one(mci_pdev
, i3000_pci_tbl
);
516 debugf0("i3000 init fail\n");
525 pci_unregister_driver(&i3000_driver
);
529 pci_dev_put(mci_pdev
);
534 static void __exit
i3000_exit(void)
536 debugf3("MC: %s()\n", __func__
);
538 pci_unregister_driver(&i3000_driver
);
539 if (!i3000_registered
) {
540 i3000_remove_one(mci_pdev
);
541 pci_dev_put(mci_pdev
);
545 module_init(i3000_init
);
546 module_exit(i3000_exit
);
548 MODULE_LICENSE("GPL");
549 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
550 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
552 module_param(edac_op_state
, int, 0444);
553 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");