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mmc: mxs-mmc: use devm_* helper to make cleanup simpler
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / mxs-mmc.c
blobd2729e117ae11257fcef91125463651f38331f82
1 /*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/highmem.h>
32 #include <linux/clk.h>
33 #include <linux/err.h>
34 #include <linux/completion.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/module.h>
41 #include <linux/fsl/mxs-dma.h>
42 #include <linux/pinctrl/consumer.h>
43 #include <linux/stmp_device.h>
44 #include <linux/mmc/mxs-mmc.h>
45
46 #define DRIVER_NAME "mxs-mmc"
47
48 /* card detect polling timeout */
49 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
50
51 #define ssp_is_old(host) ((host)->devid == IMX23_MMC)
52
53 /* SSP registers */
54 #define HW_SSP_CTRL0 0x000
55 #define BM_SSP_CTRL0_RUN (1 << 29)
56 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
57 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
58 #define BM_SSP_CTRL0_READ (1 << 25)
59 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
60 #define BP_SSP_CTRL0_BUS_WIDTH (22)
61 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
62 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
63 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
64 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
65 #define BM_SSP_CTRL0_ENABLE (1 << 16)
66 #define BP_SSP_CTRL0_XFER_COUNT (0)
67 #define BM_SSP_CTRL0_XFER_COUNT (0xffff)
68 #define HW_SSP_CMD0 0x010
69 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
70 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
71 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
72 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
73 #define BP_SSP_CMD0_BLOCK_SIZE (16)
74 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
75 #define BP_SSP_CMD0_BLOCK_COUNT (8)
76 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
77 #define BP_SSP_CMD0_CMD (0)
78 #define BM_SSP_CMD0_CMD (0xff)
79 #define HW_SSP_CMD1 0x020
80 #define HW_SSP_XFER_SIZE 0x030
81 #define HW_SSP_BLOCK_SIZE 0x040
82 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
83 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
84 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
85 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
86 #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
87 #define BP_SSP_TIMING_TIMEOUT (16)
88 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
89 #define BP_SSP_TIMING_CLOCK_DIVIDE (8)
90 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
91 #define BP_SSP_TIMING_CLOCK_RATE (0)
92 #define BM_SSP_TIMING_CLOCK_RATE (0xff)
93 #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
94 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
95 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
96 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
97 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
98 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
99 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
100 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
101 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
102 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
103 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
104 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
105 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
106 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
107 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
108 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
109 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
110 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
111 #define BM_SSP_CTRL1_POLARITY (1 << 9)
112 #define BP_SSP_CTRL1_WORD_LENGTH (4)
113 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
114 #define BP_SSP_CTRL1_SSP_MODE (0)
115 #define BM_SSP_CTRL1_SSP_MODE (0xf)
116 #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
117 #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
118 #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
119 #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
120 #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
121 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
122 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
123
124 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
125
126 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
127 BM_SSP_CTRL1_RESP_ERR_IRQ | \
128 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
129 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
130 BM_SSP_CTRL1_DATA_CRC_IRQ | \
131 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
132 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
134
135 #define SSP_PIO_NUM 3
136
137 enum mxs_mmc_id {
138 IMX23_MMC,
139 IMX28_MMC,
140 };
141
142 struct mxs_mmc_host {
143 struct mmc_host *mmc;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_data *data;
147
148 void __iomem *base;
149 struct resource *dma_res;
150 struct clk *clk;
151 unsigned int clk_rate;
152
153 struct dma_chan *dmach;
154 struct mxs_dma_data dma_data;
155 unsigned int dma_dir;
156 enum dma_transfer_direction slave_dirn;
157 u32 ssp_pio_words[SSP_PIO_NUM];
158
159 enum mxs_mmc_id devid;
160 unsigned char bus_width;
161 spinlock_t lock;
162 int sdio_irq_en;
163 };
164
165 static int mxs_mmc_get_ro(struct mmc_host *mmc)
166 {
167 struct mxs_mmc_host *host = mmc_priv(mmc);
168 struct mxs_mmc_platform_data *pdata =
169 mmc_dev(host->mmc)->platform_data;
170
171 if (!pdata)
172 return -EFAULT;
173
174 if (!gpio_is_valid(pdata->wp_gpio))
175 return -EINVAL;
176
177 return gpio_get_value(pdata->wp_gpio);
178 }
179
180 static int mxs_mmc_get_cd(struct mmc_host *mmc)
181 {
182 struct mxs_mmc_host *host = mmc_priv(mmc);
183
184 return !(readl(host->base + HW_SSP_STATUS(host)) &
185 BM_SSP_STATUS_CARD_DETECT);
186 }
187
188 static void mxs_mmc_reset(struct mxs_mmc_host *host)
189 {
190 u32 ctrl0, ctrl1;
191
192 stmp_reset_block(host->base);
193
194 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
195 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
196 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
197 BM_SSP_CTRL1_DMA_ENABLE |
198 BM_SSP_CTRL1_POLARITY |
199 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
200 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
201 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
202 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
203 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
204
205 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
206 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
207 BF_SSP(0, TIMING_CLOCK_RATE),
208 host->base + HW_SSP_TIMING(host));
209
210 if (host->sdio_irq_en) {
211 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
212 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
213 }
214
215 writel(ctrl0, host->base + HW_SSP_CTRL0);
216 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
217 }
218
219 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
220 struct mmc_command *cmd);
221
222 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
223 {
224 struct mmc_command *cmd = host->cmd;
225 struct mmc_data *data = host->data;
226 struct mmc_request *mrq = host->mrq;
227
228 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
229 if (mmc_resp_type(cmd) & MMC_RSP_136) {
230 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
231 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
232 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
233 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
234 } else {
235 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
236 }
237 }
238
239 if (data) {
240 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
241 data->sg_len, host->dma_dir);
242 /*
243 * If there was an error on any block, we mark all
244 * data blocks as being in error.
245 */
246 if (!data->error)
247 data->bytes_xfered = data->blocks * data->blksz;
248 else
249 data->bytes_xfered = 0;
250
251 host->data = NULL;
252 if (mrq->stop) {
253 mxs_mmc_start_cmd(host, mrq->stop);
254 return;
255 }
256 }
257
258 host->mrq = NULL;
259 mmc_request_done(host->mmc, mrq);
260 }
261
262 static void mxs_mmc_dma_irq_callback(void *param)
263 {
264 struct mxs_mmc_host *host = param;
265
266 mxs_mmc_request_done(host);
267 }
268
269 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
270 {
271 struct mxs_mmc_host *host = dev_id;
272 struct mmc_command *cmd = host->cmd;
273 struct mmc_data *data = host->data;
274 u32 stat;
275
276 spin_lock(&host->lock);
277
278 stat = readl(host->base + HW_SSP_CTRL1(host));
279 writel(stat & MXS_MMC_IRQ_BITS,
280 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
281
282 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
283 mmc_signal_sdio_irq(host->mmc);
284
285 spin_unlock(&host->lock);
286
287 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
288 cmd->error = -ETIMEDOUT;
289 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
290 cmd->error = -EIO;
291
292 if (data) {
293 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
294 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
295 data->error = -ETIMEDOUT;
296 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
297 data->error = -EILSEQ;
298 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
299 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
300 data->error = -EIO;
301 }
302
303 return IRQ_HANDLED;
304 }
305
306 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
307 struct mxs_mmc_host *host, unsigned long flags)
308 {
309 struct dma_async_tx_descriptor *desc;
310 struct mmc_data *data = host->data;
311 struct scatterlist * sgl;
312 unsigned int sg_len;
313
314 if (data) {
315 /* data */
316 dma_map_sg(mmc_dev(host->mmc), data->sg,
317 data->sg_len, host->dma_dir);
318 sgl = data->sg;
319 sg_len = data->sg_len;
320 } else {
321 /* pio */
322 sgl = (struct scatterlist *) host->ssp_pio_words;
323 sg_len = SSP_PIO_NUM;
324 }
325
326 desc = dmaengine_prep_slave_sg(host->dmach,
327 sgl, sg_len, host->slave_dirn, flags);
328 if (desc) {
329 desc->callback = mxs_mmc_dma_irq_callback;
330 desc->callback_param = host;
331 } else {
332 if (data)
333 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
334 data->sg_len, host->dma_dir);
335 }
336
337 return desc;
338 }
339
340 static void mxs_mmc_bc(struct mxs_mmc_host *host)
341 {
342 struct mmc_command *cmd = host->cmd;
343 struct dma_async_tx_descriptor *desc;
344 u32 ctrl0, cmd0, cmd1;
345
346 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
347 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
348 cmd1 = cmd->arg;
349
350 if (host->sdio_irq_en) {
351 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
352 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
353 }
354
355 host->ssp_pio_words[0] = ctrl0;
356 host->ssp_pio_words[1] = cmd0;
357 host->ssp_pio_words[2] = cmd1;
358 host->dma_dir = DMA_NONE;
359 host->slave_dirn = DMA_TRANS_NONE;
360 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
361 if (!desc)
362 goto out;
363
364 dmaengine_submit(desc);
365 dma_async_issue_pending(host->dmach);
366 return;
367
368 out:
369 dev_warn(mmc_dev(host->mmc),
370 "%s: failed to prep dma\n", __func__);
371 }
372
373 static void mxs_mmc_ac(struct mxs_mmc_host *host)
374 {
375 struct mmc_command *cmd = host->cmd;
376 struct dma_async_tx_descriptor *desc;
377 u32 ignore_crc, get_resp, long_resp;
378 u32 ctrl0, cmd0, cmd1;
379
380 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
381 0 : BM_SSP_CTRL0_IGNORE_CRC;
382 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
383 BM_SSP_CTRL0_GET_RESP : 0;
384 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
385 BM_SSP_CTRL0_LONG_RESP : 0;
386
387 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
388 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
389 cmd1 = cmd->arg;
390
391 if (host->sdio_irq_en) {
392 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
393 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
394 }
395
396 host->ssp_pio_words[0] = ctrl0;
397 host->ssp_pio_words[1] = cmd0;
398 host->ssp_pio_words[2] = cmd1;
399 host->dma_dir = DMA_NONE;
400 host->slave_dirn = DMA_TRANS_NONE;
401 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
402 if (!desc)
403 goto out;
404
405 dmaengine_submit(desc);
406 dma_async_issue_pending(host->dmach);
407 return;
408
409 out:
410 dev_warn(mmc_dev(host->mmc),
411 "%s: failed to prep dma\n", __func__);
412 }
413
414 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
415 {
416 const unsigned int ssp_timeout_mul = 4096;
417 /*
418 * Calculate ticks in ms since ns are large numbers
419 * and might overflow
420 */
421 const unsigned int clock_per_ms = clock_rate / 1000;
422 const unsigned int ms = ns / 1000;
423 const unsigned int ticks = ms * clock_per_ms;
424 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
425
426 WARN_ON(ssp_ticks == 0);
427 return ssp_ticks;
428 }
429
430 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
431 {
432 struct mmc_command *cmd = host->cmd;
433 struct mmc_data *data = cmd->data;
434 struct dma_async_tx_descriptor *desc;
435 struct scatterlist *sgl = data->sg, *sg;
436 unsigned int sg_len = data->sg_len;
437 int i;
438
439 unsigned short dma_data_dir, timeout;
440 enum dma_transfer_direction slave_dirn;
441 unsigned int data_size = 0, log2_blksz;
442 unsigned int blocks = data->blocks;
443
444 u32 ignore_crc, get_resp, long_resp, read;
445 u32 ctrl0, cmd0, cmd1, val;
446
447 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
448 0 : BM_SSP_CTRL0_IGNORE_CRC;
449 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
450 BM_SSP_CTRL0_GET_RESP : 0;
451 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
452 BM_SSP_CTRL0_LONG_RESP : 0;
453
454 if (data->flags & MMC_DATA_WRITE) {
455 dma_data_dir = DMA_TO_DEVICE;
456 slave_dirn = DMA_MEM_TO_DEV;
457 read = 0;
458 } else {
459 dma_data_dir = DMA_FROM_DEVICE;
460 slave_dirn = DMA_DEV_TO_MEM;
461 read = BM_SSP_CTRL0_READ;
462 }
463
464 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
465 ignore_crc | get_resp | long_resp |
466 BM_SSP_CTRL0_DATA_XFER | read |
467 BM_SSP_CTRL0_WAIT_FOR_IRQ |
468 BM_SSP_CTRL0_ENABLE;
469
470 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
471
472 /* get logarithm to base 2 of block size for setting register */
473 log2_blksz = ilog2(data->blksz);
474
475 /*
476 * take special care of the case that data size from data->sg
477 * is not equal to blocks x blksz
478 */
479 for_each_sg(sgl, sg, sg_len, i)
480 data_size += sg->length;
481
482 if (data_size != data->blocks * data->blksz)
483 blocks = 1;
484
485 /* xfer count, block size and count need to be set differently */
486 if (ssp_is_old(host)) {
487 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
488 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
489 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
490 } else {
491 writel(data_size, host->base + HW_SSP_XFER_SIZE);
492 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
493 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
494 host->base + HW_SSP_BLOCK_SIZE);
495 }
496
497 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
498 (cmd->opcode == SD_IO_RW_EXTENDED))
499 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
500
501 cmd1 = cmd->arg;
502
503 if (host->sdio_irq_en) {
504 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
505 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
506 }
507
508 /* set the timeout count */
509 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
510 val = readl(host->base + HW_SSP_TIMING(host));
511 val &= ~(BM_SSP_TIMING_TIMEOUT);
512 val |= BF_SSP(timeout, TIMING_TIMEOUT);
513 writel(val, host->base + HW_SSP_TIMING(host));
514
515 /* pio */
516 host->ssp_pio_words[0] = ctrl0;
517 host->ssp_pio_words[1] = cmd0;
518 host->ssp_pio_words[2] = cmd1;
519 host->dma_dir = DMA_NONE;
520 host->slave_dirn = DMA_TRANS_NONE;
521 desc = mxs_mmc_prep_dma(host, 0);
522 if (!desc)
523 goto out;
524
525 /* append data sg */
526 WARN_ON(host->data != NULL);
527 host->data = data;
528 host->dma_dir = dma_data_dir;
529 host->slave_dirn = slave_dirn;
530 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
531 if (!desc)
532 goto out;
533
534 dmaengine_submit(desc);
535 dma_async_issue_pending(host->dmach);
536 return;
537 out:
538 dev_warn(mmc_dev(host->mmc),
539 "%s: failed to prep dma\n", __func__);
540 }
541
542 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
543 struct mmc_command *cmd)
544 {
545 host->cmd = cmd;
546
547 switch (mmc_cmd_type(cmd)) {
548 case MMC_CMD_BC:
549 mxs_mmc_bc(host);
550 break;
551 case MMC_CMD_BCR:
552 mxs_mmc_ac(host);
553 break;
554 case MMC_CMD_AC:
555 mxs_mmc_ac(host);
556 break;
557 case MMC_CMD_ADTC:
558 mxs_mmc_adtc(host);
559 break;
560 default:
561 dev_warn(mmc_dev(host->mmc),
562 "%s: unknown MMC command\n", __func__);
563 break;
564 }
565 }
566
567 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
568 {
569 struct mxs_mmc_host *host = mmc_priv(mmc);
570
571 WARN_ON(host->mrq != NULL);
572 host->mrq = mrq;
573 mxs_mmc_start_cmd(host, mrq->cmd);
574 }
575
576 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
577 {
578 unsigned int ssp_clk, ssp_sck;
579 u32 clock_divide, clock_rate;
580 u32 val;
581
582 ssp_clk = clk_get_rate(host->clk);
583
584 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
585 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
586 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
587 if (clock_rate <= 255)
588 break;
589 }
590
591 if (clock_divide > 254) {
592 dev_err(mmc_dev(host->mmc),
593 "%s: cannot set clock to %d\n", __func__, rate);
594 return;
595 }
596
597 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
598
599 val = readl(host->base + HW_SSP_TIMING(host));
600 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
601 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
602 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
603 writel(val, host->base + HW_SSP_TIMING(host));
604
605 host->clk_rate = ssp_sck;
606
607 dev_dbg(mmc_dev(host->mmc),
608 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
609 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
610 }
611
612 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
613 {
614 struct mxs_mmc_host *host = mmc_priv(mmc);
615
616 if (ios->bus_width == MMC_BUS_WIDTH_8)
617 host->bus_width = 2;
618 else if (ios->bus_width == MMC_BUS_WIDTH_4)
619 host->bus_width = 1;
620 else
621 host->bus_width = 0;
622
623 if (ios->clock)
624 mxs_mmc_set_clk_rate(host, ios->clock);
625 }
626
627 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
628 {
629 struct mxs_mmc_host *host = mmc_priv(mmc);
630 unsigned long flags;
631
632 spin_lock_irqsave(&host->lock, flags);
633
634 host->sdio_irq_en = enable;
635
636 if (enable) {
637 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
638 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
639 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
640 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
641
642 if (readl(host->base + HW_SSP_STATUS(host)) &
643 BM_SSP_STATUS_SDIO_IRQ)
644 mmc_signal_sdio_irq(host->mmc);
645
646 } else {
647 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
648 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
649 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
650 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
651 }
652
653 spin_unlock_irqrestore(&host->lock, flags);
654 }
655
656 static const struct mmc_host_ops mxs_mmc_ops = {
657 .request = mxs_mmc_request,
658 .get_ro = mxs_mmc_get_ro,
659 .get_cd = mxs_mmc_get_cd,
660 .set_ios = mxs_mmc_set_ios,
661 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
662 };
663
664 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
665 {
666 struct mxs_mmc_host *host = param;
667
668 if (!mxs_dma_is_apbh(chan))
669 return false;
670
671 if (chan->chan_id != host->dma_res->start)
672 return false;
673
674 chan->private = &host->dma_data;
675
676 return true;
677 }
678
679 static struct platform_device_id mxs_mmc_ids[] = {
680 {
681 .name = "imx23-mmc",
682 .driver_data = IMX23_MMC,
683 }, {
684 .name = "imx28-mmc",
685 .driver_data = IMX28_MMC,
686 }, {
687 /* sentinel */
688 }
689 };
690 MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
691
692 static int mxs_mmc_probe(struct platform_device *pdev)
693 {
694 struct mxs_mmc_host *host;
695 struct mmc_host *mmc;
696 struct resource *iores, *dmares;
697 struct mxs_mmc_platform_data *pdata;
698 struct pinctrl *pinctrl;
699 int ret = 0, irq_err, irq_dma;
700 dma_cap_mask_t mask;
701
702 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
703 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
704 irq_err = platform_get_irq(pdev, 0);
705 irq_dma = platform_get_irq(pdev, 1);
706 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
707 return -EINVAL;
708
709 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
710 if (!mmc)
711 return -ENOMEM;
712
713 host = mmc_priv(mmc);
714 host->base = devm_request_and_ioremap(&pdev->dev, iores);
715 if (!host->base) {
716 ret = -EADDRNOTAVAIL;
717 goto out_mmc_free;
718 }
719
720 host->devid = pdev->id_entry->driver_data;
721 host->mmc = mmc;
722 host->dma_res = dmares;
723 host->sdio_irq_en = 0;
724
725 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
726 if (IS_ERR(pinctrl)) {
727 ret = PTR_ERR(pinctrl);
728 goto out_iounmap;
729 }
730
731 host->clk = clk_get(&pdev->dev, NULL);
732 if (IS_ERR(host->clk)) {
733 ret = PTR_ERR(host->clk);
734 goto out_mmc_free;
735 }
736 clk_prepare_enable(host->clk);
737
738 mxs_mmc_reset(host);
739
740 dma_cap_zero(mask);
741 dma_cap_set(DMA_SLAVE, mask);
742 host->dma_data.chan_irq = irq_dma;
743 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
744 if (!host->dmach) {
745 dev_err(mmc_dev(host->mmc),
746 "%s: failed to request dma\n", __func__);
747 goto out_clk_put;
748 }
749
750 /* set mmc core parameters */
751 mmc->ops = &mxs_mmc_ops;
752 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
753 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
754
755 pdata = mmc_dev(host->mmc)->platform_data;
756 if (pdata) {
757 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
758 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
759 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
760 mmc->caps |= MMC_CAP_4_BIT_DATA;
761 }
762
763 mmc->f_min = 400000;
764 mmc->f_max = 288000000;
765 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
766
767 mmc->max_segs = 52;
768 mmc->max_blk_size = 1 << 0xf;
769 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
770 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
771 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
772
773 platform_set_drvdata(pdev, mmc);
774
775 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
776 DRIVER_NAME, host);
777 if (ret)
778 goto out_free_dma;
779
780 spin_lock_init(&host->lock);
781
782 ret = mmc_add_host(mmc);
783 if (ret)
784 goto out_free_dma;
785
786 dev_info(mmc_dev(host->mmc), "initialized\n");
787
788 return 0;
789
790 out_free_dma:
791 if (host->dmach)
792 dma_release_channel(host->dmach);
793 out_clk_put:
794 clk_disable_unprepare(host->clk);
795 clk_put(host->clk);
796 out_mmc_free:
797 mmc_free_host(mmc);
798 return ret;
799 }
800
801 static int mxs_mmc_remove(struct platform_device *pdev)
802 {
803 struct mmc_host *mmc = platform_get_drvdata(pdev);
804 struct mxs_mmc_host *host = mmc_priv(mmc);
805
806 mmc_remove_host(mmc);
807
808 platform_set_drvdata(pdev, NULL);
809
810 if (host->dmach)
811 dma_release_channel(host->dmach);
812
813 clk_disable_unprepare(host->clk);
814 clk_put(host->clk);
815
816 mmc_free_host(mmc);
817
818 return 0;
819 }
820
821 #ifdef CONFIG_PM
822 static int mxs_mmc_suspend(struct device *dev)
823 {
824 struct mmc_host *mmc = dev_get_drvdata(dev);
825 struct mxs_mmc_host *host = mmc_priv(mmc);
826 int ret = 0;
827
828 ret = mmc_suspend_host(mmc);
829
830 clk_disable_unprepare(host->clk);
831
832 return ret;
833 }
834
835 static int mxs_mmc_resume(struct device *dev)
836 {
837 struct mmc_host *mmc = dev_get_drvdata(dev);
838 struct mxs_mmc_host *host = mmc_priv(mmc);
839 int ret = 0;
840
841 clk_prepare_enable(host->clk);
842
843 ret = mmc_resume_host(mmc);
844
845 return ret;
846 }
847
848 static const struct dev_pm_ops mxs_mmc_pm_ops = {
849 .suspend = mxs_mmc_suspend,
850 .resume = mxs_mmc_resume,
851 };
852 #endif
853
854 static struct platform_driver mxs_mmc_driver = {
855 .probe = mxs_mmc_probe,
856 .remove = mxs_mmc_remove,
857 .id_table = mxs_mmc_ids,
858 .driver = {
859 .name = DRIVER_NAME,
860 .owner = THIS_MODULE,
861 #ifdef CONFIG_PM
862 .pm = &mxs_mmc_pm_ops,
863 #endif
864 },
865 };
866
867 module_platform_driver(mxs_mmc_driver);
868
869 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
870 MODULE_AUTHOR("Freescale Semiconductor");
871 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree