drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  * All rights reserved.
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. The names of the above-listed copyright holders may not be used
  20  *    to endorse or promote products derived from this software without
  21  *    specific prior written permission.
  22  *
  23  * ALTERNATIVELY, this software may be distributed under the terms of the
  24  * GNU General Public License ("GPL") version 2, as published by the Free
  25  * Software Foundation.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  28  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  29  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  30  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  31  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  32  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  33  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  34  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  35  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  36  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  37  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/ioport.h>
  47 #include <linux/io.h>
  48
  49 #include "io.h"
  50
  51 /*
  52  * All these registers belong to OMAP's Wrapper around the
  53  * DesignWare USB3 Core.
  54  */
  55
  56 #define USBOTGSS_REVISION                       0x0000
  57 #define USBOTGSS_SYSCONFIG                      0x0010
  58 #define USBOTGSS_IRQ_EOI                        0x0020
  59 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  60 #define USBOTGSS_IRQSTATUS_0                    0x0028
  61 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  62 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  63 #define USBOTGSS_IRQSTATUS_RAW_1                0x0034
  64 #define USBOTGSS_IRQSTATUS_1                    0x0038
  65 #define USBOTGSS_IRQENABLE_SET_1                0x003c
  66 #define USBOTGSS_IRQENABLE_CLR_1                0x0040
  67 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  68 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  69 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  70 #define USBOTGSS_FLADJ                          0x0104
  71 #define USBOTGSS_DEBUG_CFG                      0x0108
  72 #define USBOTGSS_DEBUG_DATA                     0x010c
  73
  74 /* SYSCONFIG REGISTER */
  75 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
  76 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x)       ((x) << 4)
  77 #define USBOTGSS_SYSCONFIG_IDLEMODE(x)          ((x) << 2)
  78
  79 /* IRQ_EOI REGISTER */
  80 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
  81
  82 /* IRQS0 BITS */
  83 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
  84
  85 /* IRQ1 BITS */
  86 #define USBOTGSS_IRQ1_DMADISABLECLR             (1 << 17)
  87 #define USBOTGSS_IRQ1_OEVT                      (1 << 16)
  88 #define USBOTGSS_IRQ1_DRVVBUS_RISE              (1 << 13)
  89 #define USBOTGSS_IRQ1_CHRGVBUS_RISE             (1 << 12)
  90 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE          (1 << 11)
  91 #define USBOTGSS_IRQ1_IDPULLUP_RISE             (1 << 8)
  92 #define USBOTGSS_IRQ1_DRVVBUS_FALL              (1 << 5)
  93 #define USBOTGSS_IRQ1_CHRGVBUS_FALL             (1 << 4)
  94 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL          (1 << 3)
  95 #define USBOTGSS_IRQ1_IDPULLUP_FALL             (1 << 0)
  96
  97 /* UTMI_OTG_CTRL REGISTER */
  98 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
  99 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 100 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 101 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 102
 103 /* UTMI_OTG_STATUS REGISTER */
 104 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 105 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 106 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 107 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 108 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 109 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 110 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 111
 112 struct dwc3_omap {
 113         /* device lock */
 114         spinlock_t              lock;
 115
 116         struct platform_device  *dwc3;
 117         struct device           *dev;
 118
 119         int                     irq;
 120         void __iomem            *base;
 121
 122         void                    *context;
 123         u32                     resource_size;
 124
 125         u32                     dma_status:1;
 126 };
 127
 128 #ifdef CONFIG_PM
 129 static int dwc3_omap_suspend(struct device *dev)
 130 {
 131         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 132
 133         memcpy_fromio(omap->context, omap->base, omap->resource_size);
 134
 135         return 0;
 136 }
 137
 138 static int dwc3_omap_resume(struct device *dev)
 139 {
 140         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 141
 142         memcpy_toio(omap->base, omap->context, omap->resource_size);
 143
 144         return 0;
 145 }
 146
 147 static int dwc3_omap_idle(struct device *dev)
 148 {
 149         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 150         u32                     reg;
 151
 152         /* stop DMA Engine */
 153         reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
 154         reg &= ~(USBOTGSS_SYSCONFIG_DMADISABLE);
 155         dwc3_writel(omap->base, USBOTGSS_SYSCONFIG, reg);
 156
 157         return 0;
 158 }
 159
 160 static UNIVERSAL_DEV_PM_OPS(dwc3_omap_pm_ops, dwc3_omap_suspend,
 161                 dwc3_omap_resume, dwc3_omap_idle);
 162
 163 #define DEV_PM_OPS      (&dwc3_omap_pm_ops)
 164 #else
 165 #define DEV_PM_OPS      NULL
 166 #endif
 167
 168 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 169 {
 170         struct dwc3_omap        *omap = _omap;
 171         u32                     reg;
 172         u32                     ctrl;
 173
 174         spin_lock(&omap->lock);
 175
 176         reg = dwc3_readl(omap->base, USBOTGSS_IRQSTATUS_1);
 177         ctrl = dwc3_readl(omap->base, USBOTGSS_UTMI_OTG_CTRL);
 178
 179         if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
 180                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 181                 omap->dma_status = false;
 182         }
 183
 184         if (reg & USBOTGSS_IRQ1_OEVT)
 185                 dev_dbg(omap->dev, "OTG Event\n");
 186
 187         if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE) {
 188                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 189                 ctrl |= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;
 190         }
 191
 192         if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE) {
 193                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 194                 ctrl |= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;
 195         }
 196
 197         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE) {
 198                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 199                 ctrl |= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;
 200         }
 201
 202         if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE) {
 203                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 204                 ctrl |= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;
 205         }
 206
 207         if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL) {
 208                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 209                 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS;
 210         }
 211
 212         if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL) {
 213                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 214                 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS;
 215         }
 216
 217         if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL) {
 218                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 219                 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS;
 220         }
 221
 222         if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL) {
 223                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 224                 ctrl &= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP;
 225         }
 226
 227         dwc3_writel(omap->base, USBOTGSS_UTMI_OTG_CTRL, ctrl);
 228
 229         spin_unlock(&omap->lock);
 230
 231         return IRQ_HANDLED;
 232 }
 233
 234 static int __devinit dwc3_omap_probe(struct platform_device *pdev)
 235 {
 236         struct platform_device  *dwc3;
 237         struct dwc3_omap        *omap;
 238         struct resource         *res;
 239
 240         int                     ret = -ENOMEM;
 241         int                     irq;
 242
 243         u32                     reg;
 244
 245         void __iomem            *base;
 246         void                    *context;
 247
 248         omap = kzalloc(sizeof(*omap), GFP_KERNEL);
 249         if (!omap) {
 250                 dev_err(&pdev->dev, "not enough memory\n");
 251                 goto err0;
 252         }
 253
 254         platform_set_drvdata(pdev, omap);
 255
 256         irq = platform_get_irq(pdev, 1);
 257         if (irq < 0) {
 258                 dev_err(&pdev->dev, "missing IRQ resource\n");
 259                 ret = -EINVAL;
 260                 goto err1;
 261         }
 262
 263         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 264         if (!res) {
 265                 dev_err(&pdev->dev, "missing memory base resource\n");
 266                 ret = -EINVAL;
 267                 goto err1;
 268         }
 269
 270         base = ioremap_nocache(res->start, resource_size(res));
 271         if (!base) {
 272                 dev_err(&pdev->dev, "ioremap failed\n");
 273                 goto err1;
 274         }
 275
 276         dwc3 = platform_device_alloc("dwc3-omap", -1);
 277         if (!dwc3) {
 278                 dev_err(&pdev->dev, "couldn't allocate dwc3 device\n");
 279                 goto err2;
 280         }
 281
 282         context = kzalloc(resource_size(res), GFP_KERNEL);
 283         if (!context) {
 284                 dev_err(&pdev->dev, "couldn't allocate dwc3 context memory\n");
 285                 goto err3;
 286         }
 287
 288         spin_lock_init(&omap->lock);
 289         dma_set_coherent_mask(&dwc3->dev, pdev->dev.coherent_dma_mask);
 290
 291         dwc3->dev.parent = &pdev->dev;
 292         dwc3->dev.dma_mask = pdev->dev.dma_mask;
 293         dwc3->dev.dma_parms = pdev->dev.dma_parms;
 294         omap->resource_size = resource_size(res);
 295         omap->context   = context;
 296         omap->dev       = &pdev->dev;
 297         omap->irq       = irq;
 298         omap->base      = base;
 299         omap->dwc3      = dwc3;
 300
 301         /* check the DMA Status */
 302         reg = dwc3_readl(omap->base, USBOTGSS_SYSCONFIG);
 303         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 304
 305         ret = request_irq(omap->irq, dwc3_omap_interrupt, 0,
 306                         "dwc3-wrapper", omap);
 307         if (ret) {
 308                 dev_err(&pdev->dev, "failed to request IRQ #%d --> %d\n",
 309                                 omap->irq, ret);
 310                 goto err4;
 311         }
 312
 313         /* enable all IRQs */
 314         reg = USBOTGSS_IRQO_COREIRQ_ST;
 315         dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
 316
 317         reg = (USBOTGSS_IRQ1_OEVT |
 318                         USBOTGSS_IRQ1_DRVVBUS_RISE |
 319                         USBOTGSS_IRQ1_CHRGVBUS_RISE |
 320                         USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
 321                         USBOTGSS_IRQ1_IDPULLUP_RISE |
 322                         USBOTGSS_IRQ1_DRVVBUS_FALL |
 323                         USBOTGSS_IRQ1_CHRGVBUS_FALL |
 324                         USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
 325                         USBOTGSS_IRQ1_IDPULLUP_FALL);
 326
 327         dwc3_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
 328
 329         ret = platform_device_add_resources(dwc3, pdev->resource,
 330                         pdev->num_resources);
 331         if (ret) {
 332                 dev_err(&pdev->dev, "couldn't add resources to dwc3 device\n");
 333                 goto err5;
 334         }
 335
 336         ret = platform_device_add(dwc3);
 337         if (ret) {
 338                 dev_err(&pdev->dev, "failed to register dwc3 device\n");
 339                 goto err5;
 340         }
 341
 342         return 0;
 343
 344 err5:
 345         free_irq(omap->irq, omap);
 346
 347 err4:
 348         kfree(omap->context);
 349
 350 err3:
 351         platform_device_put(dwc3);
 352
 353 err2:
 354         iounmap(base);
 355
 356 err1:
 357         kfree(omap);
 358
 359 err0:
 360         return ret;
 361 }
 362
 363 static int __devexit dwc3_omap_remove(struct platform_device *pdev)
 364 {
 365         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 366
 367         platform_device_unregister(omap->dwc3);
 368
 369         free_irq(omap->irq, omap);
 370         iounmap(omap->base);
 371
 372         kfree(omap->context);
 373         kfree(omap);
 374
 375         return 0;
 376 }
 377
 378 static const struct of_device_id of_dwc3_matach[] = {
 379         {
 380                 "ti,dwc3",
 381         },
 382         { },
 383 };
 384 MODULE_DEVICE_TABLE(of, of_dwc3_matach);
 385
 386 static struct platform_driver dwc3_omap_driver = {
 387         .probe          = dwc3_omap_probe,
 388         .remove         = __devexit_p(dwc3_omap_remove),
 389         .driver         = {
 390                 .name   = "omap-dwc3",
 391                 .pm     = DEV_PM_OPS,
 392                 .of_match_table = of_dwc3_matach,
 393         },
 394 };
 395
 396 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 397 MODULE_LICENSE("Dual BSD/GPL");
 398 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
 399
 400 static int __devinit dwc3_omap_init(void)
 401 {
 402         return platform_driver_register(&dwc3_omap_driver);
 403 }
 404 module_init(dwc3_omap_init);
 405
 406 static void __exit dwc3_omap_exit(void)
 407 {
 408         platform_driver_unregister(&dwc3_omap_driver);
 409 }
 410 module_exit(dwc3_omap_exit);