arch/alpha/kernel/time.c

   1 /*
   2  *  linux/arch/alpha/kernel/time.c
   3  *
   4  *  Copyright (C) 1991, 1992, 1995, 1999, 2000  Linus Torvalds
   5  *
   6  * This file contains the PC-specific time handling details:
   7  * reading the RTC at bootup, etc..
   8  * 1994-07-02    Alan Modra
   9  *      fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  10  * 1995-03-26    Markus Kuhn
  11  *      fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
  12  *      precision CMOS clock update
  13  * 1997-09-10   Updated NTP code according to technical memorandum Jan '96
  14  *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  15  * 1997-01-09    Adrian Sun
  16  *      use interval timer if CONFIG_RTC=y
  17  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
  18  *      fixed tick loss calculation in timer_interrupt
  19  *      (round system clock to nearest tick instead of truncating)
  20  *      fixed algorithm in time_init for getting time from CMOS clock
  21  * 1999-04-16   Thorsten Kranzkowski (dl8bcu@gmx.net)
  22  *      fixed algorithm in do_gettimeofday() for calculating the precise time
  23  *      from processor cycle counter (now taking lost_ticks into account)
  24  * 2000-08-13   Jan-Benedict Glaw <jbglaw@lug-owl.de>
  25  *      Fixed time_init to be aware of epoches != 1900. This prevents
  26  *      booting up in 2048 for me;) Code is stolen from rtc.c.
  27  * 2003-06-03   R. Scott Bailey <scott.bailey@eds.com>
  28  *      Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
  29  */
  30 #include <linux/errno.h>
  31 #include <linux/module.h>
  32 #include <linux/sched.h>
  33 #include <linux/kernel.h>
  34 #include <linux/param.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/delay.h>
  38 #include <linux/ioport.h>
  39 #include <linux/irq.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/init.h>
  42 #include <linux/bcd.h>
  43 #include <linux/profile.h>
  44 #include <linux/irq_work.h>
  45
  46 #include <asm/uaccess.h>
  47 #include <asm/io.h>
  48 #include <asm/hwrpb.h>
  49 #include <asm/8253pit.h>
  50 #include <asm/rtc.h>
  51
  52 #include <linux/mc146818rtc.h>
  53 #include <linux/time.h>
  54 #include <linux/timex.h>
  55 #include <linux/clocksource.h>
  56
  57 #include "proto.h"
  58 #include "irq_impl.h"
  59
  60 static int set_rtc_mmss(unsigned long);
  61
  62 DEFINE_SPINLOCK(rtc_lock);
  63 EXPORT_SYMBOL(rtc_lock);
  64
  65 #define TICK_SIZE (tick_nsec / 1000)
  66
  67 /*
  68  * Shift amount by which scaled_ticks_per_cycle is scaled.  Shifting
  69  * by 48 gives us 16 bits for HZ while keeping the accuracy good even
  70  * for large CPU clock rates.
  71  */
  72 #define FIX_SHIFT       48
  73
  74 /* lump static variables together for more efficient access: */
  75 static struct {
  76         /* cycle counter last time it got invoked */
  77         __u32 last_time;
  78         /* ticks/cycle * 2^48 */
  79         unsigned long scaled_ticks_per_cycle;
  80         /* partial unused tick */
  81         unsigned long partial_tick;
  82 } state;
  83
  84 unsigned long est_cycle_freq;
  85
  86 #ifdef CONFIG_IRQ_WORK
  87
  88 DEFINE_PER_CPU(u8, irq_work_pending);
  89
  90 #define set_irq_work_pending_flag()  __get_cpu_var(irq_work_pending) = 1
  91 #define test_irq_work_pending()      __get_cpu_var(irq_work_pending)
  92 #define clear_irq_work_pending()     __get_cpu_var(irq_work_pending) = 0
  93
  94 void arch_irq_work_raise(void)
  95 {
  96         set_irq_work_pending_flag();
  97 }
  98
  99 #else  /* CONFIG_IRQ_WORK */
 100
 101 #define test_irq_work_pending()      0
 102 #define clear_irq_work_pending()
 103
 104 #endif /* CONFIG_IRQ_WORK */
 105
 106
 107 static inline __u32 rpcc(void)
 108 {
 109     __u32 result;
 110     asm volatile ("rpcc %0" : "=r"(result));
 111     return result;
 112 }
 113
 114 int update_persistent_clock(struct timespec now)
 115 {
 116         return set_rtc_mmss(now.tv_sec);
 117 }
 118
 119 void read_persistent_clock(struct timespec *ts)
 120 {
 121         unsigned int year, mon, day, hour, min, sec, epoch;
 122
 123         sec = CMOS_READ(RTC_SECONDS);
 124         min = CMOS_READ(RTC_MINUTES);
 125         hour = CMOS_READ(RTC_HOURS);
 126         day = CMOS_READ(RTC_DAY_OF_MONTH);
 127         mon = CMOS_READ(RTC_MONTH);
 128         year = CMOS_READ(RTC_YEAR);
 129
 130         if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 131                 sec = bcd2bin(sec);
 132                 min = bcd2bin(min);
 133                 hour = bcd2bin(hour);
 134                 day = bcd2bin(day);
 135                 mon = bcd2bin(mon);
 136                 year = bcd2bin(year);
 137         }
 138
 139         /* PC-like is standard; used for year >= 70 */
 140         epoch = 1900;
 141         if (year < 20)
 142                 epoch = 2000;
 143         else if (year >= 20 && year < 48)
 144                 /* NT epoch */
 145                 epoch = 1980;
 146         else if (year >= 48 && year < 70)
 147                 /* Digital UNIX epoch */
 148                 epoch = 1952;
 149
 150         printk(KERN_INFO "Using epoch = %d\n", epoch);
 151
 152         if ((year += epoch) < 1970)
 153                 year += 100;
 154
 155         ts->tv_sec = mktime(year, mon, day, hour, min, sec);
 156         ts->tv_nsec = 0;
 157 }
 158
 159
 160
 161 /*
 162  * timer_interrupt() needs to keep up the real-time clock,
 163  * as well as call the "xtime_update()" routine every clocktick
 164  */
 165 irqreturn_t timer_interrupt(int irq, void *dev)
 166 {
 167         unsigned long delta;
 168         __u32 now;
 169         long nticks;
 170
 171 #ifndef CONFIG_SMP
 172         /* Not SMP, do kernel PC profiling here.  */
 173         profile_tick(CPU_PROFILING);
 174 #endif
 175
 176         /*
 177          * Calculate how many ticks have passed since the last update,
 178          * including any previous partial leftover.  Save any resulting
 179          * fraction for the next pass.
 180          */
 181         now = rpcc();
 182         delta = now - state.last_time;
 183         state.last_time = now;
 184         delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
 185         state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
 186         nticks = delta >> FIX_SHIFT;
 187
 188         if (nticks)
 189                 xtime_update(nticks);
 190
 191         if (test_irq_work_pending()) {
 192                 clear_irq_work_pending();
 193                 irq_work_run();
 194         }
 195
 196 #ifndef CONFIG_SMP
 197         while (nticks--)
 198                 update_process_times(user_mode(get_irq_regs()));
 199 #endif
 200
 201         return IRQ_HANDLED;
 202 }
 203
 204 void __init
 205 common_init_rtc(void)
 206 {
 207         unsigned char x;
 208
 209         /* Reset periodic interrupt frequency.  */
 210         x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
 211         /* Test includes known working values on various platforms
 212            where 0x26 is wrong; we refuse to change those. */
 213         if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
 214                 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
 215                 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
 216         }
 217
 218         /* Turn on periodic interrupts.  */
 219         x = CMOS_READ(RTC_CONTROL);
 220         if (!(x & RTC_PIE)) {
 221                 printk("Turning on RTC interrupts.\n");
 222                 x |= RTC_PIE;
 223                 x &= ~(RTC_AIE | RTC_UIE);
 224                 CMOS_WRITE(x, RTC_CONTROL);
 225         }
 226         (void) CMOS_READ(RTC_INTR_FLAGS);
 227
 228         outb(0x36, 0x43);       /* pit counter 0: system timer */
 229         outb(0x00, 0x40);
 230         outb(0x00, 0x40);
 231
 232         outb(0xb6, 0x43);       /* pit counter 2: speaker */
 233         outb(0x31, 0x42);
 234         outb(0x13, 0x42);
 235
 236         init_rtc_irq();
 237 }
 238
 239 unsigned int common_get_rtc_time(struct rtc_time *time)
 240 {
 241         return __get_rtc_time(time);
 242 }
 243
 244 int common_set_rtc_time(struct rtc_time *time)
 245 {
 246         return __set_rtc_time(time);
 247 }
 248
 249 /* Validate a computed cycle counter result against the known bounds for
 250    the given processor core.  There's too much brokenness in the way of
 251    timing hardware for any one method to work everywhere.  :-(
 252
 253    Return 0 if the result cannot be trusted, otherwise return the argument.  */
 254
 255 static unsigned long __init
 256 validate_cc_value(unsigned long cc)
 257 {
 258         static struct bounds {
 259                 unsigned int min, max;
 260         } cpu_hz[] __initdata = {
 261                 [EV3_CPU]    = {   50000000,  200000000 },      /* guess */
 262                 [EV4_CPU]    = {  100000000,  300000000 },
 263                 [LCA4_CPU]   = {  100000000,  300000000 },      /* guess */
 264                 [EV45_CPU]   = {  200000000,  300000000 },
 265                 [EV5_CPU]    = {  250000000,  433000000 },
 266                 [EV56_CPU]   = {  333000000,  667000000 },
 267                 [PCA56_CPU]  = {  400000000,  600000000 },      /* guess */
 268                 [PCA57_CPU]  = {  500000000,  600000000 },      /* guess */
 269                 [EV6_CPU]    = {  466000000,  600000000 },
 270                 [EV67_CPU]   = {  600000000,  750000000 },
 271                 [EV68AL_CPU] = {  750000000,  940000000 },
 272                 [EV68CB_CPU] = { 1000000000, 1333333333 },
 273                 /* None of the following are shipping as of 2001-11-01.  */
 274                 [EV68CX_CPU] = { 1000000000, 1700000000 },      /* guess */
 275                 [EV69_CPU]   = { 1000000000, 1700000000 },      /* guess */
 276                 [EV7_CPU]    = {  800000000, 1400000000 },      /* guess */
 277                 [EV79_CPU]   = { 1000000000, 2000000000 },      /* guess */
 278         };
 279
 280         /* Allow for some drift in the crystal.  10MHz is more than enough.  */
 281         const unsigned int deviation = 10000000;
 282
 283         struct percpu_struct *cpu;
 284         unsigned int index;
 285
 286         cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
 287         index = cpu->type & 0xffffffff;
 288
 289         /* If index out of bounds, no way to validate.  */
 290         if (index >= ARRAY_SIZE(cpu_hz))
 291                 return cc;
 292
 293         /* If index contains no data, no way to validate.  */
 294         if (cpu_hz[index].max == 0)
 295                 return cc;
 296
 297         if (cc < cpu_hz[index].min - deviation
 298             || cc > cpu_hz[index].max + deviation)
 299                 return 0;
 300
 301         return cc;
 302 }
 303
 304
 305 /*
 306  * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
 307  * arch/i386/time.c.
 308  */
 309
 310 #define CALIBRATE_LATCH 0xffff
 311 #define TIMEOUT_COUNT   0x100000
 312
 313 static unsigned long __init
 314 calibrate_cc_with_pit(void)
 315 {
 316         int cc, count = 0;
 317
 318         /* Set the Gate high, disable speaker */
 319         outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 320
 321         /*
 322          * Now let's take care of CTC channel 2
 323          *
 324          * Set the Gate high, program CTC channel 2 for mode 0,
 325          * (interrupt on terminal count mode), binary count,
 326          * load 5 * LATCH count, (LSB and MSB) to begin countdown.
 327          */
 328         outb(0xb0, 0x43);               /* binary, mode 0, LSB/MSB, Ch 2 */
 329         outb(CALIBRATE_LATCH & 0xff, 0x42);     /* LSB of count */
 330         outb(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
 331
 332         cc = rpcc();
 333         do {
 334                 count++;
 335         } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
 336         cc = rpcc() - cc;
 337
 338         /* Error: ECTCNEVERSET or ECPUTOOFAST.  */
 339         if (count <= 1 || count == TIMEOUT_COUNT)
 340                 return 0;
 341
 342         return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
 343 }
 344
 345 /* The Linux interpretation of the CMOS clock register contents:
 346    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
 347    RTC registers show the second which has precisely just started.
 348    Let's hope other operating systems interpret the RTC the same way.  */
 349
 350 static unsigned long __init
 351 rpcc_after_update_in_progress(void)
 352 {
 353         do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
 354         do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
 355
 356         return rpcc();
 357 }
 358
 359 #ifndef CONFIG_SMP
 360 /* Until and unless we figure out how to get cpu cycle counters
 361    in sync and keep them there, we can't use the rpcc.  */
 362 static cycle_t read_rpcc(struct clocksource *cs)
 363 {
 364         cycle_t ret = (cycle_t)rpcc();
 365         return ret;
 366 }
 367
 368 static struct clocksource clocksource_rpcc = {
 369         .name                   = "rpcc",
 370         .rating                 = 300,
 371         .read                   = read_rpcc,
 372         .mask                   = CLOCKSOURCE_MASK(32),
 373         .flags                  = CLOCK_SOURCE_IS_CONTINUOUS
 374 };
 375
 376 static inline void register_rpcc_clocksource(long cycle_freq)
 377 {
 378         clocksource_register_hz(&clocksource_rpcc, cycle_freq);
 379 }
 380 #else /* !CONFIG_SMP */
 381 static inline void register_rpcc_clocksource(long cycle_freq)
 382 {
 383 }
 384 #endif /* !CONFIG_SMP */
 385
 386 void __init
 387 time_init(void)
 388 {
 389         unsigned int cc1, cc2;
 390         unsigned long cycle_freq, tolerance;
 391         long diff;
 392
 393         /* Calibrate CPU clock -- attempt #1.  */
 394         if (!est_cycle_freq)
 395                 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
 396
 397         cc1 = rpcc();
 398
 399         /* Calibrate CPU clock -- attempt #2.  */
 400         if (!est_cycle_freq) {
 401                 cc1 = rpcc_after_update_in_progress();
 402                 cc2 = rpcc_after_update_in_progress();
 403                 est_cycle_freq = validate_cc_value(cc2 - cc1);
 404                 cc1 = cc2;
 405         }
 406
 407         cycle_freq = hwrpb->cycle_freq;
 408         if (est_cycle_freq) {
 409                 /* If the given value is within 250 PPM of what we calculated,
 410                    accept it.  Otherwise, use what we found.  */
 411                 tolerance = cycle_freq / 4000;
 412                 diff = cycle_freq - est_cycle_freq;
 413                 if (diff < 0)
 414                         diff = -diff;
 415                 if ((unsigned long)diff > tolerance) {
 416                         cycle_freq = est_cycle_freq;
 417                         printk("HWRPB cycle frequency bogus.  "
 418                                "Estimated %lu Hz\n", cycle_freq);
 419                 } else {
 420                         est_cycle_freq = 0;
 421                 }
 422         } else if (! validate_cc_value (cycle_freq)) {
 423                 printk("HWRPB cycle frequency bogus, "
 424                        "and unable to estimate a proper value!\n");
 425         }
 426
 427         /* From John Bowman <bowman@math.ualberta.ca>: allow the values
 428            to settle, as the Update-In-Progress bit going low isn't good
 429            enough on some hardware.  2ms is our guess; we haven't found
 430            bogomips yet, but this is close on a 500Mhz box.  */
 431         __delay(1000000);
 432
 433
 434         if (HZ > (1<<16)) {
 435                 extern void __you_loose (void);
 436                 __you_loose();
 437         }
 438
 439         register_rpcc_clocksource(cycle_freq);
 440
 441         state.last_time = cc1;
 442         state.scaled_ticks_per_cycle
 443                 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
 444         state.partial_tick = 0L;
 445
 446         /* Startup the timer source. */
 447         alpha_mv.init_rtc();
 448 }
 449
 450 /*
 451  * In order to set the CMOS clock precisely, set_rtc_mmss has to be
 452  * called 500 ms after the second nowtime has started, because when
 453  * nowtime is written into the registers of the CMOS clock, it will
 454  * jump to the next second precisely 500 ms later. Check the Motorola
 455  * MC146818A or Dallas DS12887 data sheet for details.
 456  *
 457  * BUG: This routine does not handle hour overflow properly; it just
 458  *      sets the minutes. Usually you won't notice until after reboot!
 459  */
 460
 461
 462 static int
 463 set_rtc_mmss(unsigned long nowtime)
 464 {
 465         int retval = 0;
 466         int real_seconds, real_minutes, cmos_minutes;
 467         unsigned char save_control, save_freq_select;
 468
 469         /* irq are locally disabled here */
 470         spin_lock(&rtc_lock);
 471         /* Tell the clock it's being set */
 472         save_control = CMOS_READ(RTC_CONTROL);
 473         CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
 474
 475         /* Stop and reset prescaler */
 476         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
 477         CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
 478
 479         cmos_minutes = CMOS_READ(RTC_MINUTES);
 480         if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
 481                 cmos_minutes = bcd2bin(cmos_minutes);
 482
 483         /*
 484          * since we're only adjusting minutes and seconds,
 485          * don't interfere with hour overflow. This avoids
 486          * messing with unknown time zones but requires your
 487          * RTC not to be off by more than 15 minutes
 488          */
 489         real_seconds = nowtime % 60;
 490         real_minutes = nowtime / 60;
 491         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
 492                 /* correct for half hour time zone */
 493                 real_minutes += 30;
 494         }
 495         real_minutes %= 60;
 496
 497         if (abs(real_minutes - cmos_minutes) < 30) {
 498                 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
 499                         real_seconds = bin2bcd(real_seconds);
 500                         real_minutes = bin2bcd(real_minutes);
 501                 }
 502                 CMOS_WRITE(real_seconds,RTC_SECONDS);
 503                 CMOS_WRITE(real_minutes,RTC_MINUTES);
 504         } else {
 505                 printk_once(KERN_NOTICE
 506                        "set_rtc_mmss: can't update from %d to %d\n",
 507                        cmos_minutes, real_minutes);
 508                 retval = -1;
 509         }
 510
 511         /* The following flags have to be released exactly in this order,
 512          * otherwise the DS12887 (popular MC146818A clone with integrated
 513          * battery and quartz) will not reset the oscillator and will not
 514          * update precisely 500 ms later. You won't find this mentioned in
 515          * the Dallas Semiconductor data sheets, but who believes data
 516          * sheets anyway ...                           -- Markus Kuhn
 517          */
 518         CMOS_WRITE(save_control, RTC_CONTROL);
 519         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 520         spin_unlock(&rtc_lock);
 521
 522         return retval;
 523 }