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drm/i915: Update watermarks for Ironlake after dpms changes
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob1eae234ff485699c198a26cc757d3d70d9b4204f
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "drm_dp_helper.h"
38
39 #include "drm_crtc_helper.h"
40
41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
42
43 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
44 static void intel_update_watermarks(struct drm_device *dev);
45 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *);
76 };
77
78 #define I8XX_DOT_MIN 25000
79 #define I8XX_DOT_MAX 350000
80 #define I8XX_VCO_MIN 930000
81 #define I8XX_VCO_MAX 1400000
82 #define I8XX_N_MIN 3
83 #define I8XX_N_MAX 16
84 #define I8XX_M_MIN 96
85 #define I8XX_M_MAX 140
86 #define I8XX_M1_MIN 18
87 #define I8XX_M1_MAX 26
88 #define I8XX_M2_MIN 6
89 #define I8XX_M2_MAX 16
90 #define I8XX_P_MIN 4
91 #define I8XX_P_MAX 128
92 #define I8XX_P1_MIN 2
93 #define I8XX_P1_MAX 33
94 #define I8XX_P1_LVDS_MIN 1
95 #define I8XX_P1_LVDS_MAX 6
96 #define I8XX_P2_SLOW 4
97 #define I8XX_P2_FAST 2
98 #define I8XX_P2_LVDS_SLOW 14
99 #define I8XX_P2_LVDS_FAST 7
100 #define I8XX_P2_SLOW_LIMIT 165000
101
102 #define I9XX_DOT_MIN 20000
103 #define I9XX_DOT_MAX 400000
104 #define I9XX_VCO_MIN 1400000
105 #define I9XX_VCO_MAX 2800000
106 #define PINEVIEW_VCO_MIN 1700000
107 #define PINEVIEW_VCO_MAX 3500000
108 #define I9XX_N_MIN 1
109 #define I9XX_N_MAX 6
110 /* Pineview's Ncounter is a ring counter */
111 #define PINEVIEW_N_MIN 3
112 #define PINEVIEW_N_MAX 6
113 #define I9XX_M_MIN 70
114 #define I9XX_M_MAX 120
115 #define PINEVIEW_M_MIN 2
116 #define PINEVIEW_M_MAX 256
117 #define I9XX_M1_MIN 10
118 #define I9XX_M1_MAX 22
119 #define I9XX_M2_MIN 5
120 #define I9XX_M2_MAX 9
121 /* Pineview M1 is reserved, and must be 0 */
122 #define PINEVIEW_M1_MIN 0
123 #define PINEVIEW_M1_MAX 0
124 #define PINEVIEW_M2_MIN 0
125 #define PINEVIEW_M2_MAX 254
126 #define I9XX_P_SDVO_DAC_MIN 5
127 #define I9XX_P_SDVO_DAC_MAX 80
128 #define I9XX_P_LVDS_MIN 7
129 #define I9XX_P_LVDS_MAX 98
130 #define PINEVIEW_P_LVDS_MIN 7
131 #define PINEVIEW_P_LVDS_MAX 112
132 #define I9XX_P1_MIN 1
133 #define I9XX_P1_MAX 8
134 #define I9XX_P2_SDVO_DAC_SLOW 10
135 #define I9XX_P2_SDVO_DAC_FAST 5
136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
137 #define I9XX_P2_LVDS_SLOW 14
138 #define I9XX_P2_LVDS_FAST 7
139 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
140
141 /*The parameter is for SDVO on G4x platform*/
142 #define G4X_DOT_SDVO_MIN 25000
143 #define G4X_DOT_SDVO_MAX 270000
144 #define G4X_VCO_MIN 1750000
145 #define G4X_VCO_MAX 3500000
146 #define G4X_N_SDVO_MIN 1
147 #define G4X_N_SDVO_MAX 4
148 #define G4X_M_SDVO_MIN 104
149 #define G4X_M_SDVO_MAX 138
150 #define G4X_M1_SDVO_MIN 17
151 #define G4X_M1_SDVO_MAX 23
152 #define G4X_M2_SDVO_MIN 5
153 #define G4X_M2_SDVO_MAX 11
154 #define G4X_P_SDVO_MIN 10
155 #define G4X_P_SDVO_MAX 30
156 #define G4X_P1_SDVO_MIN 1
157 #define G4X_P1_SDVO_MAX 3
158 #define G4X_P2_SDVO_SLOW 10
159 #define G4X_P2_SDVO_FAST 10
160 #define G4X_P2_SDVO_LIMIT 270000
161
162 /*The parameter is for HDMI_DAC on G4x platform*/
163 #define G4X_DOT_HDMI_DAC_MIN 22000
164 #define G4X_DOT_HDMI_DAC_MAX 400000
165 #define G4X_N_HDMI_DAC_MIN 1
166 #define G4X_N_HDMI_DAC_MAX 4
167 #define G4X_M_HDMI_DAC_MIN 104
168 #define G4X_M_HDMI_DAC_MAX 138
169 #define G4X_M1_HDMI_DAC_MIN 16
170 #define G4X_M1_HDMI_DAC_MAX 23
171 #define G4X_M2_HDMI_DAC_MIN 5
172 #define G4X_M2_HDMI_DAC_MAX 11
173 #define G4X_P_HDMI_DAC_MIN 5
174 #define G4X_P_HDMI_DAC_MAX 80
175 #define G4X_P1_HDMI_DAC_MIN 1
176 #define G4X_P1_HDMI_DAC_MAX 8
177 #define G4X_P2_HDMI_DAC_SLOW 10
178 #define G4X_P2_HDMI_DAC_FAST 5
179 #define G4X_P2_HDMI_DAC_LIMIT 165000
180
181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
199
200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218
219 /*The parameter is for DISPLAY PORT on G4x platform*/
220 #define G4X_DOT_DISPLAY_PORT_MIN 161670
221 #define G4X_DOT_DISPLAY_PORT_MAX 227000
222 #define G4X_N_DISPLAY_PORT_MIN 1
223 #define G4X_N_DISPLAY_PORT_MAX 2
224 #define G4X_M_DISPLAY_PORT_MIN 97
225 #define G4X_M_DISPLAY_PORT_MAX 108
226 #define G4X_M1_DISPLAY_PORT_MIN 0x10
227 #define G4X_M1_DISPLAY_PORT_MAX 0x12
228 #define G4X_M2_DISPLAY_PORT_MIN 0x05
229 #define G4X_M2_DISPLAY_PORT_MAX 0x06
230 #define G4X_P_DISPLAY_PORT_MIN 10
231 #define G4X_P_DISPLAY_PORT_MAX 20
232 #define G4X_P1_DISPLAY_PORT_MIN 1
233 #define G4X_P1_DISPLAY_PORT_MAX 2
234 #define G4X_P2_DISPLAY_PORT_SLOW 10
235 #define G4X_P2_DISPLAY_PORT_FAST 10
236 #define G4X_P2_DISPLAY_PORT_LIMIT 0
237
238 /* Ironlake / Sandybridge */
239 /* as we calculate clock using (register_value + 2) for
240 N/M1/M2, so here the range value for them is (actual_value-2).
241 */
242 #define IRONLAKE_DOT_MIN 25000
243 #define IRONLAKE_DOT_MAX 350000
244 #define IRONLAKE_VCO_MIN 1760000
245 #define IRONLAKE_VCO_MAX 3510000
246 #define IRONLAKE_M1_MIN 12
247 #define IRONLAKE_M1_MAX 22
248 #define IRONLAKE_M2_MIN 5
249 #define IRONLAKE_M2_MAX 9
250 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
251
252 /* We have parameter ranges for different type of outputs. */
253
254 /* DAC & HDMI Refclk 120Mhz */
255 #define IRONLAKE_DAC_N_MIN 1
256 #define IRONLAKE_DAC_N_MAX 5
257 #define IRONLAKE_DAC_M_MIN 79
258 #define IRONLAKE_DAC_M_MAX 127
259 #define IRONLAKE_DAC_P_MIN 5
260 #define IRONLAKE_DAC_P_MAX 80
261 #define IRONLAKE_DAC_P1_MIN 1
262 #define IRONLAKE_DAC_P1_MAX 8
263 #define IRONLAKE_DAC_P2_SLOW 10
264 #define IRONLAKE_DAC_P2_FAST 5
265
266 /* LVDS single-channel 120Mhz refclk */
267 #define IRONLAKE_LVDS_S_N_MIN 1
268 #define IRONLAKE_LVDS_S_N_MAX 3
269 #define IRONLAKE_LVDS_S_M_MIN 79
270 #define IRONLAKE_LVDS_S_M_MAX 118
271 #define IRONLAKE_LVDS_S_P_MIN 28
272 #define IRONLAKE_LVDS_S_P_MAX 112
273 #define IRONLAKE_LVDS_S_P1_MIN 2
274 #define IRONLAKE_LVDS_S_P1_MAX 8
275 #define IRONLAKE_LVDS_S_P2_SLOW 14
276 #define IRONLAKE_LVDS_S_P2_FAST 14
277
278 /* LVDS dual-channel 120Mhz refclk */
279 #define IRONLAKE_LVDS_D_N_MIN 1
280 #define IRONLAKE_LVDS_D_N_MAX 3
281 #define IRONLAKE_LVDS_D_M_MIN 79
282 #define IRONLAKE_LVDS_D_M_MAX 127
283 #define IRONLAKE_LVDS_D_P_MIN 14
284 #define IRONLAKE_LVDS_D_P_MAX 56
285 #define IRONLAKE_LVDS_D_P1_MIN 2
286 #define IRONLAKE_LVDS_D_P1_MAX 8
287 #define IRONLAKE_LVDS_D_P2_SLOW 7
288 #define IRONLAKE_LVDS_D_P2_FAST 7
289
290 /* LVDS single-channel 100Mhz refclk */
291 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
292 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
293 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
294 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
295 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
296 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
297 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
298 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
300 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
301
302 /* LVDS dual-channel 100Mhz refclk */
303 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
304 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
305 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
306 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
307 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
308 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
309 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
310 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
312 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
313
314 /* DisplayPort */
315 #define IRONLAKE_DP_N_MIN 1
316 #define IRONLAKE_DP_N_MAX 2
317 #define IRONLAKE_DP_M_MIN 81
318 #define IRONLAKE_DP_M_MAX 90
319 #define IRONLAKE_DP_P_MIN 10
320 #define IRONLAKE_DP_P_MAX 20
321 #define IRONLAKE_DP_P2_FAST 10
322 #define IRONLAKE_DP_P2_SLOW 10
323 #define IRONLAKE_DP_P2_LIMIT 0
324 #define IRONLAKE_DP_P1_MIN 1
325 #define IRONLAKE_DP_P1_MAX 2
326
327 /* FDI */
328 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
329
330 static bool
331 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
332 int target, int refclk, intel_clock_t *best_clock);
333 static bool
334 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
335 int target, int refclk, intel_clock_t *best_clock);
336
337 static bool
338 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
339 int target, int refclk, intel_clock_t *best_clock);
340 static bool
341 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
342 int target, int refclk, intel_clock_t *best_clock);
343
344 static const intel_limit_t intel_limits_i8xx_dvo = {
345 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
346 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
347 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
348 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
349 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
350 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
351 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
352 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
353 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
354 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
355 .find_pll = intel_find_best_PLL,
356 };
357
358 static const intel_limit_t intel_limits_i8xx_lvds = {
359 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
360 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
361 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
362 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
363 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
364 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
365 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
366 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
367 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
368 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
369 .find_pll = intel_find_best_PLL,
370 };
371
372 static const intel_limit_t intel_limits_i9xx_sdvo = {
373 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
374 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
375 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
376 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
377 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
378 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
379 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
380 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
381 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
382 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
383 .find_pll = intel_find_best_PLL,
384 };
385
386 static const intel_limit_t intel_limits_i9xx_lvds = {
387 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
388 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
389 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
390 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
391 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
392 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
393 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
394 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
395 /* The single-channel range is 25-112Mhz, and dual-channel
396 * is 80-224Mhz. Prefer single channel as much as possible.
397 */
398 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
399 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
400 .find_pll = intel_find_best_PLL,
401 };
402
403 /* below parameter and function is for G4X Chipset Family*/
404 static const intel_limit_t intel_limits_g4x_sdvo = {
405 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
406 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
407 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
408 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
409 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
410 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
411 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
412 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
413 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
414 .p2_slow = G4X_P2_SDVO_SLOW,
415 .p2_fast = G4X_P2_SDVO_FAST
416 },
417 .find_pll = intel_g4x_find_best_PLL,
418 };
419
420 static const intel_limit_t intel_limits_g4x_hdmi = {
421 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
422 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
423 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
424 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
425 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
426 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
427 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
428 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
429 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
430 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
431 .p2_fast = G4X_P2_HDMI_DAC_FAST
432 },
433 .find_pll = intel_g4x_find_best_PLL,
434 };
435
436 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
437 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
438 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
439 .vco = { .min = G4X_VCO_MIN,
440 .max = G4X_VCO_MAX },
441 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
442 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
443 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
444 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
445 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
446 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
447 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
448 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
449 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
450 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
451 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
452 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
453 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
454 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
455 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
456 },
457 .find_pll = intel_g4x_find_best_PLL,
458 };
459
460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
461 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
462 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
463 .vco = { .min = G4X_VCO_MIN,
464 .max = G4X_VCO_MAX },
465 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
466 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
467 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
468 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
469 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
470 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
471 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
472 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
473 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
474 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
475 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
476 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
477 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
478 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
479 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
480 },
481 .find_pll = intel_g4x_find_best_PLL,
482 };
483
484 static const intel_limit_t intel_limits_g4x_display_port = {
485 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
486 .max = G4X_DOT_DISPLAY_PORT_MAX },
487 .vco = { .min = G4X_VCO_MIN,
488 .max = G4X_VCO_MAX},
489 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
490 .max = G4X_N_DISPLAY_PORT_MAX },
491 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
492 .max = G4X_M_DISPLAY_PORT_MAX },
493 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
494 .max = G4X_M1_DISPLAY_PORT_MAX },
495 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
496 .max = G4X_M2_DISPLAY_PORT_MAX },
497 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
498 .max = G4X_P_DISPLAY_PORT_MAX },
499 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
500 .max = G4X_P1_DISPLAY_PORT_MAX},
501 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
502 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
503 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
504 .find_pll = intel_find_pll_g4x_dp,
505 };
506
507 static const intel_limit_t intel_limits_pineview_sdvo = {
508 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
509 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
510 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
511 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
512 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
513 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
514 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
515 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
516 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
517 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
518 .find_pll = intel_find_best_PLL,
519 };
520
521 static const intel_limit_t intel_limits_pineview_lvds = {
522 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
523 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
524 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
525 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
526 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
527 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
528 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
529 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
530 /* Pineview only supports single-channel mode. */
531 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
532 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
533 .find_pll = intel_find_best_PLL,
534 };
535
536 static const intel_limit_t intel_limits_ironlake_dac = {
537 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
538 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
539 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
540 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
541 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
542 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
543 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
544 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
545 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
546 .p2_slow = IRONLAKE_DAC_P2_SLOW,
547 .p2_fast = IRONLAKE_DAC_P2_FAST },
548 .find_pll = intel_g4x_find_best_PLL,
549 };
550
551 static const intel_limit_t intel_limits_ironlake_single_lvds = {
552 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
553 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
554 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
555 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
556 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
557 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
558 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
559 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
560 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
561 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
562 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
563 .find_pll = intel_g4x_find_best_PLL,
564 };
565
566 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
567 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
568 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
569 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
570 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
571 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
572 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
573 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
574 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
575 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
576 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
577 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
578 .find_pll = intel_g4x_find_best_PLL,
579 };
580
581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
582 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
583 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
584 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
585 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
586 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
587 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
588 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
589 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
590 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
591 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
592 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
593 .find_pll = intel_g4x_find_best_PLL,
594 };
595
596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
597 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
598 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
599 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
600 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
601 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
602 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
603 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
604 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
605 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
606 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
607 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
608 .find_pll = intel_g4x_find_best_PLL,
609 };
610
611 static const intel_limit_t intel_limits_ironlake_display_port = {
612 .dot = { .min = IRONLAKE_DOT_MIN,
613 .max = IRONLAKE_DOT_MAX },
614 .vco = { .min = IRONLAKE_VCO_MIN,
615 .max = IRONLAKE_VCO_MAX},
616 .n = { .min = IRONLAKE_DP_N_MIN,
617 .max = IRONLAKE_DP_N_MAX },
618 .m = { .min = IRONLAKE_DP_M_MIN,
619 .max = IRONLAKE_DP_M_MAX },
620 .m1 = { .min = IRONLAKE_M1_MIN,
621 .max = IRONLAKE_M1_MAX },
622 .m2 = { .min = IRONLAKE_M2_MIN,
623 .max = IRONLAKE_M2_MAX },
624 .p = { .min = IRONLAKE_DP_P_MIN,
625 .max = IRONLAKE_DP_P_MAX },
626 .p1 = { .min = IRONLAKE_DP_P1_MIN,
627 .max = IRONLAKE_DP_P1_MAX},
628 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
629 .p2_slow = IRONLAKE_DP_P2_SLOW,
630 .p2_fast = IRONLAKE_DP_P2_FAST },
631 .find_pll = intel_find_pll_ironlake_dp,
632 };
633
634 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
635 {
636 struct drm_device *dev = crtc->dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
638 const intel_limit_t *limit;
639 int refclk = 120;
640
641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
642 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
643 refclk = 100;
644
645 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
646 LVDS_CLKB_POWER_UP) {
647 /* LVDS dual channel */
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_dual_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_dual_lvds;
652 } else {
653 if (refclk == 100)
654 limit = &intel_limits_ironlake_single_lvds_100m;
655 else
656 limit = &intel_limits_ironlake_single_lvds;
657 }
658 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
659 HAS_eDP)
660 limit = &intel_limits_ironlake_display_port;
661 else
662 limit = &intel_limits_ironlake_dac;
663
664 return limit;
665 }
666
667 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
668 {
669 struct drm_device *dev = crtc->dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
671 const intel_limit_t *limit;
672
673 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
674 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
675 LVDS_CLKB_POWER_UP)
676 /* LVDS with dual channel */
677 limit = &intel_limits_g4x_dual_channel_lvds;
678 else
679 /* LVDS with dual channel */
680 limit = &intel_limits_g4x_single_channel_lvds;
681 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
682 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
683 limit = &intel_limits_g4x_hdmi;
684 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
685 limit = &intel_limits_g4x_sdvo;
686 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
687 limit = &intel_limits_g4x_display_port;
688 } else /* The option is for other outputs */
689 limit = &intel_limits_i9xx_sdvo;
690
691 return limit;
692 }
693
694 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
695 {
696 struct drm_device *dev = crtc->dev;
697 const intel_limit_t *limit;
698
699 if (HAS_PCH_SPLIT(dev))
700 limit = intel_ironlake_limit(crtc);
701 else if (IS_G4X(dev)) {
702 limit = intel_g4x_limit(crtc);
703 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_i9xx_lvds;
706 else
707 limit = &intel_limits_i9xx_sdvo;
708 } else if (IS_PINEVIEW(dev)) {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_pineview_lvds;
711 else
712 limit = &intel_limits_pineview_sdvo;
713 } else {
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
715 limit = &intel_limits_i8xx_lvds;
716 else
717 limit = &intel_limits_i8xx_dvo;
718 }
719 return limit;
720 }
721
722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
723 static void pineview_clock(int refclk, intel_clock_t *clock)
724 {
725 clock->m = clock->m2 + 2;
726 clock->p = clock->p1 * clock->p2;
727 clock->vco = refclk * clock->m / clock->n;
728 clock->dot = clock->vco / clock->p;
729 }
730
731 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
732 {
733 if (IS_PINEVIEW(dev)) {
734 pineview_clock(refclk, clock);
735 return;
736 }
737 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
738 clock->p = clock->p1 * clock->p2;
739 clock->vco = refclk * clock->m / (clock->n + 2);
740 clock->dot = clock->vco / clock->p;
741 }
742
743 /**
744 * Returns whether any output on the specified pipe is of the specified type
745 */
746 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
747 {
748 struct drm_device *dev = crtc->dev;
749 struct drm_mode_config *mode_config = &dev->mode_config;
750 struct drm_encoder *l_entry;
751
752 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
753 if (l_entry && l_entry->crtc == crtc) {
754 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
755 if (intel_encoder->type == type)
756 return true;
757 }
758 }
759 return false;
760 }
761
762 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
763 /**
764 * Returns whether the given set of divisors are valid for a given refclk with
765 * the given connectors.
766 */
767
768 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
769 {
770 const intel_limit_t *limit = intel_limit (crtc);
771 struct drm_device *dev = crtc->dev;
772
773 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
774 INTELPllInvalid ("p1 out of range\n");
775 if (clock->p < limit->p.min || limit->p.max < clock->p)
776 INTELPllInvalid ("p out of range\n");
777 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
778 INTELPllInvalid ("m2 out of range\n");
779 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
780 INTELPllInvalid ("m1 out of range\n");
781 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
782 INTELPllInvalid ("m1 <= m2\n");
783 if (clock->m < limit->m.min || limit->m.max < clock->m)
784 INTELPllInvalid ("m out of range\n");
785 if (clock->n < limit->n.min || limit->n.max < clock->n)
786 INTELPllInvalid ("n out of range\n");
787 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
788 INTELPllInvalid ("vco out of range\n");
789 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
790 * connector, etc., rather than just a single range.
791 */
792 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
793 INTELPllInvalid ("dot out of range\n");
794
795 return true;
796 }
797
798 static bool
799 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
800 int target, int refclk, intel_clock_t *best_clock)
801
802 {
803 struct drm_device *dev = crtc->dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 intel_clock_t clock;
806 int err = target;
807
808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
809 (I915_READ(LVDS)) != 0) {
810 /*
811 * For LVDS, if the panel is on, just rely on its current
812 * settings for dual-channel. We haven't figured out how to
813 * reliably set up different single/dual channel state, if we
814 * even can.
815 */
816 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
817 LVDS_CLKB_POWER_UP)
818 clock.p2 = limit->p2.p2_fast;
819 else
820 clock.p2 = limit->p2.p2_slow;
821 } else {
822 if (target < limit->p2.dot_limit)
823 clock.p2 = limit->p2.p2_slow;
824 else
825 clock.p2 = limit->p2.p2_fast;
826 }
827
828 memset (best_clock, 0, sizeof (*best_clock));
829
830 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
831 clock.m1++) {
832 for (clock.m2 = limit->m2.min;
833 clock.m2 <= limit->m2.max; clock.m2++) {
834 /* m1 is always 0 in Pineview */
835 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
836 break;
837 for (clock.n = limit->n.min;
838 clock.n <= limit->n.max; clock.n++) {
839 for (clock.p1 = limit->p1.min;
840 clock.p1 <= limit->p1.max; clock.p1++) {
841 int this_err;
842
843 intel_clock(dev, refclk, &clock);
844
845 if (!intel_PLL_is_valid(crtc, &clock))
846 continue;
847
848 this_err = abs(clock.dot - target);
849 if (this_err < err) {
850 *best_clock = clock;
851 err = this_err;
852 }
853 }
854 }
855 }
856 }
857
858 return (err != target);
859 }
860
861 static bool
862 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *best_clock)
864 {
865 struct drm_device *dev = crtc->dev;
866 struct drm_i915_private *dev_priv = dev->dev_private;
867 intel_clock_t clock;
868 int max_n;
869 bool found;
870 /* approximately equals target * 0.00585 */
871 int err_most = (target >> 8) + (target >> 9);
872 found = false;
873
874 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
875 int lvds_reg;
876
877 if (HAS_PCH_SPLIT(dev))
878 lvds_reg = PCH_LVDS;
879 else
880 lvds_reg = LVDS;
881 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
882 LVDS_CLKB_POWER_UP)
883 clock.p2 = limit->p2.p2_fast;
884 else
885 clock.p2 = limit->p2.p2_slow;
886 } else {
887 if (target < limit->p2.dot_limit)
888 clock.p2 = limit->p2.p2_slow;
889 else
890 clock.p2 = limit->p2.p2_fast;
891 }
892
893 memset(best_clock, 0, sizeof(*best_clock));
894 max_n = limit->n.max;
895 /* based on hardware requirement, prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
897 /* based on hardware requirement, prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) {
900 for (clock.m2 = limit->m2.max;
901 clock.m2 >= limit->m2.min; clock.m2--) {
902 for (clock.p1 = limit->p1.max;
903 clock.p1 >= limit->p1.min; clock.p1--) {
904 int this_err;
905
906 intel_clock(dev, refclk, &clock);
907 if (!intel_PLL_is_valid(crtc, &clock))
908 continue;
909 this_err = abs(clock.dot - target) ;
910 if (this_err < err_most) {
911 *best_clock = clock;
912 err_most = this_err;
913 max_n = clock.n;
914 found = true;
915 }
916 }
917 }
918 }
919 }
920 return found;
921 }
922
923 static bool
924 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
925 int target, int refclk, intel_clock_t *best_clock)
926 {
927 struct drm_device *dev = crtc->dev;
928 intel_clock_t clock;
929
930 /* return directly when it is eDP */
931 if (HAS_eDP)
932 return true;
933
934 if (target < 200000) {
935 clock.n = 1;
936 clock.p1 = 2;
937 clock.p2 = 10;
938 clock.m1 = 12;
939 clock.m2 = 9;
940 } else {
941 clock.n = 2;
942 clock.p1 = 1;
943 clock.p2 = 10;
944 clock.m1 = 14;
945 clock.m2 = 8;
946 }
947 intel_clock(dev, refclk, &clock);
948 memcpy(best_clock, &clock, sizeof(intel_clock_t));
949 return true;
950 }
951
952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
953 static bool
954 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
955 int target, int refclk, intel_clock_t *best_clock)
956 {
957 intel_clock_t clock;
958 if (target < 200000) {
959 clock.p1 = 2;
960 clock.p2 = 10;
961 clock.n = 2;
962 clock.m1 = 23;
963 clock.m2 = 8;
964 } else {
965 clock.p1 = 1;
966 clock.p2 = 10;
967 clock.n = 1;
968 clock.m1 = 14;
969 clock.m2 = 2;
970 }
971 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
972 clock.p = (clock.p1 * clock.p2);
973 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
974 clock.vco = 0;
975 memcpy(best_clock, &clock, sizeof(intel_clock_t));
976 return true;
977 }
978
979 void
980 intel_wait_for_vblank(struct drm_device *dev)
981 {
982 /* Wait for 20ms, i.e. one cycle at 50hz. */
983 if (in_dbg_master())
984 mdelay(20); /* The kernel debugger cannot call msleep() */
985 else
986 msleep(20);
987 }
988
989 /* Parameters have changed, update FBC info */
990 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
991 {
992 struct drm_device *dev = crtc->dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_framebuffer *fb = crtc->fb;
995 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
996 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
998 int plane, i;
999 u32 fbc_ctl, fbc_ctl2;
1000
1001 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1002
1003 if (fb->pitch < dev_priv->cfb_pitch)
1004 dev_priv->cfb_pitch = fb->pitch;
1005
1006 /* FBC_CTL wants 64B units */
1007 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1008 dev_priv->cfb_fence = obj_priv->fence_reg;
1009 dev_priv->cfb_plane = intel_crtc->plane;
1010 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1011
1012 /* Clear old tags */
1013 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1014 I915_WRITE(FBC_TAG + (i * 4), 0);
1015
1016 /* Set it up... */
1017 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1018 if (obj_priv->tiling_mode != I915_TILING_NONE)
1019 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1020 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1021 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1022
1023 /* enable it... */
1024 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1025 if (IS_I945GM(dev))
1026 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1027 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1028 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1029 if (obj_priv->tiling_mode != I915_TILING_NONE)
1030 fbc_ctl |= dev_priv->cfb_fence;
1031 I915_WRITE(FBC_CONTROL, fbc_ctl);
1032
1033 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1035 }
1036
1037 void i8xx_disable_fbc(struct drm_device *dev)
1038 {
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041 u32 fbc_ctl;
1042
1043 if (!I915_HAS_FBC(dev))
1044 return;
1045
1046 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1047 return; /* Already off, just return */
1048
1049 /* Disable compression */
1050 fbc_ctl = I915_READ(FBC_CONTROL);
1051 fbc_ctl &= ~FBC_CTL_EN;
1052 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053
1054 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
1056 if (time_after(jiffies, timeout)) {
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1058 break;
1059 }
1060 ; /* do nothing */
1061 }
1062
1063 intel_wait_for_vblank(dev);
1064
1065 DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_device *dev)
1069 {
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071
1072 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1073 }
1074
1075 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1076 {
1077 struct drm_device *dev = crtc->dev;
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 struct drm_framebuffer *fb = crtc->fb;
1080 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1081 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1083 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1084 DPFC_CTL_PLANEB);
1085 unsigned long stall_watermark = 200;
1086 u32 dpfc_ctl;
1087
1088 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1089 dev_priv->cfb_fence = obj_priv->fence_reg;
1090 dev_priv->cfb_plane = intel_crtc->plane;
1091
1092 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1093 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1094 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1095 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1096 } else {
1097 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1098 }
1099
1100 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1101 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1102 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1103 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1104 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1105
1106 /* enable it... */
1107 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1108
1109 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1110 }
1111
1112 void g4x_disable_fbc(struct drm_device *dev)
1113 {
1114 struct drm_i915_private *dev_priv = dev->dev_private;
1115 u32 dpfc_ctl;
1116
1117 /* Disable compression */
1118 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122
1123 DRM_DEBUG_KMS("disabled FBC\n");
1124 }
1125
1126 static bool g4x_fbc_enabled(struct drm_device *dev)
1127 {
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1131 }
1132
1133 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1134 {
1135 struct drm_device *dev = crtc->dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
1137 struct drm_framebuffer *fb = crtc->fb;
1138 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1139 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1141 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1142 DPFC_CTL_PLANEB;
1143 unsigned long stall_watermark = 200;
1144 u32 dpfc_ctl;
1145
1146 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1147 dev_priv->cfb_fence = obj_priv->fence_reg;
1148 dev_priv->cfb_plane = intel_crtc->plane;
1149
1150 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1151 dpfc_ctl &= DPFC_RESERVED;
1152 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1153 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1154 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1155 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1156 } else {
1157 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1158 }
1159
1160 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1161 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1162 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1163 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1164 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1165 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1166 /* enable it... */
1167 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1168 DPFC_CTL_EN);
1169
1170 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1171 }
1172
1173 void ironlake_disable_fbc(struct drm_device *dev)
1174 {
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 u32 dpfc_ctl;
1177
1178 /* Disable compression */
1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180 dpfc_ctl &= ~DPFC_CTL_EN;
1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182 intel_wait_for_vblank(dev);
1183
1184 DRM_DEBUG_KMS("disabled FBC\n");
1185 }
1186
1187 static bool ironlake_fbc_enabled(struct drm_device *dev)
1188 {
1189 struct drm_i915_private *dev_priv = dev->dev_private;
1190
1191 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1192 }
1193
1194 bool intel_fbc_enabled(struct drm_device *dev)
1195 {
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197
1198 if (!dev_priv->display.fbc_enabled)
1199 return false;
1200
1201 return dev_priv->display.fbc_enabled(dev);
1202 }
1203
1204 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1205 {
1206 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1207
1208 if (!dev_priv->display.enable_fbc)
1209 return;
1210
1211 dev_priv->display.enable_fbc(crtc, interval);
1212 }
1213
1214 void intel_disable_fbc(struct drm_device *dev)
1215 {
1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217
1218 if (!dev_priv->display.disable_fbc)
1219 return;
1220
1221 dev_priv->display.disable_fbc(dev);
1222 }
1223
1224 /**
1225 * intel_update_fbc - enable/disable FBC as needed
1226 * @crtc: CRTC to point the compressor at
1227 * @mode: mode in use
1228 *
1229 * Set up the framebuffer compression hardware at mode set time. We
1230 * enable it if possible:
1231 * - plane A only (on pre-965)
1232 * - no pixel mulitply/line duplication
1233 * - no alpha buffer discard
1234 * - no dual wide
1235 * - framebuffer <= 2048 in width, 1536 in height
1236 *
1237 * We can't assume that any compression will take place (worst case),
1238 * so the compressed buffer has to be the same size as the uncompressed
1239 * one. It also must reside (along with the line length buffer) in
1240 * stolen memory.
1241 *
1242 * We need to enable/disable FBC on a global basis.
1243 */
1244 static void intel_update_fbc(struct drm_crtc *crtc,
1245 struct drm_display_mode *mode)
1246 {
1247 struct drm_device *dev = crtc->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 struct drm_framebuffer *fb = crtc->fb;
1250 struct intel_framebuffer *intel_fb;
1251 struct drm_i915_gem_object *obj_priv;
1252 struct drm_crtc *tmp_crtc;
1253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1254 int plane = intel_crtc->plane;
1255 int crtcs_enabled = 0;
1256
1257 DRM_DEBUG_KMS("\n");
1258
1259 if (!i915_powersave)
1260 return;
1261
1262 if (!I915_HAS_FBC(dev))
1263 return;
1264
1265 if (!crtc->fb)
1266 return;
1267
1268 intel_fb = to_intel_framebuffer(fb);
1269 obj_priv = to_intel_bo(intel_fb->obj);
1270
1271 /*
1272 * If FBC is already on, we just have to verify that we can
1273 * keep it that way...
1274 * Need to disable if:
1275 * - more than one pipe is active
1276 * - changing FBC params (stride, fence, mode)
1277 * - new fb is too large to fit in compressed buffer
1278 * - going to an unsupported config (interlace, pixel multiply, etc.)
1279 */
1280 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1281 if (tmp_crtc->enabled)
1282 crtcs_enabled++;
1283 }
1284 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1285 if (crtcs_enabled > 1) {
1286 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1287 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1288 goto out_disable;
1289 }
1290 if (intel_fb->obj->size > dev_priv->cfb_size) {
1291 DRM_DEBUG_KMS("framebuffer too large, disabling "
1292 "compression\n");
1293 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1294 goto out_disable;
1295 }
1296 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1297 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1298 DRM_DEBUG_KMS("mode incompatible with compression, "
1299 "disabling\n");
1300 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1301 goto out_disable;
1302 }
1303 if ((mode->hdisplay > 2048) ||
1304 (mode->vdisplay > 1536)) {
1305 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1306 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1307 goto out_disable;
1308 }
1309 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1310 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1311 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1312 goto out_disable;
1313 }
1314 if (obj_priv->tiling_mode != I915_TILING_X) {
1315 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1316 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1317 goto out_disable;
1318 }
1319
1320 /* If the kernel debugger is active, always disable compression */
1321 if (in_dbg_master())
1322 goto out_disable;
1323
1324 if (intel_fbc_enabled(dev)) {
1325 /* We can re-enable it in this case, but need to update pitch */
1326 if ((fb->pitch > dev_priv->cfb_pitch) ||
1327 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1328 (plane != dev_priv->cfb_plane))
1329 intel_disable_fbc(dev);
1330 }
1331
1332 /* Now try to turn it back on if possible */
1333 if (!intel_fbc_enabled(dev))
1334 intel_enable_fbc(crtc, 500);
1335
1336 return;
1337
1338 out_disable:
1339 /* Multiple disables should be harmless */
1340 if (intel_fbc_enabled(dev)) {
1341 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1342 intel_disable_fbc(dev);
1343 }
1344 }
1345
1346 int
1347 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1348 {
1349 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1350 u32 alignment;
1351 int ret;
1352
1353 switch (obj_priv->tiling_mode) {
1354 case I915_TILING_NONE:
1355 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1356 alignment = 128 * 1024;
1357 else if (IS_I965G(dev))
1358 alignment = 4 * 1024;
1359 else
1360 alignment = 64 * 1024;
1361 break;
1362 case I915_TILING_X:
1363 /* pin() will align the object as required by fence */
1364 alignment = 0;
1365 break;
1366 case I915_TILING_Y:
1367 /* FIXME: Is this true? */
1368 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1369 return -EINVAL;
1370 default:
1371 BUG();
1372 }
1373
1374 ret = i915_gem_object_pin(obj, alignment);
1375 if (ret != 0)
1376 return ret;
1377
1378 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1379 * fence, whereas 965+ only requires a fence if using
1380 * framebuffer compression. For simplicity, we always install
1381 * a fence as the cost is not that onerous.
1382 */
1383 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1384 obj_priv->tiling_mode != I915_TILING_NONE) {
1385 ret = i915_gem_object_get_fence_reg(obj);
1386 if (ret != 0) {
1387 i915_gem_object_unpin(obj);
1388 return ret;
1389 }
1390 }
1391
1392 return 0;
1393 }
1394
1395 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1396 static int
1397 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1398 int x, int y)
1399 {
1400 struct drm_device *dev = crtc->dev;
1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1403 struct intel_framebuffer *intel_fb;
1404 struct drm_i915_gem_object *obj_priv;
1405 struct drm_gem_object *obj;
1406 int plane = intel_crtc->plane;
1407 unsigned long Start, Offset;
1408 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1409 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1410 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1411 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1412 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1413 u32 dspcntr;
1414
1415 switch (plane) {
1416 case 0:
1417 case 1:
1418 break;
1419 default:
1420 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1421 return -EINVAL;
1422 }
1423
1424 intel_fb = to_intel_framebuffer(fb);
1425 obj = intel_fb->obj;
1426 obj_priv = to_intel_bo(obj);
1427
1428 dspcntr = I915_READ(dspcntr_reg);
1429 /* Mask out pixel format bits in case we change it */
1430 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1431 switch (fb->bits_per_pixel) {
1432 case 8:
1433 dspcntr |= DISPPLANE_8BPP;
1434 break;
1435 case 16:
1436 if (fb->depth == 15)
1437 dspcntr |= DISPPLANE_15_16BPP;
1438 else
1439 dspcntr |= DISPPLANE_16BPP;
1440 break;
1441 case 24:
1442 case 32:
1443 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1444 break;
1445 default:
1446 DRM_ERROR("Unknown color depth\n");
1447 return -EINVAL;
1448 }
1449 if (IS_I965G(dev)) {
1450 if (obj_priv->tiling_mode != I915_TILING_NONE)
1451 dspcntr |= DISPPLANE_TILED;
1452 else
1453 dspcntr &= ~DISPPLANE_TILED;
1454 }
1455
1456 if (IS_IRONLAKE(dev))
1457 /* must disable */
1458 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459
1460 I915_WRITE(dspcntr_reg, dspcntr);
1461
1462 Start = obj_priv->gtt_offset;
1463 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1466 I915_WRITE(dspstride, fb->pitch);
1467 if (IS_I965G(dev)) {
1468 I915_WRITE(dspbase, Offset);
1469 I915_READ(dspbase);
1470 I915_WRITE(dspsurf, Start);
1471 I915_READ(dspsurf);
1472 I915_WRITE(dsptileoff, (y << 16) | x);
1473 } else {
1474 I915_WRITE(dspbase, Start + Offset);
1475 I915_READ(dspbase);
1476 }
1477
1478 if ((IS_I965G(dev) || plane == 0))
1479 intel_update_fbc(crtc, &crtc->mode);
1480
1481 intel_wait_for_vblank(dev);
1482 intel_increase_pllclock(crtc, true);
1483
1484 return 0;
1485 }
1486
1487 static int
1488 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489 struct drm_framebuffer *old_fb)
1490 {
1491 struct drm_device *dev = crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 struct drm_i915_master_private *master_priv;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb;
1496 struct drm_i915_gem_object *obj_priv;
1497 struct drm_gem_object *obj;
1498 int pipe = intel_crtc->pipe;
1499 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506 u32 dspcntr;
1507 int ret;
1508
1509 /* no fb bound */
1510 if (!crtc->fb) {
1511 DRM_DEBUG_KMS("No FB bound\n");
1512 return 0;
1513 }
1514
1515 switch (plane) {
1516 case 0:
1517 case 1:
1518 break;
1519 default:
1520 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1521 return -EINVAL;
1522 }
1523
1524 intel_fb = to_intel_framebuffer(crtc->fb);
1525 obj = intel_fb->obj;
1526 obj_priv = to_intel_bo(obj);
1527
1528 mutex_lock(&dev->struct_mutex);
1529 ret = intel_pin_and_fence_fb_obj(dev, obj);
1530 if (ret != 0) {
1531 mutex_unlock(&dev->struct_mutex);
1532 return ret;
1533 }
1534
1535 ret = i915_gem_object_set_to_display_plane(obj);
1536 if (ret != 0) {
1537 i915_gem_object_unpin(obj);
1538 mutex_unlock(&dev->struct_mutex);
1539 return ret;
1540 }
1541
1542 dspcntr = I915_READ(dspcntr_reg);
1543 /* Mask out pixel format bits in case we change it */
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (crtc->fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (crtc->fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 if (crtc->fb->depth == 30)
1558 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559 else
1560 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561 break;
1562 default:
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj);
1565 mutex_unlock(&dev->struct_mutex);
1566 return -EINVAL;
1567 }
1568 if (IS_I965G(dev)) {
1569 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570 dspcntr |= DISPPLANE_TILED;
1571 else
1572 dspcntr &= ~DISPPLANE_TILED;
1573 }
1574
1575 if (HAS_PCH_SPLIT(dev))
1576 /* must disable */
1577 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579 I915_WRITE(dspcntr_reg, dspcntr);
1580
1581 Start = obj_priv->gtt_offset;
1582 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start, Offset, x, y, crtc->fb->pitch);
1586 I915_WRITE(dspstride, crtc->fb->pitch);
1587 if (IS_I965G(dev)) {
1588 I915_WRITE(dspsurf, Start);
1589 I915_WRITE(dsptileoff, (y << 16) | x);
1590 I915_WRITE(dspbase, Offset);
1591 } else {
1592 I915_WRITE(dspbase, Start + Offset);
1593 }
1594 POSTING_READ(dspbase);
1595
1596 if ((IS_I965G(dev) || plane == 0))
1597 intel_update_fbc(crtc, &crtc->mode);
1598
1599 intel_wait_for_vblank(dev);
1600
1601 if (old_fb) {
1602 intel_fb = to_intel_framebuffer(old_fb);
1603 obj_priv = to_intel_bo(intel_fb->obj);
1604 i915_gem_object_unpin(intel_fb->obj);
1605 }
1606 intel_increase_pllclock(crtc, true);
1607
1608 mutex_unlock(&dev->struct_mutex);
1609
1610 if (!dev->primary->master)
1611 return 0;
1612
1613 master_priv = dev->primary->master->driver_priv;
1614 if (!master_priv->sarea_priv)
1615 return 0;
1616
1617 if (pipe) {
1618 master_priv->sarea_priv->pipeB_x = x;
1619 master_priv->sarea_priv->pipeB_y = y;
1620 } else {
1621 master_priv->sarea_priv->pipeA_x = x;
1622 master_priv->sarea_priv->pipeA_y = y;
1623 }
1624
1625 return 0;
1626 }
1627
1628 /* Disable the VGA plane that we never use */
1629 static void i915_disable_vga (struct drm_device *dev)
1630 {
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 u8 sr1;
1633 u32 vga_reg;
1634
1635 if (HAS_PCH_SPLIT(dev))
1636 vga_reg = CPU_VGACNTRL;
1637 else
1638 vga_reg = VGACNTRL;
1639
1640 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1641 return;
1642
1643 I915_WRITE8(VGA_SR_INDEX, 1);
1644 sr1 = I915_READ8(VGA_SR_DATA);
1645 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1646 udelay(100);
1647
1648 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1649 }
1650
1651 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1652 {
1653 struct drm_device *dev = crtc->dev;
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1655 u32 dpa_ctl;
1656
1657 DRM_DEBUG_KMS("\n");
1658 dpa_ctl = I915_READ(DP_A);
1659 dpa_ctl &= ~DP_PLL_ENABLE;
1660 I915_WRITE(DP_A, dpa_ctl);
1661 }
1662
1663 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1664 {
1665 struct drm_device *dev = crtc->dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 u32 dpa_ctl;
1668
1669 dpa_ctl = I915_READ(DP_A);
1670 dpa_ctl |= DP_PLL_ENABLE;
1671 I915_WRITE(DP_A, dpa_ctl);
1672 udelay(200);
1673 }
1674
1675
1676 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1677 {
1678 struct drm_device *dev = crtc->dev;
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 u32 dpa_ctl;
1681
1682 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1683 dpa_ctl = I915_READ(DP_A);
1684 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1685
1686 if (clock < 200000) {
1687 u32 temp;
1688 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1689 /* workaround for 160Mhz:
1690 1) program 0x4600c bits 15:0 = 0x8124
1691 2) program 0x46010 bit 0 = 1
1692 3) program 0x46034 bit 24 = 1
1693 4) program 0x64000 bit 14 = 1
1694 */
1695 temp = I915_READ(0x4600c);
1696 temp &= 0xffff0000;
1697 I915_WRITE(0x4600c, temp | 0x8124);
1698
1699 temp = I915_READ(0x46010);
1700 I915_WRITE(0x46010, temp | 1);
1701
1702 temp = I915_READ(0x46034);
1703 I915_WRITE(0x46034, temp | (1 << 24));
1704 } else {
1705 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1706 }
1707 I915_WRITE(DP_A, dpa_ctl);
1708
1709 udelay(500);
1710 }
1711
1712 /* The FDI link training functions for ILK/Ibexpeak. */
1713 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1714 {
1715 struct drm_device *dev = crtc->dev;
1716 struct drm_i915_private *dev_priv = dev->dev_private;
1717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1718 int pipe = intel_crtc->pipe;
1719 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1720 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1721 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1722 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1723 u32 temp, tries = 0;
1724
1725 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1726 for train result */
1727 temp = I915_READ(fdi_rx_imr_reg);
1728 temp &= ~FDI_RX_SYMBOL_LOCK;
1729 temp &= ~FDI_RX_BIT_LOCK;
1730 I915_WRITE(fdi_rx_imr_reg, temp);
1731 I915_READ(fdi_rx_imr_reg);
1732 udelay(150);
1733
1734 /* enable CPU FDI TX and PCH FDI RX */
1735 temp = I915_READ(fdi_tx_reg);
1736 temp |= FDI_TX_ENABLE;
1737 temp &= ~(7 << 19);
1738 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1739 temp &= ~FDI_LINK_TRAIN_NONE;
1740 temp |= FDI_LINK_TRAIN_PATTERN_1;
1741 I915_WRITE(fdi_tx_reg, temp);
1742 I915_READ(fdi_tx_reg);
1743
1744 temp = I915_READ(fdi_rx_reg);
1745 temp &= ~FDI_LINK_TRAIN_NONE;
1746 temp |= FDI_LINK_TRAIN_PATTERN_1;
1747 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1748 I915_READ(fdi_rx_reg);
1749 udelay(150);
1750
1751 for (tries = 0; tries < 5; tries++) {
1752 temp = I915_READ(fdi_rx_iir_reg);
1753 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1754
1755 if ((temp & FDI_RX_BIT_LOCK)) {
1756 DRM_DEBUG_KMS("FDI train 1 done.\n");
1757 I915_WRITE(fdi_rx_iir_reg,
1758 temp | FDI_RX_BIT_LOCK);
1759 break;
1760 }
1761 }
1762 if (tries == 5)
1763 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1764
1765 /* Train 2 */
1766 temp = I915_READ(fdi_tx_reg);
1767 temp &= ~FDI_LINK_TRAIN_NONE;
1768 temp |= FDI_LINK_TRAIN_PATTERN_2;
1769 I915_WRITE(fdi_tx_reg, temp);
1770
1771 temp = I915_READ(fdi_rx_reg);
1772 temp &= ~FDI_LINK_TRAIN_NONE;
1773 temp |= FDI_LINK_TRAIN_PATTERN_2;
1774 I915_WRITE(fdi_rx_reg, temp);
1775 udelay(150);
1776
1777 tries = 0;
1778
1779 for (tries = 0; tries < 5; tries++) {
1780 temp = I915_READ(fdi_rx_iir_reg);
1781 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1782
1783 if (temp & FDI_RX_SYMBOL_LOCK) {
1784 I915_WRITE(fdi_rx_iir_reg,
1785 temp | FDI_RX_SYMBOL_LOCK);
1786 DRM_DEBUG_KMS("FDI train 2 done.\n");
1787 break;
1788 }
1789 }
1790 if (tries == 5)
1791 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1792
1793 DRM_DEBUG_KMS("FDI train done\n");
1794 }
1795
1796 static int snb_b_fdi_train_param [] = {
1797 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1798 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1799 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1800 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1801 };
1802
1803 /* The FDI link training functions for SNB/Cougarpoint. */
1804 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1805 {
1806 struct drm_device *dev = crtc->dev;
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1809 int pipe = intel_crtc->pipe;
1810 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1811 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1812 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1813 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1814 u32 temp, i;
1815
1816 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1817 for train result */
1818 temp = I915_READ(fdi_rx_imr_reg);
1819 temp &= ~FDI_RX_SYMBOL_LOCK;
1820 temp &= ~FDI_RX_BIT_LOCK;
1821 I915_WRITE(fdi_rx_imr_reg, temp);
1822 I915_READ(fdi_rx_imr_reg);
1823 udelay(150);
1824
1825 /* enable CPU FDI TX and PCH FDI RX */
1826 temp = I915_READ(fdi_tx_reg);
1827 temp |= FDI_TX_ENABLE;
1828 temp &= ~(7 << 19);
1829 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1830 temp &= ~FDI_LINK_TRAIN_NONE;
1831 temp |= FDI_LINK_TRAIN_PATTERN_1;
1832 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1833 /* SNB-B */
1834 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1835 I915_WRITE(fdi_tx_reg, temp);
1836 I915_READ(fdi_tx_reg);
1837
1838 temp = I915_READ(fdi_rx_reg);
1839 if (HAS_PCH_CPT(dev)) {
1840 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1841 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1842 } else {
1843 temp &= ~FDI_LINK_TRAIN_NONE;
1844 temp |= FDI_LINK_TRAIN_PATTERN_1;
1845 }
1846 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1847 I915_READ(fdi_rx_reg);
1848 udelay(150);
1849
1850 for (i = 0; i < 4; i++ ) {
1851 temp = I915_READ(fdi_tx_reg);
1852 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1853 temp |= snb_b_fdi_train_param[i];
1854 I915_WRITE(fdi_tx_reg, temp);
1855 udelay(500);
1856
1857 temp = I915_READ(fdi_rx_iir_reg);
1858 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1859
1860 if (temp & FDI_RX_BIT_LOCK) {
1861 I915_WRITE(fdi_rx_iir_reg,
1862 temp | FDI_RX_BIT_LOCK);
1863 DRM_DEBUG_KMS("FDI train 1 done.\n");
1864 break;
1865 }
1866 }
1867 if (i == 4)
1868 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1869
1870 /* Train 2 */
1871 temp = I915_READ(fdi_tx_reg);
1872 temp &= ~FDI_LINK_TRAIN_NONE;
1873 temp |= FDI_LINK_TRAIN_PATTERN_2;
1874 if (IS_GEN6(dev)) {
1875 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1876 /* SNB-B */
1877 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1878 }
1879 I915_WRITE(fdi_tx_reg, temp);
1880
1881 temp = I915_READ(fdi_rx_reg);
1882 if (HAS_PCH_CPT(dev)) {
1883 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1884 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1885 } else {
1886 temp &= ~FDI_LINK_TRAIN_NONE;
1887 temp |= FDI_LINK_TRAIN_PATTERN_2;
1888 }
1889 I915_WRITE(fdi_rx_reg, temp);
1890 udelay(150);
1891
1892 for (i = 0; i < 4; i++ ) {
1893 temp = I915_READ(fdi_tx_reg);
1894 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1895 temp |= snb_b_fdi_train_param[i];
1896 I915_WRITE(fdi_tx_reg, temp);
1897 udelay(500);
1898
1899 temp = I915_READ(fdi_rx_iir_reg);
1900 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1901
1902 if (temp & FDI_RX_SYMBOL_LOCK) {
1903 I915_WRITE(fdi_rx_iir_reg,
1904 temp | FDI_RX_SYMBOL_LOCK);
1905 DRM_DEBUG_KMS("FDI train 2 done.\n");
1906 break;
1907 }
1908 }
1909 if (i == 4)
1910 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1911
1912 DRM_DEBUG_KMS("FDI train done.\n");
1913 }
1914
1915 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1916 {
1917 struct drm_device *dev = crtc->dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1920 int pipe = intel_crtc->pipe;
1921 int plane = intel_crtc->plane;
1922 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1923 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1924 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1925 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1926 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1927 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1928 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1929 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1930 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1931 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1932 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1933 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1934 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1935 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1936 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1937 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1938 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1939 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1940 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1941 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1942 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1943 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1944 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1945 u32 temp;
1946 int n;
1947 u32 pipe_bpc;
1948
1949 temp = I915_READ(pipeconf_reg);
1950 pipe_bpc = temp & PIPE_BPC_MASK;
1951
1952 /* XXX: When our outputs are all unaware of DPMS modes other than off
1953 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1954 */
1955 switch (mode) {
1956 case DRM_MODE_DPMS_ON:
1957 case DRM_MODE_DPMS_STANDBY:
1958 case DRM_MODE_DPMS_SUSPEND:
1959 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1960
1961 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1962 temp = I915_READ(PCH_LVDS);
1963 if ((temp & LVDS_PORT_EN) == 0) {
1964 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1965 POSTING_READ(PCH_LVDS);
1966 }
1967 }
1968
1969 if (HAS_eDP) {
1970 /* enable eDP PLL */
1971 ironlake_enable_pll_edp(crtc);
1972 } else {
1973
1974 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1975 temp = I915_READ(fdi_rx_reg);
1976 /*
1977 * make the BPC in FDI Rx be consistent with that in
1978 * pipeconf reg.
1979 */
1980 temp &= ~(0x7 << 16);
1981 temp |= (pipe_bpc << 11);
1982 temp &= ~(7 << 19);
1983 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1984 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1985 I915_READ(fdi_rx_reg);
1986 udelay(200);
1987
1988 /* Switch from Rawclk to PCDclk */
1989 temp = I915_READ(fdi_rx_reg);
1990 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1991 I915_READ(fdi_rx_reg);
1992 udelay(200);
1993
1994 /* Enable CPU FDI TX PLL, always on for Ironlake */
1995 temp = I915_READ(fdi_tx_reg);
1996 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1997 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1998 I915_READ(fdi_tx_reg);
1999 udelay(100);
2000 }
2001 }
2002
2003 /* Enable panel fitting for LVDS */
2004 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2005 || HAS_eDP || intel_pch_has_edp(crtc)) {
2006 if (dev_priv->pch_pf_size) {
2007 temp = I915_READ(pf_ctl_reg);
2008 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
2009 I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
2010 I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
2011 } else
2012 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2013 }
2014
2015 /* Enable CPU pipe */
2016 temp = I915_READ(pipeconf_reg);
2017 if ((temp & PIPEACONF_ENABLE) == 0) {
2018 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2019 I915_READ(pipeconf_reg);
2020 udelay(100);
2021 }
2022
2023 /* configure and enable CPU plane */
2024 temp = I915_READ(dspcntr_reg);
2025 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2026 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2027 /* Flush the plane changes */
2028 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2029 }
2030
2031 if (!HAS_eDP) {
2032 /* For PCH output, training FDI link */
2033 if (IS_GEN6(dev))
2034 gen6_fdi_link_train(crtc);
2035 else
2036 ironlake_fdi_link_train(crtc);
2037
2038 /* enable PCH DPLL */
2039 temp = I915_READ(pch_dpll_reg);
2040 if ((temp & DPLL_VCO_ENABLE) == 0) {
2041 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
2042 I915_READ(pch_dpll_reg);
2043 }
2044 udelay(200);
2045
2046 if (HAS_PCH_CPT(dev)) {
2047 /* Be sure PCH DPLL SEL is set */
2048 temp = I915_READ(PCH_DPLL_SEL);
2049 if (trans_dpll_sel == 0 &&
2050 (temp & TRANSA_DPLL_ENABLE) == 0)
2051 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2052 else if (trans_dpll_sel == 1 &&
2053 (temp & TRANSB_DPLL_ENABLE) == 0)
2054 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2055 I915_WRITE(PCH_DPLL_SEL, temp);
2056 I915_READ(PCH_DPLL_SEL);
2057 }
2058
2059 /* set transcoder timing */
2060 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
2061 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
2062 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2063
2064 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2065 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2066 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2067
2068 /* enable normal train */
2069 temp = I915_READ(fdi_tx_reg);
2070 temp &= ~FDI_LINK_TRAIN_NONE;
2071 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2072 FDI_TX_ENHANCE_FRAME_ENABLE);
2073 I915_READ(fdi_tx_reg);
2074
2075 temp = I915_READ(fdi_rx_reg);
2076 if (HAS_PCH_CPT(dev)) {
2077 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2078 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2079 } else {
2080 temp &= ~FDI_LINK_TRAIN_NONE;
2081 temp |= FDI_LINK_TRAIN_NONE;
2082 }
2083 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2084 I915_READ(fdi_rx_reg);
2085
2086 /* wait one idle pattern time */
2087 udelay(100);
2088
2089 /* For PCH DP, enable TRANS_DP_CTL */
2090 if (HAS_PCH_CPT(dev) &&
2091 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2092 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2093 int reg;
2094
2095 reg = I915_READ(trans_dp_ctl);
2096 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2097 TRANS_DP_SYNC_MASK);
2098 reg |= (TRANS_DP_OUTPUT_ENABLE |
2099 TRANS_DP_ENH_FRAMING);
2100
2101 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2102 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2103 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2104 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2105
2106 switch (intel_trans_dp_port_sel(crtc)) {
2107 case PCH_DP_B:
2108 reg |= TRANS_DP_PORT_SEL_B;
2109 break;
2110 case PCH_DP_C:
2111 reg |= TRANS_DP_PORT_SEL_C;
2112 break;
2113 case PCH_DP_D:
2114 reg |= TRANS_DP_PORT_SEL_D;
2115 break;
2116 default:
2117 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2118 reg |= TRANS_DP_PORT_SEL_B;
2119 break;
2120 }
2121
2122 I915_WRITE(trans_dp_ctl, reg);
2123 POSTING_READ(trans_dp_ctl);
2124 }
2125
2126 /* enable PCH transcoder */
2127 temp = I915_READ(transconf_reg);
2128 /*
2129 * make the BPC in transcoder be consistent with
2130 * that in pipeconf reg.
2131 */
2132 temp &= ~PIPE_BPC_MASK;
2133 temp |= pipe_bpc;
2134 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2135 I915_READ(transconf_reg);
2136
2137 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
2138 ;
2139
2140 }
2141
2142 intel_crtc_load_lut(crtc);
2143
2144 intel_update_fbc(crtc, &crtc->mode);
2145 break;
2146
2147 case DRM_MODE_DPMS_OFF:
2148 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2149
2150 drm_vblank_off(dev, pipe);
2151 /* Disable display plane */
2152 temp = I915_READ(dspcntr_reg);
2153 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2154 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2155 /* Flush the plane changes */
2156 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2157 I915_READ(dspbase_reg);
2158 }
2159
2160 if (dev_priv->cfb_plane == plane &&
2161 dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
2163
2164 i915_disable_vga(dev);
2165
2166 /* disable cpu pipe, disable after all planes disabled */
2167 temp = I915_READ(pipeconf_reg);
2168 if ((temp & PIPEACONF_ENABLE) != 0) {
2169 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2170 I915_READ(pipeconf_reg);
2171 n = 0;
2172 /* wait for cpu pipe off, pipe state */
2173 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
2174 n++;
2175 if (n < 60) {
2176 udelay(500);
2177 continue;
2178 } else {
2179 DRM_DEBUG_KMS("pipe %d off delay\n",
2180 pipe);
2181 break;
2182 }
2183 }
2184 } else
2185 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2186
2187 udelay(100);
2188
2189 /* Disable PF */
2190 temp = I915_READ(pf_ctl_reg);
2191 if ((temp & PF_ENABLE) != 0) {
2192 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2193 I915_READ(pf_ctl_reg);
2194 }
2195 I915_WRITE(pf_win_size, 0);
2196 POSTING_READ(pf_win_size);
2197
2198
2199 /* disable CPU FDI tx and PCH FDI rx */
2200 temp = I915_READ(fdi_tx_reg);
2201 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2202 I915_READ(fdi_tx_reg);
2203
2204 temp = I915_READ(fdi_rx_reg);
2205 /* BPC in FDI rx is consistent with that in pipeconf */
2206 temp &= ~(0x07 << 16);
2207 temp |= (pipe_bpc << 11);
2208 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2209 I915_READ(fdi_rx_reg);
2210
2211 udelay(100);
2212
2213 /* still set train pattern 1 */
2214 temp = I915_READ(fdi_tx_reg);
2215 temp &= ~FDI_LINK_TRAIN_NONE;
2216 temp |= FDI_LINK_TRAIN_PATTERN_1;
2217 I915_WRITE(fdi_tx_reg, temp);
2218 POSTING_READ(fdi_tx_reg);
2219
2220 temp = I915_READ(fdi_rx_reg);
2221 if (HAS_PCH_CPT(dev)) {
2222 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2223 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2224 } else {
2225 temp &= ~FDI_LINK_TRAIN_NONE;
2226 temp |= FDI_LINK_TRAIN_PATTERN_1;
2227 }
2228 I915_WRITE(fdi_rx_reg, temp);
2229 POSTING_READ(fdi_rx_reg);
2230
2231 udelay(100);
2232
2233 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2234 temp = I915_READ(PCH_LVDS);
2235 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2236 I915_READ(PCH_LVDS);
2237 udelay(100);
2238 }
2239
2240 /* disable PCH transcoder */
2241 temp = I915_READ(transconf_reg);
2242 if ((temp & TRANS_ENABLE) != 0) {
2243 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2244 I915_READ(transconf_reg);
2245 n = 0;
2246 /* wait for PCH transcoder off, transcoder state */
2247 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
2248 n++;
2249 if (n < 60) {
2250 udelay(500);
2251 continue;
2252 } else {
2253 DRM_DEBUG_KMS("transcoder %d off "
2254 "delay\n", pipe);
2255 break;
2256 }
2257 }
2258 }
2259
2260 temp = I915_READ(transconf_reg);
2261 /* BPC in transcoder is consistent with that in pipeconf */
2262 temp &= ~PIPE_BPC_MASK;
2263 temp |= pipe_bpc;
2264 I915_WRITE(transconf_reg, temp);
2265 I915_READ(transconf_reg);
2266 udelay(100);
2267
2268 if (HAS_PCH_CPT(dev)) {
2269 /* disable TRANS_DP_CTL */
2270 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2271 int reg;
2272
2273 reg = I915_READ(trans_dp_ctl);
2274 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2275 I915_WRITE(trans_dp_ctl, reg);
2276 POSTING_READ(trans_dp_ctl);
2277
2278 /* disable DPLL_SEL */
2279 temp = I915_READ(PCH_DPLL_SEL);
2280 if (trans_dpll_sel == 0)
2281 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2282 else
2283 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2284 I915_WRITE(PCH_DPLL_SEL, temp);
2285 I915_READ(PCH_DPLL_SEL);
2286
2287 }
2288
2289 /* disable PCH DPLL */
2290 temp = I915_READ(pch_dpll_reg);
2291 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2292 I915_READ(pch_dpll_reg);
2293
2294 if (HAS_eDP) {
2295 ironlake_disable_pll_edp(crtc);
2296 }
2297
2298 /* Switch from PCDclk to Rawclk */
2299 temp = I915_READ(fdi_rx_reg);
2300 temp &= ~FDI_SEL_PCDCLK;
2301 I915_WRITE(fdi_rx_reg, temp);
2302 I915_READ(fdi_rx_reg);
2303
2304 /* Disable CPU FDI TX PLL */
2305 temp = I915_READ(fdi_tx_reg);
2306 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2307 I915_READ(fdi_tx_reg);
2308 udelay(100);
2309
2310 temp = I915_READ(fdi_rx_reg);
2311 temp &= ~FDI_RX_PLL_ENABLE;
2312 I915_WRITE(fdi_rx_reg, temp);
2313 I915_READ(fdi_rx_reg);
2314
2315 /* Wait for the clocks to turn off. */
2316 udelay(100);
2317 break;
2318 }
2319 }
2320
2321 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2322 {
2323 struct intel_overlay *overlay;
2324 int ret;
2325
2326 if (!enable && intel_crtc->overlay) {
2327 overlay = intel_crtc->overlay;
2328 mutex_lock(&overlay->dev->struct_mutex);
2329 for (;;) {
2330 ret = intel_overlay_switch_off(overlay);
2331 if (ret == 0)
2332 break;
2333
2334 ret = intel_overlay_recover_from_interrupt(overlay, 0);
2335 if (ret != 0) {
2336 /* overlay doesn't react anymore. Usually
2337 * results in a black screen and an unkillable
2338 * X server. */
2339 BUG();
2340 overlay->hw_wedged = HW_WEDGED;
2341 break;
2342 }
2343 }
2344 mutex_unlock(&overlay->dev->struct_mutex);
2345 }
2346 /* Let userspace switch the overlay on again. In most cases userspace
2347 * has to recompute where to put it anyway. */
2348
2349 return;
2350 }
2351
2352 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2353 {
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2357 int pipe = intel_crtc->pipe;
2358 int plane = intel_crtc->plane;
2359 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2360 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2361 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2362 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2363 u32 temp;
2364
2365 /* XXX: When our outputs are all unaware of DPMS modes other than off
2366 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2367 */
2368 switch (mode) {
2369 case DRM_MODE_DPMS_ON:
2370 case DRM_MODE_DPMS_STANDBY:
2371 case DRM_MODE_DPMS_SUSPEND:
2372 /* Enable the DPLL */
2373 temp = I915_READ(dpll_reg);
2374 if ((temp & DPLL_VCO_ENABLE) == 0) {
2375 I915_WRITE(dpll_reg, temp);
2376 I915_READ(dpll_reg);
2377 /* Wait for the clocks to stabilize. */
2378 udelay(150);
2379 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2380 I915_READ(dpll_reg);
2381 /* Wait for the clocks to stabilize. */
2382 udelay(150);
2383 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2384 I915_READ(dpll_reg);
2385 /* Wait for the clocks to stabilize. */
2386 udelay(150);
2387 }
2388
2389 /* Enable the pipe */
2390 temp = I915_READ(pipeconf_reg);
2391 if ((temp & PIPEACONF_ENABLE) == 0)
2392 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2393
2394 /* Enable the plane */
2395 temp = I915_READ(dspcntr_reg);
2396 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2397 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2398 /* Flush the plane changes */
2399 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2400 }
2401
2402 intel_crtc_load_lut(crtc);
2403
2404 if ((IS_I965G(dev) || plane == 0))
2405 intel_update_fbc(crtc, &crtc->mode);
2406
2407 /* Give the overlay scaler a chance to enable if it's on this pipe */
2408 intel_crtc_dpms_overlay(intel_crtc, true);
2409 break;
2410 case DRM_MODE_DPMS_OFF:
2411 /* Give the overlay scaler a chance to disable if it's on this pipe */
2412 intel_crtc_dpms_overlay(intel_crtc, false);
2413 drm_vblank_off(dev, pipe);
2414
2415 if (dev_priv->cfb_plane == plane &&
2416 dev_priv->display.disable_fbc)
2417 dev_priv->display.disable_fbc(dev);
2418
2419 /* Disable the VGA plane that we never use */
2420 i915_disable_vga(dev);
2421
2422 /* Disable display plane */
2423 temp = I915_READ(dspcntr_reg);
2424 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2425 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2426 /* Flush the plane changes */
2427 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2428 I915_READ(dspbase_reg);
2429 }
2430
2431 if (!IS_I9XX(dev)) {
2432 /* Wait for vblank for the disable to take effect */
2433 intel_wait_for_vblank(dev);
2434 }
2435
2436 /* Don't disable pipe A or pipe A PLLs if needed */
2437 if (pipeconf_reg == PIPEACONF &&
2438 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2439 goto skip_pipe_off;
2440
2441 /* Next, disable display pipes */
2442 temp = I915_READ(pipeconf_reg);
2443 if ((temp & PIPEACONF_ENABLE) != 0) {
2444 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2445 I915_READ(pipeconf_reg);
2446 }
2447
2448 /* Wait for vblank for the disable to take effect. */
2449 intel_wait_for_vblank(dev);
2450
2451 temp = I915_READ(dpll_reg);
2452 if ((temp & DPLL_VCO_ENABLE) != 0) {
2453 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2454 I915_READ(dpll_reg);
2455 }
2456 skip_pipe_off:
2457 /* Wait for the clocks to turn off. */
2458 udelay(150);
2459 break;
2460 }
2461 }
2462
2463 /**
2464 * Sets the power management mode of the pipe and plane.
2465 */
2466 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2467 {
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct drm_i915_master_private *master_priv;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 bool enabled;
2474
2475 intel_crtc->dpms_mode = mode;
2476 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2477
2478 /* When switching on the display, ensure that SR is disabled
2479 * with multiple pipes prior to enabling to new pipe.
2480 *
2481 * When switching off the display, make sure the cursor is
2482 * properly hidden prior to disabling the pipe.
2483 */
2484 if (mode == DRM_MODE_DPMS_ON)
2485 intel_update_watermarks(dev);
2486 else
2487 intel_crtc_update_cursor(crtc);
2488
2489 dev_priv->display.dpms(crtc, mode);
2490
2491 if (mode == DRM_MODE_DPMS_ON)
2492 intel_crtc_update_cursor(crtc);
2493 else
2494 intel_update_watermarks(dev);
2495
2496 if (!dev->primary->master)
2497 return;
2498
2499 master_priv = dev->primary->master->driver_priv;
2500 if (!master_priv->sarea_priv)
2501 return;
2502
2503 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2504
2505 switch (pipe) {
2506 case 0:
2507 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2508 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2509 break;
2510 case 1:
2511 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2512 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2513 break;
2514 default:
2515 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2516 break;
2517 }
2518 }
2519
2520 static void intel_crtc_prepare (struct drm_crtc *crtc)
2521 {
2522 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2523 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2524 }
2525
2526 static void intel_crtc_commit (struct drm_crtc *crtc)
2527 {
2528 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2529 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2530 }
2531
2532 void intel_encoder_prepare (struct drm_encoder *encoder)
2533 {
2534 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2535 /* lvds has its own version of prepare see intel_lvds_prepare */
2536 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2537 }
2538
2539 void intel_encoder_commit (struct drm_encoder *encoder)
2540 {
2541 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2542 /* lvds has its own version of commit see intel_lvds_commit */
2543 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2544 }
2545
2546 void intel_encoder_destroy(struct drm_encoder *encoder)
2547 {
2548 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2549
2550 if (intel_encoder->ddc_bus)
2551 intel_i2c_destroy(intel_encoder->ddc_bus);
2552
2553 if (intel_encoder->i2c_bus)
2554 intel_i2c_destroy(intel_encoder->i2c_bus);
2555
2556 drm_encoder_cleanup(encoder);
2557 kfree(intel_encoder);
2558 }
2559
2560 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2561 struct drm_display_mode *mode,
2562 struct drm_display_mode *adjusted_mode)
2563 {
2564 struct drm_device *dev = crtc->dev;
2565 if (HAS_PCH_SPLIT(dev)) {
2566 /* FDI link clock is fixed at 2.7G */
2567 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2568 return false;
2569 }
2570 return true;
2571 }
2572
2573 static int i945_get_display_clock_speed(struct drm_device *dev)
2574 {
2575 return 400000;
2576 }
2577
2578 static int i915_get_display_clock_speed(struct drm_device *dev)
2579 {
2580 return 333000;
2581 }
2582
2583 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2584 {
2585 return 200000;
2586 }
2587
2588 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2589 {
2590 u16 gcfgc = 0;
2591
2592 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2593
2594 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2595 return 133000;
2596 else {
2597 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2598 case GC_DISPLAY_CLOCK_333_MHZ:
2599 return 333000;
2600 default:
2601 case GC_DISPLAY_CLOCK_190_200_MHZ:
2602 return 190000;
2603 }
2604 }
2605 }
2606
2607 static int i865_get_display_clock_speed(struct drm_device *dev)
2608 {
2609 return 266000;
2610 }
2611
2612 static int i855_get_display_clock_speed(struct drm_device *dev)
2613 {
2614 u16 hpllcc = 0;
2615 /* Assume that the hardware is in the high speed state. This
2616 * should be the default.
2617 */
2618 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2619 case GC_CLOCK_133_200:
2620 case GC_CLOCK_100_200:
2621 return 200000;
2622 case GC_CLOCK_166_250:
2623 return 250000;
2624 case GC_CLOCK_100_133:
2625 return 133000;
2626 }
2627
2628 /* Shouldn't happen */
2629 return 0;
2630 }
2631
2632 static int i830_get_display_clock_speed(struct drm_device *dev)
2633 {
2634 return 133000;
2635 }
2636
2637 /**
2638 * Return the pipe currently connected to the panel fitter,
2639 * or -1 if the panel fitter is not present or not in use
2640 */
2641 int intel_panel_fitter_pipe (struct drm_device *dev)
2642 {
2643 struct drm_i915_private *dev_priv = dev->dev_private;
2644 u32 pfit_control;
2645
2646 /* i830 doesn't have a panel fitter */
2647 if (IS_I830(dev))
2648 return -1;
2649
2650 pfit_control = I915_READ(PFIT_CONTROL);
2651
2652 /* See if the panel fitter is in use */
2653 if ((pfit_control & PFIT_ENABLE) == 0)
2654 return -1;
2655
2656 /* 965 can place panel fitter on either pipe */
2657 if (IS_I965G(dev))
2658 return (pfit_control >> 29) & 0x3;
2659
2660 /* older chips can only use pipe 1 */
2661 return 1;
2662 }
2663
2664 struct fdi_m_n {
2665 u32 tu;
2666 u32 gmch_m;
2667 u32 gmch_n;
2668 u32 link_m;
2669 u32 link_n;
2670 };
2671
2672 static void
2673 fdi_reduce_ratio(u32 *num, u32 *den)
2674 {
2675 while (*num > 0xffffff || *den > 0xffffff) {
2676 *num >>= 1;
2677 *den >>= 1;
2678 }
2679 }
2680
2681 #define DATA_N 0x800000
2682 #define LINK_N 0x80000
2683
2684 static void
2685 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2686 int link_clock, struct fdi_m_n *m_n)
2687 {
2688 u64 temp;
2689
2690 m_n->tu = 64; /* default size */
2691
2692 temp = (u64) DATA_N * pixel_clock;
2693 temp = div_u64(temp, link_clock);
2694 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2695 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2696 m_n->gmch_n = DATA_N;
2697 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2698
2699 temp = (u64) LINK_N * pixel_clock;
2700 m_n->link_m = div_u64(temp, link_clock);
2701 m_n->link_n = LINK_N;
2702 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2703 }
2704
2705
2706 struct intel_watermark_params {
2707 unsigned long fifo_size;
2708 unsigned long max_wm;
2709 unsigned long default_wm;
2710 unsigned long guard_size;
2711 unsigned long cacheline_size;
2712 };
2713
2714 /* Pineview has different values for various configs */
2715 static struct intel_watermark_params pineview_display_wm = {
2716 PINEVIEW_DISPLAY_FIFO,
2717 PINEVIEW_MAX_WM,
2718 PINEVIEW_DFT_WM,
2719 PINEVIEW_GUARD_WM,
2720 PINEVIEW_FIFO_LINE_SIZE
2721 };
2722 static struct intel_watermark_params pineview_display_hplloff_wm = {
2723 PINEVIEW_DISPLAY_FIFO,
2724 PINEVIEW_MAX_WM,
2725 PINEVIEW_DFT_HPLLOFF_WM,
2726 PINEVIEW_GUARD_WM,
2727 PINEVIEW_FIFO_LINE_SIZE
2728 };
2729 static struct intel_watermark_params pineview_cursor_wm = {
2730 PINEVIEW_CURSOR_FIFO,
2731 PINEVIEW_CURSOR_MAX_WM,
2732 PINEVIEW_CURSOR_DFT_WM,
2733 PINEVIEW_CURSOR_GUARD_WM,
2734 PINEVIEW_FIFO_LINE_SIZE,
2735 };
2736 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2737 PINEVIEW_CURSOR_FIFO,
2738 PINEVIEW_CURSOR_MAX_WM,
2739 PINEVIEW_CURSOR_DFT_WM,
2740 PINEVIEW_CURSOR_GUARD_WM,
2741 PINEVIEW_FIFO_LINE_SIZE
2742 };
2743 static struct intel_watermark_params g4x_wm_info = {
2744 G4X_FIFO_SIZE,
2745 G4X_MAX_WM,
2746 G4X_MAX_WM,
2747 2,
2748 G4X_FIFO_LINE_SIZE,
2749 };
2750 static struct intel_watermark_params g4x_cursor_wm_info = {
2751 I965_CURSOR_FIFO,
2752 I965_CURSOR_MAX_WM,
2753 I965_CURSOR_DFT_WM,
2754 2,
2755 G4X_FIFO_LINE_SIZE,
2756 };
2757 static struct intel_watermark_params i965_cursor_wm_info = {
2758 I965_CURSOR_FIFO,
2759 I965_CURSOR_MAX_WM,
2760 I965_CURSOR_DFT_WM,
2761 2,
2762 I915_FIFO_LINE_SIZE,
2763 };
2764 static struct intel_watermark_params i945_wm_info = {
2765 I945_FIFO_SIZE,
2766 I915_MAX_WM,
2767 1,
2768 2,
2769 I915_FIFO_LINE_SIZE
2770 };
2771 static struct intel_watermark_params i915_wm_info = {
2772 I915_FIFO_SIZE,
2773 I915_MAX_WM,
2774 1,
2775 2,
2776 I915_FIFO_LINE_SIZE
2777 };
2778 static struct intel_watermark_params i855_wm_info = {
2779 I855GM_FIFO_SIZE,
2780 I915_MAX_WM,
2781 1,
2782 2,
2783 I830_FIFO_LINE_SIZE
2784 };
2785 static struct intel_watermark_params i830_wm_info = {
2786 I830_FIFO_SIZE,
2787 I915_MAX_WM,
2788 1,
2789 2,
2790 I830_FIFO_LINE_SIZE
2791 };
2792
2793 static struct intel_watermark_params ironlake_display_wm_info = {
2794 ILK_DISPLAY_FIFO,
2795 ILK_DISPLAY_MAXWM,
2796 ILK_DISPLAY_DFTWM,
2797 2,
2798 ILK_FIFO_LINE_SIZE
2799 };
2800
2801 static struct intel_watermark_params ironlake_cursor_wm_info = {
2802 ILK_CURSOR_FIFO,
2803 ILK_CURSOR_MAXWM,
2804 ILK_CURSOR_DFTWM,
2805 2,
2806 ILK_FIFO_LINE_SIZE
2807 };
2808
2809 static struct intel_watermark_params ironlake_display_srwm_info = {
2810 ILK_DISPLAY_SR_FIFO,
2811 ILK_DISPLAY_MAX_SRWM,
2812 ILK_DISPLAY_DFT_SRWM,
2813 2,
2814 ILK_FIFO_LINE_SIZE
2815 };
2816
2817 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2818 ILK_CURSOR_SR_FIFO,
2819 ILK_CURSOR_MAX_SRWM,
2820 ILK_CURSOR_DFT_SRWM,
2821 2,
2822 ILK_FIFO_LINE_SIZE
2823 };
2824
2825 /**
2826 * intel_calculate_wm - calculate watermark level
2827 * @clock_in_khz: pixel clock
2828 * @wm: chip FIFO params
2829 * @pixel_size: display pixel size
2830 * @latency_ns: memory latency for the platform
2831 *
2832 * Calculate the watermark level (the level at which the display plane will
2833 * start fetching from memory again). Each chip has a different display
2834 * FIFO size and allocation, so the caller needs to figure that out and pass
2835 * in the correct intel_watermark_params structure.
2836 *
2837 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2838 * on the pixel size. When it reaches the watermark level, it'll start
2839 * fetching FIFO line sized based chunks from memory until the FIFO fills
2840 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2841 * will occur, and a display engine hang could result.
2842 */
2843 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2844 struct intel_watermark_params *wm,
2845 int pixel_size,
2846 unsigned long latency_ns)
2847 {
2848 long entries_required, wm_size;
2849
2850 /*
2851 * Note: we need to make sure we don't overflow for various clock &
2852 * latency values.
2853 * clocks go from a few thousand to several hundred thousand.
2854 * latency is usually a few thousand
2855 */
2856 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2857 1000;
2858 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2859
2860 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2861
2862 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2863
2864 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2865
2866 /* Don't promote wm_size to unsigned... */
2867 if (wm_size > (long)wm->max_wm)
2868 wm_size = wm->max_wm;
2869 if (wm_size <= 0) {
2870 wm_size = wm->default_wm;
2871 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2872 " entries required = %ld, available = %lu.\n",
2873 entries_required + wm->guard_size,
2874 wm->fifo_size);
2875 }
2876
2877 return wm_size;
2878 }
2879
2880 struct cxsr_latency {
2881 int is_desktop;
2882 int is_ddr3;
2883 unsigned long fsb_freq;
2884 unsigned long mem_freq;
2885 unsigned long display_sr;
2886 unsigned long display_hpll_disable;
2887 unsigned long cursor_sr;
2888 unsigned long cursor_hpll_disable;
2889 };
2890
2891 static const struct cxsr_latency cxsr_latency_table[] = {
2892 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2893 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2894 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2895 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2896 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2897
2898 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2899 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2900 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2901 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2902 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2903
2904 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2905 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2906 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2907 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2908 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2909
2910 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2911 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2912 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2913 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2914 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2915
2916 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2917 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2918 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2919 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2920 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2921
2922 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2923 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2924 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2925 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2926 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2927 };
2928
2929 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2930 int is_ddr3,
2931 int fsb,
2932 int mem)
2933 {
2934 const struct cxsr_latency *latency;
2935 int i;
2936
2937 if (fsb == 0 || mem == 0)
2938 return NULL;
2939
2940 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2941 latency = &cxsr_latency_table[i];
2942 if (is_desktop == latency->is_desktop &&
2943 is_ddr3 == latency->is_ddr3 &&
2944 fsb == latency->fsb_freq && mem == latency->mem_freq)
2945 return latency;
2946 }
2947
2948 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2949
2950 return NULL;
2951 }
2952
2953 static void pineview_disable_cxsr(struct drm_device *dev)
2954 {
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956
2957 /* deactivate cxsr */
2958 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2959 }
2960
2961 /*
2962 * Latency for FIFO fetches is dependent on several factors:
2963 * - memory configuration (speed, channels)
2964 * - chipset
2965 * - current MCH state
2966 * It can be fairly high in some situations, so here we assume a fairly
2967 * pessimal value. It's a tradeoff between extra memory fetches (if we
2968 * set this value too high, the FIFO will fetch frequently to stay full)
2969 * and power consumption (set it too low to save power and we might see
2970 * FIFO underruns and display "flicker").
2971 *
2972 * A value of 5us seems to be a good balance; safe for very low end
2973 * platforms but not overly aggressive on lower latency configs.
2974 */
2975 static const int latency_ns = 5000;
2976
2977 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2978 {
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 uint32_t dsparb = I915_READ(DSPARB);
2981 int size;
2982
2983 size = dsparb & 0x7f;
2984 if (plane)
2985 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2986
2987 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2988 plane ? "B" : "A", size);
2989
2990 return size;
2991 }
2992
2993 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2994 {
2995 struct drm_i915_private *dev_priv = dev->dev_private;
2996 uint32_t dsparb = I915_READ(DSPARB);
2997 int size;
2998
2999 size = dsparb & 0x1ff;
3000 if (plane)
3001 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3002 size >>= 1; /* Convert to cachelines */
3003
3004 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3005 plane ? "B" : "A", size);
3006
3007 return size;
3008 }
3009
3010 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3011 {
3012 struct drm_i915_private *dev_priv = dev->dev_private;
3013 uint32_t dsparb = I915_READ(DSPARB);
3014 int size;
3015
3016 size = dsparb & 0x7f;
3017 size >>= 2; /* Convert to cachelines */
3018
3019 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3020 plane ? "B" : "A",
3021 size);
3022
3023 return size;
3024 }
3025
3026 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3027 {
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 uint32_t dsparb = I915_READ(DSPARB);
3030 int size;
3031
3032 size = dsparb & 0x7f;
3033 size >>= 1; /* Convert to cachelines */
3034
3035 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3036 plane ? "B" : "A", size);
3037
3038 return size;
3039 }
3040
3041 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3042 int planeb_clock, int sr_hdisplay, int unused,
3043 int pixel_size)
3044 {
3045 struct drm_i915_private *dev_priv = dev->dev_private;
3046 const struct cxsr_latency *latency;
3047 u32 reg;
3048 unsigned long wm;
3049 int sr_clock;
3050
3051 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3052 dev_priv->fsb_freq, dev_priv->mem_freq);
3053 if (!latency) {
3054 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3055 pineview_disable_cxsr(dev);
3056 return;
3057 }
3058
3059 if (!planea_clock || !planeb_clock) {
3060 sr_clock = planea_clock ? planea_clock : planeb_clock;
3061
3062 /* Display SR */
3063 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3064 pixel_size, latency->display_sr);
3065 reg = I915_READ(DSPFW1);
3066 reg &= ~DSPFW_SR_MASK;
3067 reg |= wm << DSPFW_SR_SHIFT;
3068 I915_WRITE(DSPFW1, reg);
3069 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3070
3071 /* cursor SR */
3072 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3073 pixel_size, latency->cursor_sr);
3074 reg = I915_READ(DSPFW3);
3075 reg &= ~DSPFW_CURSOR_SR_MASK;
3076 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3077 I915_WRITE(DSPFW3, reg);
3078
3079 /* Display HPLL off SR */
3080 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3081 pixel_size, latency->display_hpll_disable);
3082 reg = I915_READ(DSPFW3);
3083 reg &= ~DSPFW_HPLL_SR_MASK;
3084 reg |= wm & DSPFW_HPLL_SR_MASK;
3085 I915_WRITE(DSPFW3, reg);
3086
3087 /* cursor HPLL off SR */
3088 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3089 pixel_size, latency->cursor_hpll_disable);
3090 reg = I915_READ(DSPFW3);
3091 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3092 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3093 I915_WRITE(DSPFW3, reg);
3094 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3095
3096 /* activate cxsr */
3097 I915_WRITE(DSPFW3,
3098 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3099 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3100 } else {
3101 pineview_disable_cxsr(dev);
3102 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3103 }
3104 }
3105
3106 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3107 int planeb_clock, int sr_hdisplay, int sr_htotal,
3108 int pixel_size)
3109 {
3110 struct drm_i915_private *dev_priv = dev->dev_private;
3111 int total_size, cacheline_size;
3112 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3113 struct intel_watermark_params planea_params, planeb_params;
3114 unsigned long line_time_us;
3115 int sr_clock, sr_entries = 0, entries_required;
3116
3117 /* Create copies of the base settings for each pipe */
3118 planea_params = planeb_params = g4x_wm_info;
3119
3120 /* Grab a couple of global values before we overwrite them */
3121 total_size = planea_params.fifo_size;
3122 cacheline_size = planea_params.cacheline_size;
3123
3124 /*
3125 * Note: we need to make sure we don't overflow for various clock &
3126 * latency values.
3127 * clocks go from a few thousand to several hundred thousand.
3128 * latency is usually a few thousand
3129 */
3130 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3131 1000;
3132 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3133 planea_wm = entries_required + planea_params.guard_size;
3134
3135 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3136 1000;
3137 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3138 planeb_wm = entries_required + planeb_params.guard_size;
3139
3140 cursora_wm = cursorb_wm = 16;
3141 cursor_sr = 32;
3142
3143 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3144
3145 /* Calc sr entries for one plane configs */
3146 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3147 /* self-refresh has much higher latency */
3148 static const int sr_latency_ns = 12000;
3149
3150 sr_clock = planea_clock ? planea_clock : planeb_clock;
3151 line_time_us = ((sr_htotal * 1000) / sr_clock);
3152
3153 /* Use ns/us then divide to preserve precision */
3154 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3155 pixel_size * sr_hdisplay;
3156 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3157
3158 entries_required = (((sr_latency_ns / line_time_us) +
3159 1000) / 1000) * pixel_size * 64;
3160 entries_required = DIV_ROUND_UP(entries_required,
3161 g4x_cursor_wm_info.cacheline_size);
3162 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3163
3164 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3165 cursor_sr = g4x_cursor_wm_info.max_wm;
3166 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3167 "cursor %d\n", sr_entries, cursor_sr);
3168
3169 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3170 } else {
3171 /* Turn off self refresh if both pipes are enabled */
3172 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3173 & ~FW_BLC_SELF_EN);
3174 }
3175
3176 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3177 planea_wm, planeb_wm, sr_entries);
3178
3179 planea_wm &= 0x3f;
3180 planeb_wm &= 0x3f;
3181
3182 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3183 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3184 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3185 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3186 (cursora_wm << DSPFW_CURSORA_SHIFT));
3187 /* HPLL off in SR has some issues on G4x... disable it */
3188 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3189 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3190 }
3191
3192 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3193 int planeb_clock, int sr_hdisplay, int sr_htotal,
3194 int pixel_size)
3195 {
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 unsigned long line_time_us;
3198 int sr_clock, sr_entries, srwm = 1;
3199 int cursor_sr = 16;
3200
3201 /* Calc sr entries for one plane configs */
3202 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3203 /* self-refresh has much higher latency */
3204 static const int sr_latency_ns = 12000;
3205
3206 sr_clock = planea_clock ? planea_clock : planeb_clock;
3207 line_time_us = ((sr_htotal * 1000) / sr_clock);
3208
3209 /* Use ns/us then divide to preserve precision */
3210 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3211 pixel_size * sr_hdisplay;
3212 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3213 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3214 srwm = I965_FIFO_SIZE - sr_entries;
3215 if (srwm < 0)
3216 srwm = 1;
3217 srwm &= 0x1ff;
3218
3219 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3220 pixel_size * 64;
3221 sr_entries = DIV_ROUND_UP(sr_entries,
3222 i965_cursor_wm_info.cacheline_size);
3223 cursor_sr = i965_cursor_wm_info.fifo_size -
3224 (sr_entries + i965_cursor_wm_info.guard_size);
3225
3226 if (cursor_sr > i965_cursor_wm_info.max_wm)
3227 cursor_sr = i965_cursor_wm_info.max_wm;
3228
3229 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3230 "cursor %d\n", srwm, cursor_sr);
3231
3232 if (IS_I965GM(dev))
3233 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3234 } else {
3235 /* Turn off self refresh if both pipes are enabled */
3236 if (IS_I965GM(dev))
3237 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3238 & ~FW_BLC_SELF_EN);
3239 }
3240
3241 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3242 srwm);
3243
3244 /* 965 has limitations... */
3245 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3246 (8 << 0));
3247 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3248 /* update cursor SR watermark */
3249 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3250 }
3251
3252 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3253 int planeb_clock, int sr_hdisplay, int sr_htotal,
3254 int pixel_size)
3255 {
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 uint32_t fwater_lo;
3258 uint32_t fwater_hi;
3259 int total_size, cacheline_size, cwm, srwm = 1;
3260 int planea_wm, planeb_wm;
3261 struct intel_watermark_params planea_params, planeb_params;
3262 unsigned long line_time_us;
3263 int sr_clock, sr_entries = 0;
3264
3265 /* Create copies of the base settings for each pipe */
3266 if (IS_I965GM(dev) || IS_I945GM(dev))
3267 planea_params = planeb_params = i945_wm_info;
3268 else if (IS_I9XX(dev))
3269 planea_params = planeb_params = i915_wm_info;
3270 else
3271 planea_params = planeb_params = i855_wm_info;
3272
3273 /* Grab a couple of global values before we overwrite them */
3274 total_size = planea_params.fifo_size;
3275 cacheline_size = planea_params.cacheline_size;
3276
3277 /* Update per-plane FIFO sizes */
3278 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3279 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3280
3281 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3282 pixel_size, latency_ns);
3283 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3284 pixel_size, latency_ns);
3285 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3286
3287 /*
3288 * Overlay gets an aggressive default since video jitter is bad.
3289 */
3290 cwm = 2;
3291
3292 /* Calc sr entries for one plane configs */
3293 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3294 (!planea_clock || !planeb_clock)) {
3295 /* self-refresh has much higher latency */
3296 static const int sr_latency_ns = 6000;
3297
3298 sr_clock = planea_clock ? planea_clock : planeb_clock;
3299 line_time_us = ((sr_htotal * 1000) / sr_clock);
3300
3301 /* Use ns/us then divide to preserve precision */
3302 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3303 pixel_size * sr_hdisplay;
3304 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3305 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3306 srwm = total_size - sr_entries;
3307 if (srwm < 0)
3308 srwm = 1;
3309
3310 if (IS_I945G(dev) || IS_I945GM(dev))
3311 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3312 else if (IS_I915GM(dev)) {
3313 /* 915M has a smaller SRWM field */
3314 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3315 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3316 }
3317 } else {
3318 /* Turn off self refresh if both pipes are enabled */
3319 if (IS_I945G(dev) || IS_I945GM(dev)) {
3320 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3321 & ~FW_BLC_SELF_EN);
3322 } else if (IS_I915GM(dev)) {
3323 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3324 }
3325 }
3326
3327 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3328 planea_wm, planeb_wm, cwm, srwm);
3329
3330 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3331 fwater_hi = (cwm & 0x1f);
3332
3333 /* Set request length to 8 cachelines per fetch */
3334 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3335 fwater_hi = fwater_hi | (1 << 8);
3336
3337 I915_WRITE(FW_BLC, fwater_lo);
3338 I915_WRITE(FW_BLC2, fwater_hi);
3339 }
3340
3341 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3342 int unused2, int unused3, int pixel_size)
3343 {
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3346 int planea_wm;
3347
3348 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3349
3350 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3351 pixel_size, latency_ns);
3352 fwater_lo |= (3<<8) | planea_wm;
3353
3354 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3355
3356 I915_WRITE(FW_BLC, fwater_lo);
3357 }
3358
3359 #define ILK_LP0_PLANE_LATENCY 700
3360 #define ILK_LP0_CURSOR_LATENCY 1300
3361
3362 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3363 int planeb_clock, int sr_hdisplay, int sr_htotal,
3364 int pixel_size)
3365 {
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3368 int sr_wm, cursor_wm;
3369 unsigned long line_time_us;
3370 int sr_clock, entries_required;
3371 u32 reg_value;
3372 int line_count;
3373 int planea_htotal = 0, planeb_htotal = 0;
3374 struct drm_crtc *crtc;
3375
3376 /* Need htotal for all active display plane */
3377 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3379 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3380 if (intel_crtc->plane == 0)
3381 planea_htotal = crtc->mode.htotal;
3382 else
3383 planeb_htotal = crtc->mode.htotal;
3384 }
3385 }
3386
3387 /* Calculate and update the watermark for plane A */
3388 if (planea_clock) {
3389 entries_required = ((planea_clock / 1000) * pixel_size *
3390 ILK_LP0_PLANE_LATENCY) / 1000;
3391 entries_required = DIV_ROUND_UP(entries_required,
3392 ironlake_display_wm_info.cacheline_size);
3393 planea_wm = entries_required +
3394 ironlake_display_wm_info.guard_size;
3395
3396 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3397 planea_wm = ironlake_display_wm_info.max_wm;
3398
3399 /* Use the large buffer method to calculate cursor watermark */
3400 line_time_us = (planea_htotal * 1000) / planea_clock;
3401
3402 /* Use ns/us then divide to preserve precision */
3403 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3404
3405 /* calculate the cursor watermark for cursor A */
3406 entries_required = line_count * 64 * pixel_size;
3407 entries_required = DIV_ROUND_UP(entries_required,
3408 ironlake_cursor_wm_info.cacheline_size);
3409 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3410 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3411 cursora_wm = ironlake_cursor_wm_info.max_wm;
3412
3413 reg_value = I915_READ(WM0_PIPEA_ILK);
3414 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3415 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3416 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3417 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3418 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3419 "cursor: %d\n", planea_wm, cursora_wm);
3420 }
3421 /* Calculate and update the watermark for plane B */
3422 if (planeb_clock) {
3423 entries_required = ((planeb_clock / 1000) * pixel_size *
3424 ILK_LP0_PLANE_LATENCY) / 1000;
3425 entries_required = DIV_ROUND_UP(entries_required,
3426 ironlake_display_wm_info.cacheline_size);
3427 planeb_wm = entries_required +
3428 ironlake_display_wm_info.guard_size;
3429
3430 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3431 planeb_wm = ironlake_display_wm_info.max_wm;
3432
3433 /* Use the large buffer method to calculate cursor watermark */
3434 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3435
3436 /* Use ns/us then divide to preserve precision */
3437 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3438
3439 /* calculate the cursor watermark for cursor B */
3440 entries_required = line_count * 64 * pixel_size;
3441 entries_required = DIV_ROUND_UP(entries_required,
3442 ironlake_cursor_wm_info.cacheline_size);
3443 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3444 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3445 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3446
3447 reg_value = I915_READ(WM0_PIPEB_ILK);
3448 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3449 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3450 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3451 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3452 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3453 "cursor: %d\n", planeb_wm, cursorb_wm);
3454 }
3455
3456 /*
3457 * Calculate and update the self-refresh watermark only when one
3458 * display plane is used.
3459 */
3460 if (!planea_clock || !planeb_clock) {
3461
3462 /* Read the self-refresh latency. The unit is 0.5us */
3463 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3464
3465 sr_clock = planea_clock ? planea_clock : planeb_clock;
3466 line_time_us = ((sr_htotal * 1000) / sr_clock);
3467
3468 /* Use ns/us then divide to preserve precision */
3469 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3470 / 1000;
3471
3472 /* calculate the self-refresh watermark for display plane */
3473 entries_required = line_count * sr_hdisplay * pixel_size;
3474 entries_required = DIV_ROUND_UP(entries_required,
3475 ironlake_display_srwm_info.cacheline_size);
3476 sr_wm = entries_required +
3477 ironlake_display_srwm_info.guard_size;
3478
3479 /* calculate the self-refresh watermark for display cursor */
3480 entries_required = line_count * pixel_size * 64;
3481 entries_required = DIV_ROUND_UP(entries_required,
3482 ironlake_cursor_srwm_info.cacheline_size);
3483 cursor_wm = entries_required +
3484 ironlake_cursor_srwm_info.guard_size;
3485
3486 /* configure watermark and enable self-refresh */
3487 reg_value = I915_READ(WM1_LP_ILK);
3488 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3489 WM1_LP_CURSOR_MASK);
3490 reg_value |= WM1_LP_SR_EN |
3491 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3492 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3493
3494 I915_WRITE(WM1_LP_ILK, reg_value);
3495 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3496 "cursor %d\n", sr_wm, cursor_wm);
3497
3498 } else {
3499 /* Turn off self refresh if both pipes are enabled */
3500 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3501 }
3502 }
3503 /**
3504 * intel_update_watermarks - update FIFO watermark values based on current modes
3505 *
3506 * Calculate watermark values for the various WM regs based on current mode
3507 * and plane configuration.
3508 *
3509 * There are several cases to deal with here:
3510 * - normal (i.e. non-self-refresh)
3511 * - self-refresh (SR) mode
3512 * - lines are large relative to FIFO size (buffer can hold up to 2)
3513 * - lines are small relative to FIFO size (buffer can hold more than 2
3514 * lines), so need to account for TLB latency
3515 *
3516 * The normal calculation is:
3517 * watermark = dotclock * bytes per pixel * latency
3518 * where latency is platform & configuration dependent (we assume pessimal
3519 * values here).
3520 *
3521 * The SR calculation is:
3522 * watermark = (trunc(latency/line time)+1) * surface width *
3523 * bytes per pixel
3524 * where
3525 * line time = htotal / dotclock
3526 * surface width = hdisplay for normal plane and 64 for cursor
3527 * and latency is assumed to be high, as above.
3528 *
3529 * The final value programmed to the register should always be rounded up,
3530 * and include an extra 2 entries to account for clock crossings.
3531 *
3532 * We don't use the sprite, so we can ignore that. And on Crestline we have
3533 * to set the non-SR watermarks to 8.
3534 */
3535 static void intel_update_watermarks(struct drm_device *dev)
3536 {
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 struct drm_crtc *crtc;
3539 int sr_hdisplay = 0;
3540 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3541 int enabled = 0, pixel_size = 0;
3542 int sr_htotal = 0;
3543
3544 if (!dev_priv->display.update_wm)
3545 return;
3546
3547 /* Get the clock config from both planes */
3548 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3550 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3551 enabled++;
3552 if (intel_crtc->plane == 0) {
3553 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3554 intel_crtc->pipe, crtc->mode.clock);
3555 planea_clock = crtc->mode.clock;
3556 } else {
3557 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3558 intel_crtc->pipe, crtc->mode.clock);
3559 planeb_clock = crtc->mode.clock;
3560 }
3561 sr_hdisplay = crtc->mode.hdisplay;
3562 sr_clock = crtc->mode.clock;
3563 sr_htotal = crtc->mode.htotal;
3564 if (crtc->fb)
3565 pixel_size = crtc->fb->bits_per_pixel / 8;
3566 else
3567 pixel_size = 4; /* by default */
3568 }
3569 }
3570
3571 if (enabled <= 0)
3572 return;
3573
3574 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3575 sr_hdisplay, sr_htotal, pixel_size);
3576 }
3577
3578 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3579 struct drm_display_mode *mode,
3580 struct drm_display_mode *adjusted_mode,
3581 int x, int y,
3582 struct drm_framebuffer *old_fb)
3583 {
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 int pipe = intel_crtc->pipe;
3588 int plane = intel_crtc->plane;
3589 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3590 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3591 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3592 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3593 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3594 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3595 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3596 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3597 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3598 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3599 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3600 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3601 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3602 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3603 int refclk, num_connectors = 0;
3604 intel_clock_t clock, reduced_clock;
3605 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3606 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3607 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3608 bool is_edp = false;
3609 struct drm_mode_config *mode_config = &dev->mode_config;
3610 struct drm_encoder *encoder;
3611 struct intel_encoder *intel_encoder = NULL;
3612 const intel_limit_t *limit;
3613 int ret;
3614 struct fdi_m_n m_n = {0};
3615 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3616 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3617 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3618 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3619 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3620 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3621 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3622 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3623 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3624 int lvds_reg = LVDS;
3625 u32 temp;
3626 int sdvo_pixel_multiply;
3627 int target_clock;
3628
3629 drm_vblank_pre_modeset(dev, pipe);
3630
3631 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3632
3633 if (!encoder || encoder->crtc != crtc)
3634 continue;
3635
3636 intel_encoder = enc_to_intel_encoder(encoder);
3637
3638 switch (intel_encoder->type) {
3639 case INTEL_OUTPUT_LVDS:
3640 is_lvds = true;
3641 break;
3642 case INTEL_OUTPUT_SDVO:
3643 case INTEL_OUTPUT_HDMI:
3644 is_sdvo = true;
3645 if (intel_encoder->needs_tv_clock)
3646 is_tv = true;
3647 break;
3648 case INTEL_OUTPUT_DVO:
3649 is_dvo = true;
3650 break;
3651 case INTEL_OUTPUT_TVOUT:
3652 is_tv = true;
3653 break;
3654 case INTEL_OUTPUT_ANALOG:
3655 is_crt = true;
3656 break;
3657 case INTEL_OUTPUT_DISPLAYPORT:
3658 is_dp = true;
3659 break;
3660 case INTEL_OUTPUT_EDP:
3661 is_edp = true;
3662 break;
3663 }
3664
3665 num_connectors++;
3666 }
3667
3668 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3669 refclk = dev_priv->lvds_ssc_freq * 1000;
3670 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3671 refclk / 1000);
3672 } else if (IS_I9XX(dev)) {
3673 refclk = 96000;
3674 if (HAS_PCH_SPLIT(dev))
3675 refclk = 120000; /* 120Mhz refclk */
3676 } else {
3677 refclk = 48000;
3678 }
3679
3680
3681 /*
3682 * Returns a set of divisors for the desired target clock with the given
3683 * refclk, or FALSE. The returned values represent the clock equation:
3684 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3685 */
3686 limit = intel_limit(crtc);
3687 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3688 if (!ok) {
3689 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3690 drm_vblank_post_modeset(dev, pipe);
3691 return -EINVAL;
3692 }
3693
3694 /* Ensure that the cursor is valid for the new mode before changing... */
3695 intel_crtc_update_cursor(crtc);
3696
3697 if (is_lvds && dev_priv->lvds_downclock_avail) {
3698 has_reduced_clock = limit->find_pll(limit, crtc,
3699 dev_priv->lvds_downclock,
3700 refclk,
3701 &reduced_clock);
3702 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3703 /*
3704 * If the different P is found, it means that we can't
3705 * switch the display clock by using the FP0/FP1.
3706 * In such case we will disable the LVDS downclock
3707 * feature.
3708 */
3709 DRM_DEBUG_KMS("Different P is found for "
3710 "LVDS clock/downclock\n");
3711 has_reduced_clock = 0;
3712 }
3713 }
3714 /* SDVO TV has fixed PLL values depend on its clock range,
3715 this mirrors vbios setting. */
3716 if (is_sdvo && is_tv) {
3717 if (adjusted_mode->clock >= 100000
3718 && adjusted_mode->clock < 140500) {
3719 clock.p1 = 2;
3720 clock.p2 = 10;
3721 clock.n = 3;
3722 clock.m1 = 16;
3723 clock.m2 = 8;
3724 } else if (adjusted_mode->clock >= 140500
3725 && adjusted_mode->clock <= 200000) {
3726 clock.p1 = 1;
3727 clock.p2 = 10;
3728 clock.n = 6;
3729 clock.m1 = 12;
3730 clock.m2 = 8;
3731 }
3732 }
3733
3734 /* FDI link */
3735 if (HAS_PCH_SPLIT(dev)) {
3736 int lane = 0, link_bw, bpp;
3737 /* eDP doesn't require FDI link, so just set DP M/N
3738 according to current link config */
3739 if (is_edp) {
3740 target_clock = mode->clock;
3741 intel_edp_link_config(intel_encoder,
3742 &lane, &link_bw);
3743 } else {
3744 /* DP over FDI requires target mode clock
3745 instead of link clock */
3746 if (is_dp)
3747 target_clock = mode->clock;
3748 else
3749 target_clock = adjusted_mode->clock;
3750 link_bw = 270000;
3751 }
3752
3753 /* determine panel color depth */
3754 temp = I915_READ(pipeconf_reg);
3755 temp &= ~PIPE_BPC_MASK;
3756 if (is_lvds) {
3757 int lvds_reg = I915_READ(PCH_LVDS);
3758 /* the BPC will be 6 if it is 18-bit LVDS panel */
3759 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3760 temp |= PIPE_8BPC;
3761 else
3762 temp |= PIPE_6BPC;
3763 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
3764 switch (dev_priv->edp_bpp/3) {
3765 case 8:
3766 temp |= PIPE_8BPC;
3767 break;
3768 case 10:
3769 temp |= PIPE_10BPC;
3770 break;
3771 case 6:
3772 temp |= PIPE_6BPC;
3773 break;
3774 case 12:
3775 temp |= PIPE_12BPC;
3776 break;
3777 }
3778 } else
3779 temp |= PIPE_8BPC;
3780 I915_WRITE(pipeconf_reg, temp);
3781 I915_READ(pipeconf_reg);
3782
3783 switch (temp & PIPE_BPC_MASK) {
3784 case PIPE_8BPC:
3785 bpp = 24;
3786 break;
3787 case PIPE_10BPC:
3788 bpp = 30;
3789 break;
3790 case PIPE_6BPC:
3791 bpp = 18;
3792 break;
3793 case PIPE_12BPC:
3794 bpp = 36;
3795 break;
3796 default:
3797 DRM_ERROR("unknown pipe bpc value\n");
3798 bpp = 24;
3799 }
3800
3801 if (!lane) {
3802 /*
3803 * Account for spread spectrum to avoid
3804 * oversubscribing the link. Max center spread
3805 * is 2.5%; use 5% for safety's sake.
3806 */
3807 u32 bps = target_clock * bpp * 21 / 20;
3808 lane = bps / (link_bw * 8) + 1;
3809 }
3810
3811 intel_crtc->fdi_lanes = lane;
3812
3813 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3814 }
3815
3816 /* Ironlake: try to setup display ref clock before DPLL
3817 * enabling. This is only under driver's control after
3818 * PCH B stepping, previous chipset stepping should be
3819 * ignoring this setting.
3820 */
3821 if (HAS_PCH_SPLIT(dev)) {
3822 temp = I915_READ(PCH_DREF_CONTROL);
3823 /* Always enable nonspread source */
3824 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3825 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3826 I915_WRITE(PCH_DREF_CONTROL, temp);
3827 POSTING_READ(PCH_DREF_CONTROL);
3828
3829 temp &= ~DREF_SSC_SOURCE_MASK;
3830 temp |= DREF_SSC_SOURCE_ENABLE;
3831 I915_WRITE(PCH_DREF_CONTROL, temp);
3832 POSTING_READ(PCH_DREF_CONTROL);
3833
3834 udelay(200);
3835
3836 if (is_edp) {
3837 if (dev_priv->lvds_use_ssc) {
3838 temp |= DREF_SSC1_ENABLE;
3839 I915_WRITE(PCH_DREF_CONTROL, temp);
3840 POSTING_READ(PCH_DREF_CONTROL);
3841
3842 udelay(200);
3843
3844 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3845 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3846 I915_WRITE(PCH_DREF_CONTROL, temp);
3847 POSTING_READ(PCH_DREF_CONTROL);
3848 } else {
3849 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3850 I915_WRITE(PCH_DREF_CONTROL, temp);
3851 POSTING_READ(PCH_DREF_CONTROL);
3852 }
3853 }
3854 }
3855
3856 if (IS_PINEVIEW(dev)) {
3857 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3858 if (has_reduced_clock)
3859 fp2 = (1 << reduced_clock.n) << 16 |
3860 reduced_clock.m1 << 8 | reduced_clock.m2;
3861 } else {
3862 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3863 if (has_reduced_clock)
3864 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3865 reduced_clock.m2;
3866 }
3867
3868 if (!HAS_PCH_SPLIT(dev))
3869 dpll = DPLL_VGA_MODE_DIS;
3870
3871 if (IS_I9XX(dev)) {
3872 if (is_lvds)
3873 dpll |= DPLLB_MODE_LVDS;
3874 else
3875 dpll |= DPLLB_MODE_DAC_SERIAL;
3876 if (is_sdvo) {
3877 dpll |= DPLL_DVO_HIGH_SPEED;
3878 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3879 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3880 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3881 else if (HAS_PCH_SPLIT(dev))
3882 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3883 }
3884 if (is_dp)
3885 dpll |= DPLL_DVO_HIGH_SPEED;
3886
3887 /* compute bitmask from p1 value */
3888 if (IS_PINEVIEW(dev))
3889 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3890 else {
3891 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3892 /* also FPA1 */
3893 if (HAS_PCH_SPLIT(dev))
3894 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3895 if (IS_G4X(dev) && has_reduced_clock)
3896 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3897 }
3898 switch (clock.p2) {
3899 case 5:
3900 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3901 break;
3902 case 7:
3903 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3904 break;
3905 case 10:
3906 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3907 break;
3908 case 14:
3909 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3910 break;
3911 }
3912 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3913 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3914 } else {
3915 if (is_lvds) {
3916 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3917 } else {
3918 if (clock.p1 == 2)
3919 dpll |= PLL_P1_DIVIDE_BY_TWO;
3920 else
3921 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3922 if (clock.p2 == 4)
3923 dpll |= PLL_P2_DIVIDE_BY_4;
3924 }
3925 }
3926
3927 if (is_sdvo && is_tv)
3928 dpll |= PLL_REF_INPUT_TVCLKINBC;
3929 else if (is_tv)
3930 /* XXX: just matching BIOS for now */
3931 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3932 dpll |= 3;
3933 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3934 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3935 else
3936 dpll |= PLL_REF_INPUT_DREFCLK;
3937
3938 /* setup pipeconf */
3939 pipeconf = I915_READ(pipeconf_reg);
3940
3941 /* Set up the display plane register */
3942 dspcntr = DISPPLANE_GAMMA_ENABLE;
3943
3944 /* Ironlake's plane is forced to pipe, bit 24 is to
3945 enable color space conversion */
3946 if (!HAS_PCH_SPLIT(dev)) {
3947 if (pipe == 0)
3948 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3949 else
3950 dspcntr |= DISPPLANE_SEL_PIPE_B;
3951 }
3952
3953 if (pipe == 0 && !IS_I965G(dev)) {
3954 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3955 * core speed.
3956 *
3957 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3958 * pipe == 0 check?
3959 */
3960 if (mode->clock >
3961 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3962 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3963 else
3964 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3965 }
3966
3967 dspcntr |= DISPLAY_PLANE_ENABLE;
3968 pipeconf |= PIPEACONF_ENABLE;
3969 dpll |= DPLL_VCO_ENABLE;
3970
3971
3972 /* Disable the panel fitter if it was on our pipe */
3973 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3974 I915_WRITE(PFIT_CONTROL, 0);
3975
3976 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3977 drm_mode_debug_printmodeline(mode);
3978
3979 /* assign to Ironlake registers */
3980 if (HAS_PCH_SPLIT(dev)) {
3981 fp_reg = pch_fp_reg;
3982 dpll_reg = pch_dpll_reg;
3983 }
3984
3985 if (is_edp) {
3986 ironlake_disable_pll_edp(crtc);
3987 } else if ((dpll & DPLL_VCO_ENABLE)) {
3988 I915_WRITE(fp_reg, fp);
3989 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3990 I915_READ(dpll_reg);
3991 udelay(150);
3992 }
3993
3994 /* enable transcoder DPLL */
3995 if (HAS_PCH_CPT(dev)) {
3996 temp = I915_READ(PCH_DPLL_SEL);
3997 if (trans_dpll_sel == 0)
3998 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3999 else
4000 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
4001 I915_WRITE(PCH_DPLL_SEL, temp);
4002 I915_READ(PCH_DPLL_SEL);
4003 udelay(150);
4004 }
4005
4006 if (HAS_PCH_SPLIT(dev)) {
4007 pipeconf &= ~PIPE_ENABLE_DITHER;
4008 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
4009 }
4010
4011 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4012 * This is an exception to the general rule that mode_set doesn't turn
4013 * things on.
4014 */
4015 if (is_lvds) {
4016 u32 lvds;
4017
4018 if (HAS_PCH_SPLIT(dev))
4019 lvds_reg = PCH_LVDS;
4020
4021 lvds = I915_READ(lvds_reg);
4022 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4023 if (pipe == 1) {
4024 if (HAS_PCH_CPT(dev))
4025 lvds |= PORT_TRANS_B_SEL_CPT;
4026 else
4027 lvds |= LVDS_PIPEB_SELECT;
4028 } else {
4029 if (HAS_PCH_CPT(dev))
4030 lvds &= ~PORT_TRANS_SEL_MASK;
4031 else
4032 lvds &= ~LVDS_PIPEB_SELECT;
4033 }
4034 /* set the corresponsding LVDS_BORDER bit */
4035 lvds |= dev_priv->lvds_border_bits;
4036 /* Set the B0-B3 data pairs corresponding to whether we're going to
4037 * set the DPLLs for dual-channel mode or not.
4038 */
4039 if (clock.p2 == 7)
4040 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4041 else
4042 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4043
4044 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4045 * appropriately here, but we need to look more thoroughly into how
4046 * panels behave in the two modes.
4047 */
4048 /* set the dithering flag */
4049 if (IS_I965G(dev)) {
4050 if (dev_priv->lvds_dither) {
4051 if (HAS_PCH_SPLIT(dev)) {
4052 pipeconf |= PIPE_ENABLE_DITHER;
4053 pipeconf |= PIPE_DITHER_TYPE_ST01;
4054 } else
4055 lvds |= LVDS_ENABLE_DITHER;
4056 } else {
4057 if (!HAS_PCH_SPLIT(dev)) {
4058 lvds &= ~LVDS_ENABLE_DITHER;
4059 }
4060 }
4061 }
4062 I915_WRITE(lvds_reg, lvds);
4063 I915_READ(lvds_reg);
4064 }
4065 if (is_dp)
4066 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4067 else if (HAS_PCH_SPLIT(dev)) {
4068 /* For non-DP output, clear any trans DP clock recovery setting.*/
4069 if (pipe == 0) {
4070 I915_WRITE(TRANSA_DATA_M1, 0);
4071 I915_WRITE(TRANSA_DATA_N1, 0);
4072 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4073 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4074 } else {
4075 I915_WRITE(TRANSB_DATA_M1, 0);
4076 I915_WRITE(TRANSB_DATA_N1, 0);
4077 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4078 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4079 }
4080 }
4081
4082 if (!is_edp) {
4083 I915_WRITE(fp_reg, fp);
4084 I915_WRITE(dpll_reg, dpll);
4085 I915_READ(dpll_reg);
4086 /* Wait for the clocks to stabilize. */
4087 udelay(150);
4088
4089 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4090 if (is_sdvo) {
4091 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
4092 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4093 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
4094 } else
4095 I915_WRITE(dpll_md_reg, 0);
4096 } else {
4097 /* write it again -- the BIOS does, after all */
4098 I915_WRITE(dpll_reg, dpll);
4099 }
4100 I915_READ(dpll_reg);
4101 /* Wait for the clocks to stabilize. */
4102 udelay(150);
4103 }
4104
4105 if (is_lvds && has_reduced_clock && i915_powersave) {
4106 I915_WRITE(fp_reg + 4, fp2);
4107 intel_crtc->lowfreq_avail = true;
4108 if (HAS_PIPE_CXSR(dev)) {
4109 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4110 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4111 }
4112 } else {
4113 I915_WRITE(fp_reg + 4, fp);
4114 intel_crtc->lowfreq_avail = false;
4115 if (HAS_PIPE_CXSR(dev)) {
4116 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4117 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4118 }
4119 }
4120
4121 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4122 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4123 /* the chip adds 2 halflines automatically */
4124 adjusted_mode->crtc_vdisplay -= 1;
4125 adjusted_mode->crtc_vtotal -= 1;
4126 adjusted_mode->crtc_vblank_start -= 1;
4127 adjusted_mode->crtc_vblank_end -= 1;
4128 adjusted_mode->crtc_vsync_end -= 1;
4129 adjusted_mode->crtc_vsync_start -= 1;
4130 } else
4131 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4132
4133 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4134 ((adjusted_mode->crtc_htotal - 1) << 16));
4135 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4136 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4137 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4138 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4139 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4140 ((adjusted_mode->crtc_vtotal - 1) << 16));
4141 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4142 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4143 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4144 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4145 /* pipesrc and dspsize control the size that is scaled from, which should
4146 * always be the user's requested size.
4147 */
4148 if (!HAS_PCH_SPLIT(dev)) {
4149 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4150 (mode->hdisplay - 1));
4151 I915_WRITE(dsppos_reg, 0);
4152 }
4153 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4154
4155 if (HAS_PCH_SPLIT(dev)) {
4156 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4157 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
4158 I915_WRITE(link_m1_reg, m_n.link_m);
4159 I915_WRITE(link_n1_reg, m_n.link_n);
4160
4161 if (is_edp) {
4162 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4163 } else {
4164 /* enable FDI RX PLL too */
4165 temp = I915_READ(fdi_rx_reg);
4166 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4167 I915_READ(fdi_rx_reg);
4168 udelay(200);
4169
4170 /* enable FDI TX PLL too */
4171 temp = I915_READ(fdi_tx_reg);
4172 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4173 I915_READ(fdi_tx_reg);
4174
4175 /* enable FDI RX PCDCLK */
4176 temp = I915_READ(fdi_rx_reg);
4177 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4178 I915_READ(fdi_rx_reg);
4179 udelay(200);
4180 }
4181 }
4182
4183 I915_WRITE(pipeconf_reg, pipeconf);
4184 I915_READ(pipeconf_reg);
4185
4186 intel_wait_for_vblank(dev);
4187
4188 if (IS_IRONLAKE(dev)) {
4189 /* enable address swizzle for tiling buffer */
4190 temp = I915_READ(DISP_ARB_CTL);
4191 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4192 }
4193
4194 I915_WRITE(dspcntr_reg, dspcntr);
4195
4196 /* Flush the plane changes */
4197 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4198
4199 if ((IS_I965G(dev) || plane == 0))
4200 intel_update_fbc(crtc, &crtc->mode);
4201
4202 intel_update_watermarks(dev);
4203
4204 drm_vblank_post_modeset(dev, pipe);
4205
4206 return ret;
4207 }
4208
4209 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4210 void intel_crtc_load_lut(struct drm_crtc *crtc)
4211 {
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4215 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4216 int i;
4217
4218 /* The clocks have to be on to load the palette. */
4219 if (!crtc->enabled)
4220 return;
4221
4222 /* use legacy palette for Ironlake */
4223 if (HAS_PCH_SPLIT(dev))
4224 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4225 LGC_PALETTE_B;
4226
4227 for (i = 0; i < 256; i++) {
4228 I915_WRITE(palreg + 4 * i,
4229 (intel_crtc->lut_r[i] << 16) |
4230 (intel_crtc->lut_g[i] << 8) |
4231 intel_crtc->lut_b[i]);
4232 }
4233 }
4234
4235 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4236 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4237 {
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4241 int pipe = intel_crtc->pipe;
4242 int x = intel_crtc->cursor_x;
4243 int y = intel_crtc->cursor_y;
4244 uint32_t base, pos;
4245 bool visible;
4246
4247 pos = 0;
4248
4249 if (intel_crtc->cursor_on && crtc->fb) {
4250 base = intel_crtc->cursor_addr;
4251 if (x > (int) crtc->fb->width)
4252 base = 0;
4253
4254 if (y > (int) crtc->fb->height)
4255 base = 0;
4256 } else
4257 base = 0;
4258
4259 if (x < 0) {
4260 if (x + intel_crtc->cursor_width < 0)
4261 base = 0;
4262
4263 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4264 x = -x;
4265 }
4266 pos |= x << CURSOR_X_SHIFT;
4267
4268 if (y < 0) {
4269 if (y + intel_crtc->cursor_height < 0)
4270 base = 0;
4271
4272 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4273 y = -y;
4274 }
4275 pos |= y << CURSOR_Y_SHIFT;
4276
4277 visible = base != 0;
4278 if (!visible && !intel_crtc->cursor_visble)
4279 return;
4280
4281 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4282 if (intel_crtc->cursor_visble != visible) {
4283 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4284 if (base) {
4285 /* Hooray for CUR*CNTR differences */
4286 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4287 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4288 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4289 cntl |= pipe << 28; /* Connect to correct pipe */
4290 } else {
4291 cntl &= ~(CURSOR_FORMAT_MASK);
4292 cntl |= CURSOR_ENABLE;
4293 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4294 }
4295 } else {
4296 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4297 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4298 cntl |= CURSOR_MODE_DISABLE;
4299 } else {
4300 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4301 }
4302 }
4303 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4304
4305 intel_crtc->cursor_visble = visible;
4306 }
4307 /* and commit changes on next vblank */
4308 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4309
4310 if (visible)
4311 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4312 }
4313
4314 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4315 struct drm_file *file_priv,
4316 uint32_t handle,
4317 uint32_t width, uint32_t height)
4318 {
4319 struct drm_device *dev = crtc->dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4322 struct drm_gem_object *bo;
4323 struct drm_i915_gem_object *obj_priv;
4324 uint32_t addr;
4325 int ret;
4326
4327 DRM_DEBUG_KMS("\n");
4328
4329 /* if we want to turn off the cursor ignore width and height */
4330 if (!handle) {
4331 DRM_DEBUG_KMS("cursor off\n");
4332 addr = 0;
4333 bo = NULL;
4334 mutex_lock(&dev->struct_mutex);
4335 goto finish;
4336 }
4337
4338 /* Currently we only support 64x64 cursors */
4339 if (width != 64 || height != 64) {
4340 DRM_ERROR("we currently only support 64x64 cursors\n");
4341 return -EINVAL;
4342 }
4343
4344 bo = drm_gem_object_lookup(dev, file_priv, handle);
4345 if (!bo)
4346 return -ENOENT;
4347
4348 obj_priv = to_intel_bo(bo);
4349
4350 if (bo->size < width * height * 4) {
4351 DRM_ERROR("buffer is to small\n");
4352 ret = -ENOMEM;
4353 goto fail;
4354 }
4355
4356 /* we only need to pin inside GTT if cursor is non-phy */
4357 mutex_lock(&dev->struct_mutex);
4358 if (!dev_priv->info->cursor_needs_physical) {
4359 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4360 if (ret) {
4361 DRM_ERROR("failed to pin cursor bo\n");
4362 goto fail_locked;
4363 }
4364
4365 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4366 if (ret) {
4367 DRM_ERROR("failed to move cursor bo into the GTT\n");
4368 goto fail_unpin;
4369 }
4370
4371 addr = obj_priv->gtt_offset;
4372 } else {
4373 ret = i915_gem_attach_phys_object(dev, bo,
4374 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
4375 if (ret) {
4376 DRM_ERROR("failed to attach phys object\n");
4377 goto fail_locked;
4378 }
4379 addr = obj_priv->phys_obj->handle->busaddr;
4380 }
4381
4382 if (!IS_I9XX(dev))
4383 I915_WRITE(CURSIZE, (height << 12) | width);
4384
4385 finish:
4386 if (intel_crtc->cursor_bo) {
4387 if (dev_priv->info->cursor_needs_physical) {
4388 if (intel_crtc->cursor_bo != bo)
4389 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4390 } else
4391 i915_gem_object_unpin(intel_crtc->cursor_bo);
4392 drm_gem_object_unreference(intel_crtc->cursor_bo);
4393 }
4394
4395 mutex_unlock(&dev->struct_mutex);
4396
4397 intel_crtc->cursor_addr = addr;
4398 intel_crtc->cursor_bo = bo;
4399 intel_crtc->cursor_width = width;
4400 intel_crtc->cursor_height = height;
4401
4402 intel_crtc_update_cursor(crtc);
4403
4404 return 0;
4405 fail_unpin:
4406 i915_gem_object_unpin(bo);
4407 fail_locked:
4408 mutex_unlock(&dev->struct_mutex);
4409 fail:
4410 drm_gem_object_unreference_unlocked(bo);
4411 return ret;
4412 }
4413
4414 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4415 {
4416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417
4418 intel_crtc->cursor_x = x;
4419 intel_crtc->cursor_y = y;
4420
4421 intel_crtc_update_cursor(crtc);
4422
4423 return 0;
4424 }
4425
4426 /** Sets the color ramps on behalf of RandR */
4427 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4428 u16 blue, int regno)
4429 {
4430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4431
4432 intel_crtc->lut_r[regno] = red >> 8;
4433 intel_crtc->lut_g[regno] = green >> 8;
4434 intel_crtc->lut_b[regno] = blue >> 8;
4435 }
4436
4437 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4438 u16 *blue, int regno)
4439 {
4440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441
4442 *red = intel_crtc->lut_r[regno] << 8;
4443 *green = intel_crtc->lut_g[regno] << 8;
4444 *blue = intel_crtc->lut_b[regno] << 8;
4445 }
4446
4447 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4448 u16 *blue, uint32_t size)
4449 {
4450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4451 int i;
4452
4453 if (size != 256)
4454 return;
4455
4456 for (i = 0; i < 256; i++) {
4457 intel_crtc->lut_r[i] = red[i] >> 8;
4458 intel_crtc->lut_g[i] = green[i] >> 8;
4459 intel_crtc->lut_b[i] = blue[i] >> 8;
4460 }
4461
4462 intel_crtc_load_lut(crtc);
4463 }
4464
4465 /**
4466 * Get a pipe with a simple mode set on it for doing load-based monitor
4467 * detection.
4468 *
4469 * It will be up to the load-detect code to adjust the pipe as appropriate for
4470 * its requirements. The pipe will be connected to no other encoders.
4471 *
4472 * Currently this code will only succeed if there is a pipe with no encoders
4473 * configured for it. In the future, it could choose to temporarily disable
4474 * some outputs to free up a pipe for its use.
4475 *
4476 * \return crtc, or NULL if no pipes are available.
4477 */
4478
4479 /* VESA 640x480x72Hz mode to set on the pipe */
4480 static struct drm_display_mode load_detect_mode = {
4481 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4482 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4483 };
4484
4485 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4486 struct drm_connector *connector,
4487 struct drm_display_mode *mode,
4488 int *dpms_mode)
4489 {
4490 struct intel_crtc *intel_crtc;
4491 struct drm_crtc *possible_crtc;
4492 struct drm_crtc *supported_crtc =NULL;
4493 struct drm_encoder *encoder = &intel_encoder->enc;
4494 struct drm_crtc *crtc = NULL;
4495 struct drm_device *dev = encoder->dev;
4496 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4497 struct drm_crtc_helper_funcs *crtc_funcs;
4498 int i = -1;
4499
4500 /*
4501 * Algorithm gets a little messy:
4502 * - if the connector already has an assigned crtc, use it (but make
4503 * sure it's on first)
4504 * - try to find the first unused crtc that can drive this connector,
4505 * and use that if we find one
4506 * - if there are no unused crtcs available, try to use the first
4507 * one we found that supports the connector
4508 */
4509
4510 /* See if we already have a CRTC for this connector */
4511 if (encoder->crtc) {
4512 crtc = encoder->crtc;
4513 /* Make sure the crtc and connector are running */
4514 intel_crtc = to_intel_crtc(crtc);
4515 *dpms_mode = intel_crtc->dpms_mode;
4516 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4517 crtc_funcs = crtc->helper_private;
4518 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4519 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4520 }
4521 return crtc;
4522 }
4523
4524 /* Find an unused one (if possible) */
4525 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4526 i++;
4527 if (!(encoder->possible_crtcs & (1 << i)))
4528 continue;
4529 if (!possible_crtc->enabled) {
4530 crtc = possible_crtc;
4531 break;
4532 }
4533 if (!supported_crtc)
4534 supported_crtc = possible_crtc;
4535 }
4536
4537 /*
4538 * If we didn't find an unused CRTC, don't use any.
4539 */
4540 if (!crtc) {
4541 return NULL;
4542 }
4543
4544 encoder->crtc = crtc;
4545 connector->encoder = encoder;
4546 intel_encoder->load_detect_temp = true;
4547
4548 intel_crtc = to_intel_crtc(crtc);
4549 *dpms_mode = intel_crtc->dpms_mode;
4550
4551 if (!crtc->enabled) {
4552 if (!mode)
4553 mode = &load_detect_mode;
4554 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4555 } else {
4556 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4557 crtc_funcs = crtc->helper_private;
4558 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4559 }
4560
4561 /* Add this connector to the crtc */
4562 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4563 encoder_funcs->commit(encoder);
4564 }
4565 /* let the connector get through one full cycle before testing */
4566 intel_wait_for_vblank(dev);
4567
4568 return crtc;
4569 }
4570
4571 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4572 struct drm_connector *connector, int dpms_mode)
4573 {
4574 struct drm_encoder *encoder = &intel_encoder->enc;
4575 struct drm_device *dev = encoder->dev;
4576 struct drm_crtc *crtc = encoder->crtc;
4577 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4578 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4579
4580 if (intel_encoder->load_detect_temp) {
4581 encoder->crtc = NULL;
4582 connector->encoder = NULL;
4583 intel_encoder->load_detect_temp = false;
4584 crtc->enabled = drm_helper_crtc_in_use(crtc);
4585 drm_helper_disable_unused_functions(dev);
4586 }
4587
4588 /* Switch crtc and encoder back off if necessary */
4589 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4590 if (encoder->crtc == crtc)
4591 encoder_funcs->dpms(encoder, dpms_mode);
4592 crtc_funcs->dpms(crtc, dpms_mode);
4593 }
4594 }
4595
4596 /* Returns the clock of the currently programmed mode of the given pipe. */
4597 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4598 {
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4601 int pipe = intel_crtc->pipe;
4602 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4603 u32 fp;
4604 intel_clock_t clock;
4605
4606 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4607 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4608 else
4609 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4610
4611 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4612 if (IS_PINEVIEW(dev)) {
4613 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4614 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4615 } else {
4616 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4617 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4618 }
4619
4620 if (IS_I9XX(dev)) {
4621 if (IS_PINEVIEW(dev))
4622 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4623 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4624 else
4625 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4626 DPLL_FPA01_P1_POST_DIV_SHIFT);
4627
4628 switch (dpll & DPLL_MODE_MASK) {
4629 case DPLLB_MODE_DAC_SERIAL:
4630 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4631 5 : 10;
4632 break;
4633 case DPLLB_MODE_LVDS:
4634 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4635 7 : 14;
4636 break;
4637 default:
4638 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4639 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4640 return 0;
4641 }
4642
4643 /* XXX: Handle the 100Mhz refclk */
4644 intel_clock(dev, 96000, &clock);
4645 } else {
4646 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4647
4648 if (is_lvds) {
4649 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4650 DPLL_FPA01_P1_POST_DIV_SHIFT);
4651 clock.p2 = 14;
4652
4653 if ((dpll & PLL_REF_INPUT_MASK) ==
4654 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4655 /* XXX: might not be 66MHz */
4656 intel_clock(dev, 66000, &clock);
4657 } else
4658 intel_clock(dev, 48000, &clock);
4659 } else {
4660 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4661 clock.p1 = 2;
4662 else {
4663 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4664 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4665 }
4666 if (dpll & PLL_P2_DIVIDE_BY_4)
4667 clock.p2 = 4;
4668 else
4669 clock.p2 = 2;
4670
4671 intel_clock(dev, 48000, &clock);
4672 }
4673 }
4674
4675 /* XXX: It would be nice to validate the clocks, but we can't reuse
4676 * i830PllIsValid() because it relies on the xf86_config connector
4677 * configuration being accurate, which it isn't necessarily.
4678 */
4679
4680 return clock.dot;
4681 }
4682
4683 /** Returns the currently programmed mode of the given pipe. */
4684 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4685 struct drm_crtc *crtc)
4686 {
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4689 int pipe = intel_crtc->pipe;
4690 struct drm_display_mode *mode;
4691 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4692 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4693 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4694 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4695
4696 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4697 if (!mode)
4698 return NULL;
4699
4700 mode->clock = intel_crtc_clock_get(dev, crtc);
4701 mode->hdisplay = (htot & 0xffff) + 1;
4702 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4703 mode->hsync_start = (hsync & 0xffff) + 1;
4704 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4705 mode->vdisplay = (vtot & 0xffff) + 1;
4706 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4707 mode->vsync_start = (vsync & 0xffff) + 1;
4708 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4709
4710 drm_mode_set_name(mode);
4711 drm_mode_set_crtcinfo(mode, 0);
4712
4713 return mode;
4714 }
4715
4716 #define GPU_IDLE_TIMEOUT 500 /* ms */
4717
4718 /* When this timer fires, we've been idle for awhile */
4719 static void intel_gpu_idle_timer(unsigned long arg)
4720 {
4721 struct drm_device *dev = (struct drm_device *)arg;
4722 drm_i915_private_t *dev_priv = dev->dev_private;
4723
4724 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4725
4726 dev_priv->busy = false;
4727
4728 queue_work(dev_priv->wq, &dev_priv->idle_work);
4729 }
4730
4731 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4732
4733 static void intel_crtc_idle_timer(unsigned long arg)
4734 {
4735 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4736 struct drm_crtc *crtc = &intel_crtc->base;
4737 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4738
4739 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4740
4741 intel_crtc->busy = false;
4742
4743 queue_work(dev_priv->wq, &dev_priv->idle_work);
4744 }
4745
4746 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4747 {
4748 struct drm_device *dev = crtc->dev;
4749 drm_i915_private_t *dev_priv = dev->dev_private;
4750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4751 int pipe = intel_crtc->pipe;
4752 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4753 int dpll = I915_READ(dpll_reg);
4754
4755 if (HAS_PCH_SPLIT(dev))
4756 return;
4757
4758 if (!dev_priv->lvds_downclock_avail)
4759 return;
4760
4761 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4762 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4763
4764 /* Unlock panel regs */
4765 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4766 PANEL_UNLOCK_REGS);
4767
4768 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4769 I915_WRITE(dpll_reg, dpll);
4770 dpll = I915_READ(dpll_reg);
4771 intel_wait_for_vblank(dev);
4772 dpll = I915_READ(dpll_reg);
4773 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4774 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4775
4776 /* ...and lock them again */
4777 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4778 }
4779
4780 /* Schedule downclock */
4781 if (schedule)
4782 mod_timer(&intel_crtc->idle_timer, jiffies +
4783 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4784 }
4785
4786 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4787 {
4788 struct drm_device *dev = crtc->dev;
4789 drm_i915_private_t *dev_priv = dev->dev_private;
4790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4791 int pipe = intel_crtc->pipe;
4792 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4793 int dpll = I915_READ(dpll_reg);
4794
4795 if (HAS_PCH_SPLIT(dev))
4796 return;
4797
4798 if (!dev_priv->lvds_downclock_avail)
4799 return;
4800
4801 /*
4802 * Since this is called by a timer, we should never get here in
4803 * the manual case.
4804 */
4805 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4806 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4807
4808 /* Unlock panel regs */
4809 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4810 PANEL_UNLOCK_REGS);
4811
4812 dpll |= DISPLAY_RATE_SELECT_FPA1;
4813 I915_WRITE(dpll_reg, dpll);
4814 dpll = I915_READ(dpll_reg);
4815 intel_wait_for_vblank(dev);
4816 dpll = I915_READ(dpll_reg);
4817 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4818 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4819
4820 /* ...and lock them again */
4821 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4822 }
4823
4824 }
4825
4826 /**
4827 * intel_idle_update - adjust clocks for idleness
4828 * @work: work struct
4829 *
4830 * Either the GPU or display (or both) went idle. Check the busy status
4831 * here and adjust the CRTC and GPU clocks as necessary.
4832 */
4833 static void intel_idle_update(struct work_struct *work)
4834 {
4835 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4836 idle_work);
4837 struct drm_device *dev = dev_priv->dev;
4838 struct drm_crtc *crtc;
4839 struct intel_crtc *intel_crtc;
4840 int enabled = 0;
4841
4842 if (!i915_powersave)
4843 return;
4844
4845 mutex_lock(&dev->struct_mutex);
4846
4847 i915_update_gfx_val(dev_priv);
4848
4849 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4850 /* Skip inactive CRTCs */
4851 if (!crtc->fb)
4852 continue;
4853
4854 enabled++;
4855 intel_crtc = to_intel_crtc(crtc);
4856 if (!intel_crtc->busy)
4857 intel_decrease_pllclock(crtc);
4858 }
4859
4860 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4861 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4862 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4863 }
4864
4865 mutex_unlock(&dev->struct_mutex);
4866 }
4867
4868 /**
4869 * intel_mark_busy - mark the GPU and possibly the display busy
4870 * @dev: drm device
4871 * @obj: object we're operating on
4872 *
4873 * Callers can use this function to indicate that the GPU is busy processing
4874 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4875 * buffer), we'll also mark the display as busy, so we know to increase its
4876 * clock frequency.
4877 */
4878 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4879 {
4880 drm_i915_private_t *dev_priv = dev->dev_private;
4881 struct drm_crtc *crtc = NULL;
4882 struct intel_framebuffer *intel_fb;
4883 struct intel_crtc *intel_crtc;
4884
4885 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4886 return;
4887
4888 if (!dev_priv->busy) {
4889 if (IS_I945G(dev) || IS_I945GM(dev)) {
4890 u32 fw_blc_self;
4891
4892 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4893 fw_blc_self = I915_READ(FW_BLC_SELF);
4894 fw_blc_self &= ~FW_BLC_SELF_EN;
4895 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4896 }
4897 dev_priv->busy = true;
4898 } else
4899 mod_timer(&dev_priv->idle_timer, jiffies +
4900 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4901
4902 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4903 if (!crtc->fb)
4904 continue;
4905
4906 intel_crtc = to_intel_crtc(crtc);
4907 intel_fb = to_intel_framebuffer(crtc->fb);
4908 if (intel_fb->obj == obj) {
4909 if (!intel_crtc->busy) {
4910 if (IS_I945G(dev) || IS_I945GM(dev)) {
4911 u32 fw_blc_self;
4912
4913 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4914 fw_blc_self = I915_READ(FW_BLC_SELF);
4915 fw_blc_self &= ~FW_BLC_SELF_EN;
4916 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4917 }
4918 /* Non-busy -> busy, upclock */
4919 intel_increase_pllclock(crtc, true);
4920 intel_crtc->busy = true;
4921 } else {
4922 /* Busy -> busy, put off timer */
4923 mod_timer(&intel_crtc->idle_timer, jiffies +
4924 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4925 }
4926 }
4927 }
4928 }
4929
4930 static void intel_crtc_destroy(struct drm_crtc *crtc)
4931 {
4932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4933
4934 drm_crtc_cleanup(crtc);
4935 kfree(intel_crtc);
4936 }
4937
4938 struct intel_unpin_work {
4939 struct work_struct work;
4940 struct drm_device *dev;
4941 struct drm_gem_object *old_fb_obj;
4942 struct drm_gem_object *pending_flip_obj;
4943 struct drm_pending_vblank_event *event;
4944 int pending;
4945 };
4946
4947 static void intel_unpin_work_fn(struct work_struct *__work)
4948 {
4949 struct intel_unpin_work *work =
4950 container_of(__work, struct intel_unpin_work, work);
4951
4952 mutex_lock(&work->dev->struct_mutex);
4953 i915_gem_object_unpin(work->old_fb_obj);
4954 drm_gem_object_unreference(work->pending_flip_obj);
4955 drm_gem_object_unreference(work->old_fb_obj);
4956 mutex_unlock(&work->dev->struct_mutex);
4957 kfree(work);
4958 }
4959
4960 static void do_intel_finish_page_flip(struct drm_device *dev,
4961 struct drm_crtc *crtc)
4962 {
4963 drm_i915_private_t *dev_priv = dev->dev_private;
4964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965 struct intel_unpin_work *work;
4966 struct drm_i915_gem_object *obj_priv;
4967 struct drm_pending_vblank_event *e;
4968 struct timeval now;
4969 unsigned long flags;
4970
4971 /* Ignore early vblank irqs */
4972 if (intel_crtc == NULL)
4973 return;
4974
4975 spin_lock_irqsave(&dev->event_lock, flags);
4976 work = intel_crtc->unpin_work;
4977 if (work == NULL || !work->pending) {
4978 spin_unlock_irqrestore(&dev->event_lock, flags);
4979 return;
4980 }
4981
4982 intel_crtc->unpin_work = NULL;
4983 drm_vblank_put(dev, intel_crtc->pipe);
4984
4985 if (work->event) {
4986 e = work->event;
4987 do_gettimeofday(&now);
4988 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4989 e->event.tv_sec = now.tv_sec;
4990 e->event.tv_usec = now.tv_usec;
4991 list_add_tail(&e->base.link,
4992 &e->base.file_priv->event_list);
4993 wake_up_interruptible(&e->base.file_priv->event_wait);
4994 }
4995
4996 spin_unlock_irqrestore(&dev->event_lock, flags);
4997
4998 obj_priv = to_intel_bo(work->pending_flip_obj);
4999
5000 /* Initial scanout buffer will have a 0 pending flip count */
5001 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
5002 atomic_dec_and_test(&obj_priv->pending_flip))
5003 DRM_WAKEUP(&dev_priv->pending_flip_queue);
5004 schedule_work(&work->work);
5005
5006 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5007 }
5008
5009 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5010 {
5011 drm_i915_private_t *dev_priv = dev->dev_private;
5012 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5013
5014 do_intel_finish_page_flip(dev, crtc);
5015 }
5016
5017 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5018 {
5019 drm_i915_private_t *dev_priv = dev->dev_private;
5020 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5021
5022 do_intel_finish_page_flip(dev, crtc);
5023 }
5024
5025 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5026 {
5027 drm_i915_private_t *dev_priv = dev->dev_private;
5028 struct intel_crtc *intel_crtc =
5029 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5030 unsigned long flags;
5031
5032 spin_lock_irqsave(&dev->event_lock, flags);
5033 if (intel_crtc->unpin_work) {
5034 intel_crtc->unpin_work->pending = 1;
5035 } else {
5036 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5037 }
5038 spin_unlock_irqrestore(&dev->event_lock, flags);
5039 }
5040
5041 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5042 struct drm_framebuffer *fb,
5043 struct drm_pending_vblank_event *event)
5044 {
5045 struct drm_device *dev = crtc->dev;
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047 struct intel_framebuffer *intel_fb;
5048 struct drm_i915_gem_object *obj_priv;
5049 struct drm_gem_object *obj;
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051 struct intel_unpin_work *work;
5052 unsigned long flags, offset;
5053 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
5054 int ret, pipesrc;
5055 u32 flip_mask;
5056
5057 work = kzalloc(sizeof *work, GFP_KERNEL);
5058 if (work == NULL)
5059 return -ENOMEM;
5060
5061 work->event = event;
5062 work->dev = crtc->dev;
5063 intel_fb = to_intel_framebuffer(crtc->fb);
5064 work->old_fb_obj = intel_fb->obj;
5065 INIT_WORK(&work->work, intel_unpin_work_fn);
5066
5067 /* We borrow the event spin lock for protecting unpin_work */
5068 spin_lock_irqsave(&dev->event_lock, flags);
5069 if (intel_crtc->unpin_work) {
5070 spin_unlock_irqrestore(&dev->event_lock, flags);
5071 kfree(work);
5072
5073 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5074 return -EBUSY;
5075 }
5076 intel_crtc->unpin_work = work;
5077 spin_unlock_irqrestore(&dev->event_lock, flags);
5078
5079 intel_fb = to_intel_framebuffer(fb);
5080 obj = intel_fb->obj;
5081
5082 mutex_lock(&dev->struct_mutex);
5083 ret = intel_pin_and_fence_fb_obj(dev, obj);
5084 if (ret)
5085 goto cleanup_work;
5086
5087 /* Reference the objects for the scheduled work. */
5088 drm_gem_object_reference(work->old_fb_obj);
5089 drm_gem_object_reference(obj);
5090
5091 crtc->fb = fb;
5092 ret = i915_gem_object_flush_write_domain(obj);
5093 if (ret)
5094 goto cleanup_objs;
5095
5096 ret = drm_vblank_get(dev, intel_crtc->pipe);
5097 if (ret)
5098 goto cleanup_objs;
5099
5100 obj_priv = to_intel_bo(obj);
5101 atomic_inc(&obj_priv->pending_flip);
5102 work->pending_flip_obj = obj;
5103
5104 if (intel_crtc->plane)
5105 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5106 else
5107 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5108
5109 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5110 BEGIN_LP_RING(2);
5111 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5112 OUT_RING(0);
5113 ADVANCE_LP_RING();
5114 }
5115
5116 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5117 offset = obj_priv->gtt_offset;
5118 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5119
5120 BEGIN_LP_RING(4);
5121 if (IS_I965G(dev)) {
5122 OUT_RING(MI_DISPLAY_FLIP |
5123 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5124 OUT_RING(fb->pitch);
5125 OUT_RING(offset | obj_priv->tiling_mode);
5126 pipesrc = I915_READ(pipesrc_reg);
5127 OUT_RING(pipesrc & 0x0fff0fff);
5128 } else if (IS_GEN3(dev)) {
5129 OUT_RING(MI_DISPLAY_FLIP_I915 |
5130 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5131 OUT_RING(fb->pitch);
5132 OUT_RING(offset);
5133 OUT_RING(MI_NOOP);
5134 } else {
5135 OUT_RING(MI_DISPLAY_FLIP |
5136 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5137 OUT_RING(fb->pitch);
5138 OUT_RING(offset);
5139 OUT_RING(MI_NOOP);
5140 }
5141 ADVANCE_LP_RING();
5142
5143 mutex_unlock(&dev->struct_mutex);
5144
5145 trace_i915_flip_request(intel_crtc->plane, obj);
5146
5147 return 0;
5148
5149 cleanup_objs:
5150 drm_gem_object_unreference(work->old_fb_obj);
5151 drm_gem_object_unreference(obj);
5152 cleanup_work:
5153 mutex_unlock(&dev->struct_mutex);
5154
5155 spin_lock_irqsave(&dev->event_lock, flags);
5156 intel_crtc->unpin_work = NULL;
5157 spin_unlock_irqrestore(&dev->event_lock, flags);
5158
5159 kfree(work);
5160
5161 return ret;
5162 }
5163
5164 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5165 .dpms = intel_crtc_dpms,
5166 .mode_fixup = intel_crtc_mode_fixup,
5167 .mode_set = intel_crtc_mode_set,
5168 .mode_set_base = intel_pipe_set_base,
5169 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5170 .prepare = intel_crtc_prepare,
5171 .commit = intel_crtc_commit,
5172 .load_lut = intel_crtc_load_lut,
5173 };
5174
5175 static const struct drm_crtc_funcs intel_crtc_funcs = {
5176 .cursor_set = intel_crtc_cursor_set,
5177 .cursor_move = intel_crtc_cursor_move,
5178 .gamma_set = intel_crtc_gamma_set,
5179 .set_config = drm_crtc_helper_set_config,
5180 .destroy = intel_crtc_destroy,
5181 .page_flip = intel_crtc_page_flip,
5182 };
5183
5184
5185 static void intel_crtc_init(struct drm_device *dev, int pipe)
5186 {
5187 drm_i915_private_t *dev_priv = dev->dev_private;
5188 struct intel_crtc *intel_crtc;
5189 int i;
5190
5191 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5192 if (intel_crtc == NULL)
5193 return;
5194
5195 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5196
5197 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5198 intel_crtc->pipe = pipe;
5199 intel_crtc->plane = pipe;
5200 for (i = 0; i < 256; i++) {
5201 intel_crtc->lut_r[i] = i;
5202 intel_crtc->lut_g[i] = i;
5203 intel_crtc->lut_b[i] = i;
5204 }
5205
5206 /* Swap pipes & planes for FBC on pre-965 */
5207 intel_crtc->pipe = pipe;
5208 intel_crtc->plane = pipe;
5209 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5210 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5211 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5212 }
5213
5214 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5215 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5216 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5217 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5218
5219 intel_crtc->cursor_addr = 0;
5220 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5221 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5222
5223 intel_crtc->busy = false;
5224
5225 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5226 (unsigned long)intel_crtc);
5227 }
5228
5229 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5230 struct drm_file *file_priv)
5231 {
5232 drm_i915_private_t *dev_priv = dev->dev_private;
5233 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5234 struct drm_mode_object *drmmode_obj;
5235 struct intel_crtc *crtc;
5236
5237 if (!dev_priv) {
5238 DRM_ERROR("called with no initialization\n");
5239 return -EINVAL;
5240 }
5241
5242 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5243 DRM_MODE_OBJECT_CRTC);
5244
5245 if (!drmmode_obj) {
5246 DRM_ERROR("no such CRTC id\n");
5247 return -EINVAL;
5248 }
5249
5250 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5251 pipe_from_crtc_id->pipe = crtc->pipe;
5252
5253 return 0;
5254 }
5255
5256 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
5257 {
5258 struct drm_crtc *crtc = NULL;
5259
5260 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262 if (intel_crtc->pipe == pipe)
5263 break;
5264 }
5265 return crtc;
5266 }
5267
5268 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5269 {
5270 int index_mask = 0;
5271 struct drm_encoder *encoder;
5272 int entry = 0;
5273
5274 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5275 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5276 if (type_mask & intel_encoder->clone_mask)
5277 index_mask |= (1 << entry);
5278 entry++;
5279 }
5280 return index_mask;
5281 }
5282
5283
5284 static void intel_setup_outputs(struct drm_device *dev)
5285 {
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct drm_encoder *encoder;
5288 bool dpd_is_edp = false;
5289
5290 if (IS_MOBILE(dev) && !IS_I830(dev))
5291 intel_lvds_init(dev);
5292
5293 if (HAS_PCH_SPLIT(dev)) {
5294 dpd_is_edp = intel_dpd_is_edp(dev);
5295
5296 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5297 intel_dp_init(dev, DP_A);
5298
5299 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5300 intel_dp_init(dev, PCH_DP_D);
5301 }
5302
5303 intel_crt_init(dev);
5304
5305 if (HAS_PCH_SPLIT(dev)) {
5306 int found;
5307
5308 if (I915_READ(HDMIB) & PORT_DETECTED) {
5309 /* PCH SDVOB multiplex with HDMIB */
5310 found = intel_sdvo_init(dev, PCH_SDVOB);
5311 if (!found)
5312 intel_hdmi_init(dev, HDMIB);
5313 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5314 intel_dp_init(dev, PCH_DP_B);
5315 }
5316
5317 if (I915_READ(HDMIC) & PORT_DETECTED)
5318 intel_hdmi_init(dev, HDMIC);
5319
5320 if (I915_READ(HDMID) & PORT_DETECTED)
5321 intel_hdmi_init(dev, HDMID);
5322
5323 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5324 intel_dp_init(dev, PCH_DP_C);
5325
5326 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5327 intel_dp_init(dev, PCH_DP_D);
5328
5329 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5330 bool found = false;
5331
5332 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5333 DRM_DEBUG_KMS("probing SDVOB\n");
5334 found = intel_sdvo_init(dev, SDVOB);
5335 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5336 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5337 intel_hdmi_init(dev, SDVOB);
5338 }
5339
5340 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5341 DRM_DEBUG_KMS("probing DP_B\n");
5342 intel_dp_init(dev, DP_B);
5343 }
5344 }
5345
5346 /* Before G4X SDVOC doesn't have its own detect register */
5347
5348 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5349 DRM_DEBUG_KMS("probing SDVOC\n");
5350 found = intel_sdvo_init(dev, SDVOC);
5351 }
5352
5353 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5354
5355 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5356 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5357 intel_hdmi_init(dev, SDVOC);
5358 }
5359 if (SUPPORTS_INTEGRATED_DP(dev)) {
5360 DRM_DEBUG_KMS("probing DP_C\n");
5361 intel_dp_init(dev, DP_C);
5362 }
5363 }
5364
5365 if (SUPPORTS_INTEGRATED_DP(dev) &&
5366 (I915_READ(DP_D) & DP_DETECTED)) {
5367 DRM_DEBUG_KMS("probing DP_D\n");
5368 intel_dp_init(dev, DP_D);
5369 }
5370 } else if (IS_GEN2(dev))
5371 intel_dvo_init(dev);
5372
5373 if (SUPPORTS_TV(dev))
5374 intel_tv_init(dev);
5375
5376 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
5377 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
5378
5379 encoder->possible_crtcs = intel_encoder->crtc_mask;
5380 encoder->possible_clones = intel_encoder_clones(dev,
5381 intel_encoder->clone_mask);
5382 }
5383 }
5384
5385 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5386 {
5387 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5388
5389 drm_framebuffer_cleanup(fb);
5390 drm_gem_object_unreference_unlocked(intel_fb->obj);
5391
5392 kfree(intel_fb);
5393 }
5394
5395 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5396 struct drm_file *file_priv,
5397 unsigned int *handle)
5398 {
5399 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5400 struct drm_gem_object *object = intel_fb->obj;
5401
5402 return drm_gem_handle_create(file_priv, object, handle);
5403 }
5404
5405 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5406 .destroy = intel_user_framebuffer_destroy,
5407 .create_handle = intel_user_framebuffer_create_handle,
5408 };
5409
5410 int intel_framebuffer_init(struct drm_device *dev,
5411 struct intel_framebuffer *intel_fb,
5412 struct drm_mode_fb_cmd *mode_cmd,
5413 struct drm_gem_object *obj)
5414 {
5415 int ret;
5416
5417 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5418 if (ret) {
5419 DRM_ERROR("framebuffer init failed %d\n", ret);
5420 return ret;
5421 }
5422
5423 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5424 intel_fb->obj = obj;
5425 return 0;
5426 }
5427
5428 static struct drm_framebuffer *
5429 intel_user_framebuffer_create(struct drm_device *dev,
5430 struct drm_file *filp,
5431 struct drm_mode_fb_cmd *mode_cmd)
5432 {
5433 struct drm_gem_object *obj;
5434 struct intel_framebuffer *intel_fb;
5435 int ret;
5436
5437 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5438 if (!obj)
5439 return NULL;
5440
5441 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5442 if (!intel_fb)
5443 return NULL;
5444
5445 ret = intel_framebuffer_init(dev, intel_fb,
5446 mode_cmd, obj);
5447 if (ret) {
5448 drm_gem_object_unreference_unlocked(obj);
5449 kfree(intel_fb);
5450 return NULL;
5451 }
5452
5453 return &intel_fb->base;
5454 }
5455
5456 static const struct drm_mode_config_funcs intel_mode_funcs = {
5457 .fb_create = intel_user_framebuffer_create,
5458 .output_poll_changed = intel_fb_output_poll_changed,
5459 };
5460
5461 static struct drm_gem_object *
5462 intel_alloc_power_context(struct drm_device *dev)
5463 {
5464 struct drm_gem_object *pwrctx;
5465 int ret;
5466
5467 pwrctx = i915_gem_alloc_object(dev, 4096);
5468 if (!pwrctx) {
5469 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5470 return NULL;
5471 }
5472
5473 mutex_lock(&dev->struct_mutex);
5474 ret = i915_gem_object_pin(pwrctx, 4096);
5475 if (ret) {
5476 DRM_ERROR("failed to pin power context: %d\n", ret);
5477 goto err_unref;
5478 }
5479
5480 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
5481 if (ret) {
5482 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5483 goto err_unpin;
5484 }
5485 mutex_unlock(&dev->struct_mutex);
5486
5487 return pwrctx;
5488
5489 err_unpin:
5490 i915_gem_object_unpin(pwrctx);
5491 err_unref:
5492 drm_gem_object_unreference(pwrctx);
5493 mutex_unlock(&dev->struct_mutex);
5494 return NULL;
5495 }
5496
5497 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5498 {
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500 u16 rgvswctl;
5501
5502 rgvswctl = I915_READ16(MEMSWCTL);
5503 if (rgvswctl & MEMCTL_CMD_STS) {
5504 DRM_DEBUG("gpu busy, RCS change rejected\n");
5505 return false; /* still busy with another command */
5506 }
5507
5508 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5509 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5510 I915_WRITE16(MEMSWCTL, rgvswctl);
5511 POSTING_READ16(MEMSWCTL);
5512
5513 rgvswctl |= MEMCTL_CMD_STS;
5514 I915_WRITE16(MEMSWCTL, rgvswctl);
5515
5516 return true;
5517 }
5518
5519 void ironlake_enable_drps(struct drm_device *dev)
5520 {
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 u32 rgvmodectl = I915_READ(MEMMODECTL);
5523 u8 fmax, fmin, fstart, vstart;
5524 int i = 0;
5525
5526 /* 100ms RC evaluation intervals */
5527 I915_WRITE(RCUPEI, 100000);
5528 I915_WRITE(RCDNEI, 100000);
5529
5530 /* Set max/min thresholds to 90ms and 80ms respectively */
5531 I915_WRITE(RCBMAXAVG, 90000);
5532 I915_WRITE(RCBMINAVG, 80000);
5533
5534 I915_WRITE(MEMIHYST, 1);
5535
5536 /* Set up min, max, and cur for interrupt handling */
5537 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5538 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5539 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5540 MEMMODE_FSTART_SHIFT;
5541 fstart = fmax;
5542
5543 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5544 PXVFREQ_PX_SHIFT;
5545
5546 dev_priv->fmax = fstart; /* IPS callback will increase this */
5547 dev_priv->fstart = fstart;
5548
5549 dev_priv->max_delay = fmax;
5550 dev_priv->min_delay = fmin;
5551 dev_priv->cur_delay = fstart;
5552
5553 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5554 fstart);
5555
5556 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5557
5558 /*
5559 * Interrupts will be enabled in ironlake_irq_postinstall
5560 */
5561
5562 I915_WRITE(VIDSTART, vstart);
5563 POSTING_READ(VIDSTART);
5564
5565 rgvmodectl |= MEMMODE_SWMODE_EN;
5566 I915_WRITE(MEMMODECTL, rgvmodectl);
5567
5568 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
5569 if (i++ > 100) {
5570 DRM_ERROR("stuck trying to change perf mode\n");
5571 break;
5572 }
5573 msleep(1);
5574 }
5575 msleep(1);
5576
5577 ironlake_set_drps(dev, fstart);
5578
5579 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5580 I915_READ(0x112e0);
5581 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5582 dev_priv->last_count2 = I915_READ(0x112f4);
5583 getrawmonotonic(&dev_priv->last_time2);
5584 }
5585
5586 void ironlake_disable_drps(struct drm_device *dev)
5587 {
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 u16 rgvswctl = I915_READ16(MEMSWCTL);
5590
5591 /* Ack interrupts, disable EFC interrupt */
5592 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5593 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5594 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5595 I915_WRITE(DEIIR, DE_PCU_EVENT);
5596 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5597
5598 /* Go back to the starting frequency */
5599 ironlake_set_drps(dev, dev_priv->fstart);
5600 msleep(1);
5601 rgvswctl |= MEMCTL_CMD_STS;
5602 I915_WRITE(MEMSWCTL, rgvswctl);
5603 msleep(1);
5604
5605 }
5606
5607 static unsigned long intel_pxfreq(u32 vidfreq)
5608 {
5609 unsigned long freq;
5610 int div = (vidfreq & 0x3f0000) >> 16;
5611 int post = (vidfreq & 0x3000) >> 12;
5612 int pre = (vidfreq & 0x7);
5613
5614 if (!pre)
5615 return 0;
5616
5617 freq = ((div * 133333) / ((1<<post) * pre));
5618
5619 return freq;
5620 }
5621
5622 void intel_init_emon(struct drm_device *dev)
5623 {
5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 u32 lcfuse;
5626 u8 pxw[16];
5627 int i;
5628
5629 /* Disable to program */
5630 I915_WRITE(ECR, 0);
5631 POSTING_READ(ECR);
5632
5633 /* Program energy weights for various events */
5634 I915_WRITE(SDEW, 0x15040d00);
5635 I915_WRITE(CSIEW0, 0x007f0000);
5636 I915_WRITE(CSIEW1, 0x1e220004);
5637 I915_WRITE(CSIEW2, 0x04000004);
5638
5639 for (i = 0; i < 5; i++)
5640 I915_WRITE(PEW + (i * 4), 0);
5641 for (i = 0; i < 3; i++)
5642 I915_WRITE(DEW + (i * 4), 0);
5643
5644 /* Program P-state weights to account for frequency power adjustment */
5645 for (i = 0; i < 16; i++) {
5646 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5647 unsigned long freq = intel_pxfreq(pxvidfreq);
5648 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5649 PXVFREQ_PX_SHIFT;
5650 unsigned long val;
5651
5652 val = vid * vid;
5653 val *= (freq / 1000);
5654 val *= 255;
5655 val /= (127*127*900);
5656 if (val > 0xff)
5657 DRM_ERROR("bad pxval: %ld\n", val);
5658 pxw[i] = val;
5659 }
5660 /* Render standby states get 0 weight */
5661 pxw[14] = 0;
5662 pxw[15] = 0;
5663
5664 for (i = 0; i < 4; i++) {
5665 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5666 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5667 I915_WRITE(PXW + (i * 4), val);
5668 }
5669
5670 /* Adjust magic regs to magic values (more experimental results) */
5671 I915_WRITE(OGW0, 0);
5672 I915_WRITE(OGW1, 0);
5673 I915_WRITE(EG0, 0x00007f00);
5674 I915_WRITE(EG1, 0x0000000e);
5675 I915_WRITE(EG2, 0x000e0000);
5676 I915_WRITE(EG3, 0x68000300);
5677 I915_WRITE(EG4, 0x42000000);
5678 I915_WRITE(EG5, 0x00140031);
5679 I915_WRITE(EG6, 0);
5680 I915_WRITE(EG7, 0);
5681
5682 for (i = 0; i < 8; i++)
5683 I915_WRITE(PXWL + (i * 4), 0);
5684
5685 /* Enable PMON + select events */
5686 I915_WRITE(ECR, 0x80000019);
5687
5688 lcfuse = I915_READ(LCFUSE02);
5689
5690 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5691 }
5692
5693 void intel_init_clock_gating(struct drm_device *dev)
5694 {
5695 struct drm_i915_private *dev_priv = dev->dev_private;
5696
5697 /*
5698 * Disable clock gating reported to work incorrectly according to the
5699 * specs, but enable as much else as we can.
5700 */
5701 if (HAS_PCH_SPLIT(dev)) {
5702 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5703
5704 if (IS_IRONLAKE(dev)) {
5705 /* Required for FBC */
5706 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5707 /* Required for CxSR */
5708 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5709
5710 I915_WRITE(PCH_3DCGDIS0,
5711 MARIUNIT_CLOCK_GATE_DISABLE |
5712 SVSMUNIT_CLOCK_GATE_DISABLE);
5713 }
5714
5715 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5716
5717 /*
5718 * According to the spec the following bits should be set in
5719 * order to enable memory self-refresh
5720 * The bit 22/21 of 0x42004
5721 * The bit 5 of 0x42020
5722 * The bit 15 of 0x45000
5723 */
5724 if (IS_IRONLAKE(dev)) {
5725 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5726 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5727 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5728 I915_WRITE(ILK_DSPCLK_GATE,
5729 (I915_READ(ILK_DSPCLK_GATE) |
5730 ILK_DPARB_CLK_GATE));
5731 I915_WRITE(DISP_ARB_CTL,
5732 (I915_READ(DISP_ARB_CTL) |
5733 DISP_FBC_WM_DIS));
5734 }
5735 /*
5736 * Based on the document from hardware guys the following bits
5737 * should be set unconditionally in order to enable FBC.
5738 * The bit 22 of 0x42000
5739 * The bit 22 of 0x42004
5740 * The bit 7,8,9 of 0x42020.
5741 */
5742 if (IS_IRONLAKE_M(dev)) {
5743 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5744 I915_READ(ILK_DISPLAY_CHICKEN1) |
5745 ILK_FBCQ_DIS);
5746 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5747 I915_READ(ILK_DISPLAY_CHICKEN2) |
5748 ILK_DPARB_GATE);
5749 I915_WRITE(ILK_DSPCLK_GATE,
5750 I915_READ(ILK_DSPCLK_GATE) |
5751 ILK_DPFC_DIS1 |
5752 ILK_DPFC_DIS2 |
5753 ILK_CLK_FBC);
5754 }
5755 return;
5756 } else if (IS_G4X(dev)) {
5757 uint32_t dspclk_gate;
5758 I915_WRITE(RENCLK_GATE_D1, 0);
5759 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5760 GS_UNIT_CLOCK_GATE_DISABLE |
5761 CL_UNIT_CLOCK_GATE_DISABLE);
5762 I915_WRITE(RAMCLK_GATE_D, 0);
5763 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5764 OVRUNIT_CLOCK_GATE_DISABLE |
5765 OVCUNIT_CLOCK_GATE_DISABLE;
5766 if (IS_GM45(dev))
5767 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5768 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5769 } else if (IS_I965GM(dev)) {
5770 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5771 I915_WRITE(RENCLK_GATE_D2, 0);
5772 I915_WRITE(DSPCLK_GATE_D, 0);
5773 I915_WRITE(RAMCLK_GATE_D, 0);
5774 I915_WRITE16(DEUC, 0);
5775 } else if (IS_I965G(dev)) {
5776 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5777 I965_RCC_CLOCK_GATE_DISABLE |
5778 I965_RCPB_CLOCK_GATE_DISABLE |
5779 I965_ISC_CLOCK_GATE_DISABLE |
5780 I965_FBC_CLOCK_GATE_DISABLE);
5781 I915_WRITE(RENCLK_GATE_D2, 0);
5782 } else if (IS_I9XX(dev)) {
5783 u32 dstate = I915_READ(D_STATE);
5784
5785 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5786 DSTATE_DOT_CLOCK_GATING;
5787 I915_WRITE(D_STATE, dstate);
5788 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5789 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5790 } else if (IS_I830(dev)) {
5791 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5792 }
5793
5794 /*
5795 * GPU can automatically power down the render unit if given a page
5796 * to save state.
5797 */
5798 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5799 struct drm_i915_gem_object *obj_priv = NULL;
5800
5801 if (dev_priv->pwrctx) {
5802 obj_priv = to_intel_bo(dev_priv->pwrctx);
5803 } else {
5804 struct drm_gem_object *pwrctx;
5805
5806 pwrctx = intel_alloc_power_context(dev);
5807 if (pwrctx) {
5808 dev_priv->pwrctx = pwrctx;
5809 obj_priv = to_intel_bo(pwrctx);
5810 }
5811 }
5812
5813 if (obj_priv) {
5814 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5815 I915_WRITE(MCHBAR_RENDER_STANDBY,
5816 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5817 }
5818 }
5819 }
5820
5821 /* Set up chip specific display functions */
5822 static void intel_init_display(struct drm_device *dev)
5823 {
5824 struct drm_i915_private *dev_priv = dev->dev_private;
5825
5826 /* We always want a DPMS function */
5827 if (HAS_PCH_SPLIT(dev))
5828 dev_priv->display.dpms = ironlake_crtc_dpms;
5829 else
5830 dev_priv->display.dpms = i9xx_crtc_dpms;
5831
5832 if (I915_HAS_FBC(dev)) {
5833 if (IS_IRONLAKE_M(dev)) {
5834 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5835 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5836 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5837 } else if (IS_GM45(dev)) {
5838 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5839 dev_priv->display.enable_fbc = g4x_enable_fbc;
5840 dev_priv->display.disable_fbc = g4x_disable_fbc;
5841 } else if (IS_I965GM(dev)) {
5842 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5843 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5844 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5845 }
5846 /* 855GM needs testing */
5847 }
5848
5849 /* Returns the core display clock speed */
5850 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5851 dev_priv->display.get_display_clock_speed =
5852 i945_get_display_clock_speed;
5853 else if (IS_I915G(dev))
5854 dev_priv->display.get_display_clock_speed =
5855 i915_get_display_clock_speed;
5856 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5857 dev_priv->display.get_display_clock_speed =
5858 i9xx_misc_get_display_clock_speed;
5859 else if (IS_I915GM(dev))
5860 dev_priv->display.get_display_clock_speed =
5861 i915gm_get_display_clock_speed;
5862 else if (IS_I865G(dev))
5863 dev_priv->display.get_display_clock_speed =
5864 i865_get_display_clock_speed;
5865 else if (IS_I85X(dev))
5866 dev_priv->display.get_display_clock_speed =
5867 i855_get_display_clock_speed;
5868 else /* 852, 830 */
5869 dev_priv->display.get_display_clock_speed =
5870 i830_get_display_clock_speed;
5871
5872 /* For FIFO watermark updates */
5873 if (HAS_PCH_SPLIT(dev)) {
5874 if (IS_IRONLAKE(dev)) {
5875 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5876 dev_priv->display.update_wm = ironlake_update_wm;
5877 else {
5878 DRM_DEBUG_KMS("Failed to get proper latency. "
5879 "Disable CxSR\n");
5880 dev_priv->display.update_wm = NULL;
5881 }
5882 } else
5883 dev_priv->display.update_wm = NULL;
5884 } else if (IS_PINEVIEW(dev)) {
5885 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5886 dev_priv->is_ddr3,
5887 dev_priv->fsb_freq,
5888 dev_priv->mem_freq)) {
5889 DRM_INFO("failed to find known CxSR latency "
5890 "(found ddr%s fsb freq %d, mem freq %d), "
5891 "disabling CxSR\n",
5892 (dev_priv->is_ddr3 == 1) ? "3": "2",
5893 dev_priv->fsb_freq, dev_priv->mem_freq);
5894 /* Disable CxSR and never update its watermark again */
5895 pineview_disable_cxsr(dev);
5896 dev_priv->display.update_wm = NULL;
5897 } else
5898 dev_priv->display.update_wm = pineview_update_wm;
5899 } else if (IS_G4X(dev))
5900 dev_priv->display.update_wm = g4x_update_wm;
5901 else if (IS_I965G(dev))
5902 dev_priv->display.update_wm = i965_update_wm;
5903 else if (IS_I9XX(dev)) {
5904 dev_priv->display.update_wm = i9xx_update_wm;
5905 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5906 } else if (IS_I85X(dev)) {
5907 dev_priv->display.update_wm = i9xx_update_wm;
5908 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5909 } else {
5910 dev_priv->display.update_wm = i830_update_wm;
5911 if (IS_845G(dev))
5912 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5913 else
5914 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5915 }
5916 }
5917
5918 /*
5919 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5920 * resume, or other times. This quirk makes sure that's the case for
5921 * affected systems.
5922 */
5923 static void quirk_pipea_force (struct drm_device *dev)
5924 {
5925 struct drm_i915_private *dev_priv = dev->dev_private;
5926
5927 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5928 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5929 }
5930
5931 struct intel_quirk {
5932 int device;
5933 int subsystem_vendor;
5934 int subsystem_device;
5935 void (*hook)(struct drm_device *dev);
5936 };
5937
5938 struct intel_quirk intel_quirks[] = {
5939 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5940 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5941 /* HP Mini needs pipe A force quirk (LP: #322104) */
5942 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5943
5944 /* Thinkpad R31 needs pipe A force quirk */
5945 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5946 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5947 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5948
5949 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5950 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
5951 /* ThinkPad X40 needs pipe A force quirk */
5952
5953 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5954 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5955
5956 /* 855 & before need to leave pipe A & dpll A up */
5957 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5958 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5959 };
5960
5961 static void intel_init_quirks(struct drm_device *dev)
5962 {
5963 struct pci_dev *d = dev->pdev;
5964 int i;
5965
5966 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5967 struct intel_quirk *q = &intel_quirks[i];
5968
5969 if (d->device == q->device &&
5970 (d->subsystem_vendor == q->subsystem_vendor ||
5971 q->subsystem_vendor == PCI_ANY_ID) &&
5972 (d->subsystem_device == q->subsystem_device ||
5973 q->subsystem_device == PCI_ANY_ID))
5974 q->hook(dev);
5975 }
5976 }
5977
5978 void intel_modeset_init(struct drm_device *dev)
5979 {
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 int i;
5982
5983 drm_mode_config_init(dev);
5984
5985 dev->mode_config.min_width = 0;
5986 dev->mode_config.min_height = 0;
5987
5988 dev->mode_config.funcs = (void *)&intel_mode_funcs;
5989
5990 intel_init_quirks(dev);
5991
5992 intel_init_display(dev);
5993
5994 if (IS_I965G(dev)) {
5995 dev->mode_config.max_width = 8192;
5996 dev->mode_config.max_height = 8192;
5997 } else if (IS_I9XX(dev)) {
5998 dev->mode_config.max_width = 4096;
5999 dev->mode_config.max_height = 4096;
6000 } else {
6001 dev->mode_config.max_width = 2048;
6002 dev->mode_config.max_height = 2048;
6003 }
6004
6005 /* set memory base */
6006 if (IS_I9XX(dev))
6007 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6008 else
6009 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6010
6011 if (IS_MOBILE(dev) || IS_I9XX(dev))
6012 dev_priv->num_pipe = 2;
6013 else
6014 dev_priv->num_pipe = 1;
6015 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6016 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6017
6018 for (i = 0; i < dev_priv->num_pipe; i++) {
6019 intel_crtc_init(dev, i);
6020 }
6021
6022 intel_setup_outputs(dev);
6023
6024 intel_init_clock_gating(dev);
6025
6026 if (IS_IRONLAKE_M(dev)) {
6027 ironlake_enable_drps(dev);
6028 intel_init_emon(dev);
6029 }
6030
6031 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6032 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6033 (unsigned long)dev);
6034
6035 intel_setup_overlay(dev);
6036 }
6037
6038 void intel_modeset_cleanup(struct drm_device *dev)
6039 {
6040 struct drm_i915_private *dev_priv = dev->dev_private;
6041 struct drm_crtc *crtc;
6042 struct intel_crtc *intel_crtc;
6043
6044 mutex_lock(&dev->struct_mutex);
6045
6046 drm_kms_helper_poll_fini(dev);
6047 intel_fbdev_fini(dev);
6048
6049 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6050 /* Skip inactive CRTCs */
6051 if (!crtc->fb)
6052 continue;
6053
6054 intel_crtc = to_intel_crtc(crtc);
6055 intel_increase_pllclock(crtc, false);
6056 del_timer_sync(&intel_crtc->idle_timer);
6057 }
6058
6059 del_timer_sync(&dev_priv->idle_timer);
6060
6061 if (dev_priv->display.disable_fbc)
6062 dev_priv->display.disable_fbc(dev);
6063
6064 if (dev_priv->pwrctx) {
6065 struct drm_i915_gem_object *obj_priv;
6066
6067 obj_priv = to_intel_bo(dev_priv->pwrctx);
6068 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6069 I915_READ(PWRCTXA);
6070 i915_gem_object_unpin(dev_priv->pwrctx);
6071 drm_gem_object_unreference(dev_priv->pwrctx);
6072 }
6073
6074 if (IS_IRONLAKE_M(dev))
6075 ironlake_disable_drps(dev);
6076
6077 mutex_unlock(&dev->struct_mutex);
6078
6079 drm_mode_config_cleanup(dev);
6080 }
6081
6082
6083 /*
6084 * Return which encoder is currently attached for connector.
6085 */
6086 struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
6087 {
6088 struct drm_mode_object *obj;
6089 struct drm_encoder *encoder;
6090 int i;
6091
6092 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
6093 if (connector->encoder_ids[i] == 0)
6094 break;
6095
6096 obj = drm_mode_object_find(connector->dev,
6097 connector->encoder_ids[i],
6098 DRM_MODE_OBJECT_ENCODER);
6099 if (!obj)
6100 continue;
6101
6102 encoder = obj_to_encoder(obj);
6103 return encoder;
6104 }
6105 return NULL;
6106 }
6107
6108 /*
6109 * set vga decode state - true == enable VGA decode
6110 */
6111 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6112 {
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114 u16 gmch_ctrl;
6115
6116 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6117 if (state)
6118 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6119 else
6120 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6121 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6122 return 0;
6123 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree