include/asm-arm/io.h

   1 /*
   2  *  linux/include/asm-arm/io.h
   3  *
   4  *  Copyright (C) 1996-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Modifications:
  11  *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12  *                      constant addresses and variable addresses.
  13  *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14  *                      specific IO header files.
  15  *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16  *  04-Apr-1999 PJB     Added check_signature.
  17  *  12-Dec-1999 RMK     More cleanups
  18  *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19  *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20  */
  21 #ifndef __ASM_ARM_IO_H
  22 #define __ASM_ARM_IO_H
  23
  24 #ifdef __KERNEL__
  25
  26 #include <linux/types.h>
  27 #include <asm/byteorder.h>
  28 #include <asm/memory.h>
  29
  30 /*
  31  * ISA I/O bus memory addresses are 1:1 with the physical address.
  32  */
  33 #define isa_virt_to_bus virt_to_phys
  34 #define isa_page_to_bus page_to_phys
  35 #define isa_bus_to_virt phys_to_virt
  36
  37 /*
  38  * Generic IO read/write.  These perform native-endian accesses.  Note
  39  * that some architectures will want to re-define __raw_{read,write}w.
  40  */
  41 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  42 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  43 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  44
  45 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  46 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  47 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  48
  49 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
  50 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
  51 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))
  52
  53 #define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
  54 #define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  55 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
  56
  57 /*
  58  * Architecture ioremap implementation.
  59  *
  60  * __ioremap takes CPU physical address.
  61  *
  62  * __ioremap_pfn takes a Page Frame Number and an offset into that page
  63  */
  64 extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
  65 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
  66 extern void __iounmap(void __iomem *addr);
  67
  68 /*
  69  * Bad read/write accesses...
  70  */
  71 extern void __readwrite_bug(const char *fn);
  72
  73 /*
  74  * Now, pick up the machine-defined IO definitions
  75  */
  76 #include <asm/arch/io.h>
  77
  78 #ifdef __io_pci
  79 #warning machine class uses buggy __io_pci
  80 #endif
  81 #if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
  82     defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
  83 #warning machine class uses old __arch_putw or __arch_getw
  84 #endif
  85
  86 /*
  87  *  IO port access primitives
  88  *  -------------------------
  89  *
  90  * The ARM doesn't have special IO access instructions; all IO is memory
  91  * mapped.  Note that these are defined to perform little endian accesses
  92  * only.  Their primary purpose is to access PCI and ISA peripherals.
  93  *
  94  * Note that for a big endian machine, this implies that the following
  95  * big endian mode connectivity is in place, as described by numerous
  96  * ARM documents:
  97  *
  98  *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
  99  *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 100  *
 101  * The machine specific io.h include defines __io to translate an "IO"
 102  * address to a memory address.
 103  *
 104  * Note that we prevent GCC re-ordering or caching values in expressions
 105  * by introducing sequence points into the in*() definitions.  Note that
 106  * __raw_* do not guarantee this behaviour.
 107  *
 108  * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 109  */
 110 #ifdef __io
 111 #define outb(v,p)               __raw_writeb(v,__io(p))
 112 #define outw(v,p)               __raw_writew((__force __u16) \
 113                                         cpu_to_le16(v),__io(p))
 114 #define outl(v,p)               __raw_writel((__force __u32) \
 115                                         cpu_to_le32(v),__io(p))
 116
 117 #define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __v; })
 118 #define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 119                         __raw_readw(__io(p))); __v; })
 120 #define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 121                         __raw_readl(__io(p))); __v; })
 122
 123 #define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 124 #define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 125 #define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 126
 127 #define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 128 #define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 129 #define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 130 #endif
 131
 132 #define outb_p(val,port)        outb((val),(port))
 133 #define outw_p(val,port)        outw((val),(port))
 134 #define outl_p(val,port)        outl((val),(port))
 135 #define inb_p(port)             inb((port))
 136 #define inw_p(port)             inw((port))
 137 #define inl_p(port)             inl((port))
 138
 139 #define outsb_p(port,from,len)  outsb(port,from,len)
 140 #define outsw_p(port,from,len)  outsw(port,from,len)
 141 #define outsl_p(port,from,len)  outsl(port,from,len)
 142 #define insb_p(port,to,len)     insb(port,to,len)
 143 #define insw_p(port,to,len)     insw(port,to,len)
 144 #define insl_p(port,to,len)     insl(port,to,len)
 145
 146 /*
 147  * String version of IO memory access ops:
 148  */
 149 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 150 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 151 extern void _memset_io(volatile void __iomem *, int, size_t);
 152
 153 #define mmiowb()
 154
 155 /*
 156  *  Memory access primitives
 157  *  ------------------------
 158  *
 159  * These perform PCI memory accesses via an ioremap region.  They don't
 160  * take an address as such, but a cookie.
 161  *
 162  * Again, this are defined to perform little endian accesses.  See the
 163  * IO port primitives for more information.
 164  */
 165 #ifdef __mem_pci
 166 #define readb(c) ({ __u8  __v = __raw_readb(__mem_pci(c)); __v; })
 167 #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
 168                                         __raw_readw(__mem_pci(c))); __v; })
 169 #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
 170                                         __raw_readl(__mem_pci(c))); __v; })
 171 #define readb_relaxed(addr) readb(addr)
 172 #define readw_relaxed(addr) readw(addr)
 173 #define readl_relaxed(addr) readl(addr)
 174
 175 #define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
 176 #define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
 177 #define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
 178
 179 #define writeb(v,c)             __raw_writeb(v,__mem_pci(c))
 180 #define writew(v,c)             __raw_writew((__force __u16) \
 181                                         cpu_to_le16(v),__mem_pci(c))
 182 #define writel(v,c)             __raw_writel((__force __u32) \
 183                                         cpu_to_le32(v),__mem_pci(c))
 184
 185 #define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
 186 #define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
 187 #define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
 188
 189 #define memset_io(c,v,l)        _memset_io(__mem_pci(c),(v),(l))
 190 #define memcpy_fromio(a,c,l)    _memcpy_fromio((a),__mem_pci(c),(l))
 191 #define memcpy_toio(c,a,l)      _memcpy_toio(__mem_pci(c),(a),(l))
 192
 193 #define eth_io_copy_and_sum(s,c,l,b) \
 194                                 eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 195
 196 static inline int
 197 check_signature(void __iomem *io_addr, const unsigned char *signature,
 198                 int length)
 199 {
 200         int retval = 0;
 201         do {
 202                 if (readb(io_addr) != *signature)
 203                         goto out;
 204                 io_addr++;
 205                 signature++;
 206                 length--;
 207         } while (length);
 208         retval = 1;
 209 out:
 210         return retval;
 211 }
 212
 213 #elif !defined(readb)
 214
 215 #define readb(c)                        (__readwrite_bug("readb"),0)
 216 #define readw(c)                        (__readwrite_bug("readw"),0)
 217 #define readl(c)                        (__readwrite_bug("readl"),0)
 218 #define writeb(v,c)                     __readwrite_bug("writeb")
 219 #define writew(v,c)                     __readwrite_bug("writew")
 220 #define writel(v,c)                     __readwrite_bug("writel")
 221
 222 #define eth_io_copy_and_sum(s,c,l,b)    __readwrite_bug("eth_io_copy_and_sum")
 223
 224 #define check_signature(io,sig,len)     (0)
 225
 226 #endif  /* __mem_pci */
 227
 228 /*
 229  * If this architecture has ISA IO, then define the isa_read/isa_write
 230  * macros.
 231  */
 232 #ifdef __mem_isa
 233
 234 #define isa_readb(addr)                 __raw_readb(__mem_isa(addr))
 235 #define isa_readw(addr)                 __raw_readw(__mem_isa(addr))
 236 #define isa_readl(addr)                 __raw_readl(__mem_isa(addr))
 237 #define isa_writeb(val,addr)            __raw_writeb(val,__mem_isa(addr))
 238 #define isa_writew(val,addr)            __raw_writew(val,__mem_isa(addr))
 239 #define isa_writel(val,addr)            __raw_writel(val,__mem_isa(addr))
 240 #define isa_memset_io(a,b,c)            _memset_io(__mem_isa(a),(b),(c))
 241 #define isa_memcpy_fromio(a,b,c)        _memcpy_fromio((a),__mem_isa(b),(c))
 242 #define isa_memcpy_toio(a,b,c)          _memcpy_toio(__mem_isa((a)),(b),(c))
 243
 244 #define isa_eth_io_copy_and_sum(a,b,c,d) \
 245                                 eth_copy_and_sum((a),__mem_isa(b),(c),(d))
 246
 247 #else   /* __mem_isa */
 248
 249 #define isa_readb(addr)                 (__readwrite_bug("isa_readb"),0)
 250 #define isa_readw(addr)                 (__readwrite_bug("isa_readw"),0)
 251 #define isa_readl(addr)                 (__readwrite_bug("isa_readl"),0)
 252 #define isa_writeb(val,addr)            __readwrite_bug("isa_writeb")
 253 #define isa_writew(val,addr)            __readwrite_bug("isa_writew")
 254 #define isa_writel(val,addr)            __readwrite_bug("isa_writel")
 255 #define isa_memset_io(a,b,c)            __readwrite_bug("isa_memset_io")
 256 #define isa_memcpy_fromio(a,b,c)        __readwrite_bug("isa_memcpy_fromio")
 257 #define isa_memcpy_toio(a,b,c)          __readwrite_bug("isa_memcpy_toio")
 258
 259 #define isa_eth_io_copy_and_sum(a,b,c,d) \
 260                                 __readwrite_bug("isa_eth_io_copy_and_sum")
 261
 262 #endif  /* __mem_isa */
 263
 264 /*
 265  * ioremap and friends.
 266  *
 267  * ioremap takes a PCI memory address, as specified in
 268  * Documentation/IO-mapping.txt.
 269  *
 270  */
 271 #ifndef __arch_ioremap
 272 #define ioremap(cookie,size)            __ioremap(cookie,size,0)
 273 #define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0)
 274 #define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE)
 275 #define iounmap(cookie)                 __iounmap(cookie)
 276 #else
 277 #define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0)
 278 #define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0)
 279 #define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
 280 #define iounmap(cookie)                 __arch_iounmap(cookie)
 281 #endif
 282
 283 /*
 284  * io{read,write}{8,16,32} macros
 285  */
 286 #ifndef ioread8
 287 #define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __v; })
 288 #define ioread16(p)     ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
 289 #define ioread32(p)     ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
 290
 291 #define iowrite8(v,p)   __raw_writeb(v, p)
 292 #define iowrite16(v,p)  __raw_writew(cpu_to_le16(v), p)
 293 #define iowrite32(v,p)  __raw_writel(cpu_to_le32(v), p)
 294
 295 #define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 296 #define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 297 #define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 298
 299 #define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 300 #define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 301 #define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 302
 303 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 304 extern void ioport_unmap(void __iomem *addr);
 305 #endif
 306
 307 struct pci_dev;
 308
 309 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 310 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 311
 312 /*
 313  * can the hardware map this into one segment or not, given no other
 314  * constraints.
 315  */
 316 #define BIOVEC_MERGEABLE(vec1, vec2)    \
 317         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 318
 319 /*
 320  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 321  * access
 322  */
 323 #define xlate_dev_mem_ptr(p)    __va(p)
 324
 325 /*
 326  * Convert a virtual cached pointer to an uncached pointer
 327  */
 328 #define xlate_dev_kmem_ptr(p)   p
 329
 330 #endif  /* __KERNEL__ */
 331 #endif  /* __ASM_ARM_IO_H */