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drm/i915: don't write TU size to N1 reg
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_display.c
blob358c30127f1ab8ef1d052571a6fcc94c560afe8e
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static const intel_limit_t intel_limits_i8xx_dvo = {
346 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
347 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
348 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
349 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
350 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
351 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
352 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
353 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
354 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
355 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
356 .find_pll = intel_find_best_PLL,
357 };
358
359 static const intel_limit_t intel_limits_i8xx_lvds = {
360 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
361 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
362 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
363 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
364 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
365 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
366 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
367 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
368 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
369 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
370 .find_pll = intel_find_best_PLL,
371 };
372
373 static const intel_limit_t intel_limits_i9xx_sdvo = {
374 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
375 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
376 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
377 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
378 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
379 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
380 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
381 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
382 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
383 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
384 .find_pll = intel_find_best_PLL,
385 };
386
387 static const intel_limit_t intel_limits_i9xx_lvds = {
388 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
389 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
390 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
391 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
392 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
393 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
394 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
395 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
396 /* The single-channel range is 25-112Mhz, and dual-channel
397 * is 80-224Mhz. Prefer single channel as much as possible.
398 */
399 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
400 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
401 .find_pll = intel_find_best_PLL,
402 };
403
404 /* below parameter and function is for G4X Chipset Family*/
405 static const intel_limit_t intel_limits_g4x_sdvo = {
406 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
407 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
408 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
409 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
410 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
411 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
412 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
413 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
414 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
415 .p2_slow = G4X_P2_SDVO_SLOW,
416 .p2_fast = G4X_P2_SDVO_FAST
417 },
418 .find_pll = intel_g4x_find_best_PLL,
419 };
420
421 static const intel_limit_t intel_limits_g4x_hdmi = {
422 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
423 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
424 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
425 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
426 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
427 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
428 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
429 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
430 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
431 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
432 .p2_fast = G4X_P2_HDMI_DAC_FAST
433 },
434 .find_pll = intel_g4x_find_best_PLL,
435 };
436
437 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
438 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
440 .vco = { .min = G4X_VCO_MIN,
441 .max = G4X_VCO_MAX },
442 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
444 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
446 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
448 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
450 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
451 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
452 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
454 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
455 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
456 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 },
458 .find_pll = intel_g4x_find_best_PLL,
459 };
460
461 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
462 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
464 .vco = { .min = G4X_VCO_MIN,
465 .max = G4X_VCO_MAX },
466 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
468 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
470 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
472 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
474 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
475 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
476 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
478 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
479 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
480 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 },
482 .find_pll = intel_g4x_find_best_PLL,
483 };
484
485 static const intel_limit_t intel_limits_g4x_display_port = {
486 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
487 .max = G4X_DOT_DISPLAY_PORT_MAX },
488 .vco = { .min = G4X_VCO_MIN,
489 .max = G4X_VCO_MAX},
490 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
491 .max = G4X_N_DISPLAY_PORT_MAX },
492 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
493 .max = G4X_M_DISPLAY_PORT_MAX },
494 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
495 .max = G4X_M1_DISPLAY_PORT_MAX },
496 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
497 .max = G4X_M2_DISPLAY_PORT_MAX },
498 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
499 .max = G4X_P_DISPLAY_PORT_MAX },
500 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
501 .max = G4X_P1_DISPLAY_PORT_MAX},
502 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
503 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
504 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
505 .find_pll = intel_find_pll_g4x_dp,
506 };
507
508 static const intel_limit_t intel_limits_pineview_sdvo = {
509 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
510 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
511 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
512 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
513 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
514 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
515 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
516 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
517 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
518 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
519 .find_pll = intel_find_best_PLL,
520 };
521
522 static const intel_limit_t intel_limits_pineview_lvds = {
523 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
524 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
525 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
526 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
527 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
528 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
529 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
530 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
531 /* Pineview only supports single-channel mode. */
532 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
533 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
534 .find_pll = intel_find_best_PLL,
535 };
536
537 static const intel_limit_t intel_limits_ironlake_dac = {
538 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
539 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
540 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
541 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
542 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
543 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
544 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
545 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
546 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
547 .p2_slow = IRONLAKE_DAC_P2_SLOW,
548 .p2_fast = IRONLAKE_DAC_P2_FAST },
549 .find_pll = intel_g4x_find_best_PLL,
550 };
551
552 static const intel_limit_t intel_limits_ironlake_single_lvds = {
553 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
554 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
555 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
556 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
557 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
558 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
559 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
560 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
561 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
562 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
563 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
564 .find_pll = intel_g4x_find_best_PLL,
565 };
566
567 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
568 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
569 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
570 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
571 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
572 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
573 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
574 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
575 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
576 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
577 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
578 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
579 .find_pll = intel_g4x_find_best_PLL,
580 };
581
582 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
583 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
584 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
585 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
586 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
587 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
588 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
589 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
590 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
591 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
592 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
593 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
594 .find_pll = intel_g4x_find_best_PLL,
595 };
596
597 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
598 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
599 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
600 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
601 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
602 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
603 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
604 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
605 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
606 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
607 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
608 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
609 .find_pll = intel_g4x_find_best_PLL,
610 };
611
612 static const intel_limit_t intel_limits_ironlake_display_port = {
613 .dot = { .min = IRONLAKE_DOT_MIN,
614 .max = IRONLAKE_DOT_MAX },
615 .vco = { .min = IRONLAKE_VCO_MIN,
616 .max = IRONLAKE_VCO_MAX},
617 .n = { .min = IRONLAKE_DP_N_MIN,
618 .max = IRONLAKE_DP_N_MAX },
619 .m = { .min = IRONLAKE_DP_M_MIN,
620 .max = IRONLAKE_DP_M_MAX },
621 .m1 = { .min = IRONLAKE_M1_MIN,
622 .max = IRONLAKE_M1_MAX },
623 .m2 = { .min = IRONLAKE_M2_MIN,
624 .max = IRONLAKE_M2_MAX },
625 .p = { .min = IRONLAKE_DP_P_MIN,
626 .max = IRONLAKE_DP_P_MAX },
627 .p1 = { .min = IRONLAKE_DP_P1_MIN,
628 .max = IRONLAKE_DP_P1_MAX},
629 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
630 .p2_slow = IRONLAKE_DP_P2_SLOW,
631 .p2_fast = IRONLAKE_DP_P2_FAST },
632 .find_pll = intel_find_pll_ironlake_dp,
633 };
634
635 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 const intel_limit_t *limit;
640 int refclk = 120;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
643 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
644 refclk = 100;
645
646 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
647 LVDS_CLKB_POWER_UP) {
648 /* LVDS dual channel */
649 if (refclk == 100)
650 limit = &intel_limits_ironlake_dual_lvds_100m;
651 else
652 limit = &intel_limits_ironlake_dual_lvds;
653 } else {
654 if (refclk == 100)
655 limit = &intel_limits_ironlake_single_lvds_100m;
656 else
657 limit = &intel_limits_ironlake_single_lvds;
658 }
659 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
660 HAS_eDP)
661 limit = &intel_limits_ironlake_display_port;
662 else
663 limit = &intel_limits_ironlake_dac;
664
665 return limit;
666 }
667
668 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
669 {
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 const intel_limit_t *limit;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
676 LVDS_CLKB_POWER_UP)
677 /* LVDS with dual channel */
678 limit = &intel_limits_g4x_dual_channel_lvds;
679 else
680 /* LVDS with dual channel */
681 limit = &intel_limits_g4x_single_channel_lvds;
682 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
683 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
684 limit = &intel_limits_g4x_hdmi;
685 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
686 limit = &intel_limits_g4x_sdvo;
687 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
688 limit = &intel_limits_g4x_display_port;
689 } else /* The option is for other outputs */
690 limit = &intel_limits_i9xx_sdvo;
691
692 return limit;
693 }
694
695 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
696 {
697 struct drm_device *dev = crtc->dev;
698 const intel_limit_t *limit;
699
700 if (HAS_PCH_SPLIT(dev))
701 limit = intel_ironlake_limit(crtc);
702 else if (IS_G4X(dev)) {
703 limit = intel_g4x_limit(crtc);
704 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
705 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
706 limit = &intel_limits_i9xx_lvds;
707 else
708 limit = &intel_limits_i9xx_sdvo;
709 } else if (IS_PINEVIEW(dev)) {
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
711 limit = &intel_limits_pineview_lvds;
712 else
713 limit = &intel_limits_pineview_sdvo;
714 } else {
715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
716 limit = &intel_limits_i8xx_lvds;
717 else
718 limit = &intel_limits_i8xx_dvo;
719 }
720 return limit;
721 }
722
723 /* m1 is reserved as 0 in Pineview, n is a ring counter */
724 static void pineview_clock(int refclk, intel_clock_t *clock)
725 {
726 clock->m = clock->m2 + 2;
727 clock->p = clock->p1 * clock->p2;
728 clock->vco = refclk * clock->m / clock->n;
729 clock->dot = clock->vco / clock->p;
730 }
731
732 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
733 {
734 if (IS_PINEVIEW(dev)) {
735 pineview_clock(refclk, clock);
736 return;
737 }
738 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
739 clock->p = clock->p1 * clock->p2;
740 clock->vco = refclk * clock->m / (clock->n + 2);
741 clock->dot = clock->vco / clock->p;
742 }
743
744 /**
745 * Returns whether any output on the specified pipe is of the specified type
746 */
747 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
748 {
749 struct drm_device *dev = crtc->dev;
750 struct drm_mode_config *mode_config = &dev->mode_config;
751 struct intel_encoder *encoder;
752
753 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
754 if (encoder->base.crtc == crtc && encoder->type == type)
755 return true;
756
757 return false;
758 }
759
760 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
761 /**
762 * Returns whether the given set of divisors are valid for a given refclk with
763 * the given connectors.
764 */
765
766 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
767 {
768 const intel_limit_t *limit = intel_limit (crtc);
769 struct drm_device *dev = crtc->dev;
770
771 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
772 INTELPllInvalid ("p1 out of range\n");
773 if (clock->p < limit->p.min || limit->p.max < clock->p)
774 INTELPllInvalid ("p out of range\n");
775 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
776 INTELPllInvalid ("m2 out of range\n");
777 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
778 INTELPllInvalid ("m1 out of range\n");
779 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
780 INTELPllInvalid ("m1 <= m2\n");
781 if (clock->m < limit->m.min || limit->m.max < clock->m)
782 INTELPllInvalid ("m out of range\n");
783 if (clock->n < limit->n.min || limit->n.max < clock->n)
784 INTELPllInvalid ("n out of range\n");
785 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
786 INTELPllInvalid ("vco out of range\n");
787 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
788 * connector, etc., rather than just a single range.
789 */
790 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
791 INTELPllInvalid ("dot out of range\n");
792
793 return true;
794 }
795
796 static bool
797 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
798 int target, int refclk, intel_clock_t *best_clock)
799
800 {
801 struct drm_device *dev = crtc->dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 intel_clock_t clock;
804 int err = target;
805
806 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
807 (I915_READ(LVDS)) != 0) {
808 /*
809 * For LVDS, if the panel is on, just rely on its current
810 * settings for dual-channel. We haven't figured out how to
811 * reliably set up different single/dual channel state, if we
812 * even can.
813 */
814 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
815 LVDS_CLKB_POWER_UP)
816 clock.p2 = limit->p2.p2_fast;
817 else
818 clock.p2 = limit->p2.p2_slow;
819 } else {
820 if (target < limit->p2.dot_limit)
821 clock.p2 = limit->p2.p2_slow;
822 else
823 clock.p2 = limit->p2.p2_fast;
824 }
825
826 memset (best_clock, 0, sizeof (*best_clock));
827
828 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
829 clock.m1++) {
830 for (clock.m2 = limit->m2.min;
831 clock.m2 <= limit->m2.max; clock.m2++) {
832 /* m1 is always 0 in Pineview */
833 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
834 break;
835 for (clock.n = limit->n.min;
836 clock.n <= limit->n.max; clock.n++) {
837 for (clock.p1 = limit->p1.min;
838 clock.p1 <= limit->p1.max; clock.p1++) {
839 int this_err;
840
841 intel_clock(dev, refclk, &clock);
842
843 if (!intel_PLL_is_valid(crtc, &clock))
844 continue;
845
846 this_err = abs(clock.dot - target);
847 if (this_err < err) {
848 *best_clock = clock;
849 err = this_err;
850 }
851 }
852 }
853 }
854 }
855
856 return (err != target);
857 }
858
859 static bool
860 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
861 int target, int refclk, intel_clock_t *best_clock)
862 {
863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870 found = false;
871
872 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
873 int lvds_reg;
874
875 if (HAS_PCH_SPLIT(dev))
876 lvds_reg = PCH_LVDS;
877 else
878 lvds_reg = LVDS;
879 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
880 LVDS_CLKB_POWER_UP)
881 clock.p2 = limit->p2.p2_fast;
882 else
883 clock.p2 = limit->p2.p2_slow;
884 } else {
885 if (target < limit->p2.dot_limit)
886 clock.p2 = limit->p2.p2_slow;
887 else
888 clock.p2 = limit->p2.p2_fast;
889 }
890
891 memset(best_clock, 0, sizeof(*best_clock));
892 max_n = limit->n.max;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
895 /* based on hardware requirement, prefere larger m1,m2 */
896 for (clock.m1 = limit->m1.max;
897 clock.m1 >= limit->m1.min; clock.m1--) {
898 for (clock.m2 = limit->m2.max;
899 clock.m2 >= limit->m2.min; clock.m2--) {
900 for (clock.p1 = limit->p1.max;
901 clock.p1 >= limit->p1.min; clock.p1--) {
902 int this_err;
903
904 intel_clock(dev, refclk, &clock);
905 if (!intel_PLL_is_valid(crtc, &clock))
906 continue;
907 this_err = abs(clock.dot - target) ;
908 if (this_err < err_most) {
909 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 }
914 }
915 }
916 }
917 }
918 return found;
919 }
920
921 static bool
922 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
923 int target, int refclk, intel_clock_t *best_clock)
924 {
925 struct drm_device *dev = crtc->dev;
926 intel_clock_t clock;
927
928 /* return directly when it is eDP */
929 if (HAS_eDP)
930 return true;
931
932 if (target < 200000) {
933 clock.n = 1;
934 clock.p1 = 2;
935 clock.p2 = 10;
936 clock.m1 = 12;
937 clock.m2 = 9;
938 } else {
939 clock.n = 2;
940 clock.p1 = 1;
941 clock.p2 = 10;
942 clock.m1 = 14;
943 clock.m2 = 8;
944 }
945 intel_clock(dev, refclk, &clock);
946 memcpy(best_clock, &clock, sizeof(intel_clock_t));
947 return true;
948 }
949
950 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
951 static bool
952 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
953 int target, int refclk, intel_clock_t *best_clock)
954 {
955 intel_clock_t clock;
956 if (target < 200000) {
957 clock.p1 = 2;
958 clock.p2 = 10;
959 clock.n = 2;
960 clock.m1 = 23;
961 clock.m2 = 8;
962 } else {
963 clock.p1 = 1;
964 clock.p2 = 10;
965 clock.n = 1;
966 clock.m1 = 14;
967 clock.m2 = 2;
968 }
969 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
970 clock.p = (clock.p1 * clock.p2);
971 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
972 clock.vco = 0;
973 memcpy(best_clock, &clock, sizeof(intel_clock_t));
974 return true;
975 }
976
977 /**
978 * intel_wait_for_vblank - wait for vblank on a given pipe
979 * @dev: drm device
980 * @pipe: pipe to wait for
981 *
982 * Wait for vblank to occur on a given pipe. Needed for various bits of
983 * mode setting code.
984 */
985 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
986 {
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
989
990 /* Clear existing vblank status. Note this will clear any other
991 * sticky status fields as well.
992 *
993 * This races with i915_driver_irq_handler() with the result
994 * that either function could miss a vblank event. Here it is not
995 * fatal, as we will either wait upon the next vblank interrupt or
996 * timeout. Generally speaking intel_wait_for_vblank() is only
997 * called during modeset at which time the GPU should be idle and
998 * should *not* be performing page flips and thus not waiting on
999 * vblanks...
1000 * Currently, the result of us stealing a vblank from the irq
1001 * handler is that a single frame will be skipped during swapbuffers.
1002 */
1003 I915_WRITE(pipestat_reg,
1004 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1005
1006 /* Wait for vblank interrupt bit to set */
1007 if (wait_for(I915_READ(pipestat_reg) &
1008 PIPE_VBLANK_INTERRUPT_STATUS,
1009 50))
1010 DRM_DEBUG_KMS("vblank wait timed out\n");
1011 }
1012
1013 /**
1014 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1015 * @dev: drm device
1016 * @pipe: pipe to wait for
1017 *
1018 * After disabling a pipe, we can't wait for vblank in the usual way,
1019 * spinning on the vblank interrupt status bit, since we won't actually
1020 * see an interrupt when the pipe is disabled.
1021 *
1022 * So this function waits for the display line value to settle (it
1023 * usually ends up stopping at the start of the next frame).
1024 */
1025 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1026 {
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1029 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1030 u32 last_line;
1031
1032 /* Wait for the display line to settle */
1033 do {
1034 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1035 mdelay(5);
1036 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1037 time_after(timeout, jiffies));
1038
1039 if (time_after(jiffies, timeout))
1040 DRM_DEBUG_KMS("vblank wait timed out\n");
1041 }
1042
1043 /* Parameters have changed, update FBC info */
1044 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1045 {
1046 struct drm_device *dev = crtc->dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 struct drm_framebuffer *fb = crtc->fb;
1049 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1050 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1052 int plane, i;
1053 u32 fbc_ctl, fbc_ctl2;
1054
1055 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1056
1057 if (fb->pitch < dev_priv->cfb_pitch)
1058 dev_priv->cfb_pitch = fb->pitch;
1059
1060 /* FBC_CTL wants 64B units */
1061 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1062 dev_priv->cfb_fence = obj_priv->fence_reg;
1063 dev_priv->cfb_plane = intel_crtc->plane;
1064 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1065
1066 /* Clear old tags */
1067 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1068 I915_WRITE(FBC_TAG + (i * 4), 0);
1069
1070 /* Set it up... */
1071 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1072 if (obj_priv->tiling_mode != I915_TILING_NONE)
1073 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1074 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1075 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1076
1077 /* enable it... */
1078 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1079 if (IS_I945GM(dev))
1080 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1081 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1082 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1083 if (obj_priv->tiling_mode != I915_TILING_NONE)
1084 fbc_ctl |= dev_priv->cfb_fence;
1085 I915_WRITE(FBC_CONTROL, fbc_ctl);
1086
1087 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1088 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1089 }
1090
1091 void i8xx_disable_fbc(struct drm_device *dev)
1092 {
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1094 u32 fbc_ctl;
1095
1096 if (!I915_HAS_FBC(dev))
1097 return;
1098
1099 if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
1100 return; /* Already off, just return */
1101
1102 /* Disable compression */
1103 fbc_ctl = I915_READ(FBC_CONTROL);
1104 fbc_ctl &= ~FBC_CTL_EN;
1105 I915_WRITE(FBC_CONTROL, fbc_ctl);
1106
1107 /* Wait for compressing bit to clear */
1108 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1109 DRM_DEBUG_KMS("FBC idle timed out\n");
1110 return;
1111 }
1112
1113 DRM_DEBUG_KMS("disabled FBC\n");
1114 }
1115
1116 static bool i8xx_fbc_enabled(struct drm_device *dev)
1117 {
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1121 }
1122
1123 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1124 {
1125 struct drm_device *dev = crtc->dev;
1126 struct drm_i915_private *dev_priv = dev->dev_private;
1127 struct drm_framebuffer *fb = crtc->fb;
1128 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1129 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1131 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1132 DPFC_CTL_PLANEB);
1133 unsigned long stall_watermark = 200;
1134 u32 dpfc_ctl;
1135
1136 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1137 dev_priv->cfb_fence = obj_priv->fence_reg;
1138 dev_priv->cfb_plane = intel_crtc->plane;
1139
1140 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1141 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1142 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1143 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1144 } else {
1145 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1146 }
1147
1148 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1149 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1150 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1151 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1152 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1153
1154 /* enable it... */
1155 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1156
1157 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1158 }
1159
1160 void g4x_disable_fbc(struct drm_device *dev)
1161 {
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 u32 dpfc_ctl;
1164
1165 /* Disable compression */
1166 dpfc_ctl = I915_READ(DPFC_CONTROL);
1167 dpfc_ctl &= ~DPFC_CTL_EN;
1168 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1169
1170 DRM_DEBUG_KMS("disabled FBC\n");
1171 }
1172
1173 static bool g4x_fbc_enabled(struct drm_device *dev)
1174 {
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176
1177 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1178 }
1179
1180 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1181 {
1182 struct drm_device *dev = crtc->dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 struct drm_framebuffer *fb = crtc->fb;
1185 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1186 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188 int plane = (intel_crtc->plane == 0) ? DPFC_CTL_PLANEA :
1189 DPFC_CTL_PLANEB;
1190 unsigned long stall_watermark = 200;
1191 u32 dpfc_ctl;
1192
1193 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1194 dev_priv->cfb_fence = obj_priv->fence_reg;
1195 dev_priv->cfb_plane = intel_crtc->plane;
1196
1197 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1198 dpfc_ctl &= DPFC_RESERVED;
1199 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1200 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1201 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1202 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1203 } else {
1204 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1205 }
1206
1207 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1212 I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1213 /* enable it... */
1214 I915_WRITE(ILK_DPFC_CONTROL, I915_READ(ILK_DPFC_CONTROL) |
1215 DPFC_CTL_EN);
1216
1217 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1218 }
1219
1220 void ironlake_disable_fbc(struct drm_device *dev)
1221 {
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1223 u32 dpfc_ctl;
1224
1225 /* Disable compression */
1226 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1227 dpfc_ctl &= ~DPFC_CTL_EN;
1228 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1229
1230 DRM_DEBUG_KMS("disabled FBC\n");
1231 }
1232
1233 static bool ironlake_fbc_enabled(struct drm_device *dev)
1234 {
1235 struct drm_i915_private *dev_priv = dev->dev_private;
1236
1237 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1238 }
1239
1240 bool intel_fbc_enabled(struct drm_device *dev)
1241 {
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243
1244 if (!dev_priv->display.fbc_enabled)
1245 return false;
1246
1247 return dev_priv->display.fbc_enabled(dev);
1248 }
1249
1250 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1251 {
1252 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1253
1254 if (!dev_priv->display.enable_fbc)
1255 return;
1256
1257 dev_priv->display.enable_fbc(crtc, interval);
1258 }
1259
1260 void intel_disable_fbc(struct drm_device *dev)
1261 {
1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263
1264 if (!dev_priv->display.disable_fbc)
1265 return;
1266
1267 dev_priv->display.disable_fbc(dev);
1268 }
1269
1270 /**
1271 * intel_update_fbc - enable/disable FBC as needed
1272 * @crtc: CRTC to point the compressor at
1273 * @mode: mode in use
1274 *
1275 * Set up the framebuffer compression hardware at mode set time. We
1276 * enable it if possible:
1277 * - plane A only (on pre-965)
1278 * - no pixel mulitply/line duplication
1279 * - no alpha buffer discard
1280 * - no dual wide
1281 * - framebuffer <= 2048 in width, 1536 in height
1282 *
1283 * We can't assume that any compression will take place (worst case),
1284 * so the compressed buffer has to be the same size as the uncompressed
1285 * one. It also must reside (along with the line length buffer) in
1286 * stolen memory.
1287 *
1288 * We need to enable/disable FBC on a global basis.
1289 */
1290 static void intel_update_fbc(struct drm_crtc *crtc,
1291 struct drm_display_mode *mode)
1292 {
1293 struct drm_device *dev = crtc->dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 struct drm_framebuffer *fb = crtc->fb;
1296 struct intel_framebuffer *intel_fb;
1297 struct drm_i915_gem_object *obj_priv;
1298 struct drm_crtc *tmp_crtc;
1299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1300 int plane = intel_crtc->plane;
1301 int crtcs_enabled = 0;
1302
1303 DRM_DEBUG_KMS("\n");
1304
1305 if (!i915_powersave)
1306 return;
1307
1308 if (!I915_HAS_FBC(dev))
1309 return;
1310
1311 if (!crtc->fb)
1312 return;
1313
1314 intel_fb = to_intel_framebuffer(fb);
1315 obj_priv = to_intel_bo(intel_fb->obj);
1316
1317 /*
1318 * If FBC is already on, we just have to verify that we can
1319 * keep it that way...
1320 * Need to disable if:
1321 * - more than one pipe is active
1322 * - changing FBC params (stride, fence, mode)
1323 * - new fb is too large to fit in compressed buffer
1324 * - going to an unsupported config (interlace, pixel multiply, etc.)
1325 */
1326 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1327 if (tmp_crtc->enabled)
1328 crtcs_enabled++;
1329 }
1330 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
1331 if (crtcs_enabled > 1) {
1332 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1333 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1334 goto out_disable;
1335 }
1336 if (intel_fb->obj->size > dev_priv->cfb_size) {
1337 DRM_DEBUG_KMS("framebuffer too large, disabling "
1338 "compression\n");
1339 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1340 goto out_disable;
1341 }
1342 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1343 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1344 DRM_DEBUG_KMS("mode incompatible with compression, "
1345 "disabling\n");
1346 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1347 goto out_disable;
1348 }
1349 if ((mode->hdisplay > 2048) ||
1350 (mode->vdisplay > 1536)) {
1351 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1352 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1353 goto out_disable;
1354 }
1355 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1356 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1357 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1358 goto out_disable;
1359 }
1360 if (obj_priv->tiling_mode != I915_TILING_X) {
1361 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1362 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1363 goto out_disable;
1364 }
1365
1366 /* If the kernel debugger is active, always disable compression */
1367 if (in_dbg_master())
1368 goto out_disable;
1369
1370 if (intel_fbc_enabled(dev)) {
1371 /* We can re-enable it in this case, but need to update pitch */
1372 if ((fb->pitch > dev_priv->cfb_pitch) ||
1373 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1374 (plane != dev_priv->cfb_plane))
1375 intel_disable_fbc(dev);
1376 }
1377
1378 /* Now try to turn it back on if possible */
1379 if (!intel_fbc_enabled(dev))
1380 intel_enable_fbc(crtc, 500);
1381
1382 return;
1383
1384 out_disable:
1385 /* Multiple disables should be harmless */
1386 if (intel_fbc_enabled(dev)) {
1387 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1388 intel_disable_fbc(dev);
1389 }
1390 }
1391
1392 int
1393 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1394 {
1395 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1396 u32 alignment;
1397 int ret;
1398
1399 switch (obj_priv->tiling_mode) {
1400 case I915_TILING_NONE:
1401 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1402 alignment = 128 * 1024;
1403 else if (IS_I965G(dev))
1404 alignment = 4 * 1024;
1405 else
1406 alignment = 64 * 1024;
1407 break;
1408 case I915_TILING_X:
1409 /* pin() will align the object as required by fence */
1410 alignment = 0;
1411 break;
1412 case I915_TILING_Y:
1413 /* FIXME: Is this true? */
1414 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1415 return -EINVAL;
1416 default:
1417 BUG();
1418 }
1419
1420 ret = i915_gem_object_pin(obj, alignment);
1421 if (ret != 0)
1422 return ret;
1423
1424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1425 * fence, whereas 965+ only requires a fence if using
1426 * framebuffer compression. For simplicity, we always install
1427 * a fence as the cost is not that onerous.
1428 */
1429 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1430 obj_priv->tiling_mode != I915_TILING_NONE) {
1431 ret = i915_gem_object_get_fence_reg(obj);
1432 if (ret != 0) {
1433 i915_gem_object_unpin(obj);
1434 return ret;
1435 }
1436 }
1437
1438 return 0;
1439 }
1440
1441 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1442 static int
1443 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1444 int x, int y)
1445 {
1446 struct drm_device *dev = crtc->dev;
1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1449 struct intel_framebuffer *intel_fb;
1450 struct drm_i915_gem_object *obj_priv;
1451 struct drm_gem_object *obj;
1452 int plane = intel_crtc->plane;
1453 unsigned long Start, Offset;
1454 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1455 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1456 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1457 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1458 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1459 u32 dspcntr;
1460
1461 switch (plane) {
1462 case 0:
1463 case 1:
1464 break;
1465 default:
1466 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1467 return -EINVAL;
1468 }
1469
1470 intel_fb = to_intel_framebuffer(fb);
1471 obj = intel_fb->obj;
1472 obj_priv = to_intel_bo(obj);
1473
1474 dspcntr = I915_READ(dspcntr_reg);
1475 /* Mask out pixel format bits in case we change it */
1476 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1477 switch (fb->bits_per_pixel) {
1478 case 8:
1479 dspcntr |= DISPPLANE_8BPP;
1480 break;
1481 case 16:
1482 if (fb->depth == 15)
1483 dspcntr |= DISPPLANE_15_16BPP;
1484 else
1485 dspcntr |= DISPPLANE_16BPP;
1486 break;
1487 case 24:
1488 case 32:
1489 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1490 break;
1491 default:
1492 DRM_ERROR("Unknown color depth\n");
1493 return -EINVAL;
1494 }
1495 if (IS_I965G(dev)) {
1496 if (obj_priv->tiling_mode != I915_TILING_NONE)
1497 dspcntr |= DISPPLANE_TILED;
1498 else
1499 dspcntr &= ~DISPPLANE_TILED;
1500 }
1501
1502 if (HAS_PCH_SPLIT(dev))
1503 /* must disable */
1504 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1505
1506 I915_WRITE(dspcntr_reg, dspcntr);
1507
1508 Start = obj_priv->gtt_offset;
1509 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1510
1511 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1512 Start, Offset, x, y, fb->pitch);
1513 I915_WRITE(dspstride, fb->pitch);
1514 if (IS_I965G(dev)) {
1515 I915_WRITE(dspsurf, Start);
1516 I915_WRITE(dsptileoff, (y << 16) | x);
1517 I915_WRITE(dspbase, Offset);
1518 } else {
1519 I915_WRITE(dspbase, Start + Offset);
1520 }
1521 POSTING_READ(dspbase);
1522
1523 if (IS_I965G(dev) || plane == 0)
1524 intel_update_fbc(crtc, &crtc->mode);
1525
1526 intel_wait_for_vblank(dev, intel_crtc->pipe);
1527 intel_increase_pllclock(crtc);
1528
1529 return 0;
1530 }
1531
1532 static int
1533 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1534 struct drm_framebuffer *old_fb)
1535 {
1536 struct drm_device *dev = crtc->dev;
1537 struct drm_i915_master_private *master_priv;
1538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539 struct intel_framebuffer *intel_fb;
1540 struct drm_i915_gem_object *obj_priv;
1541 struct drm_gem_object *obj;
1542 int pipe = intel_crtc->pipe;
1543 int plane = intel_crtc->plane;
1544 int ret;
1545
1546 /* no fb bound */
1547 if (!crtc->fb) {
1548 DRM_DEBUG_KMS("No FB bound\n");
1549 return 0;
1550 }
1551
1552 switch (plane) {
1553 case 0:
1554 case 1:
1555 break;
1556 default:
1557 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1558 return -EINVAL;
1559 }
1560
1561 intel_fb = to_intel_framebuffer(crtc->fb);
1562 obj = intel_fb->obj;
1563 obj_priv = to_intel_bo(obj);
1564
1565 mutex_lock(&dev->struct_mutex);
1566 ret = intel_pin_and_fence_fb_obj(dev, obj);
1567 if (ret != 0) {
1568 mutex_unlock(&dev->struct_mutex);
1569 return ret;
1570 }
1571
1572 ret = i915_gem_object_set_to_display_plane(obj);
1573 if (ret != 0) {
1574 i915_gem_object_unpin(obj);
1575 mutex_unlock(&dev->struct_mutex);
1576 return ret;
1577 }
1578
1579 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1580 if (ret) {
1581 i915_gem_object_unpin(obj);
1582 mutex_unlock(&dev->struct_mutex);
1583 return ret;
1584 }
1585
1586 if (old_fb) {
1587 intel_fb = to_intel_framebuffer(old_fb);
1588 obj_priv = to_intel_bo(intel_fb->obj);
1589 i915_gem_object_unpin(intel_fb->obj);
1590 }
1591
1592 mutex_unlock(&dev->struct_mutex);
1593
1594 if (!dev->primary->master)
1595 return 0;
1596
1597 master_priv = dev->primary->master->driver_priv;
1598 if (!master_priv->sarea_priv)
1599 return 0;
1600
1601 if (pipe) {
1602 master_priv->sarea_priv->pipeB_x = x;
1603 master_priv->sarea_priv->pipeB_y = y;
1604 } else {
1605 master_priv->sarea_priv->pipeA_x = x;
1606 master_priv->sarea_priv->pipeA_y = y;
1607 }
1608
1609 return 0;
1610 }
1611
1612 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1613 {
1614 struct drm_device *dev = crtc->dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 u32 dpa_ctl;
1617
1618 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1619 dpa_ctl = I915_READ(DP_A);
1620 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1621
1622 if (clock < 200000) {
1623 u32 temp;
1624 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1625 /* workaround for 160Mhz:
1626 1) program 0x4600c bits 15:0 = 0x8124
1627 2) program 0x46010 bit 0 = 1
1628 3) program 0x46034 bit 24 = 1
1629 4) program 0x64000 bit 14 = 1
1630 */
1631 temp = I915_READ(0x4600c);
1632 temp &= 0xffff0000;
1633 I915_WRITE(0x4600c, temp | 0x8124);
1634
1635 temp = I915_READ(0x46010);
1636 I915_WRITE(0x46010, temp | 1);
1637
1638 temp = I915_READ(0x46034);
1639 I915_WRITE(0x46034, temp | (1 << 24));
1640 } else {
1641 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1642 }
1643 I915_WRITE(DP_A, dpa_ctl);
1644
1645 udelay(500);
1646 }
1647
1648 /* The FDI link training functions for ILK/Ibexpeak. */
1649 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1650 {
1651 struct drm_device *dev = crtc->dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1654 int pipe = intel_crtc->pipe;
1655 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1656 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1657 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1658 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1659 u32 temp, tries = 0;
1660
1661 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1662 for train result */
1663 temp = I915_READ(fdi_rx_imr_reg);
1664 temp &= ~FDI_RX_SYMBOL_LOCK;
1665 temp &= ~FDI_RX_BIT_LOCK;
1666 I915_WRITE(fdi_rx_imr_reg, temp);
1667 I915_READ(fdi_rx_imr_reg);
1668 udelay(150);
1669
1670 /* enable CPU FDI TX and PCH FDI RX */
1671 temp = I915_READ(fdi_tx_reg);
1672 temp |= FDI_TX_ENABLE;
1673 temp &= ~(7 << 19);
1674 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1675 temp &= ~FDI_LINK_TRAIN_NONE;
1676 temp |= FDI_LINK_TRAIN_PATTERN_1;
1677 I915_WRITE(fdi_tx_reg, temp);
1678 I915_READ(fdi_tx_reg);
1679
1680 temp = I915_READ(fdi_rx_reg);
1681 temp &= ~FDI_LINK_TRAIN_NONE;
1682 temp |= FDI_LINK_TRAIN_PATTERN_1;
1683 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1684 I915_READ(fdi_rx_reg);
1685 udelay(150);
1686
1687 for (tries = 0; tries < 5; tries++) {
1688 temp = I915_READ(fdi_rx_iir_reg);
1689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1690
1691 if ((temp & FDI_RX_BIT_LOCK)) {
1692 DRM_DEBUG_KMS("FDI train 1 done.\n");
1693 I915_WRITE(fdi_rx_iir_reg,
1694 temp | FDI_RX_BIT_LOCK);
1695 break;
1696 }
1697 }
1698 if (tries == 5)
1699 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1700
1701 /* Train 2 */
1702 temp = I915_READ(fdi_tx_reg);
1703 temp &= ~FDI_LINK_TRAIN_NONE;
1704 temp |= FDI_LINK_TRAIN_PATTERN_2;
1705 I915_WRITE(fdi_tx_reg, temp);
1706
1707 temp = I915_READ(fdi_rx_reg);
1708 temp &= ~FDI_LINK_TRAIN_NONE;
1709 temp |= FDI_LINK_TRAIN_PATTERN_2;
1710 I915_WRITE(fdi_rx_reg, temp);
1711 udelay(150);
1712
1713 tries = 0;
1714
1715 for (tries = 0; tries < 5; tries++) {
1716 temp = I915_READ(fdi_rx_iir_reg);
1717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1718
1719 if (temp & FDI_RX_SYMBOL_LOCK) {
1720 I915_WRITE(fdi_rx_iir_reg,
1721 temp | FDI_RX_SYMBOL_LOCK);
1722 DRM_DEBUG_KMS("FDI train 2 done.\n");
1723 break;
1724 }
1725 }
1726 if (tries == 5)
1727 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1728
1729 DRM_DEBUG_KMS("FDI train done\n");
1730 }
1731
1732 static int snb_b_fdi_train_param [] = {
1733 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1734 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1735 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1736 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1737 };
1738
1739 /* The FDI link training functions for SNB/Cougarpoint. */
1740 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1741 {
1742 struct drm_device *dev = crtc->dev;
1743 struct drm_i915_private *dev_priv = dev->dev_private;
1744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1745 int pipe = intel_crtc->pipe;
1746 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1747 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1748 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1749 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1750 u32 temp, i;
1751
1752 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1753 for train result */
1754 temp = I915_READ(fdi_rx_imr_reg);
1755 temp &= ~FDI_RX_SYMBOL_LOCK;
1756 temp &= ~FDI_RX_BIT_LOCK;
1757 I915_WRITE(fdi_rx_imr_reg, temp);
1758 I915_READ(fdi_rx_imr_reg);
1759 udelay(150);
1760
1761 /* enable CPU FDI TX and PCH FDI RX */
1762 temp = I915_READ(fdi_tx_reg);
1763 temp |= FDI_TX_ENABLE;
1764 temp &= ~(7 << 19);
1765 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1766 temp &= ~FDI_LINK_TRAIN_NONE;
1767 temp |= FDI_LINK_TRAIN_PATTERN_1;
1768 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1769 /* SNB-B */
1770 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1771 I915_WRITE(fdi_tx_reg, temp);
1772 I915_READ(fdi_tx_reg);
1773
1774 temp = I915_READ(fdi_rx_reg);
1775 if (HAS_PCH_CPT(dev)) {
1776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1777 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1778 } else {
1779 temp &= ~FDI_LINK_TRAIN_NONE;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1;
1781 }
1782 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1783 I915_READ(fdi_rx_reg);
1784 udelay(150);
1785
1786 for (i = 0; i < 4; i++ ) {
1787 temp = I915_READ(fdi_tx_reg);
1788 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1789 temp |= snb_b_fdi_train_param[i];
1790 I915_WRITE(fdi_tx_reg, temp);
1791 udelay(500);
1792
1793 temp = I915_READ(fdi_rx_iir_reg);
1794 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1795
1796 if (temp & FDI_RX_BIT_LOCK) {
1797 I915_WRITE(fdi_rx_iir_reg,
1798 temp | FDI_RX_BIT_LOCK);
1799 DRM_DEBUG_KMS("FDI train 1 done.\n");
1800 break;
1801 }
1802 }
1803 if (i == 4)
1804 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1805
1806 /* Train 2 */
1807 temp = I915_READ(fdi_tx_reg);
1808 temp &= ~FDI_LINK_TRAIN_NONE;
1809 temp |= FDI_LINK_TRAIN_PATTERN_2;
1810 if (IS_GEN6(dev)) {
1811 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1812 /* SNB-B */
1813 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1814 }
1815 I915_WRITE(fdi_tx_reg, temp);
1816
1817 temp = I915_READ(fdi_rx_reg);
1818 if (HAS_PCH_CPT(dev)) {
1819 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1820 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1821 } else {
1822 temp &= ~FDI_LINK_TRAIN_NONE;
1823 temp |= FDI_LINK_TRAIN_PATTERN_2;
1824 }
1825 I915_WRITE(fdi_rx_reg, temp);
1826 udelay(150);
1827
1828 for (i = 0; i < 4; i++ ) {
1829 temp = I915_READ(fdi_tx_reg);
1830 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1831 temp |= snb_b_fdi_train_param[i];
1832 I915_WRITE(fdi_tx_reg, temp);
1833 udelay(500);
1834
1835 temp = I915_READ(fdi_rx_iir_reg);
1836 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1837
1838 if (temp & FDI_RX_SYMBOL_LOCK) {
1839 I915_WRITE(fdi_rx_iir_reg,
1840 temp | FDI_RX_SYMBOL_LOCK);
1841 DRM_DEBUG_KMS("FDI train 2 done.\n");
1842 break;
1843 }
1844 }
1845 if (i == 4)
1846 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1847
1848 DRM_DEBUG_KMS("FDI train done.\n");
1849 }
1850
1851 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1852 {
1853 struct drm_device *dev = crtc->dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1856 int pipe = intel_crtc->pipe;
1857 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1858 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1859 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1860 u32 temp;
1861 u32 pipe_bpc;
1862
1863 temp = I915_READ(pipeconf_reg);
1864 pipe_bpc = temp & PIPE_BPC_MASK;
1865
1866 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1867 temp = I915_READ(fdi_rx_reg);
1868 /*
1869 * make the BPC in FDI Rx be consistent with that in
1870 * pipeconf reg.
1871 */
1872 temp &= ~(0x7 << 16);
1873 temp |= (pipe_bpc << 11);
1874 temp &= ~(7 << 19);
1875 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1876 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1877 I915_READ(fdi_rx_reg);
1878 udelay(200);
1879
1880 /* Switch from Rawclk to PCDclk */
1881 temp = I915_READ(fdi_rx_reg);
1882 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1883 I915_READ(fdi_rx_reg);
1884 udelay(200);
1885
1886 /* Enable CPU FDI TX PLL, always on for Ironlake */
1887 temp = I915_READ(fdi_tx_reg);
1888 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1889 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1890 I915_READ(fdi_tx_reg);
1891 udelay(100);
1892 }
1893 }
1894
1895 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1896 {
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 int pipe = intel_crtc->pipe;
1901 int plane = intel_crtc->plane;
1902 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1903 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1904 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1905 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1906 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1907 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1908 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1909 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1910 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1911 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1912 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1913 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1914 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1915 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1916 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1917 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1918 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1919 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1920 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1921 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1922 u32 temp;
1923 u32 pipe_bpc;
1924
1925 temp = I915_READ(pipeconf_reg);
1926 pipe_bpc = temp & PIPE_BPC_MASK;
1927
1928 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1929 temp = I915_READ(PCH_LVDS);
1930 if ((temp & LVDS_PORT_EN) == 0) {
1931 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1932 POSTING_READ(PCH_LVDS);
1933 }
1934 }
1935
1936 ironlake_fdi_enable(crtc);
1937
1938 /* Enable panel fitting for LVDS */
1939 if (dev_priv->pch_pf_size &&
1940 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1941 || HAS_eDP || intel_pch_has_edp(crtc))) {
1942 /* Force use of hard-coded filter coefficients
1943 * as some pre-programmed values are broken,
1944 * e.g. x201.
1945 */
1946 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1947 PF_ENABLE | PF_FILTER_MED_3x3);
1948 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1949 dev_priv->pch_pf_pos);
1950 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1951 dev_priv->pch_pf_size);
1952 }
1953
1954 /* Enable CPU pipe */
1955 temp = I915_READ(pipeconf_reg);
1956 if ((temp & PIPEACONF_ENABLE) == 0) {
1957 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1958 I915_READ(pipeconf_reg);
1959 udelay(100);
1960 }
1961
1962 /* configure and enable CPU plane */
1963 temp = I915_READ(dspcntr_reg);
1964 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1965 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1966 /* Flush the plane changes */
1967 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1968 }
1969
1970 /* For PCH output, training FDI link */
1971 if (IS_GEN6(dev))
1972 gen6_fdi_link_train(crtc);
1973 else
1974 ironlake_fdi_link_train(crtc);
1975
1976 /* enable PCH DPLL */
1977 temp = I915_READ(pch_dpll_reg);
1978 if ((temp & DPLL_VCO_ENABLE) == 0) {
1979 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1980 I915_READ(pch_dpll_reg);
1981 }
1982 udelay(200);
1983
1984 if (HAS_PCH_CPT(dev)) {
1985 /* Be sure PCH DPLL SEL is set */
1986 temp = I915_READ(PCH_DPLL_SEL);
1987 if (trans_dpll_sel == 0 &&
1988 (temp & TRANSA_DPLL_ENABLE) == 0)
1989 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1990 else if (trans_dpll_sel == 1 &&
1991 (temp & TRANSB_DPLL_ENABLE) == 0)
1992 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1993 I915_WRITE(PCH_DPLL_SEL, temp);
1994 I915_READ(PCH_DPLL_SEL);
1995 }
1996 /* set transcoder timing */
1997 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1998 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1999 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
2000
2001 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
2002 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
2003 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
2004
2005 /* enable normal train */
2006 temp = I915_READ(fdi_tx_reg);
2007 temp &= ~FDI_LINK_TRAIN_NONE;
2008 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
2009 FDI_TX_ENHANCE_FRAME_ENABLE);
2010 I915_READ(fdi_tx_reg);
2011
2012 temp = I915_READ(fdi_rx_reg);
2013 if (HAS_PCH_CPT(dev)) {
2014 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2015 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2016 } else {
2017 temp &= ~FDI_LINK_TRAIN_NONE;
2018 temp |= FDI_LINK_TRAIN_NONE;
2019 }
2020 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2021 I915_READ(fdi_rx_reg);
2022
2023 /* wait one idle pattern time */
2024 udelay(100);
2025
2026 /* For PCH DP, enable TRANS_DP_CTL */
2027 if (HAS_PCH_CPT(dev) &&
2028 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2029 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2030 int reg;
2031
2032 reg = I915_READ(trans_dp_ctl);
2033 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2034 TRANS_DP_SYNC_MASK);
2035 reg |= (TRANS_DP_OUTPUT_ENABLE |
2036 TRANS_DP_ENH_FRAMING);
2037
2038 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2039 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2040 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2041 reg |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2042
2043 switch (intel_trans_dp_port_sel(crtc)) {
2044 case PCH_DP_B:
2045 reg |= TRANS_DP_PORT_SEL_B;
2046 break;
2047 case PCH_DP_C:
2048 reg |= TRANS_DP_PORT_SEL_C;
2049 break;
2050 case PCH_DP_D:
2051 reg |= TRANS_DP_PORT_SEL_D;
2052 break;
2053 default:
2054 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2055 reg |= TRANS_DP_PORT_SEL_B;
2056 break;
2057 }
2058
2059 I915_WRITE(trans_dp_ctl, reg);
2060 POSTING_READ(trans_dp_ctl);
2061 }
2062
2063 /* enable PCH transcoder */
2064 temp = I915_READ(transconf_reg);
2065 /*
2066 * make the BPC in transcoder be consistent with
2067 * that in pipeconf reg.
2068 */
2069 temp &= ~PIPE_BPC_MASK;
2070 temp |= pipe_bpc;
2071 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2072 I915_READ(transconf_reg);
2073
2074 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100))
2075 DRM_ERROR("failed to enable transcoder\n");
2076
2077 intel_crtc_load_lut(crtc);
2078
2079 intel_update_fbc(crtc, &crtc->mode);
2080 }
2081
2082 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2083 {
2084 struct drm_device *dev = crtc->dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 int pipe = intel_crtc->pipe;
2088 int plane = intel_crtc->plane;
2089 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2090 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2091 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2092 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2093 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
2094 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2095 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
2096 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
2097 u32 temp;
2098 u32 pipe_bpc;
2099
2100 temp = I915_READ(pipeconf_reg);
2101 pipe_bpc = temp & PIPE_BPC_MASK;
2102
2103 drm_vblank_off(dev, pipe);
2104 /* Disable display plane */
2105 temp = I915_READ(dspcntr_reg);
2106 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2107 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2108 /* Flush the plane changes */
2109 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2110 I915_READ(dspbase_reg);
2111 }
2112
2113 if (dev_priv->cfb_plane == plane &&
2114 dev_priv->display.disable_fbc)
2115 dev_priv->display.disable_fbc(dev);
2116
2117 /* disable cpu pipe, disable after all planes disabled */
2118 temp = I915_READ(pipeconf_reg);
2119 if ((temp & PIPEACONF_ENABLE) != 0) {
2120 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2121
2122 /* wait for cpu pipe off, pipe state */
2123 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2124 DRM_ERROR("failed to turn off cpu pipe\n");
2125 } else
2126 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2127
2128 udelay(100);
2129
2130 /* Disable PF */
2131 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2132 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2133
2134 /* disable CPU FDI tx and PCH FDI rx */
2135 temp = I915_READ(fdi_tx_reg);
2136 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
2137 I915_READ(fdi_tx_reg);
2138
2139 temp = I915_READ(fdi_rx_reg);
2140 /* BPC in FDI rx is consistent with that in pipeconf */
2141 temp &= ~(0x07 << 16);
2142 temp |= (pipe_bpc << 11);
2143 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
2144 I915_READ(fdi_rx_reg);
2145
2146 udelay(100);
2147
2148 /* still set train pattern 1 */
2149 temp = I915_READ(fdi_tx_reg);
2150 temp &= ~FDI_LINK_TRAIN_NONE;
2151 temp |= FDI_LINK_TRAIN_PATTERN_1;
2152 I915_WRITE(fdi_tx_reg, temp);
2153 POSTING_READ(fdi_tx_reg);
2154
2155 temp = I915_READ(fdi_rx_reg);
2156 if (HAS_PCH_CPT(dev)) {
2157 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2158 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2159 } else {
2160 temp &= ~FDI_LINK_TRAIN_NONE;
2161 temp |= FDI_LINK_TRAIN_PATTERN_1;
2162 }
2163 I915_WRITE(fdi_rx_reg, temp);
2164 POSTING_READ(fdi_rx_reg);
2165
2166 udelay(100);
2167
2168 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2169 temp = I915_READ(PCH_LVDS);
2170 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2171 I915_READ(PCH_LVDS);
2172 udelay(100);
2173 }
2174
2175 /* disable PCH transcoder */
2176 temp = I915_READ(transconf_reg);
2177 if ((temp & TRANS_ENABLE) != 0) {
2178 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2179
2180 /* wait for PCH transcoder off, transcoder state */
2181 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50))
2182 DRM_ERROR("failed to disable transcoder\n");
2183 }
2184
2185 temp = I915_READ(transconf_reg);
2186 /* BPC in transcoder is consistent with that in pipeconf */
2187 temp &= ~PIPE_BPC_MASK;
2188 temp |= pipe_bpc;
2189 I915_WRITE(transconf_reg, temp);
2190 I915_READ(transconf_reg);
2191 udelay(100);
2192
2193 if (HAS_PCH_CPT(dev)) {
2194 /* disable TRANS_DP_CTL */
2195 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2196 int reg;
2197
2198 reg = I915_READ(trans_dp_ctl);
2199 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2200 I915_WRITE(trans_dp_ctl, reg);
2201 POSTING_READ(trans_dp_ctl);
2202
2203 /* disable DPLL_SEL */
2204 temp = I915_READ(PCH_DPLL_SEL);
2205 if (trans_dpll_sel == 0)
2206 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2207 else
2208 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2209 I915_WRITE(PCH_DPLL_SEL, temp);
2210 I915_READ(PCH_DPLL_SEL);
2211
2212 }
2213
2214 /* disable PCH DPLL */
2215 temp = I915_READ(pch_dpll_reg);
2216 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2217 I915_READ(pch_dpll_reg);
2218
2219 /* Switch from PCDclk to Rawclk */
2220 temp = I915_READ(fdi_rx_reg);
2221 temp &= ~FDI_SEL_PCDCLK;
2222 I915_WRITE(fdi_rx_reg, temp);
2223 I915_READ(fdi_rx_reg);
2224
2225 /* Disable CPU FDI TX PLL */
2226 temp = I915_READ(fdi_tx_reg);
2227 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2228 I915_READ(fdi_tx_reg);
2229 udelay(100);
2230
2231 temp = I915_READ(fdi_rx_reg);
2232 temp &= ~FDI_RX_PLL_ENABLE;
2233 I915_WRITE(fdi_rx_reg, temp);
2234 I915_READ(fdi_rx_reg);
2235
2236 /* Wait for the clocks to turn off. */
2237 udelay(100);
2238 }
2239
2240 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2241 {
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243 int pipe = intel_crtc->pipe;
2244 int plane = intel_crtc->plane;
2245
2246 /* XXX: When our outputs are all unaware of DPMS modes other than off
2247 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2248 */
2249 switch (mode) {
2250 case DRM_MODE_DPMS_ON:
2251 case DRM_MODE_DPMS_STANDBY:
2252 case DRM_MODE_DPMS_SUSPEND:
2253 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2254 ironlake_crtc_enable(crtc);
2255 break;
2256
2257 case DRM_MODE_DPMS_OFF:
2258 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2259 ironlake_crtc_disable(crtc);
2260 break;
2261 }
2262 }
2263
2264 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2265 {
2266 if (!enable && intel_crtc->overlay) {
2267 struct drm_device *dev = intel_crtc->base.dev;
2268
2269 mutex_lock(&dev->struct_mutex);
2270 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2271 mutex_unlock(&dev->struct_mutex);
2272 }
2273
2274 /* Let userspace switch the overlay on again. In most cases userspace
2275 * has to recompute where to put it anyway.
2276 */
2277 }
2278
2279 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2280 {
2281 struct drm_device *dev = crtc->dev;
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2284 int pipe = intel_crtc->pipe;
2285 int plane = intel_crtc->plane;
2286 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2287 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2288 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2289 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2290 u32 temp;
2291
2292 /* Enable the DPLL */
2293 temp = I915_READ(dpll_reg);
2294 if ((temp & DPLL_VCO_ENABLE) == 0) {
2295 I915_WRITE(dpll_reg, temp);
2296 I915_READ(dpll_reg);
2297 /* Wait for the clocks to stabilize. */
2298 udelay(150);
2299 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2300 I915_READ(dpll_reg);
2301 /* Wait for the clocks to stabilize. */
2302 udelay(150);
2303 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
2304 I915_READ(dpll_reg);
2305 /* Wait for the clocks to stabilize. */
2306 udelay(150);
2307 }
2308
2309 /* Enable the pipe */
2310 temp = I915_READ(pipeconf_reg);
2311 if ((temp & PIPEACONF_ENABLE) == 0)
2312 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
2313
2314 /* Enable the plane */
2315 temp = I915_READ(dspcntr_reg);
2316 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2317 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
2318 /* Flush the plane changes */
2319 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2320 }
2321
2322 intel_crtc_load_lut(crtc);
2323
2324 if ((IS_I965G(dev) || plane == 0))
2325 intel_update_fbc(crtc, &crtc->mode);
2326
2327 /* Give the overlay scaler a chance to enable if it's on this pipe */
2328 intel_crtc_dpms_overlay(intel_crtc, true);
2329 }
2330
2331 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2332 {
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 int plane = intel_crtc->plane;
2338 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2339 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2340 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
2341 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2342 u32 temp;
2343
2344 /* Give the overlay scaler a chance to disable if it's on this pipe */
2345 intel_crtc_dpms_overlay(intel_crtc, false);
2346 drm_vblank_off(dev, pipe);
2347
2348 if (dev_priv->cfb_plane == plane &&
2349 dev_priv->display.disable_fbc)
2350 dev_priv->display.disable_fbc(dev);
2351
2352 /* Disable display plane */
2353 temp = I915_READ(dspcntr_reg);
2354 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2355 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2356 /* Flush the plane changes */
2357 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2358 I915_READ(dspbase_reg);
2359 }
2360
2361 if (!IS_I9XX(dev)) {
2362 /* Wait for vblank for the disable to take effect */
2363 intel_wait_for_vblank_off(dev, pipe);
2364 }
2365
2366 /* Don't disable pipe A or pipe A PLLs if needed */
2367 if (pipeconf_reg == PIPEACONF &&
2368 (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2369 goto skip_pipe_off;
2370
2371 /* Next, disable display pipes */
2372 temp = I915_READ(pipeconf_reg);
2373 if ((temp & PIPEACONF_ENABLE) != 0) {
2374 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2375 I915_READ(pipeconf_reg);
2376 }
2377
2378 /* Wait for vblank for the disable to take effect. */
2379 intel_wait_for_vblank_off(dev, pipe);
2380
2381 temp = I915_READ(dpll_reg);
2382 if ((temp & DPLL_VCO_ENABLE) != 0) {
2383 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2384 I915_READ(dpll_reg);
2385 }
2386 skip_pipe_off:
2387 /* Wait for the clocks to turn off. */
2388 udelay(150);
2389 }
2390
2391 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2392 {
2393 /* XXX: When our outputs are all unaware of DPMS modes other than off
2394 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2395 */
2396 switch (mode) {
2397 case DRM_MODE_DPMS_ON:
2398 case DRM_MODE_DPMS_STANDBY:
2399 case DRM_MODE_DPMS_SUSPEND:
2400 i9xx_crtc_enable(crtc);
2401 break;
2402 case DRM_MODE_DPMS_OFF:
2403 i9xx_crtc_disable(crtc);
2404 break;
2405 }
2406 }
2407
2408 /*
2409 * When we disable a pipe, we need to clear any pending scanline wait events
2410 * to avoid hanging the ring, which we assume we are waiting on.
2411 */
2412 static void intel_clear_scanline_wait(struct drm_device *dev)
2413 {
2414 struct drm_i915_private *dev_priv = dev->dev_private;
2415 u32 tmp;
2416
2417 if (IS_GEN2(dev))
2418 /* Can't break the hang on i8xx */
2419 return;
2420
2421 tmp = I915_READ(PRB0_CTL);
2422 if (tmp & RING_WAIT) {
2423 I915_WRITE(PRB0_CTL, tmp);
2424 POSTING_READ(PRB0_CTL);
2425 }
2426 }
2427
2428 /**
2429 * Sets the power management mode of the pipe and plane.
2430 */
2431 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2432 {
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct drm_i915_master_private *master_priv;
2436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437 int pipe = intel_crtc->pipe;
2438 bool enabled;
2439
2440 if (intel_crtc->dpms_mode == mode)
2441 return;
2442
2443 intel_crtc->dpms_mode = mode;
2444 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2445
2446 /* When switching on the display, ensure that SR is disabled
2447 * with multiple pipes prior to enabling to new pipe.
2448 *
2449 * When switching off the display, make sure the cursor is
2450 * properly hidden and there are no pending waits prior to
2451 * disabling the pipe.
2452 */
2453 if (mode == DRM_MODE_DPMS_ON)
2454 intel_update_watermarks(dev);
2455 else
2456 intel_crtc_update_cursor(crtc);
2457
2458 dev_priv->display.dpms(crtc, mode);
2459
2460 if (mode == DRM_MODE_DPMS_ON)
2461 intel_crtc_update_cursor(crtc);
2462 else {
2463 /* XXX Note that this is not a complete solution, but a hack
2464 * to avoid the most frequently hit hang.
2465 */
2466 intel_clear_scanline_wait(dev);
2467
2468 intel_update_watermarks(dev);
2469 }
2470
2471 if (!dev->primary->master)
2472 return;
2473
2474 master_priv = dev->primary->master->driver_priv;
2475 if (!master_priv->sarea_priv)
2476 return;
2477
2478 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2479
2480 switch (pipe) {
2481 case 0:
2482 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2483 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2484 break;
2485 case 1:
2486 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2487 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2488 break;
2489 default:
2490 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2491 break;
2492 }
2493 }
2494
2495 /* Prepare for a mode set.
2496 *
2497 * Note we could be a lot smarter here. We need to figure out which outputs
2498 * will be enabled, which disabled (in short, how the config will changes)
2499 * and perform the minimum necessary steps to accomplish that, e.g. updating
2500 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2501 * panel fitting is in the proper state, etc.
2502 */
2503 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2504 {
2505 struct drm_device *dev = crtc->dev;
2506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2507
2508 intel_crtc->cursor_on = false;
2509 intel_crtc_update_cursor(crtc);
2510
2511 i9xx_crtc_disable(crtc);
2512 intel_clear_scanline_wait(dev);
2513 }
2514
2515 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2516 {
2517 struct drm_device *dev = crtc->dev;
2518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2519
2520 intel_update_watermarks(dev);
2521 i9xx_crtc_enable(crtc);
2522
2523 intel_crtc->cursor_on = true;
2524 intel_crtc_update_cursor(crtc);
2525 }
2526
2527 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2528 {
2529 struct drm_device *dev = crtc->dev;
2530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2531
2532 intel_crtc->cursor_on = false;
2533 intel_crtc_update_cursor(crtc);
2534
2535 ironlake_crtc_disable(crtc);
2536 intel_clear_scanline_wait(dev);
2537 }
2538
2539 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2540 {
2541 struct drm_device *dev = crtc->dev;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543
2544 intel_update_watermarks(dev);
2545 ironlake_crtc_enable(crtc);
2546
2547 intel_crtc->cursor_on = true;
2548 intel_crtc_update_cursor(crtc);
2549 }
2550
2551 void intel_encoder_prepare (struct drm_encoder *encoder)
2552 {
2553 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2554 /* lvds has its own version of prepare see intel_lvds_prepare */
2555 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2556 }
2557
2558 void intel_encoder_commit (struct drm_encoder *encoder)
2559 {
2560 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2561 /* lvds has its own version of commit see intel_lvds_commit */
2562 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2563 }
2564
2565 void intel_encoder_destroy(struct drm_encoder *encoder)
2566 {
2567 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2568
2569 if (intel_encoder->ddc_bus)
2570 intel_i2c_destroy(intel_encoder->ddc_bus);
2571
2572 if (intel_encoder->i2c_bus)
2573 intel_i2c_destroy(intel_encoder->i2c_bus);
2574
2575 drm_encoder_cleanup(encoder);
2576 kfree(intel_encoder);
2577 }
2578
2579 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2580 struct drm_display_mode *mode,
2581 struct drm_display_mode *adjusted_mode)
2582 {
2583 struct drm_device *dev = crtc->dev;
2584 if (HAS_PCH_SPLIT(dev)) {
2585 /* FDI link clock is fixed at 2.7G */
2586 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2587 return false;
2588 }
2589 return true;
2590 }
2591
2592 static int i945_get_display_clock_speed(struct drm_device *dev)
2593 {
2594 return 400000;
2595 }
2596
2597 static int i915_get_display_clock_speed(struct drm_device *dev)
2598 {
2599 return 333000;
2600 }
2601
2602 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2603 {
2604 return 200000;
2605 }
2606
2607 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2608 {
2609 u16 gcfgc = 0;
2610
2611 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2612
2613 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2614 return 133000;
2615 else {
2616 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2617 case GC_DISPLAY_CLOCK_333_MHZ:
2618 return 333000;
2619 default:
2620 case GC_DISPLAY_CLOCK_190_200_MHZ:
2621 return 190000;
2622 }
2623 }
2624 }
2625
2626 static int i865_get_display_clock_speed(struct drm_device *dev)
2627 {
2628 return 266000;
2629 }
2630
2631 static int i855_get_display_clock_speed(struct drm_device *dev)
2632 {
2633 u16 hpllcc = 0;
2634 /* Assume that the hardware is in the high speed state. This
2635 * should be the default.
2636 */
2637 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2638 case GC_CLOCK_133_200:
2639 case GC_CLOCK_100_200:
2640 return 200000;
2641 case GC_CLOCK_166_250:
2642 return 250000;
2643 case GC_CLOCK_100_133:
2644 return 133000;
2645 }
2646
2647 /* Shouldn't happen */
2648 return 0;
2649 }
2650
2651 static int i830_get_display_clock_speed(struct drm_device *dev)
2652 {
2653 return 133000;
2654 }
2655
2656 /**
2657 * Return the pipe currently connected to the panel fitter,
2658 * or -1 if the panel fitter is not present or not in use
2659 */
2660 int intel_panel_fitter_pipe (struct drm_device *dev)
2661 {
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 u32 pfit_control;
2664
2665 /* i830 doesn't have a panel fitter */
2666 if (IS_I830(dev))
2667 return -1;
2668
2669 pfit_control = I915_READ(PFIT_CONTROL);
2670
2671 /* See if the panel fitter is in use */
2672 if ((pfit_control & PFIT_ENABLE) == 0)
2673 return -1;
2674
2675 /* 965 can place panel fitter on either pipe */
2676 if (IS_I965G(dev))
2677 return (pfit_control >> 29) & 0x3;
2678
2679 /* older chips can only use pipe 1 */
2680 return 1;
2681 }
2682
2683 struct fdi_m_n {
2684 u32 tu;
2685 u32 gmch_m;
2686 u32 gmch_n;
2687 u32 link_m;
2688 u32 link_n;
2689 };
2690
2691 static void
2692 fdi_reduce_ratio(u32 *num, u32 *den)
2693 {
2694 while (*num > 0xffffff || *den > 0xffffff) {
2695 *num >>= 1;
2696 *den >>= 1;
2697 }
2698 }
2699
2700 #define DATA_N 0x800000
2701 #define LINK_N 0x80000
2702
2703 static void
2704 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2705 int link_clock, struct fdi_m_n *m_n)
2706 {
2707 u64 temp;
2708
2709 m_n->tu = 64; /* default size */
2710
2711 temp = (u64) DATA_N * pixel_clock;
2712 temp = div_u64(temp, link_clock);
2713 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2714 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2715 m_n->gmch_n = DATA_N;
2716 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2717
2718 temp = (u64) LINK_N * pixel_clock;
2719 m_n->link_m = div_u64(temp, link_clock);
2720 m_n->link_n = LINK_N;
2721 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2722 }
2723
2724
2725 struct intel_watermark_params {
2726 unsigned long fifo_size;
2727 unsigned long max_wm;
2728 unsigned long default_wm;
2729 unsigned long guard_size;
2730 unsigned long cacheline_size;
2731 };
2732
2733 /* Pineview has different values for various configs */
2734 static struct intel_watermark_params pineview_display_wm = {
2735 PINEVIEW_DISPLAY_FIFO,
2736 PINEVIEW_MAX_WM,
2737 PINEVIEW_DFT_WM,
2738 PINEVIEW_GUARD_WM,
2739 PINEVIEW_FIFO_LINE_SIZE
2740 };
2741 static struct intel_watermark_params pineview_display_hplloff_wm = {
2742 PINEVIEW_DISPLAY_FIFO,
2743 PINEVIEW_MAX_WM,
2744 PINEVIEW_DFT_HPLLOFF_WM,
2745 PINEVIEW_GUARD_WM,
2746 PINEVIEW_FIFO_LINE_SIZE
2747 };
2748 static struct intel_watermark_params pineview_cursor_wm = {
2749 PINEVIEW_CURSOR_FIFO,
2750 PINEVIEW_CURSOR_MAX_WM,
2751 PINEVIEW_CURSOR_DFT_WM,
2752 PINEVIEW_CURSOR_GUARD_WM,
2753 PINEVIEW_FIFO_LINE_SIZE,
2754 };
2755 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2756 PINEVIEW_CURSOR_FIFO,
2757 PINEVIEW_CURSOR_MAX_WM,
2758 PINEVIEW_CURSOR_DFT_WM,
2759 PINEVIEW_CURSOR_GUARD_WM,
2760 PINEVIEW_FIFO_LINE_SIZE
2761 };
2762 static struct intel_watermark_params g4x_wm_info = {
2763 G4X_FIFO_SIZE,
2764 G4X_MAX_WM,
2765 G4X_MAX_WM,
2766 2,
2767 G4X_FIFO_LINE_SIZE,
2768 };
2769 static struct intel_watermark_params g4x_cursor_wm_info = {
2770 I965_CURSOR_FIFO,
2771 I965_CURSOR_MAX_WM,
2772 I965_CURSOR_DFT_WM,
2773 2,
2774 G4X_FIFO_LINE_SIZE,
2775 };
2776 static struct intel_watermark_params i965_cursor_wm_info = {
2777 I965_CURSOR_FIFO,
2778 I965_CURSOR_MAX_WM,
2779 I965_CURSOR_DFT_WM,
2780 2,
2781 I915_FIFO_LINE_SIZE,
2782 };
2783 static struct intel_watermark_params i945_wm_info = {
2784 I945_FIFO_SIZE,
2785 I915_MAX_WM,
2786 1,
2787 2,
2788 I915_FIFO_LINE_SIZE
2789 };
2790 static struct intel_watermark_params i915_wm_info = {
2791 I915_FIFO_SIZE,
2792 I915_MAX_WM,
2793 1,
2794 2,
2795 I915_FIFO_LINE_SIZE
2796 };
2797 static struct intel_watermark_params i855_wm_info = {
2798 I855GM_FIFO_SIZE,
2799 I915_MAX_WM,
2800 1,
2801 2,
2802 I830_FIFO_LINE_SIZE
2803 };
2804 static struct intel_watermark_params i830_wm_info = {
2805 I830_FIFO_SIZE,
2806 I915_MAX_WM,
2807 1,
2808 2,
2809 I830_FIFO_LINE_SIZE
2810 };
2811
2812 static struct intel_watermark_params ironlake_display_wm_info = {
2813 ILK_DISPLAY_FIFO,
2814 ILK_DISPLAY_MAXWM,
2815 ILK_DISPLAY_DFTWM,
2816 2,
2817 ILK_FIFO_LINE_SIZE
2818 };
2819
2820 static struct intel_watermark_params ironlake_cursor_wm_info = {
2821 ILK_CURSOR_FIFO,
2822 ILK_CURSOR_MAXWM,
2823 ILK_CURSOR_DFTWM,
2824 2,
2825 ILK_FIFO_LINE_SIZE
2826 };
2827
2828 static struct intel_watermark_params ironlake_display_srwm_info = {
2829 ILK_DISPLAY_SR_FIFO,
2830 ILK_DISPLAY_MAX_SRWM,
2831 ILK_DISPLAY_DFT_SRWM,
2832 2,
2833 ILK_FIFO_LINE_SIZE
2834 };
2835
2836 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2837 ILK_CURSOR_SR_FIFO,
2838 ILK_CURSOR_MAX_SRWM,
2839 ILK_CURSOR_DFT_SRWM,
2840 2,
2841 ILK_FIFO_LINE_SIZE
2842 };
2843
2844 /**
2845 * intel_calculate_wm - calculate watermark level
2846 * @clock_in_khz: pixel clock
2847 * @wm: chip FIFO params
2848 * @pixel_size: display pixel size
2849 * @latency_ns: memory latency for the platform
2850 *
2851 * Calculate the watermark level (the level at which the display plane will
2852 * start fetching from memory again). Each chip has a different display
2853 * FIFO size and allocation, so the caller needs to figure that out and pass
2854 * in the correct intel_watermark_params structure.
2855 *
2856 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2857 * on the pixel size. When it reaches the watermark level, it'll start
2858 * fetching FIFO line sized based chunks from memory until the FIFO fills
2859 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2860 * will occur, and a display engine hang could result.
2861 */
2862 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2863 struct intel_watermark_params *wm,
2864 int pixel_size,
2865 unsigned long latency_ns)
2866 {
2867 long entries_required, wm_size;
2868
2869 /*
2870 * Note: we need to make sure we don't overflow for various clock &
2871 * latency values.
2872 * clocks go from a few thousand to several hundred thousand.
2873 * latency is usually a few thousand
2874 */
2875 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2876 1000;
2877 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2878
2879 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2880
2881 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2882
2883 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2884
2885 /* Don't promote wm_size to unsigned... */
2886 if (wm_size > (long)wm->max_wm)
2887 wm_size = wm->max_wm;
2888 if (wm_size <= 0)
2889 wm_size = wm->default_wm;
2890 return wm_size;
2891 }
2892
2893 struct cxsr_latency {
2894 int is_desktop;
2895 int is_ddr3;
2896 unsigned long fsb_freq;
2897 unsigned long mem_freq;
2898 unsigned long display_sr;
2899 unsigned long display_hpll_disable;
2900 unsigned long cursor_sr;
2901 unsigned long cursor_hpll_disable;
2902 };
2903
2904 static const struct cxsr_latency cxsr_latency_table[] = {
2905 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2906 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2907 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2908 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2909 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2910
2911 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2912 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2913 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2914 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2915 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2916
2917 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2918 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2919 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2920 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2921 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2922
2923 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2924 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2925 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2926 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2927 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2928
2929 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2930 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2931 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2932 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2933 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2934
2935 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2936 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2937 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2938 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2939 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2940 };
2941
2942 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2943 int is_ddr3,
2944 int fsb,
2945 int mem)
2946 {
2947 const struct cxsr_latency *latency;
2948 int i;
2949
2950 if (fsb == 0 || mem == 0)
2951 return NULL;
2952
2953 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2954 latency = &cxsr_latency_table[i];
2955 if (is_desktop == latency->is_desktop &&
2956 is_ddr3 == latency->is_ddr3 &&
2957 fsb == latency->fsb_freq && mem == latency->mem_freq)
2958 return latency;
2959 }
2960
2961 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2962
2963 return NULL;
2964 }
2965
2966 static void pineview_disable_cxsr(struct drm_device *dev)
2967 {
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969
2970 /* deactivate cxsr */
2971 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2972 }
2973
2974 /*
2975 * Latency for FIFO fetches is dependent on several factors:
2976 * - memory configuration (speed, channels)
2977 * - chipset
2978 * - current MCH state
2979 * It can be fairly high in some situations, so here we assume a fairly
2980 * pessimal value. It's a tradeoff between extra memory fetches (if we
2981 * set this value too high, the FIFO will fetch frequently to stay full)
2982 * and power consumption (set it too low to save power and we might see
2983 * FIFO underruns and display "flicker").
2984 *
2985 * A value of 5us seems to be a good balance; safe for very low end
2986 * platforms but not overly aggressive on lower latency configs.
2987 */
2988 static const int latency_ns = 5000;
2989
2990 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2991 {
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 uint32_t dsparb = I915_READ(DSPARB);
2994 int size;
2995
2996 size = dsparb & 0x7f;
2997 if (plane)
2998 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2999
3000 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3001 plane ? "B" : "A", size);
3002
3003 return size;
3004 }
3005
3006 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3007 {
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 uint32_t dsparb = I915_READ(DSPARB);
3010 int size;
3011
3012 size = dsparb & 0x1ff;
3013 if (plane)
3014 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3015 size >>= 1; /* Convert to cachelines */
3016
3017 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3018 plane ? "B" : "A", size);
3019
3020 return size;
3021 }
3022
3023 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3024 {
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 uint32_t dsparb = I915_READ(DSPARB);
3027 int size;
3028
3029 size = dsparb & 0x7f;
3030 size >>= 2; /* Convert to cachelines */
3031
3032 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3033 plane ? "B" : "A",
3034 size);
3035
3036 return size;
3037 }
3038
3039 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3040 {
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 uint32_t dsparb = I915_READ(DSPARB);
3043 int size;
3044
3045 size = dsparb & 0x7f;
3046 size >>= 1; /* Convert to cachelines */
3047
3048 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3049 plane ? "B" : "A", size);
3050
3051 return size;
3052 }
3053
3054 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3055 int planeb_clock, int sr_hdisplay, int unused,
3056 int pixel_size)
3057 {
3058 struct drm_i915_private *dev_priv = dev->dev_private;
3059 const struct cxsr_latency *latency;
3060 u32 reg;
3061 unsigned long wm;
3062 int sr_clock;
3063
3064 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3065 dev_priv->fsb_freq, dev_priv->mem_freq);
3066 if (!latency) {
3067 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3068 pineview_disable_cxsr(dev);
3069 return;
3070 }
3071
3072 if (!planea_clock || !planeb_clock) {
3073 sr_clock = planea_clock ? planea_clock : planeb_clock;
3074
3075 /* Display SR */
3076 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3077 pixel_size, latency->display_sr);
3078 reg = I915_READ(DSPFW1);
3079 reg &= ~DSPFW_SR_MASK;
3080 reg |= wm << DSPFW_SR_SHIFT;
3081 I915_WRITE(DSPFW1, reg);
3082 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3083
3084 /* cursor SR */
3085 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3086 pixel_size, latency->cursor_sr);
3087 reg = I915_READ(DSPFW3);
3088 reg &= ~DSPFW_CURSOR_SR_MASK;
3089 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3090 I915_WRITE(DSPFW3, reg);
3091
3092 /* Display HPLL off SR */
3093 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3094 pixel_size, latency->display_hpll_disable);
3095 reg = I915_READ(DSPFW3);
3096 reg &= ~DSPFW_HPLL_SR_MASK;
3097 reg |= wm & DSPFW_HPLL_SR_MASK;
3098 I915_WRITE(DSPFW3, reg);
3099
3100 /* cursor HPLL off SR */
3101 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3102 pixel_size, latency->cursor_hpll_disable);
3103 reg = I915_READ(DSPFW3);
3104 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3105 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3106 I915_WRITE(DSPFW3, reg);
3107 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3108
3109 /* activate cxsr */
3110 I915_WRITE(DSPFW3,
3111 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3112 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3113 } else {
3114 pineview_disable_cxsr(dev);
3115 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3116 }
3117 }
3118
3119 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3120 int planeb_clock, int sr_hdisplay, int sr_htotal,
3121 int pixel_size)
3122 {
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 int total_size, cacheline_size;
3125 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3126 struct intel_watermark_params planea_params, planeb_params;
3127 unsigned long line_time_us;
3128 int sr_clock, sr_entries = 0, entries_required;
3129
3130 /* Create copies of the base settings for each pipe */
3131 planea_params = planeb_params = g4x_wm_info;
3132
3133 /* Grab a couple of global values before we overwrite them */
3134 total_size = planea_params.fifo_size;
3135 cacheline_size = planea_params.cacheline_size;
3136
3137 /*
3138 * Note: we need to make sure we don't overflow for various clock &
3139 * latency values.
3140 * clocks go from a few thousand to several hundred thousand.
3141 * latency is usually a few thousand
3142 */
3143 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3144 1000;
3145 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3146 planea_wm = entries_required + planea_params.guard_size;
3147
3148 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3149 1000;
3150 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3151 planeb_wm = entries_required + planeb_params.guard_size;
3152
3153 cursora_wm = cursorb_wm = 16;
3154 cursor_sr = 32;
3155
3156 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3157
3158 /* Calc sr entries for one plane configs */
3159 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3160 /* self-refresh has much higher latency */
3161 static const int sr_latency_ns = 12000;
3162
3163 sr_clock = planea_clock ? planea_clock : planeb_clock;
3164 line_time_us = ((sr_htotal * 1000) / sr_clock);
3165
3166 /* Use ns/us then divide to preserve precision */
3167 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3168 pixel_size * sr_hdisplay;
3169 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3170
3171 entries_required = (((sr_latency_ns / line_time_us) +
3172 1000) / 1000) * pixel_size * 64;
3173 entries_required = DIV_ROUND_UP(entries_required,
3174 g4x_cursor_wm_info.cacheline_size);
3175 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3176
3177 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3178 cursor_sr = g4x_cursor_wm_info.max_wm;
3179 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3180 "cursor %d\n", sr_entries, cursor_sr);
3181
3182 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3183 } else {
3184 /* Turn off self refresh if both pipes are enabled */
3185 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3186 & ~FW_BLC_SELF_EN);
3187 }
3188
3189 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3190 planea_wm, planeb_wm, sr_entries);
3191
3192 planea_wm &= 0x3f;
3193 planeb_wm &= 0x3f;
3194
3195 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3196 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3197 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3198 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3199 (cursora_wm << DSPFW_CURSORA_SHIFT));
3200 /* HPLL off in SR has some issues on G4x... disable it */
3201 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3202 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3203 }
3204
3205 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3206 int planeb_clock, int sr_hdisplay, int sr_htotal,
3207 int pixel_size)
3208 {
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210 unsigned long line_time_us;
3211 int sr_clock, sr_entries, srwm = 1;
3212 int cursor_sr = 16;
3213
3214 /* Calc sr entries for one plane configs */
3215 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3216 /* self-refresh has much higher latency */
3217 static const int sr_latency_ns = 12000;
3218
3219 sr_clock = planea_clock ? planea_clock : planeb_clock;
3220 line_time_us = ((sr_htotal * 1000) / sr_clock);
3221
3222 /* Use ns/us then divide to preserve precision */
3223 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3224 pixel_size * sr_hdisplay;
3225 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3226 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3227 srwm = I965_FIFO_SIZE - sr_entries;
3228 if (srwm < 0)
3229 srwm = 1;
3230 srwm &= 0x1ff;
3231
3232 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3233 pixel_size * 64;
3234 sr_entries = DIV_ROUND_UP(sr_entries,
3235 i965_cursor_wm_info.cacheline_size);
3236 cursor_sr = i965_cursor_wm_info.fifo_size -
3237 (sr_entries + i965_cursor_wm_info.guard_size);
3238
3239 if (cursor_sr > i965_cursor_wm_info.max_wm)
3240 cursor_sr = i965_cursor_wm_info.max_wm;
3241
3242 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3243 "cursor %d\n", srwm, cursor_sr);
3244
3245 if (IS_I965GM(dev))
3246 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3247 } else {
3248 /* Turn off self refresh if both pipes are enabled */
3249 if (IS_I965GM(dev))
3250 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3251 & ~FW_BLC_SELF_EN);
3252 }
3253
3254 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3255 srwm);
3256
3257 /* 965 has limitations... */
3258 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3259 (8 << 0));
3260 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3261 /* update cursor SR watermark */
3262 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3263 }
3264
3265 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3266 int planeb_clock, int sr_hdisplay, int sr_htotal,
3267 int pixel_size)
3268 {
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 uint32_t fwater_lo;
3271 uint32_t fwater_hi;
3272 int total_size, cacheline_size, cwm, srwm = 1;
3273 int planea_wm, planeb_wm;
3274 struct intel_watermark_params planea_params, planeb_params;
3275 unsigned long line_time_us;
3276 int sr_clock, sr_entries = 0;
3277
3278 /* Create copies of the base settings for each pipe */
3279 if (IS_I965GM(dev) || IS_I945GM(dev))
3280 planea_params = planeb_params = i945_wm_info;
3281 else if (IS_I9XX(dev))
3282 planea_params = planeb_params = i915_wm_info;
3283 else
3284 planea_params = planeb_params = i855_wm_info;
3285
3286 /* Grab a couple of global values before we overwrite them */
3287 total_size = planea_params.fifo_size;
3288 cacheline_size = planea_params.cacheline_size;
3289
3290 /* Update per-plane FIFO sizes */
3291 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3292 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3293
3294 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3295 pixel_size, latency_ns);
3296 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3297 pixel_size, latency_ns);
3298 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3299
3300 /*
3301 * Overlay gets an aggressive default since video jitter is bad.
3302 */
3303 cwm = 2;
3304
3305 /* Calc sr entries for one plane configs */
3306 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3307 (!planea_clock || !planeb_clock)) {
3308 /* self-refresh has much higher latency */
3309 static const int sr_latency_ns = 6000;
3310
3311 sr_clock = planea_clock ? planea_clock : planeb_clock;
3312 line_time_us = ((sr_htotal * 1000) / sr_clock);
3313
3314 /* Use ns/us then divide to preserve precision */
3315 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3316 pixel_size * sr_hdisplay;
3317 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3318 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3319 srwm = total_size - sr_entries;
3320 if (srwm < 0)
3321 srwm = 1;
3322
3323 if (IS_I945G(dev) || IS_I945GM(dev))
3324 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3325 else if (IS_I915GM(dev)) {
3326 /* 915M has a smaller SRWM field */
3327 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3328 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3329 }
3330 } else {
3331 /* Turn off self refresh if both pipes are enabled */
3332 if (IS_I945G(dev) || IS_I945GM(dev)) {
3333 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3334 & ~FW_BLC_SELF_EN);
3335 } else if (IS_I915GM(dev)) {
3336 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3337 }
3338 }
3339
3340 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3341 planea_wm, planeb_wm, cwm, srwm);
3342
3343 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3344 fwater_hi = (cwm & 0x1f);
3345
3346 /* Set request length to 8 cachelines per fetch */
3347 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3348 fwater_hi = fwater_hi | (1 << 8);
3349
3350 I915_WRITE(FW_BLC, fwater_lo);
3351 I915_WRITE(FW_BLC2, fwater_hi);
3352 }
3353
3354 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3355 int unused2, int unused3, int pixel_size)
3356 {
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3359 int planea_wm;
3360
3361 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3362
3363 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3364 pixel_size, latency_ns);
3365 fwater_lo |= (3<<8) | planea_wm;
3366
3367 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3368
3369 I915_WRITE(FW_BLC, fwater_lo);
3370 }
3371
3372 #define ILK_LP0_PLANE_LATENCY 700
3373 #define ILK_LP0_CURSOR_LATENCY 1300
3374
3375 static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3376 int planeb_clock, int sr_hdisplay, int sr_htotal,
3377 int pixel_size)
3378 {
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3381 int sr_wm, cursor_wm;
3382 unsigned long line_time_us;
3383 int sr_clock, entries_required;
3384 u32 reg_value;
3385 int line_count;
3386 int planea_htotal = 0, planeb_htotal = 0;
3387 struct drm_crtc *crtc;
3388
3389 /* Need htotal for all active display plane */
3390 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3393 if (intel_crtc->plane == 0)
3394 planea_htotal = crtc->mode.htotal;
3395 else
3396 planeb_htotal = crtc->mode.htotal;
3397 }
3398 }
3399
3400 /* Calculate and update the watermark for plane A */
3401 if (planea_clock) {
3402 entries_required = ((planea_clock / 1000) * pixel_size *
3403 ILK_LP0_PLANE_LATENCY) / 1000;
3404 entries_required = DIV_ROUND_UP(entries_required,
3405 ironlake_display_wm_info.cacheline_size);
3406 planea_wm = entries_required +
3407 ironlake_display_wm_info.guard_size;
3408
3409 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3410 planea_wm = ironlake_display_wm_info.max_wm;
3411
3412 /* Use the large buffer method to calculate cursor watermark */
3413 line_time_us = (planea_htotal * 1000) / planea_clock;
3414
3415 /* Use ns/us then divide to preserve precision */
3416 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3417
3418 /* calculate the cursor watermark for cursor A */
3419 entries_required = line_count * 64 * pixel_size;
3420 entries_required = DIV_ROUND_UP(entries_required,
3421 ironlake_cursor_wm_info.cacheline_size);
3422 cursora_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3423 if (cursora_wm > ironlake_cursor_wm_info.max_wm)
3424 cursora_wm = ironlake_cursor_wm_info.max_wm;
3425
3426 reg_value = I915_READ(WM0_PIPEA_ILK);
3427 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3428 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3429 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3430 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3431 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3432 "cursor: %d\n", planea_wm, cursora_wm);
3433 }
3434 /* Calculate and update the watermark for plane B */
3435 if (planeb_clock) {
3436 entries_required = ((planeb_clock / 1000) * pixel_size *
3437 ILK_LP0_PLANE_LATENCY) / 1000;
3438 entries_required = DIV_ROUND_UP(entries_required,
3439 ironlake_display_wm_info.cacheline_size);
3440 planeb_wm = entries_required +
3441 ironlake_display_wm_info.guard_size;
3442
3443 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3444 planeb_wm = ironlake_display_wm_info.max_wm;
3445
3446 /* Use the large buffer method to calculate cursor watermark */
3447 line_time_us = (planeb_htotal * 1000) / planeb_clock;
3448
3449 /* Use ns/us then divide to preserve precision */
3450 line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3451
3452 /* calculate the cursor watermark for cursor B */
3453 entries_required = line_count * 64 * pixel_size;
3454 entries_required = DIV_ROUND_UP(entries_required,
3455 ironlake_cursor_wm_info.cacheline_size);
3456 cursorb_wm = entries_required + ironlake_cursor_wm_info.guard_size;
3457 if (cursorb_wm > ironlake_cursor_wm_info.max_wm)
3458 cursorb_wm = ironlake_cursor_wm_info.max_wm;
3459
3460 reg_value = I915_READ(WM0_PIPEB_ILK);
3461 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3462 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3463 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3464 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3465 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3466 "cursor: %d\n", planeb_wm, cursorb_wm);
3467 }
3468
3469 /*
3470 * Calculate and update the self-refresh watermark only when one
3471 * display plane is used.
3472 */
3473 if (!planea_clock || !planeb_clock) {
3474
3475 /* Read the self-refresh latency. The unit is 0.5us */
3476 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3477
3478 sr_clock = planea_clock ? planea_clock : planeb_clock;
3479 line_time_us = ((sr_htotal * 1000) / sr_clock);
3480
3481 /* Use ns/us then divide to preserve precision */
3482 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3483 / 1000;
3484
3485 /* calculate the self-refresh watermark for display plane */
3486 entries_required = line_count * sr_hdisplay * pixel_size;
3487 entries_required = DIV_ROUND_UP(entries_required,
3488 ironlake_display_srwm_info.cacheline_size);
3489 sr_wm = entries_required +
3490 ironlake_display_srwm_info.guard_size;
3491
3492 /* calculate the self-refresh watermark for display cursor */
3493 entries_required = line_count * pixel_size * 64;
3494 entries_required = DIV_ROUND_UP(entries_required,
3495 ironlake_cursor_srwm_info.cacheline_size);
3496 cursor_wm = entries_required +
3497 ironlake_cursor_srwm_info.guard_size;
3498
3499 /* configure watermark and enable self-refresh */
3500 reg_value = I915_READ(WM1_LP_ILK);
3501 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3502 WM1_LP_CURSOR_MASK);
3503 reg_value |= WM1_LP_SR_EN |
3504 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3505 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3506
3507 I915_WRITE(WM1_LP_ILK, reg_value);
3508 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3509 "cursor %d\n", sr_wm, cursor_wm);
3510
3511 } else {
3512 /* Turn off self refresh if both pipes are enabled */
3513 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3514 }
3515 }
3516 /**
3517 * intel_update_watermarks - update FIFO watermark values based on current modes
3518 *
3519 * Calculate watermark values for the various WM regs based on current mode
3520 * and plane configuration.
3521 *
3522 * There are several cases to deal with here:
3523 * - normal (i.e. non-self-refresh)
3524 * - self-refresh (SR) mode
3525 * - lines are large relative to FIFO size (buffer can hold up to 2)
3526 * - lines are small relative to FIFO size (buffer can hold more than 2
3527 * lines), so need to account for TLB latency
3528 *
3529 * The normal calculation is:
3530 * watermark = dotclock * bytes per pixel * latency
3531 * where latency is platform & configuration dependent (we assume pessimal
3532 * values here).
3533 *
3534 * The SR calculation is:
3535 * watermark = (trunc(latency/line time)+1) * surface width *
3536 * bytes per pixel
3537 * where
3538 * line time = htotal / dotclock
3539 * surface width = hdisplay for normal plane and 64 for cursor
3540 * and latency is assumed to be high, as above.
3541 *
3542 * The final value programmed to the register should always be rounded up,
3543 * and include an extra 2 entries to account for clock crossings.
3544 *
3545 * We don't use the sprite, so we can ignore that. And on Crestline we have
3546 * to set the non-SR watermarks to 8.
3547 */
3548 static void intel_update_watermarks(struct drm_device *dev)
3549 {
3550 struct drm_i915_private *dev_priv = dev->dev_private;
3551 struct drm_crtc *crtc;
3552 int sr_hdisplay = 0;
3553 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3554 int enabled = 0, pixel_size = 0;
3555 int sr_htotal = 0;
3556
3557 if (!dev_priv->display.update_wm)
3558 return;
3559
3560 /* Get the clock config from both planes */
3561 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3564 enabled++;
3565 if (intel_crtc->plane == 0) {
3566 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3567 intel_crtc->pipe, crtc->mode.clock);
3568 planea_clock = crtc->mode.clock;
3569 } else {
3570 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3571 intel_crtc->pipe, crtc->mode.clock);
3572 planeb_clock = crtc->mode.clock;
3573 }
3574 sr_hdisplay = crtc->mode.hdisplay;
3575 sr_clock = crtc->mode.clock;
3576 sr_htotal = crtc->mode.htotal;
3577 if (crtc->fb)
3578 pixel_size = crtc->fb->bits_per_pixel / 8;
3579 else
3580 pixel_size = 4; /* by default */
3581 }
3582 }
3583
3584 if (enabled <= 0)
3585 return;
3586
3587 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3588 sr_hdisplay, sr_htotal, pixel_size);
3589 }
3590
3591 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3592 struct drm_display_mode *mode,
3593 struct drm_display_mode *adjusted_mode,
3594 int x, int y,
3595 struct drm_framebuffer *old_fb)
3596 {
3597 struct drm_device *dev = crtc->dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600 int pipe = intel_crtc->pipe;
3601 int plane = intel_crtc->plane;
3602 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
3603 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3604 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
3605 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
3606 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
3607 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
3608 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
3609 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
3610 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
3611 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
3612 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
3613 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
3614 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
3615 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
3616 int refclk, num_connectors = 0;
3617 intel_clock_t clock, reduced_clock;
3618 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3619 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3620 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3621 struct intel_encoder *has_edp_encoder = NULL;
3622 struct drm_mode_config *mode_config = &dev->mode_config;
3623 struct drm_encoder *encoder;
3624 const intel_limit_t *limit;
3625 int ret;
3626 struct fdi_m_n m_n = {0};
3627 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
3628 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
3629 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
3630 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
3631 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
3632 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
3633 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3634 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3635 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
3636 int lvds_reg = LVDS;
3637 u32 temp;
3638 int target_clock;
3639
3640 drm_vblank_pre_modeset(dev, pipe);
3641
3642 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3643 struct intel_encoder *intel_encoder;
3644
3645 if (encoder->crtc != crtc)
3646 continue;
3647
3648 intel_encoder = to_intel_encoder(encoder);
3649 switch (intel_encoder->type) {
3650 case INTEL_OUTPUT_LVDS:
3651 is_lvds = true;
3652 break;
3653 case INTEL_OUTPUT_SDVO:
3654 case INTEL_OUTPUT_HDMI:
3655 is_sdvo = true;
3656 if (intel_encoder->needs_tv_clock)
3657 is_tv = true;
3658 break;
3659 case INTEL_OUTPUT_DVO:
3660 is_dvo = true;
3661 break;
3662 case INTEL_OUTPUT_TVOUT:
3663 is_tv = true;
3664 break;
3665 case INTEL_OUTPUT_ANALOG:
3666 is_crt = true;
3667 break;
3668 case INTEL_OUTPUT_DISPLAYPORT:
3669 is_dp = true;
3670 break;
3671 case INTEL_OUTPUT_EDP:
3672 has_edp_encoder = intel_encoder;
3673 break;
3674 }
3675
3676 num_connectors++;
3677 }
3678
3679 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3680 refclk = dev_priv->lvds_ssc_freq * 1000;
3681 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3682 refclk / 1000);
3683 } else if (IS_I9XX(dev)) {
3684 refclk = 96000;
3685 if (HAS_PCH_SPLIT(dev))
3686 refclk = 120000; /* 120Mhz refclk */
3687 } else {
3688 refclk = 48000;
3689 }
3690
3691
3692 /*
3693 * Returns a set of divisors for the desired target clock with the given
3694 * refclk, or FALSE. The returned values represent the clock equation:
3695 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3696 */
3697 limit = intel_limit(crtc);
3698 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3699 if (!ok) {
3700 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3701 drm_vblank_post_modeset(dev, pipe);
3702 return -EINVAL;
3703 }
3704
3705 /* Ensure that the cursor is valid for the new mode before changing... */
3706 intel_crtc_update_cursor(crtc);
3707
3708 if (is_lvds && dev_priv->lvds_downclock_avail) {
3709 has_reduced_clock = limit->find_pll(limit, crtc,
3710 dev_priv->lvds_downclock,
3711 refclk,
3712 &reduced_clock);
3713 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3714 /*
3715 * If the different P is found, it means that we can't
3716 * switch the display clock by using the FP0/FP1.
3717 * In such case we will disable the LVDS downclock
3718 * feature.
3719 */
3720 DRM_DEBUG_KMS("Different P is found for "
3721 "LVDS clock/downclock\n");
3722 has_reduced_clock = 0;
3723 }
3724 }
3725 /* SDVO TV has fixed PLL values depend on its clock range,
3726 this mirrors vbios setting. */
3727 if (is_sdvo && is_tv) {
3728 if (adjusted_mode->clock >= 100000
3729 && adjusted_mode->clock < 140500) {
3730 clock.p1 = 2;
3731 clock.p2 = 10;
3732 clock.n = 3;
3733 clock.m1 = 16;
3734 clock.m2 = 8;
3735 } else if (adjusted_mode->clock >= 140500
3736 && adjusted_mode->clock <= 200000) {
3737 clock.p1 = 1;
3738 clock.p2 = 10;
3739 clock.n = 6;
3740 clock.m1 = 12;
3741 clock.m2 = 8;
3742 }
3743 }
3744
3745 /* FDI link */
3746 if (HAS_PCH_SPLIT(dev)) {
3747 int lane = 0, link_bw, bpp;
3748 /* eDP doesn't require FDI link, so just set DP M/N
3749 according to current link config */
3750 if (has_edp_encoder) {
3751 target_clock = mode->clock;
3752 intel_edp_link_config(has_edp_encoder,
3753 &lane, &link_bw);
3754 } else {
3755 /* DP over FDI requires target mode clock
3756 instead of link clock */
3757 if (is_dp)
3758 target_clock = mode->clock;
3759 else
3760 target_clock = adjusted_mode->clock;
3761 link_bw = 270000;
3762 }
3763
3764 /* determine panel color depth */
3765 temp = I915_READ(pipeconf_reg);
3766 temp &= ~PIPE_BPC_MASK;
3767 if (is_lvds) {
3768 int lvds_reg = I915_READ(PCH_LVDS);
3769 /* the BPC will be 6 if it is 18-bit LVDS panel */
3770 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3771 temp |= PIPE_8BPC;
3772 else
3773 temp |= PIPE_6BPC;
3774 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3775 switch (dev_priv->edp_bpp/3) {
3776 case 8:
3777 temp |= PIPE_8BPC;
3778 break;
3779 case 10:
3780 temp |= PIPE_10BPC;
3781 break;
3782 case 6:
3783 temp |= PIPE_6BPC;
3784 break;
3785 case 12:
3786 temp |= PIPE_12BPC;
3787 break;
3788 }
3789 } else
3790 temp |= PIPE_8BPC;
3791 I915_WRITE(pipeconf_reg, temp);
3792 I915_READ(pipeconf_reg);
3793
3794 switch (temp & PIPE_BPC_MASK) {
3795 case PIPE_8BPC:
3796 bpp = 24;
3797 break;
3798 case PIPE_10BPC:
3799 bpp = 30;
3800 break;
3801 case PIPE_6BPC:
3802 bpp = 18;
3803 break;
3804 case PIPE_12BPC:
3805 bpp = 36;
3806 break;
3807 default:
3808 DRM_ERROR("unknown pipe bpc value\n");
3809 bpp = 24;
3810 }
3811
3812 if (!lane) {
3813 /*
3814 * Account for spread spectrum to avoid
3815 * oversubscribing the link. Max center spread
3816 * is 2.5%; use 5% for safety's sake.
3817 */
3818 u32 bps = target_clock * bpp * 21 / 20;
3819 lane = bps / (link_bw * 8) + 1;
3820 }
3821
3822 intel_crtc->fdi_lanes = lane;
3823
3824 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3825 }
3826
3827 /* Ironlake: try to setup display ref clock before DPLL
3828 * enabling. This is only under driver's control after
3829 * PCH B stepping, previous chipset stepping should be
3830 * ignoring this setting.
3831 */
3832 if (HAS_PCH_SPLIT(dev)) {
3833 temp = I915_READ(PCH_DREF_CONTROL);
3834 /* Always enable nonspread source */
3835 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3836 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3837 I915_WRITE(PCH_DREF_CONTROL, temp);
3838 POSTING_READ(PCH_DREF_CONTROL);
3839
3840 temp &= ~DREF_SSC_SOURCE_MASK;
3841 temp |= DREF_SSC_SOURCE_ENABLE;
3842 I915_WRITE(PCH_DREF_CONTROL, temp);
3843 POSTING_READ(PCH_DREF_CONTROL);
3844
3845 udelay(200);
3846
3847 if (has_edp_encoder) {
3848 if (dev_priv->lvds_use_ssc) {
3849 temp |= DREF_SSC1_ENABLE;
3850 I915_WRITE(PCH_DREF_CONTROL, temp);
3851 POSTING_READ(PCH_DREF_CONTROL);
3852
3853 udelay(200);
3854
3855 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3856 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3857 I915_WRITE(PCH_DREF_CONTROL, temp);
3858 POSTING_READ(PCH_DREF_CONTROL);
3859 } else {
3860 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3861 I915_WRITE(PCH_DREF_CONTROL, temp);
3862 POSTING_READ(PCH_DREF_CONTROL);
3863 }
3864 }
3865 }
3866
3867 if (IS_PINEVIEW(dev)) {
3868 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3869 if (has_reduced_clock)
3870 fp2 = (1 << reduced_clock.n) << 16 |
3871 reduced_clock.m1 << 8 | reduced_clock.m2;
3872 } else {
3873 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3874 if (has_reduced_clock)
3875 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3876 reduced_clock.m2;
3877 }
3878
3879 if (!HAS_PCH_SPLIT(dev))
3880 dpll = DPLL_VGA_MODE_DIS;
3881
3882 if (IS_I9XX(dev)) {
3883 if (is_lvds)
3884 dpll |= DPLLB_MODE_LVDS;
3885 else
3886 dpll |= DPLLB_MODE_DAC_SERIAL;
3887 if (is_sdvo) {
3888 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3889 if (pixel_multiplier > 1) {
3890 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3891 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3892 else if (HAS_PCH_SPLIT(dev))
3893 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3894 }
3895 dpll |= DPLL_DVO_HIGH_SPEED;
3896 }
3897 if (is_dp)
3898 dpll |= DPLL_DVO_HIGH_SPEED;
3899
3900 /* compute bitmask from p1 value */
3901 if (IS_PINEVIEW(dev))
3902 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3903 else {
3904 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3905 /* also FPA1 */
3906 if (HAS_PCH_SPLIT(dev))
3907 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3908 if (IS_G4X(dev) && has_reduced_clock)
3909 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3910 }
3911 switch (clock.p2) {
3912 case 5:
3913 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3914 break;
3915 case 7:
3916 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3917 break;
3918 case 10:
3919 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3920 break;
3921 case 14:
3922 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3923 break;
3924 }
3925 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3926 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3927 } else {
3928 if (is_lvds) {
3929 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3930 } else {
3931 if (clock.p1 == 2)
3932 dpll |= PLL_P1_DIVIDE_BY_TWO;
3933 else
3934 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3935 if (clock.p2 == 4)
3936 dpll |= PLL_P2_DIVIDE_BY_4;
3937 }
3938 }
3939
3940 if (is_sdvo && is_tv)
3941 dpll |= PLL_REF_INPUT_TVCLKINBC;
3942 else if (is_tv)
3943 /* XXX: just matching BIOS for now */
3944 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3945 dpll |= 3;
3946 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3947 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3948 else
3949 dpll |= PLL_REF_INPUT_DREFCLK;
3950
3951 /* setup pipeconf */
3952 pipeconf = I915_READ(pipeconf_reg);
3953
3954 /* Set up the display plane register */
3955 dspcntr = DISPPLANE_GAMMA_ENABLE;
3956
3957 /* Ironlake's plane is forced to pipe, bit 24 is to
3958 enable color space conversion */
3959 if (!HAS_PCH_SPLIT(dev)) {
3960 if (pipe == 0)
3961 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3962 else
3963 dspcntr |= DISPPLANE_SEL_PIPE_B;
3964 }
3965
3966 if (pipe == 0 && !IS_I965G(dev)) {
3967 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3968 * core speed.
3969 *
3970 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3971 * pipe == 0 check?
3972 */
3973 if (mode->clock >
3974 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3975 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3976 else
3977 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3978 }
3979
3980 dspcntr |= DISPLAY_PLANE_ENABLE;
3981 pipeconf |= PIPEACONF_ENABLE;
3982 dpll |= DPLL_VCO_ENABLE;
3983
3984
3985 /* Disable the panel fitter if it was on our pipe */
3986 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3987 I915_WRITE(PFIT_CONTROL, 0);
3988
3989 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3990 drm_mode_debug_printmodeline(mode);
3991
3992 /* assign to Ironlake registers */
3993 if (HAS_PCH_SPLIT(dev)) {
3994 fp_reg = pch_fp_reg;
3995 dpll_reg = pch_dpll_reg;
3996 }
3997
3998 if (!has_edp_encoder) {
3999 I915_WRITE(fp_reg, fp);
4000 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4001 I915_READ(dpll_reg);
4002 udelay(150);
4003 }
4004
4005 /* enable transcoder DPLL */
4006 if (HAS_PCH_CPT(dev)) {
4007 temp = I915_READ(PCH_DPLL_SEL);
4008 if (trans_dpll_sel == 0)
4009 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
4010 else
4011 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
4012 I915_WRITE(PCH_DPLL_SEL, temp);
4013 I915_READ(PCH_DPLL_SEL);
4014 udelay(150);
4015 }
4016
4017 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4018 * This is an exception to the general rule that mode_set doesn't turn
4019 * things on.
4020 */
4021 if (is_lvds) {
4022 u32 lvds;
4023
4024 if (HAS_PCH_SPLIT(dev))
4025 lvds_reg = PCH_LVDS;
4026
4027 lvds = I915_READ(lvds_reg);
4028 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4029 if (pipe == 1) {
4030 if (HAS_PCH_CPT(dev))
4031 lvds |= PORT_TRANS_B_SEL_CPT;
4032 else
4033 lvds |= LVDS_PIPEB_SELECT;
4034 } else {
4035 if (HAS_PCH_CPT(dev))
4036 lvds &= ~PORT_TRANS_SEL_MASK;
4037 else
4038 lvds &= ~LVDS_PIPEB_SELECT;
4039 }
4040 /* set the corresponsding LVDS_BORDER bit */
4041 lvds |= dev_priv->lvds_border_bits;
4042 /* Set the B0-B3 data pairs corresponding to whether we're going to
4043 * set the DPLLs for dual-channel mode or not.
4044 */
4045 if (clock.p2 == 7)
4046 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4047 else
4048 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4049
4050 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4051 * appropriately here, but we need to look more thoroughly into how
4052 * panels behave in the two modes.
4053 */
4054 /* set the dithering flag on non-PCH LVDS as needed */
4055 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4056 if (dev_priv->lvds_dither)
4057 lvds |= LVDS_ENABLE_DITHER;
4058 else
4059 lvds &= ~LVDS_ENABLE_DITHER;
4060 }
4061 I915_WRITE(lvds_reg, lvds);
4062 I915_READ(lvds_reg);
4063 }
4064
4065 /* set the dithering flag and clear for anything other than a panel. */
4066 if (HAS_PCH_SPLIT(dev)) {
4067 pipeconf &= ~PIPECONF_DITHER_EN;
4068 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4069 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4070 pipeconf |= PIPECONF_DITHER_EN;
4071 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4072 }
4073 }
4074
4075 if (is_dp)
4076 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4077 else if (HAS_PCH_SPLIT(dev)) {
4078 /* For non-DP output, clear any trans DP clock recovery setting.*/
4079 if (pipe == 0) {
4080 I915_WRITE(TRANSA_DATA_M1, 0);
4081 I915_WRITE(TRANSA_DATA_N1, 0);
4082 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4083 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4084 } else {
4085 I915_WRITE(TRANSB_DATA_M1, 0);
4086 I915_WRITE(TRANSB_DATA_N1, 0);
4087 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4088 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4089 }
4090 }
4091
4092 if (!has_edp_encoder) {
4093 I915_WRITE(fp_reg, fp);
4094 I915_WRITE(dpll_reg, dpll);
4095 I915_READ(dpll_reg);
4096 /* Wait for the clocks to stabilize. */
4097 udelay(150);
4098
4099 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4100 if (is_sdvo) {
4101 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4102 if (pixel_multiplier > 1)
4103 pixel_multiplier = (pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4104 else
4105 pixel_multiplier = 0;
4106
4107 I915_WRITE(dpll_md_reg,
4108 (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
4109 pixel_multiplier);
4110 } else
4111 I915_WRITE(dpll_md_reg, 0);
4112 } else {
4113 /* write it again -- the BIOS does, after all */
4114 I915_WRITE(dpll_reg, dpll);
4115 }
4116 I915_READ(dpll_reg);
4117 /* Wait for the clocks to stabilize. */
4118 udelay(150);
4119 }
4120
4121 if (is_lvds && has_reduced_clock && i915_powersave) {
4122 I915_WRITE(fp_reg + 4, fp2);
4123 intel_crtc->lowfreq_avail = true;
4124 if (HAS_PIPE_CXSR(dev)) {
4125 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4126 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4127 }
4128 } else {
4129 I915_WRITE(fp_reg + 4, fp);
4130 intel_crtc->lowfreq_avail = false;
4131 if (HAS_PIPE_CXSR(dev)) {
4132 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4133 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4134 }
4135 }
4136
4137 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4138 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4139 /* the chip adds 2 halflines automatically */
4140 adjusted_mode->crtc_vdisplay -= 1;
4141 adjusted_mode->crtc_vtotal -= 1;
4142 adjusted_mode->crtc_vblank_start -= 1;
4143 adjusted_mode->crtc_vblank_end -= 1;
4144 adjusted_mode->crtc_vsync_end -= 1;
4145 adjusted_mode->crtc_vsync_start -= 1;
4146 } else
4147 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4148
4149 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
4150 ((adjusted_mode->crtc_htotal - 1) << 16));
4151 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
4152 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4153 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
4154 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4155 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
4156 ((adjusted_mode->crtc_vtotal - 1) << 16));
4157 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
4158 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4159 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
4160 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4161 /* pipesrc and dspsize control the size that is scaled from, which should
4162 * always be the user's requested size.
4163 */
4164 if (!HAS_PCH_SPLIT(dev)) {
4165 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
4166 (mode->hdisplay - 1));
4167 I915_WRITE(dsppos_reg, 0);
4168 }
4169 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4170
4171 if (HAS_PCH_SPLIT(dev)) {
4172 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
4173 I915_WRITE(data_n1_reg, m_n.gmch_n);
4174 I915_WRITE(link_m1_reg, m_n.link_m);
4175 I915_WRITE(link_n1_reg, m_n.link_n);
4176
4177 if (has_edp_encoder) {
4178 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4179 } else {
4180 /* enable FDI RX PLL too */
4181 temp = I915_READ(fdi_rx_reg);
4182 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
4183 I915_READ(fdi_rx_reg);
4184 udelay(200);
4185
4186 /* enable FDI TX PLL too */
4187 temp = I915_READ(fdi_tx_reg);
4188 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
4189 I915_READ(fdi_tx_reg);
4190
4191 /* enable FDI RX PCDCLK */
4192 temp = I915_READ(fdi_rx_reg);
4193 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
4194 I915_READ(fdi_rx_reg);
4195 udelay(200);
4196 }
4197 }
4198
4199 I915_WRITE(pipeconf_reg, pipeconf);
4200 I915_READ(pipeconf_reg);
4201
4202 intel_wait_for_vblank(dev, pipe);
4203
4204 if (IS_IRONLAKE(dev)) {
4205 /* enable address swizzle for tiling buffer */
4206 temp = I915_READ(DISP_ARB_CTL);
4207 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4208 }
4209
4210 I915_WRITE(dspcntr_reg, dspcntr);
4211
4212 /* Flush the plane changes */
4213 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4214
4215 intel_update_watermarks(dev);
4216
4217 drm_vblank_post_modeset(dev, pipe);
4218
4219 return ret;
4220 }
4221
4222 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4223 void intel_crtc_load_lut(struct drm_crtc *crtc)
4224 {
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4229 int i;
4230
4231 /* The clocks have to be on to load the palette. */
4232 if (!crtc->enabled)
4233 return;
4234
4235 /* use legacy palette for Ironlake */
4236 if (HAS_PCH_SPLIT(dev))
4237 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4238 LGC_PALETTE_B;
4239
4240 for (i = 0; i < 256; i++) {
4241 I915_WRITE(palreg + 4 * i,
4242 (intel_crtc->lut_r[i] << 16) |
4243 (intel_crtc->lut_g[i] << 8) |
4244 intel_crtc->lut_b[i]);
4245 }
4246 }
4247
4248 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4249 {
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4253 bool visible = base != 0;
4254 u32 cntl;
4255
4256 if (intel_crtc->cursor_visible == visible)
4257 return;
4258
4259 cntl = I915_READ(CURACNTR);
4260 if (visible) {
4261 /* On these chipsets we can only modify the base whilst
4262 * the cursor is disabled.
4263 */
4264 I915_WRITE(CURABASE, base);
4265
4266 cntl &= ~(CURSOR_FORMAT_MASK);
4267 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4268 cntl |= CURSOR_ENABLE |
4269 CURSOR_GAMMA_ENABLE |
4270 CURSOR_FORMAT_ARGB;
4271 } else
4272 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4273 I915_WRITE(CURACNTR, cntl);
4274
4275 intel_crtc->cursor_visible = visible;
4276 }
4277
4278 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4279 {
4280 struct drm_device *dev = crtc->dev;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4283 int pipe = intel_crtc->pipe;
4284 bool visible = base != 0;
4285
4286 if (intel_crtc->cursor_visible != visible) {
4287 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4288 if (base) {
4289 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4290 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4291 cntl |= pipe << 28; /* Connect to correct pipe */
4292 } else {
4293 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4294 cntl |= CURSOR_MODE_DISABLE;
4295 }
4296 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4297
4298 intel_crtc->cursor_visible = visible;
4299 }
4300 /* and commit changes on next vblank */
4301 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4302 }
4303
4304 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4305 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4306 {
4307 struct drm_device *dev = crtc->dev;
4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4310 int pipe = intel_crtc->pipe;
4311 int x = intel_crtc->cursor_x;
4312 int y = intel_crtc->cursor_y;
4313 u32 base, pos;
4314 bool visible;
4315
4316 pos = 0;
4317
4318 if (intel_crtc->cursor_on && crtc->fb) {
4319 base = intel_crtc->cursor_addr;
4320 if (x > (int) crtc->fb->width)
4321 base = 0;
4322
4323 if (y > (int) crtc->fb->height)
4324 base = 0;
4325 } else
4326 base = 0;
4327
4328 if (x < 0) {
4329 if (x + intel_crtc->cursor_width < 0)
4330 base = 0;
4331
4332 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4333 x = -x;
4334 }
4335 pos |= x << CURSOR_X_SHIFT;
4336
4337 if (y < 0) {
4338 if (y + intel_crtc->cursor_height < 0)
4339 base = 0;
4340
4341 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4342 y = -y;
4343 }
4344 pos |= y << CURSOR_Y_SHIFT;
4345
4346 visible = base != 0;
4347 if (!visible && !intel_crtc->cursor_visible)
4348 return;
4349
4350 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4351 if (IS_845G(dev) || IS_I865G(dev))
4352 i845_update_cursor(crtc, base);
4353 else
4354 i9xx_update_cursor(crtc, base);
4355
4356 if (visible)
4357 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4358 }
4359
4360 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4361 struct drm_file *file_priv,
4362 uint32_t handle,
4363 uint32_t width, uint32_t height)
4364 {
4365 struct drm_device *dev = crtc->dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4368 struct drm_gem_object *bo;
4369 struct drm_i915_gem_object *obj_priv;
4370 uint32_t addr;
4371 int ret;
4372
4373 DRM_DEBUG_KMS("\n");
4374
4375 /* if we want to turn off the cursor ignore width and height */
4376 if (!handle) {
4377 DRM_DEBUG_KMS("cursor off\n");
4378 addr = 0;
4379 bo = NULL;
4380 mutex_lock(&dev->struct_mutex);
4381 goto finish;
4382 }
4383
4384 /* Currently we only support 64x64 cursors */
4385 if (width != 64 || height != 64) {
4386 DRM_ERROR("we currently only support 64x64 cursors\n");
4387 return -EINVAL;
4388 }
4389
4390 bo = drm_gem_object_lookup(dev, file_priv, handle);
4391 if (!bo)
4392 return -ENOENT;
4393
4394 obj_priv = to_intel_bo(bo);
4395
4396 if (bo->size < width * height * 4) {
4397 DRM_ERROR("buffer is to small\n");
4398 ret = -ENOMEM;
4399 goto fail;
4400 }
4401
4402 /* we only need to pin inside GTT if cursor is non-phy */
4403 mutex_lock(&dev->struct_mutex);
4404 if (!dev_priv->info->cursor_needs_physical) {
4405 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4406 if (ret) {
4407 DRM_ERROR("failed to pin cursor bo\n");
4408 goto fail_locked;
4409 }
4410
4411 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4412 if (ret) {
4413 DRM_ERROR("failed to move cursor bo into the GTT\n");
4414 goto fail_unpin;
4415 }
4416
4417 addr = obj_priv->gtt_offset;
4418 } else {
4419 int align = IS_I830(dev) ? 16 * 1024 : 256;
4420 ret = i915_gem_attach_phys_object(dev, bo,
4421 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4422 align);
4423 if (ret) {
4424 DRM_ERROR("failed to attach phys object\n");
4425 goto fail_locked;
4426 }
4427 addr = obj_priv->phys_obj->handle->busaddr;
4428 }
4429
4430 if (!IS_I9XX(dev))
4431 I915_WRITE(CURSIZE, (height << 12) | width);
4432
4433 finish:
4434 if (intel_crtc->cursor_bo) {
4435 if (dev_priv->info->cursor_needs_physical) {
4436 if (intel_crtc->cursor_bo != bo)
4437 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4438 } else
4439 i915_gem_object_unpin(intel_crtc->cursor_bo);
4440 drm_gem_object_unreference(intel_crtc->cursor_bo);
4441 }
4442
4443 mutex_unlock(&dev->struct_mutex);
4444
4445 intel_crtc->cursor_addr = addr;
4446 intel_crtc->cursor_bo = bo;
4447 intel_crtc->cursor_width = width;
4448 intel_crtc->cursor_height = height;
4449
4450 intel_crtc_update_cursor(crtc);
4451
4452 return 0;
4453 fail_unpin:
4454 i915_gem_object_unpin(bo);
4455 fail_locked:
4456 mutex_unlock(&dev->struct_mutex);
4457 fail:
4458 drm_gem_object_unreference_unlocked(bo);
4459 return ret;
4460 }
4461
4462 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4463 {
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465
4466 intel_crtc->cursor_x = x;
4467 intel_crtc->cursor_y = y;
4468
4469 intel_crtc_update_cursor(crtc);
4470
4471 return 0;
4472 }
4473
4474 /** Sets the color ramps on behalf of RandR */
4475 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4476 u16 blue, int regno)
4477 {
4478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4479
4480 intel_crtc->lut_r[regno] = red >> 8;
4481 intel_crtc->lut_g[regno] = green >> 8;
4482 intel_crtc->lut_b[regno] = blue >> 8;
4483 }
4484
4485 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4486 u16 *blue, int regno)
4487 {
4488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4489
4490 *red = intel_crtc->lut_r[regno] << 8;
4491 *green = intel_crtc->lut_g[regno] << 8;
4492 *blue = intel_crtc->lut_b[regno] << 8;
4493 }
4494
4495 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4496 u16 *blue, uint32_t start, uint32_t size)
4497 {
4498 int end = (start + size > 256) ? 256 : start + size, i;
4499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4500
4501 for (i = start; i < end; i++) {
4502 intel_crtc->lut_r[i] = red[i] >> 8;
4503 intel_crtc->lut_g[i] = green[i] >> 8;
4504 intel_crtc->lut_b[i] = blue[i] >> 8;
4505 }
4506
4507 intel_crtc_load_lut(crtc);
4508 }
4509
4510 /**
4511 * Get a pipe with a simple mode set on it for doing load-based monitor
4512 * detection.
4513 *
4514 * It will be up to the load-detect code to adjust the pipe as appropriate for
4515 * its requirements. The pipe will be connected to no other encoders.
4516 *
4517 * Currently this code will only succeed if there is a pipe with no encoders
4518 * configured for it. In the future, it could choose to temporarily disable
4519 * some outputs to free up a pipe for its use.
4520 *
4521 * \return crtc, or NULL if no pipes are available.
4522 */
4523
4524 /* VESA 640x480x72Hz mode to set on the pipe */
4525 static struct drm_display_mode load_detect_mode = {
4526 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4527 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4528 };
4529
4530 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4531 struct drm_connector *connector,
4532 struct drm_display_mode *mode,
4533 int *dpms_mode)
4534 {
4535 struct intel_crtc *intel_crtc;
4536 struct drm_crtc *possible_crtc;
4537 struct drm_crtc *supported_crtc =NULL;
4538 struct drm_encoder *encoder = &intel_encoder->base;
4539 struct drm_crtc *crtc = NULL;
4540 struct drm_device *dev = encoder->dev;
4541 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4542 struct drm_crtc_helper_funcs *crtc_funcs;
4543 int i = -1;
4544
4545 /*
4546 * Algorithm gets a little messy:
4547 * - if the connector already has an assigned crtc, use it (but make
4548 * sure it's on first)
4549 * - try to find the first unused crtc that can drive this connector,
4550 * and use that if we find one
4551 * - if there are no unused crtcs available, try to use the first
4552 * one we found that supports the connector
4553 */
4554
4555 /* See if we already have a CRTC for this connector */
4556 if (encoder->crtc) {
4557 crtc = encoder->crtc;
4558 /* Make sure the crtc and connector are running */
4559 intel_crtc = to_intel_crtc(crtc);
4560 *dpms_mode = intel_crtc->dpms_mode;
4561 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4562 crtc_funcs = crtc->helper_private;
4563 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4564 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4565 }
4566 return crtc;
4567 }
4568
4569 /* Find an unused one (if possible) */
4570 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4571 i++;
4572 if (!(encoder->possible_crtcs & (1 << i)))
4573 continue;
4574 if (!possible_crtc->enabled) {
4575 crtc = possible_crtc;
4576 break;
4577 }
4578 if (!supported_crtc)
4579 supported_crtc = possible_crtc;
4580 }
4581
4582 /*
4583 * If we didn't find an unused CRTC, don't use any.
4584 */
4585 if (!crtc) {
4586 return NULL;
4587 }
4588
4589 encoder->crtc = crtc;
4590 connector->encoder = encoder;
4591 intel_encoder->load_detect_temp = true;
4592
4593 intel_crtc = to_intel_crtc(crtc);
4594 *dpms_mode = intel_crtc->dpms_mode;
4595
4596 if (!crtc->enabled) {
4597 if (!mode)
4598 mode = &load_detect_mode;
4599 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4600 } else {
4601 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4602 crtc_funcs = crtc->helper_private;
4603 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4604 }
4605
4606 /* Add this connector to the crtc */
4607 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4608 encoder_funcs->commit(encoder);
4609 }
4610 /* let the connector get through one full cycle before testing */
4611 intel_wait_for_vblank(dev, intel_crtc->pipe);
4612
4613 return crtc;
4614 }
4615
4616 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4617 struct drm_connector *connector, int dpms_mode)
4618 {
4619 struct drm_encoder *encoder = &intel_encoder->base;
4620 struct drm_device *dev = encoder->dev;
4621 struct drm_crtc *crtc = encoder->crtc;
4622 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4623 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4624
4625 if (intel_encoder->load_detect_temp) {
4626 encoder->crtc = NULL;
4627 connector->encoder = NULL;
4628 intel_encoder->load_detect_temp = false;
4629 crtc->enabled = drm_helper_crtc_in_use(crtc);
4630 drm_helper_disable_unused_functions(dev);
4631 }
4632
4633 /* Switch crtc and encoder back off if necessary */
4634 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4635 if (encoder->crtc == crtc)
4636 encoder_funcs->dpms(encoder, dpms_mode);
4637 crtc_funcs->dpms(crtc, dpms_mode);
4638 }
4639 }
4640
4641 /* Returns the clock of the currently programmed mode of the given pipe. */
4642 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4643 {
4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4646 int pipe = intel_crtc->pipe;
4647 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4648 u32 fp;
4649 intel_clock_t clock;
4650
4651 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4652 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4653 else
4654 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4655
4656 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4657 if (IS_PINEVIEW(dev)) {
4658 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4659 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4660 } else {
4661 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4662 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4663 }
4664
4665 if (IS_I9XX(dev)) {
4666 if (IS_PINEVIEW(dev))
4667 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4668 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4669 else
4670 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4671 DPLL_FPA01_P1_POST_DIV_SHIFT);
4672
4673 switch (dpll & DPLL_MODE_MASK) {
4674 case DPLLB_MODE_DAC_SERIAL:
4675 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4676 5 : 10;
4677 break;
4678 case DPLLB_MODE_LVDS:
4679 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4680 7 : 14;
4681 break;
4682 default:
4683 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4684 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4685 return 0;
4686 }
4687
4688 /* XXX: Handle the 100Mhz refclk */
4689 intel_clock(dev, 96000, &clock);
4690 } else {
4691 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4692
4693 if (is_lvds) {
4694 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4695 DPLL_FPA01_P1_POST_DIV_SHIFT);
4696 clock.p2 = 14;
4697
4698 if ((dpll & PLL_REF_INPUT_MASK) ==
4699 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4700 /* XXX: might not be 66MHz */
4701 intel_clock(dev, 66000, &clock);
4702 } else
4703 intel_clock(dev, 48000, &clock);
4704 } else {
4705 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4706 clock.p1 = 2;
4707 else {
4708 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4709 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4710 }
4711 if (dpll & PLL_P2_DIVIDE_BY_4)
4712 clock.p2 = 4;
4713 else
4714 clock.p2 = 2;
4715
4716 intel_clock(dev, 48000, &clock);
4717 }
4718 }
4719
4720 /* XXX: It would be nice to validate the clocks, but we can't reuse
4721 * i830PllIsValid() because it relies on the xf86_config connector
4722 * configuration being accurate, which it isn't necessarily.
4723 */
4724
4725 return clock.dot;
4726 }
4727
4728 /** Returns the currently programmed mode of the given pipe. */
4729 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4730 struct drm_crtc *crtc)
4731 {
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734 int pipe = intel_crtc->pipe;
4735 struct drm_display_mode *mode;
4736 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4737 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4738 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4739 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4740
4741 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4742 if (!mode)
4743 return NULL;
4744
4745 mode->clock = intel_crtc_clock_get(dev, crtc);
4746 mode->hdisplay = (htot & 0xffff) + 1;
4747 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4748 mode->hsync_start = (hsync & 0xffff) + 1;
4749 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4750 mode->vdisplay = (vtot & 0xffff) + 1;
4751 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4752 mode->vsync_start = (vsync & 0xffff) + 1;
4753 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4754
4755 drm_mode_set_name(mode);
4756 drm_mode_set_crtcinfo(mode, 0);
4757
4758 return mode;
4759 }
4760
4761 #define GPU_IDLE_TIMEOUT 500 /* ms */
4762
4763 /* When this timer fires, we've been idle for awhile */
4764 static void intel_gpu_idle_timer(unsigned long arg)
4765 {
4766 struct drm_device *dev = (struct drm_device *)arg;
4767 drm_i915_private_t *dev_priv = dev->dev_private;
4768
4769 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4770
4771 dev_priv->busy = false;
4772
4773 queue_work(dev_priv->wq, &dev_priv->idle_work);
4774 }
4775
4776 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4777
4778 static void intel_crtc_idle_timer(unsigned long arg)
4779 {
4780 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4781 struct drm_crtc *crtc = &intel_crtc->base;
4782 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4783
4784 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4785
4786 intel_crtc->busy = false;
4787
4788 queue_work(dev_priv->wq, &dev_priv->idle_work);
4789 }
4790
4791 static void intel_increase_pllclock(struct drm_crtc *crtc)
4792 {
4793 struct drm_device *dev = crtc->dev;
4794 drm_i915_private_t *dev_priv = dev->dev_private;
4795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4796 int pipe = intel_crtc->pipe;
4797 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4798 int dpll = I915_READ(dpll_reg);
4799
4800 if (HAS_PCH_SPLIT(dev))
4801 return;
4802
4803 if (!dev_priv->lvds_downclock_avail)
4804 return;
4805
4806 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4807 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4808
4809 /* Unlock panel regs */
4810 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4811 PANEL_UNLOCK_REGS);
4812
4813 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4814 I915_WRITE(dpll_reg, dpll);
4815 dpll = I915_READ(dpll_reg);
4816 intel_wait_for_vblank(dev, pipe);
4817 dpll = I915_READ(dpll_reg);
4818 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4819 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4820
4821 /* ...and lock them again */
4822 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4823 }
4824
4825 /* Schedule downclock */
4826 mod_timer(&intel_crtc->idle_timer, jiffies +
4827 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4828 }
4829
4830 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4831 {
4832 struct drm_device *dev = crtc->dev;
4833 drm_i915_private_t *dev_priv = dev->dev_private;
4834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835 int pipe = intel_crtc->pipe;
4836 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4837 int dpll = I915_READ(dpll_reg);
4838
4839 if (HAS_PCH_SPLIT(dev))
4840 return;
4841
4842 if (!dev_priv->lvds_downclock_avail)
4843 return;
4844
4845 /*
4846 * Since this is called by a timer, we should never get here in
4847 * the manual case.
4848 */
4849 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4850 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4851
4852 /* Unlock panel regs */
4853 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4854 PANEL_UNLOCK_REGS);
4855
4856 dpll |= DISPLAY_RATE_SELECT_FPA1;
4857 I915_WRITE(dpll_reg, dpll);
4858 dpll = I915_READ(dpll_reg);
4859 intel_wait_for_vblank(dev, pipe);
4860 dpll = I915_READ(dpll_reg);
4861 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4862 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4863
4864 /* ...and lock them again */
4865 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4866 }
4867
4868 }
4869
4870 /**
4871 * intel_idle_update - adjust clocks for idleness
4872 * @work: work struct
4873 *
4874 * Either the GPU or display (or both) went idle. Check the busy status
4875 * here and adjust the CRTC and GPU clocks as necessary.
4876 */
4877 static void intel_idle_update(struct work_struct *work)
4878 {
4879 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4880 idle_work);
4881 struct drm_device *dev = dev_priv->dev;
4882 struct drm_crtc *crtc;
4883 struct intel_crtc *intel_crtc;
4884 int enabled = 0;
4885
4886 if (!i915_powersave)
4887 return;
4888
4889 mutex_lock(&dev->struct_mutex);
4890
4891 i915_update_gfx_val(dev_priv);
4892
4893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4894 /* Skip inactive CRTCs */
4895 if (!crtc->fb)
4896 continue;
4897
4898 enabled++;
4899 intel_crtc = to_intel_crtc(crtc);
4900 if (!intel_crtc->busy)
4901 intel_decrease_pllclock(crtc);
4902 }
4903
4904 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4905 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4906 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4907 }
4908
4909 mutex_unlock(&dev->struct_mutex);
4910 }
4911
4912 /**
4913 * intel_mark_busy - mark the GPU and possibly the display busy
4914 * @dev: drm device
4915 * @obj: object we're operating on
4916 *
4917 * Callers can use this function to indicate that the GPU is busy processing
4918 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4919 * buffer), we'll also mark the display as busy, so we know to increase its
4920 * clock frequency.
4921 */
4922 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4923 {
4924 drm_i915_private_t *dev_priv = dev->dev_private;
4925 struct drm_crtc *crtc = NULL;
4926 struct intel_framebuffer *intel_fb;
4927 struct intel_crtc *intel_crtc;
4928
4929 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4930 return;
4931
4932 if (!dev_priv->busy) {
4933 if (IS_I945G(dev) || IS_I945GM(dev)) {
4934 u32 fw_blc_self;
4935
4936 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4937 fw_blc_self = I915_READ(FW_BLC_SELF);
4938 fw_blc_self &= ~FW_BLC_SELF_EN;
4939 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4940 }
4941 dev_priv->busy = true;
4942 } else
4943 mod_timer(&dev_priv->idle_timer, jiffies +
4944 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4945
4946 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4947 if (!crtc->fb)
4948 continue;
4949
4950 intel_crtc = to_intel_crtc(crtc);
4951 intel_fb = to_intel_framebuffer(crtc->fb);
4952 if (intel_fb->obj == obj) {
4953 if (!intel_crtc->busy) {
4954 if (IS_I945G(dev) || IS_I945GM(dev)) {
4955 u32 fw_blc_self;
4956
4957 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4958 fw_blc_self = I915_READ(FW_BLC_SELF);
4959 fw_blc_self &= ~FW_BLC_SELF_EN;
4960 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4961 }
4962 /* Non-busy -> busy, upclock */
4963 intel_increase_pllclock(crtc);
4964 intel_crtc->busy = true;
4965 } else {
4966 /* Busy -> busy, put off timer */
4967 mod_timer(&intel_crtc->idle_timer, jiffies +
4968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4969 }
4970 }
4971 }
4972 }
4973
4974 static void intel_crtc_destroy(struct drm_crtc *crtc)
4975 {
4976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4977 struct drm_device *dev = crtc->dev;
4978 struct intel_unpin_work *work;
4979 unsigned long flags;
4980
4981 spin_lock_irqsave(&dev->event_lock, flags);
4982 work = intel_crtc->unpin_work;
4983 intel_crtc->unpin_work = NULL;
4984 spin_unlock_irqrestore(&dev->event_lock, flags);
4985
4986 if (work) {
4987 cancel_work_sync(&work->work);
4988 kfree(work);
4989 }
4990
4991 drm_crtc_cleanup(crtc);
4992
4993 kfree(intel_crtc);
4994 }
4995
4996 static void intel_unpin_work_fn(struct work_struct *__work)
4997 {
4998 struct intel_unpin_work *work =
4999 container_of(__work, struct intel_unpin_work, work);
5000
5001 mutex_lock(&work->dev->struct_mutex);
5002 i915_gem_object_unpin(work->old_fb_obj);
5003 drm_gem_object_unreference(work->pending_flip_obj);
5004 drm_gem_object_unreference(work->old_fb_obj);
5005 mutex_unlock(&work->dev->struct_mutex);
5006 kfree(work);
5007 }
5008
5009 static void do_intel_finish_page_flip(struct drm_device *dev,
5010 struct drm_crtc *crtc)
5011 {
5012 drm_i915_private_t *dev_priv = dev->dev_private;
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 struct intel_unpin_work *work;
5015 struct drm_i915_gem_object *obj_priv;
5016 struct drm_pending_vblank_event *e;
5017 struct timeval now;
5018 unsigned long flags;
5019
5020 /* Ignore early vblank irqs */
5021 if (intel_crtc == NULL)
5022 return;
5023
5024 spin_lock_irqsave(&dev->event_lock, flags);
5025 work = intel_crtc->unpin_work;
5026 if (work == NULL || !work->pending) {
5027 spin_unlock_irqrestore(&dev->event_lock, flags);
5028 return;
5029 }
5030
5031 intel_crtc->unpin_work = NULL;
5032 drm_vblank_put(dev, intel_crtc->pipe);
5033
5034 if (work->event) {
5035 e = work->event;
5036 do_gettimeofday(&now);
5037 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
5038 e->event.tv_sec = now.tv_sec;
5039 e->event.tv_usec = now.tv_usec;
5040 list_add_tail(&e->base.link,
5041 &e->base.file_priv->event_list);
5042 wake_up_interruptible(&e->base.file_priv->event_wait);
5043 }
5044
5045 spin_unlock_irqrestore(&dev->event_lock, flags);
5046
5047 obj_priv = to_intel_bo(work->pending_flip_obj);
5048
5049 /* Initial scanout buffer will have a 0 pending flip count */
5050 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
5051 atomic_dec_and_test(&obj_priv->pending_flip))
5052 DRM_WAKEUP(&dev_priv->pending_flip_queue);
5053 schedule_work(&work->work);
5054
5055 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5056 }
5057
5058 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5059 {
5060 drm_i915_private_t *dev_priv = dev->dev_private;
5061 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5062
5063 do_intel_finish_page_flip(dev, crtc);
5064 }
5065
5066 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5067 {
5068 drm_i915_private_t *dev_priv = dev->dev_private;
5069 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5070
5071 do_intel_finish_page_flip(dev, crtc);
5072 }
5073
5074 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5075 {
5076 drm_i915_private_t *dev_priv = dev->dev_private;
5077 struct intel_crtc *intel_crtc =
5078 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5079 unsigned long flags;
5080
5081 spin_lock_irqsave(&dev->event_lock, flags);
5082 if (intel_crtc->unpin_work) {
5083 if ((++intel_crtc->unpin_work->pending) > 1)
5084 DRM_ERROR("Prepared flip multiple times\n");
5085 } else {
5086 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5087 }
5088 spin_unlock_irqrestore(&dev->event_lock, flags);
5089 }
5090
5091 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5092 struct drm_framebuffer *fb,
5093 struct drm_pending_vblank_event *event)
5094 {
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 struct intel_framebuffer *intel_fb;
5098 struct drm_i915_gem_object *obj_priv;
5099 struct drm_gem_object *obj;
5100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5101 struct intel_unpin_work *work;
5102 unsigned long flags, offset;
5103 int pipe = intel_crtc->pipe;
5104 u32 pf, pipesrc;
5105 int ret;
5106
5107 work = kzalloc(sizeof *work, GFP_KERNEL);
5108 if (work == NULL)
5109 return -ENOMEM;
5110
5111 work->event = event;
5112 work->dev = crtc->dev;
5113 intel_fb = to_intel_framebuffer(crtc->fb);
5114 work->old_fb_obj = intel_fb->obj;
5115 INIT_WORK(&work->work, intel_unpin_work_fn);
5116
5117 /* We borrow the event spin lock for protecting unpin_work */
5118 spin_lock_irqsave(&dev->event_lock, flags);
5119 if (intel_crtc->unpin_work) {
5120 spin_unlock_irqrestore(&dev->event_lock, flags);
5121 kfree(work);
5122
5123 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5124 return -EBUSY;
5125 }
5126 intel_crtc->unpin_work = work;
5127 spin_unlock_irqrestore(&dev->event_lock, flags);
5128
5129 intel_fb = to_intel_framebuffer(fb);
5130 obj = intel_fb->obj;
5131
5132 mutex_lock(&dev->struct_mutex);
5133 ret = intel_pin_and_fence_fb_obj(dev, obj);
5134 if (ret)
5135 goto cleanup_work;
5136
5137 /* Reference the objects for the scheduled work. */
5138 drm_gem_object_reference(work->old_fb_obj);
5139 drm_gem_object_reference(obj);
5140
5141 crtc->fb = fb;
5142 ret = i915_gem_object_flush_write_domain(obj);
5143 if (ret)
5144 goto cleanup_objs;
5145
5146 ret = drm_vblank_get(dev, intel_crtc->pipe);
5147 if (ret)
5148 goto cleanup_objs;
5149
5150 obj_priv = to_intel_bo(obj);
5151 atomic_inc(&obj_priv->pending_flip);
5152 work->pending_flip_obj = obj;
5153
5154 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5155 u32 flip_mask;
5156
5157 if (intel_crtc->plane)
5158 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5159 else
5160 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5161
5162 BEGIN_LP_RING(2);
5163 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5164 OUT_RING(0);
5165 ADVANCE_LP_RING();
5166 }
5167
5168 work->enable_stall_check = true;
5169
5170 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5171 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5172
5173 BEGIN_LP_RING(4);
5174 switch(INTEL_INFO(dev)->gen) {
5175 case 2:
5176 OUT_RING(MI_DISPLAY_FLIP |
5177 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5178 OUT_RING(fb->pitch);
5179 OUT_RING(obj_priv->gtt_offset + offset);
5180 OUT_RING(MI_NOOP);
5181 break;
5182
5183 case 3:
5184 OUT_RING(MI_DISPLAY_FLIP_I915 |
5185 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5186 OUT_RING(fb->pitch);
5187 OUT_RING(obj_priv->gtt_offset + offset);
5188 OUT_RING(MI_NOOP);
5189 break;
5190
5191 case 4:
5192 case 5:
5193 /* i965+ uses the linear or tiled offsets from the
5194 * Display Registers (which do not change across a page-flip)
5195 * so we need only reprogram the base address.
5196 */
5197 OUT_RING(MI_DISPLAY_FLIP |
5198 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5199 OUT_RING(fb->pitch);
5200 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5201
5202 /* XXX Enabling the panel-fitter across page-flip is so far
5203 * untested on non-native modes, so ignore it for now.
5204 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5205 */
5206 pf = 0;
5207 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5208 OUT_RING(pf | pipesrc);
5209 break;
5210
5211 case 6:
5212 OUT_RING(MI_DISPLAY_FLIP |
5213 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5214 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5215 OUT_RING(obj_priv->gtt_offset);
5216
5217 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5218 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5219 OUT_RING(pf | pipesrc);
5220 break;
5221 }
5222 ADVANCE_LP_RING();
5223
5224 mutex_unlock(&dev->struct_mutex);
5225
5226 trace_i915_flip_request(intel_crtc->plane, obj);
5227
5228 return 0;
5229
5230 cleanup_objs:
5231 drm_gem_object_unreference(work->old_fb_obj);
5232 drm_gem_object_unreference(obj);
5233 cleanup_work:
5234 mutex_unlock(&dev->struct_mutex);
5235
5236 spin_lock_irqsave(&dev->event_lock, flags);
5237 intel_crtc->unpin_work = NULL;
5238 spin_unlock_irqrestore(&dev->event_lock, flags);
5239
5240 kfree(work);
5241
5242 return ret;
5243 }
5244
5245 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5246 .dpms = intel_crtc_dpms,
5247 .mode_fixup = intel_crtc_mode_fixup,
5248 .mode_set = intel_crtc_mode_set,
5249 .mode_set_base = intel_pipe_set_base,
5250 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5251 .load_lut = intel_crtc_load_lut,
5252 };
5253
5254 static const struct drm_crtc_funcs intel_crtc_funcs = {
5255 .cursor_set = intel_crtc_cursor_set,
5256 .cursor_move = intel_crtc_cursor_move,
5257 .gamma_set = intel_crtc_gamma_set,
5258 .set_config = drm_crtc_helper_set_config,
5259 .destroy = intel_crtc_destroy,
5260 .page_flip = intel_crtc_page_flip,
5261 };
5262
5263
5264 static void intel_crtc_init(struct drm_device *dev, int pipe)
5265 {
5266 drm_i915_private_t *dev_priv = dev->dev_private;
5267 struct intel_crtc *intel_crtc;
5268 int i;
5269
5270 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5271 if (intel_crtc == NULL)
5272 return;
5273
5274 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5275
5276 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5277 intel_crtc->pipe = pipe;
5278 intel_crtc->plane = pipe;
5279 for (i = 0; i < 256; i++) {
5280 intel_crtc->lut_r[i] = i;
5281 intel_crtc->lut_g[i] = i;
5282 intel_crtc->lut_b[i] = i;
5283 }
5284
5285 /* Swap pipes & planes for FBC on pre-965 */
5286 intel_crtc->pipe = pipe;
5287 intel_crtc->plane = pipe;
5288 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5289 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5290 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5291 }
5292
5293 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5294 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5295 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5296 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5297
5298 intel_crtc->cursor_addr = 0;
5299 intel_crtc->dpms_mode = -1;
5300
5301 if (HAS_PCH_SPLIT(dev)) {
5302 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5303 intel_helper_funcs.commit = ironlake_crtc_commit;
5304 } else {
5305 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5306 intel_helper_funcs.commit = i9xx_crtc_commit;
5307 }
5308
5309 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5310
5311 intel_crtc->busy = false;
5312
5313 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5314 (unsigned long)intel_crtc);
5315 }
5316
5317 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5318 struct drm_file *file_priv)
5319 {
5320 drm_i915_private_t *dev_priv = dev->dev_private;
5321 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5322 struct drm_mode_object *drmmode_obj;
5323 struct intel_crtc *crtc;
5324
5325 if (!dev_priv) {
5326 DRM_ERROR("called with no initialization\n");
5327 return -EINVAL;
5328 }
5329
5330 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5331 DRM_MODE_OBJECT_CRTC);
5332
5333 if (!drmmode_obj) {
5334 DRM_ERROR("no such CRTC id\n");
5335 return -EINVAL;
5336 }
5337
5338 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5339 pipe_from_crtc_id->pipe = crtc->pipe;
5340
5341 return 0;
5342 }
5343
5344 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5345 {
5346 struct intel_encoder *encoder;
5347 int index_mask = 0;
5348 int entry = 0;
5349
5350 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5351 if (type_mask & encoder->clone_mask)
5352 index_mask |= (1 << entry);
5353 entry++;
5354 }
5355
5356 return index_mask;
5357 }
5358
5359 static void intel_setup_outputs(struct drm_device *dev)
5360 {
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 struct intel_encoder *encoder;
5363 bool dpd_is_edp = false;
5364
5365 if (IS_MOBILE(dev) && !IS_I830(dev))
5366 intel_lvds_init(dev);
5367
5368 if (HAS_PCH_SPLIT(dev)) {
5369 dpd_is_edp = intel_dpd_is_edp(dev);
5370
5371 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5372 intel_dp_init(dev, DP_A);
5373
5374 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5375 intel_dp_init(dev, PCH_DP_D);
5376 }
5377
5378 intel_crt_init(dev);
5379
5380 if (HAS_PCH_SPLIT(dev)) {
5381 int found;
5382
5383 if (I915_READ(HDMIB) & PORT_DETECTED) {
5384 /* PCH SDVOB multiplex with HDMIB */
5385 found = intel_sdvo_init(dev, PCH_SDVOB);
5386 if (!found)
5387 intel_hdmi_init(dev, HDMIB);
5388 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5389 intel_dp_init(dev, PCH_DP_B);
5390 }
5391
5392 if (I915_READ(HDMIC) & PORT_DETECTED)
5393 intel_hdmi_init(dev, HDMIC);
5394
5395 if (I915_READ(HDMID) & PORT_DETECTED)
5396 intel_hdmi_init(dev, HDMID);
5397
5398 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5399 intel_dp_init(dev, PCH_DP_C);
5400
5401 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5402 intel_dp_init(dev, PCH_DP_D);
5403
5404 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5405 bool found = false;
5406
5407 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5408 DRM_DEBUG_KMS("probing SDVOB\n");
5409 found = intel_sdvo_init(dev, SDVOB);
5410 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5411 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5412 intel_hdmi_init(dev, SDVOB);
5413 }
5414
5415 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5416 DRM_DEBUG_KMS("probing DP_B\n");
5417 intel_dp_init(dev, DP_B);
5418 }
5419 }
5420
5421 /* Before G4X SDVOC doesn't have its own detect register */
5422
5423 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5424 DRM_DEBUG_KMS("probing SDVOC\n");
5425 found = intel_sdvo_init(dev, SDVOC);
5426 }
5427
5428 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5429
5430 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5431 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5432 intel_hdmi_init(dev, SDVOC);
5433 }
5434 if (SUPPORTS_INTEGRATED_DP(dev)) {
5435 DRM_DEBUG_KMS("probing DP_C\n");
5436 intel_dp_init(dev, DP_C);
5437 }
5438 }
5439
5440 if (SUPPORTS_INTEGRATED_DP(dev) &&
5441 (I915_READ(DP_D) & DP_DETECTED)) {
5442 DRM_DEBUG_KMS("probing DP_D\n");
5443 intel_dp_init(dev, DP_D);
5444 }
5445 } else if (IS_GEN2(dev))
5446 intel_dvo_init(dev);
5447
5448 if (SUPPORTS_TV(dev))
5449 intel_tv_init(dev);
5450
5451 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5452 encoder->base.possible_crtcs = encoder->crtc_mask;
5453 encoder->base.possible_clones =
5454 intel_encoder_clones(dev, encoder->clone_mask);
5455 }
5456 }
5457
5458 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5459 {
5460 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5461
5462 drm_framebuffer_cleanup(fb);
5463 drm_gem_object_unreference_unlocked(intel_fb->obj);
5464
5465 kfree(intel_fb);
5466 }
5467
5468 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5469 struct drm_file *file_priv,
5470 unsigned int *handle)
5471 {
5472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5473 struct drm_gem_object *object = intel_fb->obj;
5474
5475 return drm_gem_handle_create(file_priv, object, handle);
5476 }
5477
5478 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5479 .destroy = intel_user_framebuffer_destroy,
5480 .create_handle = intel_user_framebuffer_create_handle,
5481 };
5482
5483 int intel_framebuffer_init(struct drm_device *dev,
5484 struct intel_framebuffer *intel_fb,
5485 struct drm_mode_fb_cmd *mode_cmd,
5486 struct drm_gem_object *obj)
5487 {
5488 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5489 int ret;
5490
5491 if (obj_priv->tiling_mode == I915_TILING_Y)
5492 return -EINVAL;
5493
5494 if (mode_cmd->pitch & 63)
5495 return -EINVAL;
5496
5497 switch (mode_cmd->bpp) {
5498 case 8:
5499 case 16:
5500 case 24:
5501 case 32:
5502 break;
5503 default:
5504 return -EINVAL;
5505 }
5506
5507 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5508 if (ret) {
5509 DRM_ERROR("framebuffer init failed %d\n", ret);
5510 return ret;
5511 }
5512
5513 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5514 intel_fb->obj = obj;
5515 return 0;
5516 }
5517
5518 static struct drm_framebuffer *
5519 intel_user_framebuffer_create(struct drm_device *dev,
5520 struct drm_file *filp,
5521 struct drm_mode_fb_cmd *mode_cmd)
5522 {
5523 struct drm_gem_object *obj;
5524 struct intel_framebuffer *intel_fb;
5525 int ret;
5526
5527 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5528 if (!obj)
5529 return ERR_PTR(-ENOENT);
5530
5531 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5532 if (!intel_fb)
5533 return ERR_PTR(-ENOMEM);
5534
5535 ret = intel_framebuffer_init(dev, intel_fb,
5536 mode_cmd, obj);
5537 if (ret) {
5538 drm_gem_object_unreference_unlocked(obj);
5539 kfree(intel_fb);
5540 return ERR_PTR(ret);
5541 }
5542
5543 return &intel_fb->base;
5544 }
5545
5546 static const struct drm_mode_config_funcs intel_mode_funcs = {
5547 .fb_create = intel_user_framebuffer_create,
5548 .output_poll_changed = intel_fb_output_poll_changed,
5549 };
5550
5551 static struct drm_gem_object *
5552 intel_alloc_context_page(struct drm_device *dev)
5553 {
5554 struct drm_gem_object *ctx;
5555 int ret;
5556
5557 ctx = i915_gem_alloc_object(dev, 4096);
5558 if (!ctx) {
5559 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5560 return NULL;
5561 }
5562
5563 mutex_lock(&dev->struct_mutex);
5564 ret = i915_gem_object_pin(ctx, 4096);
5565 if (ret) {
5566 DRM_ERROR("failed to pin power context: %d\n", ret);
5567 goto err_unref;
5568 }
5569
5570 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5571 if (ret) {
5572 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5573 goto err_unpin;
5574 }
5575 mutex_unlock(&dev->struct_mutex);
5576
5577 return ctx;
5578
5579 err_unpin:
5580 i915_gem_object_unpin(ctx);
5581 err_unref:
5582 drm_gem_object_unreference(ctx);
5583 mutex_unlock(&dev->struct_mutex);
5584 return NULL;
5585 }
5586
5587 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5588 {
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 u16 rgvswctl;
5591
5592 rgvswctl = I915_READ16(MEMSWCTL);
5593 if (rgvswctl & MEMCTL_CMD_STS) {
5594 DRM_DEBUG("gpu busy, RCS change rejected\n");
5595 return false; /* still busy with another command */
5596 }
5597
5598 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5599 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5600 I915_WRITE16(MEMSWCTL, rgvswctl);
5601 POSTING_READ16(MEMSWCTL);
5602
5603 rgvswctl |= MEMCTL_CMD_STS;
5604 I915_WRITE16(MEMSWCTL, rgvswctl);
5605
5606 return true;
5607 }
5608
5609 void ironlake_enable_drps(struct drm_device *dev)
5610 {
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 u32 rgvmodectl = I915_READ(MEMMODECTL);
5613 u8 fmax, fmin, fstart, vstart;
5614
5615 /* 100ms RC evaluation intervals */
5616 I915_WRITE(RCUPEI, 100000);
5617 I915_WRITE(RCDNEI, 100000);
5618
5619 /* Set max/min thresholds to 90ms and 80ms respectively */
5620 I915_WRITE(RCBMAXAVG, 90000);
5621 I915_WRITE(RCBMINAVG, 80000);
5622
5623 I915_WRITE(MEMIHYST, 1);
5624
5625 /* Set up min, max, and cur for interrupt handling */
5626 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5627 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5628 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5629 MEMMODE_FSTART_SHIFT;
5630 fstart = fmax;
5631
5632 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5633 PXVFREQ_PX_SHIFT;
5634
5635 dev_priv->fmax = fstart; /* IPS callback will increase this */
5636 dev_priv->fstart = fstart;
5637
5638 dev_priv->max_delay = fmax;
5639 dev_priv->min_delay = fmin;
5640 dev_priv->cur_delay = fstart;
5641
5642 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5643 fstart);
5644
5645 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5646
5647 /*
5648 * Interrupts will be enabled in ironlake_irq_postinstall
5649 */
5650
5651 I915_WRITE(VIDSTART, vstart);
5652 POSTING_READ(VIDSTART);
5653
5654 rgvmodectl |= MEMMODE_SWMODE_EN;
5655 I915_WRITE(MEMMODECTL, rgvmodectl);
5656
5657 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5658 DRM_ERROR("stuck trying to change perf mode\n");
5659 msleep(1);
5660
5661 ironlake_set_drps(dev, fstart);
5662
5663 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5664 I915_READ(0x112e0);
5665 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5666 dev_priv->last_count2 = I915_READ(0x112f4);
5667 getrawmonotonic(&dev_priv->last_time2);
5668 }
5669
5670 void ironlake_disable_drps(struct drm_device *dev)
5671 {
5672 struct drm_i915_private *dev_priv = dev->dev_private;
5673 u16 rgvswctl = I915_READ16(MEMSWCTL);
5674
5675 /* Ack interrupts, disable EFC interrupt */
5676 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5677 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5678 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5679 I915_WRITE(DEIIR, DE_PCU_EVENT);
5680 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5681
5682 /* Go back to the starting frequency */
5683 ironlake_set_drps(dev, dev_priv->fstart);
5684 msleep(1);
5685 rgvswctl |= MEMCTL_CMD_STS;
5686 I915_WRITE(MEMSWCTL, rgvswctl);
5687 msleep(1);
5688
5689 }
5690
5691 static unsigned long intel_pxfreq(u32 vidfreq)
5692 {
5693 unsigned long freq;
5694 int div = (vidfreq & 0x3f0000) >> 16;
5695 int post = (vidfreq & 0x3000) >> 12;
5696 int pre = (vidfreq & 0x7);
5697
5698 if (!pre)
5699 return 0;
5700
5701 freq = ((div * 133333) / ((1<<post) * pre));
5702
5703 return freq;
5704 }
5705
5706 void intel_init_emon(struct drm_device *dev)
5707 {
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 u32 lcfuse;
5710 u8 pxw[16];
5711 int i;
5712
5713 /* Disable to program */
5714 I915_WRITE(ECR, 0);
5715 POSTING_READ(ECR);
5716
5717 /* Program energy weights for various events */
5718 I915_WRITE(SDEW, 0x15040d00);
5719 I915_WRITE(CSIEW0, 0x007f0000);
5720 I915_WRITE(CSIEW1, 0x1e220004);
5721 I915_WRITE(CSIEW2, 0x04000004);
5722
5723 for (i = 0; i < 5; i++)
5724 I915_WRITE(PEW + (i * 4), 0);
5725 for (i = 0; i < 3; i++)
5726 I915_WRITE(DEW + (i * 4), 0);
5727
5728 /* Program P-state weights to account for frequency power adjustment */
5729 for (i = 0; i < 16; i++) {
5730 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5731 unsigned long freq = intel_pxfreq(pxvidfreq);
5732 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5733 PXVFREQ_PX_SHIFT;
5734 unsigned long val;
5735
5736 val = vid * vid;
5737 val *= (freq / 1000);
5738 val *= 255;
5739 val /= (127*127*900);
5740 if (val > 0xff)
5741 DRM_ERROR("bad pxval: %ld\n", val);
5742 pxw[i] = val;
5743 }
5744 /* Render standby states get 0 weight */
5745 pxw[14] = 0;
5746 pxw[15] = 0;
5747
5748 for (i = 0; i < 4; i++) {
5749 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5750 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5751 I915_WRITE(PXW + (i * 4), val);
5752 }
5753
5754 /* Adjust magic regs to magic values (more experimental results) */
5755 I915_WRITE(OGW0, 0);
5756 I915_WRITE(OGW1, 0);
5757 I915_WRITE(EG0, 0x00007f00);
5758 I915_WRITE(EG1, 0x0000000e);
5759 I915_WRITE(EG2, 0x000e0000);
5760 I915_WRITE(EG3, 0x68000300);
5761 I915_WRITE(EG4, 0x42000000);
5762 I915_WRITE(EG5, 0x00140031);
5763 I915_WRITE(EG6, 0);
5764 I915_WRITE(EG7, 0);
5765
5766 for (i = 0; i < 8; i++)
5767 I915_WRITE(PXWL + (i * 4), 0);
5768
5769 /* Enable PMON + select events */
5770 I915_WRITE(ECR, 0x80000019);
5771
5772 lcfuse = I915_READ(LCFUSE02);
5773
5774 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5775 }
5776
5777 void intel_init_clock_gating(struct drm_device *dev)
5778 {
5779 struct drm_i915_private *dev_priv = dev->dev_private;
5780
5781 /*
5782 * Disable clock gating reported to work incorrectly according to the
5783 * specs, but enable as much else as we can.
5784 */
5785 if (HAS_PCH_SPLIT(dev)) {
5786 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5787
5788 if (IS_IRONLAKE(dev)) {
5789 /* Required for FBC */
5790 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5791 /* Required for CxSR */
5792 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5793
5794 I915_WRITE(PCH_3DCGDIS0,
5795 MARIUNIT_CLOCK_GATE_DISABLE |
5796 SVSMUNIT_CLOCK_GATE_DISABLE);
5797 }
5798
5799 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5800
5801 /*
5802 * According to the spec the following bits should be set in
5803 * order to enable memory self-refresh
5804 * The bit 22/21 of 0x42004
5805 * The bit 5 of 0x42020
5806 * The bit 15 of 0x45000
5807 */
5808 if (IS_IRONLAKE(dev)) {
5809 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5810 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5811 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5812 I915_WRITE(ILK_DSPCLK_GATE,
5813 (I915_READ(ILK_DSPCLK_GATE) |
5814 ILK_DPARB_CLK_GATE));
5815 I915_WRITE(DISP_ARB_CTL,
5816 (I915_READ(DISP_ARB_CTL) |
5817 DISP_FBC_WM_DIS));
5818 }
5819 /*
5820 * Based on the document from hardware guys the following bits
5821 * should be set unconditionally in order to enable FBC.
5822 * The bit 22 of 0x42000
5823 * The bit 22 of 0x42004
5824 * The bit 7,8,9 of 0x42020.
5825 */
5826 if (IS_IRONLAKE_M(dev)) {
5827 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5828 I915_READ(ILK_DISPLAY_CHICKEN1) |
5829 ILK_FBCQ_DIS);
5830 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5831 I915_READ(ILK_DISPLAY_CHICKEN2) |
5832 ILK_DPARB_GATE);
5833 I915_WRITE(ILK_DSPCLK_GATE,
5834 I915_READ(ILK_DSPCLK_GATE) |
5835 ILK_DPFC_DIS1 |
5836 ILK_DPFC_DIS2 |
5837 ILK_CLK_FBC);
5838 }
5839 return;
5840 } else if (IS_G4X(dev)) {
5841 uint32_t dspclk_gate;
5842 I915_WRITE(RENCLK_GATE_D1, 0);
5843 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5844 GS_UNIT_CLOCK_GATE_DISABLE |
5845 CL_UNIT_CLOCK_GATE_DISABLE);
5846 I915_WRITE(RAMCLK_GATE_D, 0);
5847 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5848 OVRUNIT_CLOCK_GATE_DISABLE |
5849 OVCUNIT_CLOCK_GATE_DISABLE;
5850 if (IS_GM45(dev))
5851 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5852 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5853 } else if (IS_I965GM(dev)) {
5854 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5855 I915_WRITE(RENCLK_GATE_D2, 0);
5856 I915_WRITE(DSPCLK_GATE_D, 0);
5857 I915_WRITE(RAMCLK_GATE_D, 0);
5858 I915_WRITE16(DEUC, 0);
5859 } else if (IS_I965G(dev)) {
5860 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5861 I965_RCC_CLOCK_GATE_DISABLE |
5862 I965_RCPB_CLOCK_GATE_DISABLE |
5863 I965_ISC_CLOCK_GATE_DISABLE |
5864 I965_FBC_CLOCK_GATE_DISABLE);
5865 I915_WRITE(RENCLK_GATE_D2, 0);
5866 } else if (IS_I9XX(dev)) {
5867 u32 dstate = I915_READ(D_STATE);
5868
5869 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5870 DSTATE_DOT_CLOCK_GATING;
5871 I915_WRITE(D_STATE, dstate);
5872 } else if (IS_I85X(dev) || IS_I865G(dev)) {
5873 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5874 } else if (IS_I830(dev)) {
5875 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5876 }
5877
5878 /*
5879 * GPU can automatically power down the render unit if given a page
5880 * to save state.
5881 */
5882 if (IS_IRONLAKE_M(dev)) {
5883 if (dev_priv->renderctx == NULL)
5884 dev_priv->renderctx = intel_alloc_context_page(dev);
5885 if (dev_priv->renderctx) {
5886 struct drm_i915_gem_object *obj_priv;
5887 obj_priv = to_intel_bo(dev_priv->renderctx);
5888 if (obj_priv) {
5889 BEGIN_LP_RING(4);
5890 OUT_RING(MI_SET_CONTEXT);
5891 OUT_RING(obj_priv->gtt_offset |
5892 MI_MM_SPACE_GTT |
5893 MI_SAVE_EXT_STATE_EN |
5894 MI_RESTORE_EXT_STATE_EN |
5895 MI_RESTORE_INHIBIT);
5896 OUT_RING(MI_NOOP);
5897 OUT_RING(MI_FLUSH);
5898 ADVANCE_LP_RING();
5899 }
5900 } else
5901 DRM_DEBUG_KMS("Failed to allocate render context."
5902 "Disable RC6\n");
5903 }
5904
5905 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5906 struct drm_i915_gem_object *obj_priv = NULL;
5907
5908 if (dev_priv->pwrctx) {
5909 obj_priv = to_intel_bo(dev_priv->pwrctx);
5910 } else {
5911 struct drm_gem_object *pwrctx;
5912
5913 pwrctx = intel_alloc_context_page(dev);
5914 if (pwrctx) {
5915 dev_priv->pwrctx = pwrctx;
5916 obj_priv = to_intel_bo(pwrctx);
5917 }
5918 }
5919
5920 if (obj_priv) {
5921 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5922 I915_WRITE(MCHBAR_RENDER_STANDBY,
5923 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5924 }
5925 }
5926 }
5927
5928 /* Set up chip specific display functions */
5929 static void intel_init_display(struct drm_device *dev)
5930 {
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932
5933 /* We always want a DPMS function */
5934 if (HAS_PCH_SPLIT(dev))
5935 dev_priv->display.dpms = ironlake_crtc_dpms;
5936 else
5937 dev_priv->display.dpms = i9xx_crtc_dpms;
5938
5939 if (I915_HAS_FBC(dev)) {
5940 if (IS_IRONLAKE_M(dev)) {
5941 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5942 dev_priv->display.enable_fbc = ironlake_enable_fbc;
5943 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5944 } else if (IS_GM45(dev)) {
5945 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5946 dev_priv->display.enable_fbc = g4x_enable_fbc;
5947 dev_priv->display.disable_fbc = g4x_disable_fbc;
5948 } else if (IS_I965GM(dev)) {
5949 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5950 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5951 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5952 }
5953 /* 855GM needs testing */
5954 }
5955
5956 /* Returns the core display clock speed */
5957 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5958 dev_priv->display.get_display_clock_speed =
5959 i945_get_display_clock_speed;
5960 else if (IS_I915G(dev))
5961 dev_priv->display.get_display_clock_speed =
5962 i915_get_display_clock_speed;
5963 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5964 dev_priv->display.get_display_clock_speed =
5965 i9xx_misc_get_display_clock_speed;
5966 else if (IS_I915GM(dev))
5967 dev_priv->display.get_display_clock_speed =
5968 i915gm_get_display_clock_speed;
5969 else if (IS_I865G(dev))
5970 dev_priv->display.get_display_clock_speed =
5971 i865_get_display_clock_speed;
5972 else if (IS_I85X(dev))
5973 dev_priv->display.get_display_clock_speed =
5974 i855_get_display_clock_speed;
5975 else /* 852, 830 */
5976 dev_priv->display.get_display_clock_speed =
5977 i830_get_display_clock_speed;
5978
5979 /* For FIFO watermark updates */
5980 if (HAS_PCH_SPLIT(dev)) {
5981 if (IS_IRONLAKE(dev)) {
5982 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5983 dev_priv->display.update_wm = ironlake_update_wm;
5984 else {
5985 DRM_DEBUG_KMS("Failed to get proper latency. "
5986 "Disable CxSR\n");
5987 dev_priv->display.update_wm = NULL;
5988 }
5989 } else
5990 dev_priv->display.update_wm = NULL;
5991 } else if (IS_PINEVIEW(dev)) {
5992 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5993 dev_priv->is_ddr3,
5994 dev_priv->fsb_freq,
5995 dev_priv->mem_freq)) {
5996 DRM_INFO("failed to find known CxSR latency "
5997 "(found ddr%s fsb freq %d, mem freq %d), "
5998 "disabling CxSR\n",
5999 (dev_priv->is_ddr3 == 1) ? "3": "2",
6000 dev_priv->fsb_freq, dev_priv->mem_freq);
6001 /* Disable CxSR and never update its watermark again */
6002 pineview_disable_cxsr(dev);
6003 dev_priv->display.update_wm = NULL;
6004 } else
6005 dev_priv->display.update_wm = pineview_update_wm;
6006 } else if (IS_G4X(dev))
6007 dev_priv->display.update_wm = g4x_update_wm;
6008 else if (IS_I965G(dev))
6009 dev_priv->display.update_wm = i965_update_wm;
6010 else if (IS_I9XX(dev)) {
6011 dev_priv->display.update_wm = i9xx_update_wm;
6012 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6013 } else if (IS_I85X(dev)) {
6014 dev_priv->display.update_wm = i9xx_update_wm;
6015 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6016 } else {
6017 dev_priv->display.update_wm = i830_update_wm;
6018 if (IS_845G(dev))
6019 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6020 else
6021 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6022 }
6023 }
6024
6025 /*
6026 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6027 * resume, or other times. This quirk makes sure that's the case for
6028 * affected systems.
6029 */
6030 static void quirk_pipea_force (struct drm_device *dev)
6031 {
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033
6034 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6035 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6036 }
6037
6038 struct intel_quirk {
6039 int device;
6040 int subsystem_vendor;
6041 int subsystem_device;
6042 void (*hook)(struct drm_device *dev);
6043 };
6044
6045 struct intel_quirk intel_quirks[] = {
6046 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6047 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6048 /* HP Mini needs pipe A force quirk (LP: #322104) */
6049 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6050
6051 /* Thinkpad R31 needs pipe A force quirk */
6052 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6053 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6054 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6055
6056 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6057 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6058 /* ThinkPad X40 needs pipe A force quirk */
6059
6060 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6061 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6062
6063 /* 855 & before need to leave pipe A & dpll A up */
6064 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6065 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6066 };
6067
6068 static void intel_init_quirks(struct drm_device *dev)
6069 {
6070 struct pci_dev *d = dev->pdev;
6071 int i;
6072
6073 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6074 struct intel_quirk *q = &intel_quirks[i];
6075
6076 if (d->device == q->device &&
6077 (d->subsystem_vendor == q->subsystem_vendor ||
6078 q->subsystem_vendor == PCI_ANY_ID) &&
6079 (d->subsystem_device == q->subsystem_device ||
6080 q->subsystem_device == PCI_ANY_ID))
6081 q->hook(dev);
6082 }
6083 }
6084
6085 /* Disable the VGA plane that we never use */
6086 static void i915_disable_vga(struct drm_device *dev)
6087 {
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 u8 sr1;
6090 u32 vga_reg;
6091
6092 if (HAS_PCH_SPLIT(dev))
6093 vga_reg = CPU_VGACNTRL;
6094 else
6095 vga_reg = VGACNTRL;
6096
6097 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6098 outb(1, VGA_SR_INDEX);
6099 sr1 = inb(VGA_SR_DATA);
6100 outb(sr1 | 1<<5, VGA_SR_DATA);
6101 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6102 udelay(300);
6103
6104 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6105 POSTING_READ(vga_reg);
6106 }
6107
6108 void intel_modeset_init(struct drm_device *dev)
6109 {
6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111 int i;
6112
6113 drm_mode_config_init(dev);
6114
6115 dev->mode_config.min_width = 0;
6116 dev->mode_config.min_height = 0;
6117
6118 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6119
6120 intel_init_quirks(dev);
6121
6122 intel_init_display(dev);
6123
6124 if (IS_I965G(dev)) {
6125 dev->mode_config.max_width = 8192;
6126 dev->mode_config.max_height = 8192;
6127 } else if (IS_I9XX(dev)) {
6128 dev->mode_config.max_width = 4096;
6129 dev->mode_config.max_height = 4096;
6130 } else {
6131 dev->mode_config.max_width = 2048;
6132 dev->mode_config.max_height = 2048;
6133 }
6134
6135 /* set memory base */
6136 if (IS_I9XX(dev))
6137 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6138 else
6139 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6140
6141 if (IS_MOBILE(dev) || IS_I9XX(dev))
6142 dev_priv->num_pipe = 2;
6143 else
6144 dev_priv->num_pipe = 1;
6145 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6146 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6147
6148 for (i = 0; i < dev_priv->num_pipe; i++) {
6149 intel_crtc_init(dev, i);
6150 }
6151
6152 intel_setup_outputs(dev);
6153
6154 intel_init_clock_gating(dev);
6155
6156 /* Just disable it once at startup */
6157 i915_disable_vga(dev);
6158
6159 if (IS_IRONLAKE_M(dev)) {
6160 ironlake_enable_drps(dev);
6161 intel_init_emon(dev);
6162 }
6163
6164 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6165 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6166 (unsigned long)dev);
6167
6168 intel_setup_overlay(dev);
6169 }
6170
6171 void intel_modeset_cleanup(struct drm_device *dev)
6172 {
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct drm_crtc *crtc;
6175 struct intel_crtc *intel_crtc;
6176
6177 mutex_lock(&dev->struct_mutex);
6178
6179 drm_kms_helper_poll_fini(dev);
6180 intel_fbdev_fini(dev);
6181
6182 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6183 /* Skip inactive CRTCs */
6184 if (!crtc->fb)
6185 continue;
6186
6187 intel_crtc = to_intel_crtc(crtc);
6188 intel_increase_pllclock(crtc);
6189 }
6190
6191 if (dev_priv->display.disable_fbc)
6192 dev_priv->display.disable_fbc(dev);
6193
6194 if (dev_priv->renderctx) {
6195 struct drm_i915_gem_object *obj_priv;
6196
6197 obj_priv = to_intel_bo(dev_priv->renderctx);
6198 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6199 I915_READ(CCID);
6200 i915_gem_object_unpin(dev_priv->renderctx);
6201 drm_gem_object_unreference(dev_priv->renderctx);
6202 }
6203
6204 if (dev_priv->pwrctx) {
6205 struct drm_i915_gem_object *obj_priv;
6206
6207 obj_priv = to_intel_bo(dev_priv->pwrctx);
6208 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6209 I915_READ(PWRCTXA);
6210 i915_gem_object_unpin(dev_priv->pwrctx);
6211 drm_gem_object_unreference(dev_priv->pwrctx);
6212 }
6213
6214 if (IS_IRONLAKE_M(dev))
6215 ironlake_disable_drps(dev);
6216
6217 mutex_unlock(&dev->struct_mutex);
6218
6219 /* Disable the irq before mode object teardown, for the irq might
6220 * enqueue unpin/hotplug work. */
6221 drm_irq_uninstall(dev);
6222 cancel_work_sync(&dev_priv->hotplug_work);
6223
6224 /* Shut off idle work before the crtcs get freed. */
6225 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6226 intel_crtc = to_intel_crtc(crtc);
6227 del_timer_sync(&intel_crtc->idle_timer);
6228 }
6229 del_timer_sync(&dev_priv->idle_timer);
6230 cancel_work_sync(&dev_priv->idle_work);
6231
6232 drm_mode_config_cleanup(dev);
6233 }
6234
6235 /*
6236 * Return which encoder is currently attached for connector.
6237 */
6238 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6239 {
6240 return &intel_attached_encoder(connector)->base;
6241 }
6242
6243 void intel_connector_attach_encoder(struct intel_connector *connector,
6244 struct intel_encoder *encoder)
6245 {
6246 connector->encoder = encoder;
6247 drm_mode_connector_attach_encoder(&connector->base,
6248 &encoder->base);
6249 }
6250
6251 /*
6252 * set vga decode state - true == enable VGA decode
6253 */
6254 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6255 {
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 u16 gmch_ctrl;
6258
6259 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6260 if (state)
6261 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6262 else
6263 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6264 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6265 return 0;
6266 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree