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PCI Hotplug: cpqphp: refactor cpqphp_save_slot_config
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / pci / hotplug / cpqphp_pci.c
blob1f1c90dd791d2d2107261802ea6ebc71c5942c64
1 /*
2 * Compaq Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <greg@kroah.com>
26 *
27 */
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/slab.h>
33 #include <linux/workqueue.h>
34 #include <linux/proc_fs.h>
35 #include <linux/pci.h>
36 #include <linux/pci_hotplug.h>
37 #include "../pci.h"
38 #include "cpqphp.h"
39 #include "cpqphp_nvram.h"
40 #include <asm/pci_x86.h>
41
42
43 u8 cpqhp_nic_irq;
44 u8 cpqhp_disk_irq;
45
46 static u16 unused_IRQ;
47
48 /*
49 * detect_HRT_floating_pointer
50 *
51 * find the Hot Plug Resource Table in the specified region of memory.
52 *
53 */
54 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
55 {
56 void __iomem *fp;
57 void __iomem *endp;
58 u8 temp1, temp2, temp3, temp4;
59 int status = 0;
60
61 endp = (end - sizeof(struct hrt) + 1);
62
63 for (fp = begin; fp <= endp; fp += 16) {
64 temp1 = readb(fp + SIG0);
65 temp2 = readb(fp + SIG1);
66 temp3 = readb(fp + SIG2);
67 temp4 = readb(fp + SIG3);
68 if (temp1 == '$' &&
69 temp2 == 'H' &&
70 temp3 == 'R' &&
71 temp4 == 'T') {
72 status = 1;
73 break;
74 }
75 }
76
77 if (!status)
78 fp = NULL;
79
80 dbg("Discovered Hotplug Resource Table at %p\n", fp);
81 return fp;
82 }
83
84
85 int cpqhp_configure_device (struct controller* ctrl, struct pci_func* func)
86 {
87 unsigned char bus;
88 struct pci_bus *child;
89 int num;
90
91 if (func->pci_dev == NULL)
92 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
93
94 /* No pci device, we need to create it then */
95 if (func->pci_dev == NULL) {
96 dbg("INFO: pci_dev still null\n");
97
98 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
99 if (num)
100 pci_bus_add_devices(ctrl->pci_dev->bus);
101
102 func->pci_dev = pci_find_slot(func->bus, PCI_DEVFN(func->device, func->function));
103 if (func->pci_dev == NULL) {
104 dbg("ERROR: pci_dev still null\n");
105 return 0;
106 }
107 }
108
109 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
110 pci_read_config_byte(func->pci_dev, PCI_SECONDARY_BUS, &bus);
111 child = (struct pci_bus*) pci_add_new_bus(func->pci_dev->bus, (func->pci_dev), bus);
112 pci_do_scan_bus(child);
113 }
114
115 return 0;
116 }
117
118
119 int cpqhp_unconfigure_device(struct pci_func* func)
120 {
121 int j;
122
123 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
124
125 for (j=0; j<8 ; j++) {
126 struct pci_dev* temp = pci_find_slot(func->bus, PCI_DEVFN(func->device, j));
127 if (temp)
128 pci_remove_bus_device(temp);
129 }
130 return 0;
131 }
132
133 static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
134 {
135 u32 vendID = 0;
136
137 if (pci_bus_read_config_dword (bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
138 return -1;
139 if (vendID == 0xffffffff)
140 return -1;
141 return pci_bus_read_config_dword (bus, devfn, offset, value);
142 }
143
144
145 /*
146 * cpqhp_set_irq
147 *
148 * @bus_num: bus number of PCI device
149 * @dev_num: device number of PCI device
150 * @slot: pointer to u8 where slot number will be returned
151 */
152 int cpqhp_set_irq (u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
153 {
154 int rc = 0;
155
156 if (cpqhp_legacy_mode) {
157 struct pci_dev *fakedev;
158 struct pci_bus *fakebus;
159 u16 temp_word;
160
161 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
162 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
163 if (!fakedev || !fakebus) {
164 kfree(fakedev);
165 kfree(fakebus);
166 return -ENOMEM;
167 }
168
169 fakedev->devfn = dev_num << 3;
170 fakedev->bus = fakebus;
171 fakebus->number = bus_num;
172 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
173 __func__, dev_num, bus_num, int_pin, irq_num);
174 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
175 kfree(fakedev);
176 kfree(fakebus);
177 dbg("%s: rc %d\n", __func__, rc);
178 if (!rc)
179 return !rc;
180
181 /* set the Edge Level Control Register (ELCR) */
182 temp_word = inb(0x4d0);
183 temp_word |= inb(0x4d1) << 8;
184
185 temp_word |= 0x01 << irq_num;
186
187 /* This should only be for x86 as it sets the Edge Level
188 * Control Register
189 */
190 outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
191 0xFF00) >> 8), 0x4d1); rc = 0; }
192
193 return rc;
194 }
195
196
197 /*
198 * WTF??? This function isn't in the code, yet a function calls it, but the
199 * compiler optimizes it away? strange. Here as a placeholder to keep the
200 * compiler happy.
201 */
202 static int PCI_ScanBusNonBridge (u8 bus, u8 device)
203 {
204 return 0;
205 }
206
207 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 * dev_num)
208 {
209 u16 tdevice;
210 u32 work;
211 u8 tbus;
212
213 ctrl->pci_bus->number = bus_num;
214
215 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
216 /* Scan for access first */
217 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
218 continue;
219 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
220 /* Yep we got one. Not a bridge ? */
221 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
222 *dev_num = tdevice;
223 dbg("found it !\n");
224 return 0;
225 }
226 }
227 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
228 /* Scan for access first */
229 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
230 continue;
231 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
232 /* Yep we got one. bridge ? */
233 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
234 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
235 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
236 if (PCI_ScanBusNonBridge(tbus, tdevice) == 0)
237 return 0;
238 }
239 }
240
241 return -1;
242 }
243
244
245 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
246 {
247 struct irq_routing_table *PCIIRQRoutingInfoLength;
248 long len;
249 long loop;
250 u32 work;
251
252 u8 tbus, tdevice, tslot;
253
254 PCIIRQRoutingInfoLength = pcibios_get_irq_routing_table();
255 if (!PCIIRQRoutingInfoLength)
256 return -1;
257
258 len = (PCIIRQRoutingInfoLength->size -
259 sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
260 /* Make sure I got at least one entry */
261 if (len == 0) {
262 kfree(PCIIRQRoutingInfoLength );
263 return -1;
264 }
265
266 for (loop = 0; loop < len; ++loop) {
267 tbus = PCIIRQRoutingInfoLength->slots[loop].bus;
268 tdevice = PCIIRQRoutingInfoLength->slots[loop].devfn;
269 tslot = PCIIRQRoutingInfoLength->slots[loop].slot;
270
271 if (tslot == slot) {
272 *bus_num = tbus;
273 *dev_num = tdevice;
274 ctrl->pci_bus->number = tbus;
275 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
276 if (!nobridge || (work == 0xffffffff)) {
277 kfree(PCIIRQRoutingInfoLength );
278 return 0;
279 }
280
281 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
282 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
283 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
284
285 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
286 pci_bus_read_config_byte (ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
287 dbg("Scan bus for Non Bridge: bus %d\n", tbus);
288 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
289 *bus_num = tbus;
290 kfree(PCIIRQRoutingInfoLength );
291 return 0;
292 }
293 } else {
294 kfree(PCIIRQRoutingInfoLength );
295 return 0;
296 }
297
298 }
299 }
300 kfree(PCIIRQRoutingInfoLength );
301 return -1;
302 }
303
304
305 int cpqhp_get_bus_dev (struct controller *ctrl, u8 * bus_num, u8 * dev_num, u8 slot)
306 {
307 /* plain (bridges allowed) */
308 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
309 }
310
311
312 /* More PCI configuration routines; this time centered around hotplug
313 * controller
314 */
315
316
317 /*
318 * cpqhp_save_config
319 *
320 * Reads configuration for all slots in a PCI bus and saves info.
321 *
322 * Note: For non-hot plug busses, the slot # saved is the device #
323 *
324 * returns 0 if success
325 */
326 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
327 {
328 long rc;
329 u8 class_code;
330 u8 header_type;
331 u32 ID;
332 u8 secondary_bus;
333 struct pci_func *new_slot;
334 int sub_bus;
335 int FirstSupported;
336 int LastSupported;
337 int max_functions;
338 int function;
339 u8 DevError;
340 int device = 0;
341 int cloop = 0;
342 int stop_it;
343 int index;
344
345 /* Decide which slots are supported */
346
347 if (is_hot_plug) {
348 /*
349 * is_hot_plug is the slot mask
350 */
351 FirstSupported = is_hot_plug >> 4;
352 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
353 } else {
354 FirstSupported = 0;
355 LastSupported = 0x1F;
356 }
357
358 /* Save PCI configuration space for all devices in supported slots */
359 ctrl->pci_bus->number = busnumber;
360 for (device = FirstSupported; device <= LastSupported; device++) {
361 ID = 0xFFFFFFFF;
362 rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
363
364 if (ID != 0xFFFFFFFF) { /* device in slot */
365 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
366 if (rc)
367 return rc;
368
369 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
370 if (rc)
371 return rc;
372
373 /* If multi-function device, set max_functions to 8 */
374 if (header_type & 0x80)
375 max_functions = 8;
376 else
377 max_functions = 1;
378
379 function = 0;
380
381 do {
382 DevError = 0;
383 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
384 /* Recurse the subordinate bus
385 * get the subordinate bus number
386 */
387 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
388 if (rc) {
389 return rc;
390 } else {
391 sub_bus = (int) secondary_bus;
392
393 /* Save secondary bus cfg spc
394 * with this recursive call.
395 */
396 rc = cpqhp_save_config(ctrl, sub_bus, 0);
397 if (rc)
398 return rc;
399 ctrl->pci_bus->number = busnumber;
400 }
401 }
402
403 index = 0;
404 new_slot = cpqhp_slot_find(busnumber, device, index++);
405 while (new_slot &&
406 (new_slot->function != (u8) function))
407 new_slot = cpqhp_slot_find(busnumber, device, index++);
408
409 if (!new_slot) {
410 /* Setup slot structure. */
411 new_slot = cpqhp_slot_create(busnumber);
412
413 if (new_slot == NULL)
414 return(1);
415 }
416
417 new_slot->bus = (u8) busnumber;
418 new_slot->device = (u8) device;
419 new_slot->function = (u8) function;
420 new_slot->is_a_board = 1;
421 new_slot->switch_save = 0x10;
422 /* In case of unsupported board */
423 new_slot->status = DevError;
424 new_slot->pci_dev = pci_find_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
425
426 for (cloop = 0; cloop < 0x20; cloop++) {
427 rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
428 if (rc)
429 return rc;
430 }
431
432 function++;
433
434 stop_it = 0;
435
436 /* this loop skips to the next present function
437 * reading in Class Code and Header type.
438 */
439
440 while ((function < max_functions)&&(!stop_it)) {
441 rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
442 if (ID == 0xFFFFFFFF) { /* nothing there. */
443 function++;
444 } else { /* Something there */
445 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
446 if (rc)
447 return rc;
448
449 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
450 if (rc)
451 return rc;
452
453 stop_it++;
454 }
455 }
456
457 } while (function < max_functions);
458 } /* End of IF (device in slot?) */
459 else if (is_hot_plug) {
460 /* Setup slot structure with entry for empty slot */
461 new_slot = cpqhp_slot_create(busnumber);
462
463 if (new_slot == NULL) {
464 return(1);
465 }
466
467 new_slot->bus = (u8) busnumber;
468 new_slot->device = (u8) device;
469 new_slot->function = 0;
470 new_slot->is_a_board = 0;
471 new_slot->presence_save = 0;
472 new_slot->switch_save = 0;
473 }
474 } /* End of FOR loop */
475
476 return(0);
477 }
478
479
480 /*
481 * cpqhp_save_slot_config
482 *
483 * Saves configuration info for all PCI devices in a given slot
484 * including subordinate busses.
485 *
486 * returns 0 if success
487 */
488 int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func * new_slot)
489 {
490 long rc;
491 u8 class_code;
492 u8 header_type;
493 u32 ID;
494 u8 secondary_bus;
495 int sub_bus;
496 int max_functions;
497 int function = 0;
498 int cloop = 0;
499 int stop_it;
500
501 ID = 0xFFFFFFFF;
502
503 ctrl->pci_bus->number = new_slot->bus;
504 pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
505
506 if (ID == 0xFFFFFFFF)
507 return 2;
508
509 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
510 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
511
512 if (header_type & 0x80) /* Multi-function device */
513 max_functions = 8;
514 else
515 max_functions = 1;
516
517 while (function < max_functions) {
518 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
519 /* Recurse the subordinate bus */
520 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
521
522 sub_bus = (int) secondary_bus;
523
524 /* Save the config headers for the secondary
525 * bus.
526 */
527 rc = cpqhp_save_config(ctrl, sub_bus, 0);
528 if (rc)
529 return(rc);
530 ctrl->pci_bus->number = new_slot->bus;
531
532 }
533
534 new_slot->status = 0;
535
536 for (cloop = 0; cloop < 0x20; cloop++)
537 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop]));
538
539 function++;
540
541 stop_it = 0;
542
543 /* this loop skips to the next present function
544 * reading in the Class Code and the Header type.
545 */
546 while ((function < max_functions) && (!stop_it)) {
547 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
548
549 if (ID == 0xFFFFFFFF)
550 function++;
551 else {
552 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
553 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
554 stop_it++;
555 }
556 }
557
558 }
559
560 return 0;
561 }
562
563
564 /*
565 * cpqhp_save_base_addr_length
566 *
567 * Saves the length of all base address registers for the
568 * specified slot. this is for hot plug REPLACE
569 *
570 * returns 0 if success
571 */
572 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func * func)
573 {
574 u8 cloop;
575 u8 header_type;
576 u8 secondary_bus;
577 u8 type;
578 int sub_bus;
579 u32 temp_register;
580 u32 base;
581 u32 rc;
582 struct pci_func *next;
583 int index = 0;
584 struct pci_bus *pci_bus = ctrl->pci_bus;
585 unsigned int devfn;
586
587 func = cpqhp_slot_find(func->bus, func->device, index++);
588
589 while (func != NULL) {
590 pci_bus->number = func->bus;
591 devfn = PCI_DEVFN(func->device, func->function);
592
593 /* Check for Bridge */
594 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
595
596 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
597 pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
598
599 sub_bus = (int) secondary_bus;
600
601 next = cpqhp_slot_list[sub_bus];
602
603 while (next != NULL) {
604 rc = cpqhp_save_base_addr_length(ctrl, next);
605 if (rc)
606 return rc;
607
608 next = next->next;
609 }
610 pci_bus->number = func->bus;
611
612 /* FIXME: this loop is duplicated in the non-bridge
613 * case. The two could be rolled together Figure out
614 * IO and memory base lengths
615 */
616 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
617 temp_register = 0xFFFFFFFF;
618 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
619 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
620 /* If this register is implemented */
621 if (base) {
622 if (base & 0x01L) {
623 /* IO base
624 * set base = amount of IO space
625 * requested
626 */
627 base = base & 0xFFFFFFFE;
628 base = (~base) + 1;
629
630 type = 1;
631 } else {
632 /* memory base */
633 base = base & 0xFFFFFFF0;
634 base = (~base) + 1;
635
636 type = 0;
637 }
638 } else {
639 base = 0x0L;
640 type = 0;
641 }
642
643 /* Save information in slot structure */
644 func->base_length[(cloop - 0x10) >> 2] =
645 base;
646 func->base_type[(cloop - 0x10) >> 2] = type;
647
648 } /* End of base register loop */
649
650 } else if ((header_type & 0x7F) == 0x00) {
651 /* Figure out IO and memory base lengths */
652 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
653 temp_register = 0xFFFFFFFF;
654 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
655 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
656
657 /* If this register is implemented */
658 if (base) {
659 if (base & 0x01L) {
660 /* IO base
661 * base = amount of IO space
662 * requested
663 */
664 base = base & 0xFFFFFFFE;
665 base = (~base) + 1;
666
667 type = 1;
668 } else {
669 /* memory base
670 * base = amount of memory
671 * space requested
672 */
673 base = base & 0xFFFFFFF0;
674 base = (~base) + 1;
675
676 type = 0;
677 }
678 } else {
679 base = 0x0L;
680 type = 0;
681 }
682
683 /* Save information in slot structure */
684 func->base_length[(cloop - 0x10) >> 2] = base;
685 func->base_type[(cloop - 0x10) >> 2] = type;
686
687 } /* End of base register loop */
688
689 } else { /* Some other unknown header type */
690 }
691
692 /* find the next device in this slot */
693 func = cpqhp_slot_find(func->bus, func->device, index++);
694 }
695
696 return(0);
697 }
698
699
700 /*
701 * cpqhp_save_used_resources
702 *
703 * Stores used resource information for existing boards. this is
704 * for boards that were in the system when this driver was loaded.
705 * this function is for hot plug ADD
706 *
707 * returns 0 if success
708 */
709 int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func * func)
710 {
711 u8 cloop;
712 u8 header_type;
713 u8 secondary_bus;
714 u8 temp_byte;
715 u8 b_base;
716 u8 b_length;
717 u16 command;
718 u16 save_command;
719 u16 w_base;
720 u16 w_length;
721 u32 temp_register;
722 u32 save_base;
723 u32 base;
724 int index = 0;
725 struct pci_resource *mem_node;
726 struct pci_resource *p_mem_node;
727 struct pci_resource *io_node;
728 struct pci_resource *bus_node;
729 struct pci_bus *pci_bus = ctrl->pci_bus;
730 unsigned int devfn;
731
732 func = cpqhp_slot_find(func->bus, func->device, index++);
733
734 while ((func != NULL) && func->is_a_board) {
735 pci_bus->number = func->bus;
736 devfn = PCI_DEVFN(func->device, func->function);
737
738 /* Save the command register */
739 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
740
741 /* disable card */
742 command = 0x00;
743 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
744
745 /* Check for Bridge */
746 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
747
748 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
749 /* Clear Bridge Control Register */
750 command = 0x00;
751 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
752 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
753 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
754
755 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
756 if (!bus_node)
757 return -ENOMEM;
758
759 bus_node->base = secondary_bus;
760 bus_node->length = temp_byte - secondary_bus + 1;
761
762 bus_node->next = func->bus_head;
763 func->bus_head = bus_node;
764
765 /* Save IO base and Limit registers */
766 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
767 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
768
769 if ((b_base <= b_length) && (save_command & 0x01)) {
770 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
771 if (!io_node)
772 return -ENOMEM;
773
774 io_node->base = (b_base & 0xF0) << 8;
775 io_node->length = (b_length - b_base + 0x10) << 8;
776
777 io_node->next = func->io_head;
778 func->io_head = io_node;
779 }
780
781 /* Save memory base and Limit registers */
782 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
783 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
784
785 if ((w_base <= w_length) && (save_command & 0x02)) {
786 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
787 if (!mem_node)
788 return -ENOMEM;
789
790 mem_node->base = w_base << 16;
791 mem_node->length = (w_length - w_base + 0x10) << 16;
792
793 mem_node->next = func->mem_head;
794 func->mem_head = mem_node;
795 }
796
797 /* Save prefetchable memory base and Limit registers */
798 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
799 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
800
801 if ((w_base <= w_length) && (save_command & 0x02)) {
802 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
803 if (!p_mem_node)
804 return -ENOMEM;
805
806 p_mem_node->base = w_base << 16;
807 p_mem_node->length = (w_length - w_base + 0x10) << 16;
808
809 p_mem_node->next = func->p_mem_head;
810 func->p_mem_head = p_mem_node;
811 }
812 /* Figure out IO and memory base lengths */
813 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
814 pci_bus_read_config_dword (pci_bus, devfn, cloop, &save_base);
815
816 temp_register = 0xFFFFFFFF;
817 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
818 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
819
820 temp_register = base;
821
822 /* If this register is implemented */
823 if (base) {
824 if (((base & 0x03L) == 0x01)
825 && (save_command & 0x01)) {
826 /* IO base
827 * set temp_register = amount
828 * of IO space requested
829 */
830 temp_register = base & 0xFFFFFFFE;
831 temp_register = (~temp_register) + 1;
832
833 io_node = kmalloc(sizeof(*io_node),
834 GFP_KERNEL);
835 if (!io_node)
836 return -ENOMEM;
837
838 io_node->base =
839 save_base & (~0x03L);
840 io_node->length = temp_register;
841
842 io_node->next = func->io_head;
843 func->io_head = io_node;
844 } else
845 if (((base & 0x0BL) == 0x08)
846 && (save_command & 0x02)) {
847 /* prefetchable memory base */
848 temp_register = base & 0xFFFFFFF0;
849 temp_register = (~temp_register) + 1;
850
851 p_mem_node = kmalloc(sizeof(*p_mem_node),
852 GFP_KERNEL);
853 if (!p_mem_node)
854 return -ENOMEM;
855
856 p_mem_node->base = save_base & (~0x0FL);
857 p_mem_node->length = temp_register;
858
859 p_mem_node->next = func->p_mem_head;
860 func->p_mem_head = p_mem_node;
861 } else
862 if (((base & 0x0BL) == 0x00)
863 && (save_command & 0x02)) {
864 /* prefetchable memory base */
865 temp_register = base & 0xFFFFFFF0;
866 temp_register = (~temp_register) + 1;
867
868 mem_node = kmalloc(sizeof(*mem_node),
869 GFP_KERNEL);
870 if (!mem_node)
871 return -ENOMEM;
872
873 mem_node->base = save_base & (~0x0FL);
874 mem_node->length = temp_register;
875
876 mem_node->next = func->mem_head;
877 func->mem_head = mem_node;
878 } else
879 return(1);
880 }
881 } /* End of base register loop */
882 /* Standard header */
883 } else if ((header_type & 0x7F) == 0x00) {
884 /* Figure out IO and memory base lengths */
885 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
886 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
887
888 temp_register = 0xFFFFFFFF;
889 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
890 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
891
892 temp_register = base;
893
894 /* If this register is implemented */
895 if (base) {
896 if (((base & 0x03L) == 0x01)
897 && (save_command & 0x01)) {
898 /* IO base
899 * set temp_register = amount
900 * of IO space requested
901 */
902 temp_register = base & 0xFFFFFFFE;
903 temp_register = (~temp_register) + 1;
904
905 io_node = kmalloc(sizeof(*io_node),
906 GFP_KERNEL);
907 if (!io_node)
908 return -ENOMEM;
909
910 io_node->base = save_base & (~0x01L);
911 io_node->length = temp_register;
912
913 io_node->next = func->io_head;
914 func->io_head = io_node;
915 } else
916 if (((base & 0x0BL) == 0x08)
917 && (save_command & 0x02)) {
918 /* prefetchable memory base */
919 temp_register = base & 0xFFFFFFF0;
920 temp_register = (~temp_register) + 1;
921
922 p_mem_node = kmalloc(sizeof(*p_mem_node),
923 GFP_KERNEL);
924 if (!p_mem_node)
925 return -ENOMEM;
926
927 p_mem_node->base = save_base & (~0x0FL);
928 p_mem_node->length = temp_register;
929
930 p_mem_node->next = func->p_mem_head;
931 func->p_mem_head = p_mem_node;
932 } else
933 if (((base & 0x0BL) == 0x00)
934 && (save_command & 0x02)) {
935 /* prefetchable memory base */
936 temp_register = base & 0xFFFFFFF0;
937 temp_register = (~temp_register) + 1;
938
939 mem_node = kmalloc(sizeof(*mem_node),
940 GFP_KERNEL);
941 if (!mem_node)
942 return -ENOMEM;
943
944 mem_node->base = save_base & (~0x0FL);
945 mem_node->length = temp_register;
946
947 mem_node->next = func->mem_head;
948 func->mem_head = mem_node;
949 } else
950 return(1);
951 }
952 } /* End of base register loop */
953 /* Some other unknown header type */
954 } else {
955 }
956
957 /* find the next device in this slot */
958 func = cpqhp_slot_find(func->bus, func->device, index++);
959 }
960
961 return(0);
962 }
963
964
965 /*
966 * cpqhp_configure_board
967 *
968 * Copies saved configuration information to one slot.
969 * this is called recursively for bridge devices.
970 * this is for hot plug REPLACE!
971 *
972 * returns 0 if success
973 */
974 int cpqhp_configure_board(struct controller *ctrl, struct pci_func * func)
975 {
976 int cloop;
977 u8 header_type;
978 u8 secondary_bus;
979 int sub_bus;
980 struct pci_func *next;
981 u32 temp;
982 u32 rc;
983 int index = 0;
984 struct pci_bus *pci_bus = ctrl->pci_bus;
985 unsigned int devfn;
986
987 func = cpqhp_slot_find(func->bus, func->device, index++);
988
989 while (func != NULL) {
990 pci_bus->number = func->bus;
991 devfn = PCI_DEVFN(func->device, func->function);
992
993 /* Start at the top of config space so that the control
994 * registers are programmed last
995 */
996 for (cloop = 0x3C; cloop > 0; cloop -= 4) {
997 pci_bus_write_config_dword (pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
998 }
999
1000 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1001
1002 /* If this is a bridge device, restore subordinate devices */
1003 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1004 pci_bus_read_config_byte (pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
1005
1006 sub_bus = (int) secondary_bus;
1007
1008 next = cpqhp_slot_list[sub_bus];
1009
1010 while (next != NULL) {
1011 rc = cpqhp_configure_board(ctrl, next);
1012 if (rc)
1013 return rc;
1014
1015 next = next->next;
1016 }
1017 } else {
1018
1019 /* Check all the base Address Registers to make sure
1020 * they are the same. If not, the board is different.
1021 */
1022
1023 for (cloop = 16; cloop < 40; cloop += 4) {
1024 pci_bus_read_config_dword (pci_bus, devfn, cloop, &temp);
1025
1026 if (temp != func->config_space[cloop >> 2]) {
1027 dbg("Config space compare failure!!! offset = %x\n", cloop);
1028 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
1029 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
1030 return 1;
1031 }
1032 }
1033 }
1034
1035 func->configured = 1;
1036
1037 func = cpqhp_slot_find(func->bus, func->device, index++);
1038 }
1039
1040 return 0;
1041 }
1042
1043
1044 /*
1045 * cpqhp_valid_replace
1046 *
1047 * this function checks to see if a board is the same as the
1048 * one it is replacing. this check will detect if the device's
1049 * vendor or device id's are the same
1050 *
1051 * returns 0 if the board is the same nonzero otherwise
1052 */
1053 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func * func)
1054 {
1055 u8 cloop;
1056 u8 header_type;
1057 u8 secondary_bus;
1058 u8 type;
1059 u32 temp_register = 0;
1060 u32 base;
1061 u32 rc;
1062 struct pci_func *next;
1063 int index = 0;
1064 struct pci_bus *pci_bus = ctrl->pci_bus;
1065 unsigned int devfn;
1066
1067 if (!func->is_a_board)
1068 return(ADD_NOT_SUPPORTED);
1069
1070 func = cpqhp_slot_find(func->bus, func->device, index++);
1071
1072 while (func != NULL) {
1073 pci_bus->number = func->bus;
1074 devfn = PCI_DEVFN(func->device, func->function);
1075
1076 pci_bus_read_config_dword (pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1077
1078 /* No adapter present */
1079 if (temp_register == 0xFFFFFFFF)
1080 return(NO_ADAPTER_PRESENT);
1081
1082 if (temp_register != func->config_space[0])
1083 return(ADAPTER_NOT_SAME);
1084
1085 /* Check for same revision number and class code */
1086 pci_bus_read_config_dword (pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1087
1088 /* Adapter not the same */
1089 if (temp_register != func->config_space[0x08 >> 2])
1090 return(ADAPTER_NOT_SAME);
1091
1092 /* Check for Bridge */
1093 pci_bus_read_config_byte (pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1094
1095 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1096 /* In order to continue checking, we must program the
1097 * bus registers in the bridge to respond to accesses
1098 * for its subordinate bus(es)
1099 */
1100
1101 temp_register = func->config_space[0x18 >> 2];
1102 pci_bus_write_config_dword (pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1103
1104 secondary_bus = (temp_register >> 8) & 0xFF;
1105
1106 next = cpqhp_slot_list[secondary_bus];
1107
1108 while (next != NULL) {
1109 rc = cpqhp_valid_replace(ctrl, next);
1110 if (rc)
1111 return rc;
1112
1113 next = next->next;
1114 }
1115
1116 }
1117 /* Check to see if it is a standard config header */
1118 else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1119 /* Check subsystem vendor and ID */
1120 pci_bus_read_config_dword (pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1121
1122 if (temp_register != func->config_space[0x2C >> 2]) {
1123 /* If it's a SMART-2 and the register isn't
1124 * filled in, ignore the difference because
1125 * they just have an old rev of the firmware
1126 */
1127 if (!((func->config_space[0] == 0xAE100E11)
1128 && (temp_register == 0x00L)))
1129 return(ADAPTER_NOT_SAME);
1130 }
1131 /* Figure out IO and memory base lengths */
1132 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1133 temp_register = 0xFFFFFFFF;
1134 pci_bus_write_config_dword (pci_bus, devfn, cloop, temp_register);
1135 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base);
1136
1137 /* If this register is implemented */
1138 if (base) {
1139 if (base & 0x01L) {
1140 /* IO base
1141 * set base = amount of IO
1142 * space requested
1143 */
1144 base = base & 0xFFFFFFFE;
1145 base = (~base) + 1;
1146
1147 type = 1;
1148 } else {
1149 /* memory base */
1150 base = base & 0xFFFFFFF0;
1151 base = (~base) + 1;
1152
1153 type = 0;
1154 }
1155 } else {
1156 base = 0x0L;
1157 type = 0;
1158 }
1159
1160 /* Check information in slot structure */
1161 if (func->base_length[(cloop - 0x10) >> 2] != base)
1162 return(ADAPTER_NOT_SAME);
1163
1164 if (func->base_type[(cloop - 0x10) >> 2] != type)
1165 return(ADAPTER_NOT_SAME);
1166
1167 } /* End of base register loop */
1168
1169 } /* End of (type 0 config space) else */
1170 else {
1171 /* this is not a type 0 or 1 config space header so
1172 * we don't know how to do it
1173 */
1174 return(DEVICE_TYPE_NOT_SUPPORTED);
1175 }
1176
1177 /* Get the next function */
1178 func = cpqhp_slot_find(func->bus, func->device, index++);
1179 }
1180
1181
1182 return 0;
1183 }
1184
1185
1186 /*
1187 * cpqhp_find_available_resources
1188 *
1189 * Finds available memory, IO, and IRQ resources for programming
1190 * devices which may be added to the system
1191 * this function is for hot plug ADD!
1192 *
1193 * returns 0 if success
1194 */
1195 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1196 {
1197 u8 temp;
1198 u8 populated_slot;
1199 u8 bridged_slot;
1200 void __iomem *one_slot;
1201 void __iomem *rom_resource_table;
1202 struct pci_func *func = NULL;
1203 int i = 10, index;
1204 u32 temp_dword, rc;
1205 struct pci_resource *mem_node;
1206 struct pci_resource *p_mem_node;
1207 struct pci_resource *io_node;
1208 struct pci_resource *bus_node;
1209
1210 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1211 dbg("rom_resource_table = %p\n", rom_resource_table);
1212
1213 if (rom_resource_table == NULL) {
1214 return -ENODEV;
1215 }
1216 /* Sum all resources and setup resource maps */
1217 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1218 dbg("unused_IRQ = %x\n", unused_IRQ);
1219
1220 temp = 0;
1221 while (unused_IRQ) {
1222 if (unused_IRQ & 1) {
1223 cpqhp_disk_irq = temp;
1224 break;
1225 }
1226 unused_IRQ = unused_IRQ >> 1;
1227 temp++;
1228 }
1229
1230 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1231 unused_IRQ = unused_IRQ >> 1;
1232 temp++;
1233
1234 while (unused_IRQ) {
1235 if (unused_IRQ & 1) {
1236 cpqhp_nic_irq = temp;
1237 break;
1238 }
1239 unused_IRQ = unused_IRQ >> 1;
1240 temp++;
1241 }
1242
1243 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1244 unused_IRQ = readl(rom_resource_table + PCIIRQ);
1245
1246 temp = 0;
1247
1248 if (!cpqhp_nic_irq) {
1249 cpqhp_nic_irq = ctrl->cfgspc_irq;
1250 }
1251
1252 if (!cpqhp_disk_irq) {
1253 cpqhp_disk_irq = ctrl->cfgspc_irq;
1254 }
1255
1256 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1257
1258 rc = compaq_nvram_load(rom_start, ctrl);
1259 if (rc)
1260 return rc;
1261
1262 one_slot = rom_resource_table + sizeof (struct hrt);
1263
1264 i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1265 dbg("number_of_entries = %d\n", i);
1266
1267 if (!readb(one_slot + SECONDARY_BUS))
1268 return 1;
1269
1270 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1271
1272 while (i && readb(one_slot + SECONDARY_BUS)) {
1273 u8 dev_func = readb(one_slot + DEV_FUNC);
1274 u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1275 u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1276 u8 max_bus = readb(one_slot + MAX_BUS);
1277 u16 io_base = readw(one_slot + IO_BASE);
1278 u16 io_length = readw(one_slot + IO_LENGTH);
1279 u16 mem_base = readw(one_slot + MEM_BASE);
1280 u16 mem_length = readw(one_slot + MEM_LENGTH);
1281 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1282 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1283
1284 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
1285 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1286 primary_bus, secondary_bus, max_bus);
1287
1288 /* If this entry isn't for our controller's bus, ignore it */
1289 if (primary_bus != ctrl->bus) {
1290 i--;
1291 one_slot += sizeof (struct slot_rt);
1292 continue;
1293 }
1294 /* find out if this entry is for an occupied slot */
1295 ctrl->pci_bus->number = primary_bus;
1296 pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1297 dbg("temp_D_word = %x\n", temp_dword);
1298
1299 if (temp_dword != 0xFFFFFFFF) {
1300 index = 0;
1301 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1302
1303 while (func && (func->function != (dev_func & 0x07))) {
1304 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1305 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1306 }
1307
1308 /* If we can't find a match, skip this table entry */
1309 if (!func) {
1310 i--;
1311 one_slot += sizeof (struct slot_rt);
1312 continue;
1313 }
1314 /* this may not work and shouldn't be used */
1315 if (secondary_bus != primary_bus)
1316 bridged_slot = 1;
1317 else
1318 bridged_slot = 0;
1319
1320 populated_slot = 1;
1321 } else {
1322 populated_slot = 0;
1323 bridged_slot = 0;
1324 }
1325
1326
1327 /* If we've got a valid IO base, use it */
1328
1329 temp_dword = io_base + io_length;
1330
1331 if ((io_base) && (temp_dword < 0x10000)) {
1332 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1333 if (!io_node)
1334 return -ENOMEM;
1335
1336 io_node->base = io_base;
1337 io_node->length = io_length;
1338
1339 dbg("found io_node(base, length) = %x, %x\n",
1340 io_node->base, io_node->length);
1341 dbg("populated slot =%d \n", populated_slot);
1342 if (!populated_slot) {
1343 io_node->next = ctrl->io_head;
1344 ctrl->io_head = io_node;
1345 } else {
1346 io_node->next = func->io_head;
1347 func->io_head = io_node;
1348 }
1349 }
1350
1351 /* If we've got a valid memory base, use it */
1352 temp_dword = mem_base + mem_length;
1353 if ((mem_base) && (temp_dword < 0x10000)) {
1354 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1355 if (!mem_node)
1356 return -ENOMEM;
1357
1358 mem_node->base = mem_base << 16;
1359
1360 mem_node->length = mem_length << 16;
1361
1362 dbg("found mem_node(base, length) = %x, %x\n",
1363 mem_node->base, mem_node->length);
1364 dbg("populated slot =%d \n", populated_slot);
1365 if (!populated_slot) {
1366 mem_node->next = ctrl->mem_head;
1367 ctrl->mem_head = mem_node;
1368 } else {
1369 mem_node->next = func->mem_head;
1370 func->mem_head = mem_node;
1371 }
1372 }
1373
1374 /* If we've got a valid prefetchable memory base, and
1375 * the base + length isn't greater than 0xFFFF
1376 */
1377 temp_dword = pre_mem_base + pre_mem_length;
1378 if ((pre_mem_base) && (temp_dword < 0x10000)) {
1379 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1380 if (!p_mem_node)
1381 return -ENOMEM;
1382
1383 p_mem_node->base = pre_mem_base << 16;
1384
1385 p_mem_node->length = pre_mem_length << 16;
1386 dbg("found p_mem_node(base, length) = %x, %x\n",
1387 p_mem_node->base, p_mem_node->length);
1388 dbg("populated slot =%d \n", populated_slot);
1389
1390 if (!populated_slot) {
1391 p_mem_node->next = ctrl->p_mem_head;
1392 ctrl->p_mem_head = p_mem_node;
1393 } else {
1394 p_mem_node->next = func->p_mem_head;
1395 func->p_mem_head = p_mem_node;
1396 }
1397 }
1398
1399 /* If we've got a valid bus number, use it
1400 * The second condition is to ignore bus numbers on
1401 * populated slots that don't have PCI-PCI bridges
1402 */
1403 if (secondary_bus && (secondary_bus != primary_bus)) {
1404 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1405 if (!bus_node)
1406 return -ENOMEM;
1407
1408 bus_node->base = secondary_bus;
1409 bus_node->length = max_bus - secondary_bus + 1;
1410 dbg("found bus_node(base, length) = %x, %x\n",
1411 bus_node->base, bus_node->length);
1412 dbg("populated slot =%d \n", populated_slot);
1413 if (!populated_slot) {
1414 bus_node->next = ctrl->bus_head;
1415 ctrl->bus_head = bus_node;
1416 } else {
1417 bus_node->next = func->bus_head;
1418 func->bus_head = bus_node;
1419 }
1420 }
1421
1422 i--;
1423 one_slot += sizeof (struct slot_rt);
1424 }
1425
1426 /* If all of the following fail, we don't have any resources for
1427 * hot plug add
1428 */
1429 rc = 1;
1430 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1431 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1432 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1433 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1434
1435 return rc;
1436 }
1437
1438
1439 /*
1440 * cpqhp_return_board_resources
1441 *
1442 * this routine returns all resources allocated to a board to
1443 * the available pool.
1444 *
1445 * returns 0 if success
1446 */
1447 int cpqhp_return_board_resources(struct pci_func * func, struct resource_lists * resources)
1448 {
1449 int rc = 0;
1450 struct pci_resource *node;
1451 struct pci_resource *t_node;
1452 dbg("%s\n", __func__);
1453
1454 if (!func)
1455 return 1;
1456
1457 node = func->io_head;
1458 func->io_head = NULL;
1459 while (node) {
1460 t_node = node->next;
1461 return_resource(&(resources->io_head), node);
1462 node = t_node;
1463 }
1464
1465 node = func->mem_head;
1466 func->mem_head = NULL;
1467 while (node) {
1468 t_node = node->next;
1469 return_resource(&(resources->mem_head), node);
1470 node = t_node;
1471 }
1472
1473 node = func->p_mem_head;
1474 func->p_mem_head = NULL;
1475 while (node) {
1476 t_node = node->next;
1477 return_resource(&(resources->p_mem_head), node);
1478 node = t_node;
1479 }
1480
1481 node = func->bus_head;
1482 func->bus_head = NULL;
1483 while (node) {
1484 t_node = node->next;
1485 return_resource(&(resources->bus_head), node);
1486 node = t_node;
1487 }
1488
1489 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1490 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1491 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1492 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1493
1494 return rc;
1495 }
1496
1497
1498 /*
1499 * cpqhp_destroy_resource_list
1500 *
1501 * Puts node back in the resource list pointed to by head
1502 */
1503 void cpqhp_destroy_resource_list (struct resource_lists * resources)
1504 {
1505 struct pci_resource *res, *tres;
1506
1507 res = resources->io_head;
1508 resources->io_head = NULL;
1509
1510 while (res) {
1511 tres = res;
1512 res = res->next;
1513 kfree(tres);
1514 }
1515
1516 res = resources->mem_head;
1517 resources->mem_head = NULL;
1518
1519 while (res) {
1520 tres = res;
1521 res = res->next;
1522 kfree(tres);
1523 }
1524
1525 res = resources->p_mem_head;
1526 resources->p_mem_head = NULL;
1527
1528 while (res) {
1529 tres = res;
1530 res = res->next;
1531 kfree(tres);
1532 }
1533
1534 res = resources->bus_head;
1535 resources->bus_head = NULL;
1536
1537 while (res) {
1538 tres = res;
1539 res = res->next;
1540 kfree(tres);
1541 }
1542 }
1543
1544
1545 /*
1546 * cpqhp_destroy_board_resources
1547 *
1548 * Puts node back in the resource list pointed to by head
1549 */
1550 void cpqhp_destroy_board_resources (struct pci_func * func)
1551 {
1552 struct pci_resource *res, *tres;
1553
1554 res = func->io_head;
1555 func->io_head = NULL;
1556
1557 while (res) {
1558 tres = res;
1559 res = res->next;
1560 kfree(tres);
1561 }
1562
1563 res = func->mem_head;
1564 func->mem_head = NULL;
1565
1566 while (res) {
1567 tres = res;
1568 res = res->next;
1569 kfree(tres);
1570 }
1571
1572 res = func->p_mem_head;
1573 func->p_mem_head = NULL;
1574
1575 while (res) {
1576 tres = res;
1577 res = res->next;
1578 kfree(tres);
1579 }
1580
1581 res = func->bus_head;
1582 func->bus_head = NULL;
1583
1584 while (res) {
1585 tres = res;
1586 res = res->next;
1587 kfree(tres);
1588 }
1589 }
1590
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree