drivers/media/dvb/frontends/dibx000_common.h

   1 #ifndef DIBX000_COMMON_H
   2 #define DIBX000_COMMON_H
   3
   4 enum dibx000_i2c_interface {
   5         DIBX000_I2C_INTERFACE_TUNER = 0,
   6         DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
   7         DIBX000_I2C_INTERFACE_GPIO_3_4 = 2,
   8         DIBX000_I2C_INTERFACE_GPIO_6_7 = 3
   9 };
  10
  11 struct dibx000_i2c_master {
  12 #define DIB3000MC 1
  13 #define DIB7000   2
  14 #define DIB7000P  11
  15 #define DIB7000MC 12
  16 #define DIB8000   13
  17         u16 device_rev;
  18
  19         enum dibx000_i2c_interface selected_interface;
  20
  21 //      struct i2c_adapter  tuner_i2c_adap;
  22         struct i2c_adapter gated_tuner_i2c_adap;
  23         struct i2c_adapter master_i2c_adap_gpio12;
  24         struct i2c_adapter master_i2c_adap_gpio34;
  25         struct i2c_adapter master_i2c_adap_gpio67;
  26
  27         struct i2c_adapter *i2c_adap;
  28         u8 i2c_addr;
  29
  30         u16 base_reg;
  31 };
  32
  33 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
  34                                         u16 device_rev, struct i2c_adapter *i2c_adap,
  35                                         u8 i2c_addr);
  36 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
  37                                                         *mst,
  38                                                         enum dibx000_i2c_interface
  39                                                         intf, int gating);
  40 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
  41 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
  42 extern int dibx000_i2c_set_speed(struct i2c_adapter *i2c_adap, u16 speed);
  43
  44 extern u32 systime(void);
  45
  46 #define BAND_LBAND 0x01
  47 #define BAND_UHF   0x02
  48 #define BAND_VHF   0x04
  49 #define BAND_SBAND 0x08
  50 #define BAND_FM    0x10
  51 #define BAND_CBAND 0x20
  52
  53 #define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 170000 ? BAND_CBAND : \
  54                                                                         (freq_kHz) <= 115000 ? BAND_FM : \
  55                                                                         (freq_kHz) <= 250000 ? BAND_VHF : \
  56                                                                         (freq_kHz) <= 863000 ? BAND_UHF : \
  57                                                                         (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
  58
  59 struct dibx000_agc_config {
  60         /* defines the capabilities of this AGC-setting - using the BAND_-defines */
  61         u8 band_caps;
  62
  63         u16 setup;
  64
  65         u16 inv_gain;
  66         u16 time_stabiliz;
  67
  68         u8 alpha_level;
  69         u16 thlock;
  70
  71         u8 wbd_inv;
  72         u16 wbd_ref;
  73         u8 wbd_sel;
  74         u8 wbd_alpha;
  75
  76         u16 agc1_max;
  77         u16 agc1_min;
  78         u16 agc2_max;
  79         u16 agc2_min;
  80
  81         u8 agc1_pt1;
  82         u8 agc1_pt2;
  83         u8 agc1_pt3;
  84
  85         u8 agc1_slope1;
  86         u8 agc1_slope2;
  87
  88         u8 agc2_pt1;
  89         u8 agc2_pt2;
  90
  91         u8 agc2_slope1;
  92         u8 agc2_slope2;
  93
  94         u8 alpha_mant;
  95         u8 alpha_exp;
  96
  97         u8 beta_mant;
  98         u8 beta_exp;
  99
 100         u8 perform_agc_softsplit;
 101
 102         struct {
 103                 u16 min;
 104                 u16 max;
 105                 u16 min_thres;
 106                 u16 max_thres;
 107         } split;
 108 };
 109
 110 struct dibx000_bandwidth_config {
 111         u32 internal;
 112         u32 sampling;
 113
 114         u8 pll_prediv;
 115         u8 pll_ratio;
 116         u8 pll_range;
 117         u8 pll_reset;
 118         u8 pll_bypass;
 119
 120         u8 enable_refdiv;
 121         u8 bypclk_div;
 122         u8 IO_CLK_en_core;
 123         u8 ADClkSrc;
 124         u8 modulo;
 125
 126         u16 sad_cfg;
 127
 128         u32 ifreq;
 129         u32 timf;
 130
 131         u32 xtal_hz;
 132 };
 133
 134 enum dibx000_adc_states {
 135         DIBX000_SLOW_ADC_ON = 0,
 136         DIBX000_SLOW_ADC_OFF,
 137         DIBX000_ADC_ON,
 138         DIBX000_ADC_OFF,
 139         DIBX000_VBG_ENABLE,
 140         DIBX000_VBG_DISABLE,
 141 };
 142
 143 #define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ  ? 8000 : \
 144                              (v) == BANDWIDTH_7_MHZ  ? 7000 : \
 145                              (v) == BANDWIDTH_6_MHZ  ? 6000 : 8000 )
 146
 147 #define BANDWIDTH_TO_INDEX(v) ( \
 148         (v) == 8000 ? BANDWIDTH_8_MHZ : \
 149                 (v) == 7000 ? BANDWIDTH_7_MHZ : \
 150                 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
 151
 152 /* Chip output mode. */
 153 #define OUTMODE_HIGH_Z              0
 154 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
 155 #define OUTMODE_MPEG2_PAR_CONT_CLK  2
 156 #define OUTMODE_MPEG2_SERIAL        7
 157 #define OUTMODE_DIVERSITY           4
 158 #define OUTMODE_MPEG2_FIFO          5
 159 #define OUTMODE_ANALOG_ADC          6
 160
 161 enum frontend_tune_state {
 162     CT_TUNER_START = 10,
 163     CT_TUNER_STEP_0,
 164     CT_TUNER_STEP_1,
 165     CT_TUNER_STEP_2,
 166     CT_TUNER_STEP_3,
 167     CT_TUNER_STEP_4,
 168     CT_TUNER_STEP_5,
 169     CT_TUNER_STEP_6,
 170     CT_TUNER_STEP_7,
 171     CT_TUNER_STOP,
 172
 173     CT_AGC_START = 20,
 174     CT_AGC_STEP_0,
 175     CT_AGC_STEP_1,
 176     CT_AGC_STEP_2,
 177     CT_AGC_STEP_3,
 178     CT_AGC_STEP_4,
 179     CT_AGC_STOP,
 180
 181         CT_DEMOD_START = 30,
 182     CT_DEMOD_STEP_1,
 183     CT_DEMOD_STEP_2,
 184     CT_DEMOD_STEP_3,
 185     CT_DEMOD_STEP_4,
 186     CT_DEMOD_STEP_5,
 187     CT_DEMOD_STEP_6,
 188     CT_DEMOD_STEP_7,
 189     CT_DEMOD_STEP_8,
 190     CT_DEMOD_STEP_9,
 191     CT_DEMOD_STEP_10,
 192     CT_DEMOD_SEARCH_NEXT = 41,
 193     CT_DEMOD_STEP_LOCKED,
 194     CT_DEMOD_STOP,
 195
 196     CT_DONE = 100,
 197     CT_SHUTDOWN,
 198
 199 };
 200
 201 struct dvb_frontend_parametersContext {
 202 #define CHANNEL_STATUS_PARAMETERS_UNKNOWN   0x01
 203 #define CHANNEL_STATUS_PARAMETERS_SET       0x02
 204     u8 status;
 205     u32 tune_time_estimation[2];
 206     s32 tps_available;
 207     u16 tps[9];
 208 };
 209
 210 #define FE_STATUS_TUNE_FAILED          0
 211 #define FE_STATUS_TUNE_TIMED_OUT      -1
 212 #define FE_STATUS_TUNE_TIME_TOO_SHORT -2
 213 #define FE_STATUS_TUNE_PENDING        -3
 214 #define FE_STATUS_STD_SUCCESS         -4
 215 #define FE_STATUS_FFT_SUCCESS         -5
 216 #define FE_STATUS_DEMOD_SUCCESS       -6
 217 #define FE_STATUS_LOCKED              -7
 218 #define FE_STATUS_DATA_LOCKED         -8
 219
 220 #define FE_CALLBACK_TIME_NEVER 0xffffffff
 221
 222 #define ABS(x) ((x<0)?(-x):(x))
 223
 224 #define DATA_BUS_ACCESS_MODE_8BIT                 0x01
 225 #define DATA_BUS_ACCESS_MODE_16BIT                0x02
 226 #define DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT 0x10
 227
 228 struct dibGPIOFunction {
 229 #define BOARD_GPIO_COMPONENT_BUS_ADAPTER 1
 230 #define BOARD_GPIO_COMPONENT_DEMOD       2
 231         u8 component;
 232
 233 #define BOARD_GPIO_FUNCTION_BOARD_ON      1
 234 #define BOARD_GPIO_FUNCTION_BOARD_OFF     2
 235 #define BOARD_GPIO_FUNCTION_COMPONENT_ON  3
 236 #define BOARD_GPIO_FUNCTION_COMPONENT_OFF 4
 237 #define BOARD_GPIO_FUNCTION_SUBBAND_PWM   5
 238 #define BOARD_GPIO_FUNCTION_SUBBAND_GPIO   6
 239         u8 function;
 240
 241 /* mask, direction and value are used specify which GPIO to change GPIO0
 242  * is LSB and possible GPIO31 is MSB.  The same bit-position as in the
 243  * mask is used for the direction and the value. Direction == 1 is OUT,
 244  * 0 == IN. For direction "OUT" value is either 1 or 0, for direction IN
 245  * value has no meaning.
 246  *
 247  * In case of BOARD_GPIO_FUNCTION_PWM mask is giving the GPIO to be
 248  * used to do the PWM. Direction gives the PWModulator to be used.
 249  * Value gives the PWM value in device-dependent scale.
 250  */
 251         u32 mask;
 252         u32 direction;
 253         u32 value;
 254 };
 255
 256 #define MAX_NB_SUBBANDS   8
 257 struct dibSubbandSelection {
 258         u8  size; /* Actual number of subbands. */
 259         struct {
 260                 u16 f_mhz;
 261                 struct dibGPIOFunction gpio;
 262         } subband[MAX_NB_SUBBANDS];
 263 };
 264
 265 #define DEMOD_TIMF_SET    0x00
 266 #define DEMOD_TIMF_GET    0x01
 267 #define DEMOD_TIMF_UPDATE 0x02
 268
 269 #endif