2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/slab.h>
43 #include <linux/interrupt.h>
44 #include <linux/spinlock.h>
45 #include <linux/platform_device.h>
46 #include <linux/platform_data/dwc3-omap.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/ioport.h>
54 * All these registers belong to OMAP's Wrapper around the
55 * DesignWare USB3 Core.
58 #define USBOTGSS_REVISION 0x0000
59 #define USBOTGSS_SYSCONFIG 0x0010
60 #define USBOTGSS_IRQ_EOI 0x0020
61 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
62 #define USBOTGSS_IRQSTATUS_0 0x0028
63 #define USBOTGSS_IRQENABLE_SET_0 0x002c
64 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
65 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034
66 #define USBOTGSS_IRQSTATUS_1 0x0038
67 #define USBOTGSS_IRQENABLE_SET_1 0x003c
68 #define USBOTGSS_IRQENABLE_CLR_1 0x0040
69 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
70 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
71 #define USBOTGSS_MMRAM_OFFSET 0x0100
72 #define USBOTGSS_FLADJ 0x0104
73 #define USBOTGSS_DEBUG_CFG 0x0108
74 #define USBOTGSS_DEBUG_DATA 0x010c
76 /* SYSCONFIG REGISTER */
77 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
78 #define USBOTGSS_SYSCONFIG_STANDBYMODE(x) ((x) << 4)
79 #define USBOTGSS_SYSCONFIG_IDLEMODE(x) ((x) << 2)
81 /* IRQ_EOI REGISTER */
82 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
85 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
88 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
89 #define USBOTGSS_IRQ1_OEVT (1 << 16)
90 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
91 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
92 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
93 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
94 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
95 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
96 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
97 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
99 /* UTMI_OTG_CTRL REGISTER */
100 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
101 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
102 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
103 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
105 /* UTMI_OTG_STATUS REGISTER */
106 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
107 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
108 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
109 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
110 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
111 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
112 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
118 struct platform_device
*dwc3
;
130 static irqreturn_t
dwc3_omap_interrupt(int irq
, void *_omap
)
132 struct dwc3_omap
*omap
= _omap
;
136 spin_lock(&omap
->lock
);
138 reg
= dwc3_readl(omap
->base
, USBOTGSS_IRQSTATUS_1
);
139 ctrl
= dwc3_readl(omap
->base
, USBOTGSS_UTMI_OTG_CTRL
);
141 if (reg
& USBOTGSS_IRQ1_DMADISABLECLR
) {
142 dev_dbg(omap
->dev
, "DMA Disable was Cleared\n");
143 omap
->dma_status
= false;
146 if (reg
& USBOTGSS_IRQ1_OEVT
)
147 dev_dbg(omap
->dev
, "OTG Event\n");
149 if (reg
& USBOTGSS_IRQ1_DRVVBUS_RISE
) {
150 dev_dbg(omap
->dev
, "DRVVBUS Rise\n");
151 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_DRVVBUS
;
154 if (reg
& USBOTGSS_IRQ1_CHRGVBUS_RISE
) {
155 dev_dbg(omap
->dev
, "CHRGVBUS Rise\n");
156 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS
;
159 if (reg
& USBOTGSS_IRQ1_DISCHRGVBUS_RISE
) {
160 dev_dbg(omap
->dev
, "DISCHRGVBUS Rise\n");
161 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS
;
164 if (reg
& USBOTGSS_IRQ1_IDPULLUP_RISE
) {
165 dev_dbg(omap
->dev
, "IDPULLUP Rise\n");
166 ctrl
|= USBOTGSS_UTMI_OTG_CTRL_IDPULLUP
;
169 if (reg
& USBOTGSS_IRQ1_DRVVBUS_FALL
) {
170 dev_dbg(omap
->dev
, "DRVVBUS Fall\n");
171 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_DRVVBUS
;
174 if (reg
& USBOTGSS_IRQ1_CHRGVBUS_FALL
) {
175 dev_dbg(omap
->dev
, "CHRGVBUS Fall\n");
176 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS
;
179 if (reg
& USBOTGSS_IRQ1_DISCHRGVBUS_FALL
) {
180 dev_dbg(omap
->dev
, "DISCHRGVBUS Fall\n");
181 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS
;
184 if (reg
& USBOTGSS_IRQ1_IDPULLUP_FALL
) {
185 dev_dbg(omap
->dev
, "IDPULLUP Fall\n");
186 ctrl
&= ~USBOTGSS_UTMI_OTG_CTRL_IDPULLUP
;
189 dwc3_writel(omap
->base
, USBOTGSS_UTMI_OTG_CTRL
, ctrl
);
191 spin_unlock(&omap
->lock
);
196 static int __devinit
dwc3_omap_probe(struct platform_device
*pdev
)
198 struct dwc3_omap_data
*pdata
= pdev
->dev
.platform_data
;
199 struct platform_device
*dwc3
;
200 struct dwc3_omap
*omap
;
201 struct resource
*res
;
211 omap
= kzalloc(sizeof(*omap
), GFP_KERNEL
);
213 dev_err(&pdev
->dev
, "not enough memory\n");
217 platform_set_drvdata(pdev
, omap
);
219 irq
= platform_get_irq(pdev
, 1);
221 dev_err(&pdev
->dev
, "missing IRQ resource\n");
226 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
228 dev_err(&pdev
->dev
, "missing memory base resource\n");
233 base
= ioremap_nocache(res
->start
, resource_size(res
));
235 dev_err(&pdev
->dev
, "ioremap failed\n");
239 dwc3
= platform_device_alloc("dwc3-omap", -1);
241 dev_err(&pdev
->dev
, "couldn't allocate dwc3 device\n");
245 context
= kzalloc(resource_size(res
), GFP_KERNEL
);
247 dev_err(&pdev
->dev
, "couldn't allocate dwc3 context memory\n");
251 spin_lock_init(&omap
->lock
);
252 dma_set_coherent_mask(&dwc3
->dev
, pdev
->dev
.coherent_dma_mask
);
254 dwc3
->dev
.parent
= &pdev
->dev
;
255 dwc3
->dev
.dma_mask
= pdev
->dev
.dma_mask
;
256 dwc3
->dev
.dma_parms
= pdev
->dev
.dma_parms
;
257 omap
->resource_size
= resource_size(res
);
258 omap
->context
= context
;
259 omap
->dev
= &pdev
->dev
;
264 reg
= dwc3_readl(omap
->base
, USBOTGSS_UTMI_OTG_STATUS
);
267 dev_dbg(&pdev
->dev
, "missing platform data\n");
269 switch (pdata
->utmi_mode
) {
270 case DWC3_OMAP_UTMI_MODE_SW
:
271 reg
|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE
;
273 case DWC3_OMAP_UTMI_MODE_HW
:
274 reg
&= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE
;
277 dev_dbg(&pdev
->dev
, "UNKNOWN utmi mode %d\n",
282 dwc3_writel(omap
->base
, USBOTGSS_UTMI_OTG_STATUS
, reg
);
284 /* check the DMA Status */
285 reg
= dwc3_readl(omap
->base
, USBOTGSS_SYSCONFIG
);
286 omap
->dma_status
= !!(reg
& USBOTGSS_SYSCONFIG_DMADISABLE
);
288 ret
= request_irq(omap
->irq
, dwc3_omap_interrupt
, 0,
291 dev_err(&pdev
->dev
, "failed to request IRQ #%d --> %d\n",
296 /* enable all IRQs */
297 reg
= USBOTGSS_IRQO_COREIRQ_ST
;
298 dwc3_writel(omap
->base
, USBOTGSS_IRQENABLE_SET_0
, reg
);
300 reg
= (USBOTGSS_IRQ1_OEVT
|
301 USBOTGSS_IRQ1_DRVVBUS_RISE
|
302 USBOTGSS_IRQ1_CHRGVBUS_RISE
|
303 USBOTGSS_IRQ1_DISCHRGVBUS_RISE
|
304 USBOTGSS_IRQ1_IDPULLUP_RISE
|
305 USBOTGSS_IRQ1_DRVVBUS_FALL
|
306 USBOTGSS_IRQ1_CHRGVBUS_FALL
|
307 USBOTGSS_IRQ1_DISCHRGVBUS_FALL
|
308 USBOTGSS_IRQ1_IDPULLUP_FALL
);
310 dwc3_writel(omap
->base
, USBOTGSS_IRQENABLE_SET_1
, reg
);
312 ret
= platform_device_add_resources(dwc3
, pdev
->resource
,
313 pdev
->num_resources
);
315 dev_err(&pdev
->dev
, "couldn't add resources to dwc3 device\n");
319 ret
= platform_device_add(dwc3
);
321 dev_err(&pdev
->dev
, "failed to register dwc3 device\n");
328 free_irq(omap
->irq
, omap
);
331 kfree(omap
->context
);
334 platform_device_put(dwc3
);
346 static int __devexit
dwc3_omap_remove(struct platform_device
*pdev
)
348 struct dwc3_omap
*omap
= platform_get_drvdata(pdev
);
350 platform_device_unregister(omap
->dwc3
);
352 free_irq(omap
->irq
, omap
);
355 kfree(omap
->context
);
361 static const struct of_device_id of_dwc3_matach
[] = {
367 MODULE_DEVICE_TABLE(of
, of_dwc3_matach
);
369 static struct platform_driver dwc3_omap_driver
= {
370 .probe
= dwc3_omap_probe
,
371 .remove
= __devexit_p(dwc3_omap_remove
),
374 .of_match_table
= of_dwc3_matach
,
378 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
379 MODULE_LICENSE("Dual BSD/GPL");
380 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
382 static int __devinit
dwc3_omap_init(void)
384 return platform_driver_register(&dwc3_omap_driver
);
386 module_init(dwc3_omap_init
);
388 static void __exit
dwc3_omap_exit(void)
390 platform_driver_unregister(&dwc3_omap_driver
);
392 module_exit(dwc3_omap_exit
);