drivers/staging/dt3155/dt3155_io.h

   1 /*
   2
   3 Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
   4                     Jason Lapenta, Scott Smedley
   5
   6 This file is part of the DT3155 Device Driver.
   7
   8 The DT3155 Device Driver is free software; you can redistribute it
   9 and/or modify it under the terms of the GNU General Public License as
  10 published by the Free Software Foundation; either version 2 of the
  11 License, or (at your option) any later version.
  12
  13 The DT3155 Device Driver is distributed in the hope that it will be
  14 useful, but WITHOUT ANY WARRANTY; without even the implied warranty
  15 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with the DT3155 Device Driver; if not, write to the Free
  20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 MA 02111-1307 USA
  22
  23
  24 -- Changes --
  25
  26   Date     Programmer  Description of changes made
  27   -------------------------------------------------------------------
  28   24-Jul-2002 SS       GPL licence.
  29
  30 */
  31
  32 /* This code is a modified version of examples provided by Data Translations.*/
  33
  34 #ifndef DT3155_IO_INC
  35 #define DT3155_IO_INC
  36
  37 /* macros to access registers */
  38
  39 #define WriteMReg(Address, Data)        (*((u64 *)(Address)) = Data)
  40 #define ReadMReg(Address, Data)         (Data = *((u64 *)(Address)))
  41
  42 /***************** 32 bit register globals  **************/
  43
  44 /*  offsets for 32-bit memory mapped registers */
  45
  46 #define EVEN_DMA_START          0x000
  47 #define ODD_DMA_START           0x00C
  48 #define EVEN_DMA_STRIDE         0x018
  49 #define ODD_DMA_STRIDE          0x024
  50 #define EVEN_PIXEL_FMT          0x030
  51 #define ODD_PIXEL_FMT           0x034
  52 #define FIFO_TRIGGER            0x038
  53 #define XFER_MODE               0x03C
  54 #define CSR1                    0x040
  55 #define RETRY_WAIT_CNT          0x044
  56 #define INT_CSR                 0x048
  57 #define EVEN_FLD_MASK           0x04C
  58 #define ODD_FLD_MASK            0x050
  59 #define MASK_LENGTH             0x054
  60 #define FIFO_FLAG_CNT           0x058
  61 #define IIC_CLK_DUR             0x05C
  62 #define IIC_CSR1                0x060
  63 #define IIC_CSR2                0x064
  64 #define EVEN_DMA_UPPR_LMT       0x08C
  65 #define ODD_DMA_UPPR_LMT        0x090
  66
  67 #define CLK_DUR_VAL             0x01010101
  68
  69
  70
  71 /******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
  72
  73 typedef union fifo_trigger_tag {
  74         u64   reg;
  75         struct {
  76                 u64 PACKED:6;
  77                 u64       :9;
  78                 u64 PLANER:7;
  79                 u64       :9;
  80         } fld;
  81 } FIFO_TRIGGER_R;
  82
  83 typedef union xfer_mode_tag {
  84         u64   reg;
  85         struct {
  86                 u64             :2;
  87                 u64 FIELD_TOGGLE:1;
  88                 u64             :5;
  89                 u64             :2;
  90                 u64             :22;
  91         } fld;
  92 } XFER_MODE_R;
  93
  94 typedef union csr1_tag {
  95         u64   reg;
  96         struct {
  97                 u64 CAP_CONT_EVE:1;
  98                 u64 CAP_CONT_ODD:1;
  99                 u64 CAP_SNGL_EVE:1;
 100                 u64 CAP_SNGL_ODD:1;
 101                 u64 FLD_DN_EVE  :1;
 102                 u64 FLD_DN_ODD  :1;
 103                 u64 SRST        :1;
 104                 u64 FIFO_EN     :1;
 105                 u64 FLD_CRPT_EVE:1;
 106                 u64 FLD_CRPT_ODD:1;
 107                 u64 ADDR_ERR_EVE:1;
 108                 u64 ADDR_ERR_ODD:1;
 109                 u64 CRPT_DIS    :1;
 110                 u64 RANGE_EN    :1;
 111                 u64             :16;
 112         } fld;
 113 } CSR1_R;
 114
 115 typedef union retry_wait_cnt_tag {
 116         u64   reg;
 117         struct {
 118                 u64 RTRY_WAIT_CNT:8;
 119                 u64              :24;
 120         } fld;
 121 } RETRY_WAIT_CNT_R;
 122
 123 typedef union int_csr_tag {
 124         u64   reg;
 125         struct {
 126                 u64 FLD_END_EVE   :1;
 127                 u64 FLD_END_ODD   :1;
 128                 u64 FLD_START     :1;
 129                 u64               :5;
 130                 u64 FLD_END_EVE_EN:1;
 131                 u64 FLD_END_ODD_EN:1;
 132                 u64 FLD_START_EN  :1;
 133                 u64               :21;
 134         } fld;
 135 } INT_CSR_R;
 136
 137 typedef union mask_length_tag {
 138         u64   reg;
 139         struct {
 140                 u64 MASK_LEN_EVE:5;
 141                 u64             :11;
 142                 u64 MASK_LEN_ODD:5;
 143                 u64             :11;
 144         } fld;
 145 } MASK_LENGTH_R;
 146
 147 typedef union fifo_flag_cnt_tag {
 148         u64   reg;
 149         struct {
 150                 u64 AF_COUNT:7;
 151                 u64         :9;
 152                 u64 AE_COUNT:7;
 153                 u64         :9;
 154         } fld;
 155 } FIFO_FLAG_CNT_R;
 156
 157 typedef union iic_clk_dur {
 158         u64   reg;
 159         struct {
 160                 u64 PHASE_1:8;
 161                 u64 PHASE_2:8;
 162                 u64 PHASE_3:8;
 163                 u64 PHASE_4:8;
 164         } fld;
 165 } IIC_CLK_DUR_R;
 166
 167 typedef union iic_csr1_tag {
 168         u64   reg;
 169         struct {
 170                 u64 AUTO_EN     :1;
 171                 u64 BYPASS      :1;
 172                 u64 SDA_OUT     :1;
 173                 u64 SCL_OUT     :1;
 174                 u64             :4;
 175                 u64 AUTO_ABORT  :1;
 176                 u64 DIRECT_ABORT:1;
 177                 u64 SDA_IN      :1;
 178                 u64 SCL_IN      :1;
 179                 u64             :4;
 180                 u64 AUTO_ADDR   :8;
 181                 u64 RD_DATA     :8;
 182         } fld;
 183 } IIC_CSR1_R;
 184
 185 /**********************************
 186  * iic_csr2_tag
 187  */
 188 typedef union iic_csr2_tag {
 189         u64   reg;
 190         struct {
 191                 u64 DIR_WR_DATA :8;
 192                 u64 DIR_SUB_ADDR:8;
 193                 u64 DIR_RD      :1;
 194                 u64 DIR_ADDR    :7;
 195                 u64 NEW_CYCLE   :1;
 196                 u64             :7;
 197         } fld;
 198 }  IIC_CSR2_R;
 199
 200 /* use for both EVEN and ODD DMA UPPER LIMITS */
 201
 202 /*
 203  * dma_upper_lmt_tag
 204  */
 205 typedef union dma_upper_lmt_tag   {
 206         u64 reg;
 207         struct {
 208                 u64 DMA_UPPER_LMT_VAL:24;
 209                 u64                  :8;
 210         } fld;
 211 } DMA_UPPER_LMT_R;
 212
 213
 214 /*
 215  * Global declarations of local copies of boards' 32 bit registers
 216  */
 217 extern u64 even_dma_start_r;            /*  bit 0 should always be 0 */
 218 extern u64 odd_dma_start_r;             /*               ..          */
 219 extern u64 even_dma_stride_r;   /*  bits 0&1 should always be 0 */
 220 extern u64 odd_dma_stride_r;            /*               ..             */
 221 extern u64 even_pixel_fmt_r;
 222 extern u64 odd_pixel_fmt_r;
 223
 224 extern FIFO_TRIGGER_R           fifo_trigger_r;
 225 extern XFER_MODE_R              xfer_mode_r;
 226 extern CSR1_R                   csr1_r;
 227 extern RETRY_WAIT_CNT_R         retry_wait_cnt_r;
 228 extern INT_CSR_R                int_csr_r;
 229
 230 extern u64 even_fld_mask_r;
 231 extern u64 odd_fld_mask_r;
 232
 233 extern MASK_LENGTH_R            mask_length_r;
 234 extern FIFO_FLAG_CNT_R          fifo_flag_cnt_r;
 235 extern IIC_CLK_DUR_R            iic_clk_dur_r;
 236 extern IIC_CSR1_R               iic_csr1_r;
 237 extern IIC_CSR2_R               iic_csr2_r;
 238 extern DMA_UPPER_LMT_R          even_dma_upper_lmt_r;
 239 extern DMA_UPPER_LMT_R          odd_dma_upper_lmt_r;
 240
 241
 242
 243 /***************** 8 bit I2C register globals  ***********/
 244 #define CSR2            0x010   /* indices of 8-bit I2C mapped reg's*/
 245 #define EVEN_CSR        0x011
 246 #define ODD_CSR         0x012
 247 #define CONFIG          0x013
 248 #define DT_ID           0x01F
 249 #define X_CLIP_START    0x020
 250 #define Y_CLIP_START    0x022
 251 #define X_CLIP_END      0x024
 252 #define Y_CLIP_END      0x026
 253 #define AD_ADDR         0x030
 254 #define AD_LUT          0x031
 255 #define AD_CMD          0x032
 256 #define DIG_OUT         0x040
 257 #define PM_LUT_ADDR     0x050
 258 #define PM_LUT_DATA     0x051
 259
 260
 261 /******** Assignments and Typedefs for 8 bit I2C Registers********************/
 262
 263 typedef union i2c_csr2_tag {
 264         u8 reg;
 265         struct {
 266                 u8 CHROM_FIL:1;
 267                 u8 SYNC_SNTL:1;
 268                 u8 HZ50:1;
 269                 u8 SYNC_PRESENT:1;
 270                 u8 BUSY_EVE:1;
 271                 u8 BUSY_ODD:1;
 272                 u8 DISP_PASS:1;
 273         } fld;
 274 } I2C_CSR2;
 275
 276 typedef union i2c_even_csr_tag {
 277         u8    reg;
 278         struct {
 279                 u8 DONE_EVE :1;
 280                 u8 SNGL_EVE :1;
 281                 u8 ERROR_EVE:1;
 282                 u8          :5;
 283         } fld;
 284 } I2C_EVEN_CSR;
 285
 286 typedef union i2c_odd_csr_tag {
 287         u8 reg;
 288         struct {
 289                 u8 DONE_ODD:1;
 290                 u8 SNGL_ODD:1;
 291                 u8 ERROR_ODD:1;
 292                 u8 :5;
 293         } fld;
 294 } I2C_ODD_CSR;
 295
 296 typedef union i2c_config_tag {
 297         u8 reg;
 298         struct {
 299                 u8 ACQ_MODE:2;
 300                 u8 EXT_TRIG_EN:1;
 301                 u8 EXT_TRIG_POL:1;
 302                 u8 H_SCALE:1;
 303                 u8 CLIP:1;
 304                 u8 PM_LUT_SEL:1;
 305                 u8 PM_LUT_PGM:1;
 306         } fld;
 307 } I2C_CONFIG;
 308
 309
 310 typedef union i2c_ad_cmd_tag {
 311         /* bits can have 3 different meanings depending on value of AD_ADDR */
 312         u8 reg;
 313         /* Bt252 Command Register if AD_ADDR = 00h */
 314         struct {
 315                 u8             :2;
 316                 u8 SYNC_LVL_SEL:2;
 317                 u8 SYNC_CNL_SEL:2;
 318                 u8 DIGITIZE_CNL_SEL1:2;
 319                 } bt252_command;
 320
 321         /* Bt252 IOUT0 register if AD_ADDR = 01h */
 322         struct {
 323                 u8 IOUT_DATA:8;
 324         } bt252_iout0;
 325
 326         /* BT252 IOUT1 register if AD_ADDR = 02h */
 327         struct {
 328                 u8 IOUT_DATA:8;
 329         } bt252_iout1;
 330 } I2C_AD_CMD;
 331
 332
 333 /***** Global declarations of local copies of boards' 8 bit I2C registers ***/
 334
 335 extern I2C_CSR2                 i2c_csr2;
 336 extern I2C_EVEN_CSR             i2c_even_csr;
 337 extern I2C_ODD_CSR              i2c_odd_csr;
 338 extern I2C_CONFIG               i2c_config;
 339 extern u8                       i2c_dt_id;
 340 extern u8                       i2c_x_clip_start;
 341 extern u8                       i2c_y_clip_start;
 342 extern u8                       i2c_x_clip_end;
 343 extern u8                       i2c_y_clip_end;
 344 extern u8                       i2c_ad_addr;
 345 extern u8                       i2c_ad_lut;
 346 extern I2C_AD_CMD               i2c_ad_cmd;
 347 extern u8                       i2c_dig_out;
 348 extern u8                       i2c_pm_lut_addr;
 349 extern u8                       i2c_pm_lut_data;
 350
 351 /* Functions for Global use */
 352
 353 /* access 8-bit IIC registers */
 354
 355 extern int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal);
 356 extern int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal);
 357
 358 #endif