2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return (le32_to_cpu(trb
->link
.control
) & TRB_TYPE_BITMASK
)
117 == TRB_TYPE(TRB_LINK
);
120 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
122 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
123 return ((le32_to_cpu(link
->control
) & TRB_TYPE_BITMASK
) ==
127 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
128 * TRB is in a new segment. This does not skip over link TRBs, and it does not
129 * effect the ring dequeue or enqueue pointers.
131 static void next_trb(struct xhci_hcd
*xhci
,
132 struct xhci_ring
*ring
,
133 struct xhci_segment
**seg
,
134 union xhci_trb
**trb
)
136 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
138 *trb
= ((*seg
)->trbs
);
145 * See Cycle bit rules. SW is the consumer for the event ring only.
146 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
148 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
150 union xhci_trb
*next
= ++(ring
->dequeue
);
151 unsigned long long addr
;
154 /* Update the dequeue pointer further if that was a link TRB or we're at
155 * the end of an event ring segment (which doesn't have link TRBS)
157 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
158 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
159 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
161 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
163 (unsigned int) ring
->cycle_state
);
165 ring
->deq_seg
= ring
->deq_seg
->next
;
166 ring
->dequeue
= ring
->deq_seg
->trbs
;
167 next
= ring
->dequeue
;
169 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
170 if (ring
== xhci
->event_ring
)
171 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
172 else if (ring
== xhci
->cmd_ring
)
173 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
175 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
179 * See Cycle bit rules. SW is the consumer for the event ring only.
180 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
182 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
183 * chain bit is set), then set the chain bit in all the following link TRBs.
184 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
185 * have their chain bit cleared (so that each Link TRB is a separate TD).
187 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
188 * set, but other sections talk about dealing with the chain bit set. This was
189 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
190 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
192 * @more_trbs_coming: Will you enqueue more TRBs before calling
193 * prepare_transfer()?
195 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
196 bool consumer
, bool more_trbs_coming
)
199 union xhci_trb
*next
;
200 unsigned long long addr
;
202 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
203 next
= ++(ring
->enqueue
);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
211 if (ring
!= xhci
->event_ring
) {
213 * If the caller doesn't plan on enqueueing more
214 * TDs before ringing the doorbell, then we
215 * don't want to give the link TRB to the
216 * hardware just yet. We'll give the link TRB
217 * back in prepare_ring() just before we enqueue
218 * the TD at the top of the ring.
220 if (!chain
&& !more_trbs_coming
)
223 /* If we're not dealing with 0.95 hardware,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!xhci_link_trb_quirk(xhci
)) {
228 next
->link
.control
&=
229 cpu_to_le32(~TRB_CHAIN
);
230 next
->link
.control
|=
233 /* Give this link TRB to the hardware */
235 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
237 /* Toggle the cycle bit after the last ring segment. */
238 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
239 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
241 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
243 (unsigned int) ring
->cycle_state
);
246 ring
->enq_seg
= ring
->enq_seg
->next
;
247 ring
->enqueue
= ring
->enq_seg
->trbs
;
248 next
= ring
->enqueue
;
250 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
251 if (ring
== xhci
->event_ring
)
252 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
253 else if (ring
== xhci
->cmd_ring
)
254 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
256 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
260 * Check to see if there's room to enqueue num_trbs on the ring. See rules
262 * FIXME: this would be simpler and faster if we just kept track of the number
263 * of free TRBs in a ring.
265 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
266 unsigned int num_trbs
)
269 union xhci_trb
*enq
= ring
->enqueue
;
270 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
271 struct xhci_segment
*cur_seg
;
272 unsigned int left_on_ring
;
274 /* If we are currently pointing to a link TRB, advance the
275 * enqueue pointer before checking for space */
276 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
277 enq_seg
= enq_seg
->next
;
281 /* Check if ring is empty */
282 if (enq
== ring
->dequeue
) {
283 /* Can't use link trbs */
284 left_on_ring
= TRBS_PER_SEGMENT
- 1;
285 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
286 cur_seg
= cur_seg
->next
)
287 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
289 /* Always need one TRB free in the ring. */
291 if (num_trbs
> left_on_ring
) {
292 xhci_warn(xhci
, "Not enough room on ring; "
293 "need %u TRBs, %u TRBs left\n",
294 num_trbs
, left_on_ring
);
299 /* Make sure there's an extra empty TRB available */
300 for (i
= 0; i
<= num_trbs
; ++i
) {
301 if (enq
== ring
->dequeue
)
304 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
305 enq_seg
= enq_seg
->next
;
312 /* Ring the host controller doorbell after placing a command on the ring */
313 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
315 xhci_dbg(xhci
, "// Ding dong!\n");
316 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
317 /* Flush PCI posted writes */
318 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
321 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
322 unsigned int slot_id
,
323 unsigned int ep_index
,
324 unsigned int stream_id
)
326 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
327 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
328 unsigned int ep_state
= ep
->ep_state
;
330 /* Don't ring the doorbell for this endpoint if there are pending
331 * cancellations because we don't want to interrupt processing.
332 * We don't want to restart any stream rings if there's a set dequeue
333 * pointer command pending because the device can choose to start any
334 * stream once the endpoint is on the HW schedule.
335 * FIXME - check all the stream rings for pending cancellations.
337 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
338 (ep_state
& EP_HALTED
))
340 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
341 /* The CPU has better things to do at this point than wait for a
342 * write-posting flush. It'll get there soon enough.
346 /* Ring the doorbell for any rings with pending URBs */
347 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
348 unsigned int slot_id
,
349 unsigned int ep_index
)
351 unsigned int stream_id
;
352 struct xhci_virt_ep
*ep
;
354 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
356 /* A ring has pending URBs if its TD list is not empty */
357 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
358 if (!(list_empty(&ep
->ring
->td_list
)))
359 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
363 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
365 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
366 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
367 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
373 * Find the segment that trb is in. Start searching in start_seg.
374 * If we must move past a segment that has a link TRB with a toggle cycle state
375 * bit set, then we will toggle the value pointed at by cycle_state.
377 static struct xhci_segment
*find_trb_seg(
378 struct xhci_segment
*start_seg
,
379 union xhci_trb
*trb
, int *cycle_state
)
381 struct xhci_segment
*cur_seg
= start_seg
;
382 struct xhci_generic_trb
*generic_trb
;
384 while (cur_seg
->trbs
> trb
||
385 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
386 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
387 if (le32_to_cpu(generic_trb
->field
[3]) & LINK_TOGGLE
)
389 cur_seg
= cur_seg
->next
;
390 if (cur_seg
== start_seg
)
391 /* Looped over the entire list. Oops! */
398 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
399 unsigned int slot_id
, unsigned int ep_index
,
400 unsigned int stream_id
)
402 struct xhci_virt_ep
*ep
;
404 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
405 /* Common case: no streams */
406 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
409 if (stream_id
== 0) {
411 "WARN: Slot ID %u, ep index %u has streams, "
412 "but URB has no stream ID.\n",
417 if (stream_id
< ep
->stream_info
->num_streams
)
418 return ep
->stream_info
->stream_rings
[stream_id
];
421 "WARN: Slot ID %u, ep index %u has "
422 "stream IDs 1 to %u allocated, "
423 "but stream ID %u is requested.\n",
425 ep
->stream_info
->num_streams
- 1,
430 /* Get the right ring for the given URB.
431 * If the endpoint supports streams, boundary check the URB's stream ID.
432 * If the endpoint doesn't support streams, return the singular endpoint ring.
434 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
437 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
438 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
442 * Move the xHC's endpoint ring dequeue pointer past cur_td.
443 * Record the new state of the xHC's endpoint ring dequeue segment,
444 * dequeue pointer, and new consumer cycle state in state.
445 * Update our internal representation of the ring's dequeue pointer.
447 * We do this in three jumps:
448 * - First we update our new ring state to be the same as when the xHC stopped.
449 * - Then we traverse the ring to find the segment that contains
450 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
451 * any link TRBs with the toggle cycle bit set.
452 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
453 * if we've moved it past a link TRB with the toggle cycle bit set.
455 * Some of the uses of xhci_generic_trb are grotty, but if they're done
456 * with correct __le32 accesses they should work fine. Only users of this are
459 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
460 unsigned int slot_id
, unsigned int ep_index
,
461 unsigned int stream_id
, struct xhci_td
*cur_td
,
462 struct xhci_dequeue_state
*state
)
464 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
465 struct xhci_ring
*ep_ring
;
466 struct xhci_generic_trb
*trb
;
467 struct xhci_ep_ctx
*ep_ctx
;
470 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
471 ep_index
, stream_id
);
473 xhci_warn(xhci
, "WARN can't find new dequeue state "
474 "for invalid stream ID %u.\n",
478 state
->new_cycle_state
= 0;
479 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
480 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
481 dev
->eps
[ep_index
].stopped_trb
,
482 &state
->new_cycle_state
);
483 if (!state
->new_deq_seg
) {
488 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
489 xhci_dbg(xhci
, "Finding endpoint context\n");
490 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
491 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
493 state
->new_deq_ptr
= cur_td
->last_trb
;
494 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
495 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
497 &state
->new_cycle_state
);
498 if (!state
->new_deq_seg
) {
503 trb
= &state
->new_deq_ptr
->generic
;
504 if ((le32_to_cpu(trb
->field
[3]) & TRB_TYPE_BITMASK
) ==
505 TRB_TYPE(TRB_LINK
) && (le32_to_cpu(trb
->field
[3]) & LINK_TOGGLE
))
506 state
->new_cycle_state
^= 0x1;
507 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
510 * If there is only one segment in a ring, find_trb_seg()'s while loop
511 * will not run, and it will return before it has a chance to see if it
512 * needs to toggle the cycle bit. It can't tell if the stalled transfer
513 * ended just before the link TRB on a one-segment ring, or if the TD
514 * wrapped around the top of the ring, because it doesn't have the TD in
515 * question. Look for the one-segment case where stalled TRB's address
516 * is greater than the new dequeue pointer address.
518 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
519 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
520 state
->new_cycle_state
^= 0x1;
521 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
523 /* Don't update the ring cycle state for the producer (us). */
524 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
526 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
527 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
528 (unsigned long long) addr
);
531 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
532 struct xhci_td
*cur_td
)
534 struct xhci_segment
*cur_seg
;
535 union xhci_trb
*cur_trb
;
537 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
539 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
540 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) & TRB_TYPE_BITMASK
)
541 == TRB_TYPE(TRB_LINK
)) {
542 /* Unchain any chained Link TRBs, but
543 * leave the pointers intact.
545 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
546 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
547 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
548 "in seg %p (0x%llx dma)\n",
550 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
552 (unsigned long long)cur_seg
->dma
);
554 cur_trb
->generic
.field
[0] = 0;
555 cur_trb
->generic
.field
[1] = 0;
556 cur_trb
->generic
.field
[2] = 0;
557 /* Preserve only the cycle bit of this TRB */
558 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
559 cur_trb
->generic
.field
[3] |= cpu_to_le32(
560 TRB_TYPE(TRB_TR_NOOP
));
561 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
562 "in seg %p (0x%llx dma)\n",
564 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
566 (unsigned long long)cur_seg
->dma
);
568 if (cur_trb
== cur_td
->last_trb
)
573 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
574 unsigned int ep_index
, unsigned int stream_id
,
575 struct xhci_segment
*deq_seg
,
576 union xhci_trb
*deq_ptr
, u32 cycle_state
);
578 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
579 unsigned int slot_id
, unsigned int ep_index
,
580 unsigned int stream_id
,
581 struct xhci_dequeue_state
*deq_state
)
583 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
585 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
586 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
587 deq_state
->new_deq_seg
,
588 (unsigned long long)deq_state
->new_deq_seg
->dma
,
589 deq_state
->new_deq_ptr
,
590 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
591 deq_state
->new_cycle_state
);
592 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
593 deq_state
->new_deq_seg
,
594 deq_state
->new_deq_ptr
,
595 (u32
) deq_state
->new_cycle_state
);
596 /* Stop the TD queueing code from ringing the doorbell until
597 * this command completes. The HC won't set the dequeue pointer
598 * if the ring is running, and ringing the doorbell starts the
601 ep
->ep_state
|= SET_DEQ_PENDING
;
604 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
605 struct xhci_virt_ep
*ep
)
607 ep
->ep_state
&= ~EP_HALT_PENDING
;
608 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
609 * timer is running on another CPU, we don't decrement stop_cmds_pending
610 * (since we didn't successfully stop the watchdog timer).
612 if (del_timer(&ep
->stop_cmd_timer
))
613 ep
->stop_cmds_pending
--;
616 /* Must be called with xhci->lock held in interrupt context */
617 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
618 struct xhci_td
*cur_td
, int status
, char *adjective
)
622 struct urb_priv
*urb_priv
;
625 urb_priv
= urb
->hcpriv
;
627 hcd
= bus_to_hcd(urb
->dev
->bus
);
629 /* Only giveback urb when this is the last td in urb */
630 if (urb_priv
->td_cnt
== urb_priv
->length
) {
631 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
632 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
633 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
634 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
635 usb_amd_quirk_pll_enable();
638 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
639 xhci_dbg(xhci
, "Giveback %s URB %p\n", adjective
, urb
);
641 spin_unlock(&xhci
->lock
);
642 usb_hcd_giveback_urb(hcd
, urb
, status
);
643 xhci_urb_free_priv(xhci
, urb_priv
);
644 spin_lock(&xhci
->lock
);
645 xhci_dbg(xhci
, "%s URB given back\n", adjective
);
650 * When we get a command completion for a Stop Endpoint Command, we need to
651 * unlink any cancelled TDs from the ring. There are two ways to do that:
653 * 1. If the HW was in the middle of processing the TD that needs to be
654 * cancelled, then we must move the ring's dequeue pointer past the last TRB
655 * in the TD with a Set Dequeue Pointer Command.
656 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
657 * bit cleared) so that the HW will skip over them.
659 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
660 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
662 unsigned int slot_id
;
663 unsigned int ep_index
;
664 struct xhci_virt_device
*virt_dev
;
665 struct xhci_ring
*ep_ring
;
666 struct xhci_virt_ep
*ep
;
667 struct list_head
*entry
;
668 struct xhci_td
*cur_td
= NULL
;
669 struct xhci_td
*last_unlinked_td
;
671 struct xhci_dequeue_state deq_state
;
673 if (unlikely(TRB_TO_SUSPEND_PORT(
674 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
675 slot_id
= TRB_TO_SLOT_ID(
676 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
677 virt_dev
= xhci
->devs
[slot_id
];
679 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
682 xhci_warn(xhci
, "Stop endpoint command "
683 "completion for disabled slot %u\n",
688 memset(&deq_state
, 0, sizeof(deq_state
));
689 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
690 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
691 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
693 if (list_empty(&ep
->cancelled_td_list
)) {
694 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
695 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
699 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
700 * We have the xHCI lock, so nothing can modify this list until we drop
701 * it. We're also in the event handler, so we can't get re-interrupted
702 * if another Stop Endpoint command completes
704 list_for_each(entry
, &ep
->cancelled_td_list
) {
705 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
706 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
708 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
709 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
711 /* This shouldn't happen unless a driver is mucking
712 * with the stream ID after submission. This will
713 * leave the TD on the hardware ring, and the hardware
714 * will try to execute it, and may access a buffer
715 * that has already been freed. In the best case, the
716 * hardware will execute it, and the event handler will
717 * ignore the completion event for that TD, since it was
718 * removed from the td_list for that endpoint. In
719 * short, don't muck with the stream ID after
722 xhci_warn(xhci
, "WARN Cancelled URB %p "
723 "has invalid stream ID %u.\n",
725 cur_td
->urb
->stream_id
);
726 goto remove_finished_td
;
729 * If we stopped on the TD we need to cancel, then we have to
730 * move the xHC endpoint ring dequeue pointer past this TD.
732 if (cur_td
== ep
->stopped_td
)
733 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
734 cur_td
->urb
->stream_id
,
737 td_to_noop(xhci
, ep_ring
, cur_td
);
740 * The event handler won't see a completion for this TD anymore,
741 * so remove it from the endpoint ring's TD list. Keep it in
742 * the cancelled TD list for URB completion later.
744 list_del(&cur_td
->td_list
);
746 last_unlinked_td
= cur_td
;
747 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
749 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
750 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
751 xhci_queue_new_dequeue_state(xhci
,
753 ep
->stopped_td
->urb
->stream_id
,
755 xhci_ring_cmd_db(xhci
);
757 /* Otherwise ring the doorbell(s) to restart queued transfers */
758 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
760 ep
->stopped_td
= NULL
;
761 ep
->stopped_trb
= NULL
;
764 * Drop the lock and complete the URBs in the cancelled TD list.
765 * New TDs to be cancelled might be added to the end of the list before
766 * we can complete all the URBs for the TDs we already unlinked.
767 * So stop when we've completed the URB for the last TD we unlinked.
770 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
771 struct xhci_td
, cancelled_td_list
);
772 list_del(&cur_td
->cancelled_td_list
);
774 /* Clean up the cancelled URB */
775 /* Doesn't matter what we pass for status, since the core will
776 * just overwrite it (because the URB has been unlinked).
778 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
780 /* Stop processing the cancelled list if the watchdog timer is
783 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
785 } while (cur_td
!= last_unlinked_td
);
787 /* Return to the event handler with xhci->lock re-acquired */
790 /* Watchdog timer function for when a stop endpoint command fails to complete.
791 * In this case, we assume the host controller is broken or dying or dead. The
792 * host may still be completing some other events, so we have to be careful to
793 * let the event ring handler and the URB dequeueing/enqueueing functions know
794 * through xhci->state.
796 * The timer may also fire if the host takes a very long time to respond to the
797 * command, and the stop endpoint command completion handler cannot delete the
798 * timer before the timer function is called. Another endpoint cancellation may
799 * sneak in before the timer function can grab the lock, and that may queue
800 * another stop endpoint command and add the timer back. So we cannot use a
801 * simple flag to say whether there is a pending stop endpoint command for a
802 * particular endpoint.
804 * Instead we use a combination of that flag and a counter for the number of
805 * pending stop endpoint commands. If the timer is the tail end of the last
806 * stop endpoint command, and the endpoint's command is still pending, we assume
809 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
811 struct xhci_hcd
*xhci
;
812 struct xhci_virt_ep
*ep
;
813 struct xhci_virt_ep
*temp_ep
;
814 struct xhci_ring
*ring
;
815 struct xhci_td
*cur_td
;
818 ep
= (struct xhci_virt_ep
*) arg
;
821 spin_lock(&xhci
->lock
);
823 ep
->stop_cmds_pending
--;
824 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
825 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
826 "xHCI as DYING, exiting.\n");
827 spin_unlock(&xhci
->lock
);
830 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
831 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
833 spin_unlock(&xhci
->lock
);
837 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
838 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
839 /* Oops, HC is dead or dying or at least not responding to the stop
842 xhci
->xhc_state
|= XHCI_STATE_DYING
;
843 /* Disable interrupts from the host controller and start halting it */
845 spin_unlock(&xhci
->lock
);
847 ret
= xhci_halt(xhci
);
849 spin_lock(&xhci
->lock
);
851 /* This is bad; the host is not responding to commands and it's
852 * not allowing itself to be halted. At least interrupts are
853 * disabled. If we call usb_hc_died(), it will attempt to
854 * disconnect all device drivers under this host. Those
855 * disconnect() methods will wait for all URBs to be unlinked,
856 * so we must complete them.
858 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
859 xhci_warn(xhci
, "Completing active URBs anyway.\n");
860 /* We could turn all TDs on the rings to no-ops. This won't
861 * help if the host has cached part of the ring, and is slow if
862 * we want to preserve the cycle bit. Skip it and hope the host
863 * doesn't touch the memory.
866 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
869 for (j
= 0; j
< 31; j
++) {
870 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
871 ring
= temp_ep
->ring
;
874 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
875 "ep index %u\n", i
, j
);
876 while (!list_empty(&ring
->td_list
)) {
877 cur_td
= list_first_entry(&ring
->td_list
,
880 list_del(&cur_td
->td_list
);
881 if (!list_empty(&cur_td
->cancelled_td_list
))
882 list_del(&cur_td
->cancelled_td_list
);
883 xhci_giveback_urb_in_irq(xhci
, cur_td
,
884 -ESHUTDOWN
, "killed");
886 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
887 cur_td
= list_first_entry(
888 &temp_ep
->cancelled_td_list
,
891 list_del(&cur_td
->cancelled_td_list
);
892 xhci_giveback_urb_in_irq(xhci
, cur_td
,
893 -ESHUTDOWN
, "killed");
897 spin_unlock(&xhci
->lock
);
898 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
899 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
900 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
904 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
905 * we need to clear the set deq pending flag in the endpoint ring state, so that
906 * the TD queueing code can ring the doorbell again. We also need to ring the
907 * endpoint doorbell to restart the ring, but only if there aren't more
908 * cancellations pending.
910 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
911 struct xhci_event_cmd
*event
,
914 unsigned int slot_id
;
915 unsigned int ep_index
;
916 unsigned int stream_id
;
917 struct xhci_ring
*ep_ring
;
918 struct xhci_virt_device
*dev
;
919 struct xhci_ep_ctx
*ep_ctx
;
920 struct xhci_slot_ctx
*slot_ctx
;
922 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
923 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
924 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
925 dev
= xhci
->devs
[slot_id
];
927 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
929 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
930 "freed stream ID %u\n",
932 /* XXX: Harmless??? */
933 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
937 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
938 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
940 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
941 unsigned int ep_state
;
942 unsigned int slot_state
;
944 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
946 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
947 "of stream ID configuration\n");
950 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
951 "to incorrect slot or ep state.\n");
952 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
953 ep_state
&= EP_STATE_MASK
;
954 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
955 slot_state
= GET_SLOT_STATE(slot_state
);
956 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
957 slot_state
, ep_state
);
960 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
961 "slot %u was not enabled.\n", slot_id
);
964 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
965 "completion code of %u.\n",
966 GET_COMP_CODE(le32_to_cpu(event
->status
)));
969 /* OK what do we do now? The endpoint state is hosed, and we
970 * should never get to this point if the synchronization between
971 * queueing, and endpoint state are correct. This might happen
972 * if the device gets disconnected after we've finished
973 * cancelling URBs, which might not be an error...
976 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
977 le64_to_cpu(ep_ctx
->deq
));
978 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
979 dev
->eps
[ep_index
].queued_deq_ptr
) ==
980 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
981 /* Update the ring's dequeue segment and dequeue pointer
982 * to reflect the new position.
984 ep_ring
->deq_seg
= dev
->eps
[ep_index
].queued_deq_seg
;
985 ep_ring
->dequeue
= dev
->eps
[ep_index
].queued_deq_ptr
;
987 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
988 "Ptr command & xHCI internal state.\n");
989 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
990 dev
->eps
[ep_index
].queued_deq_seg
,
991 dev
->eps
[ep_index
].queued_deq_ptr
);
995 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
996 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
997 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
998 /* Restart any rings with pending URBs */
999 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1002 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1003 struct xhci_event_cmd
*event
,
1004 union xhci_trb
*trb
)
1007 unsigned int ep_index
;
1009 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1010 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1011 /* This command will only fail if the endpoint wasn't halted,
1012 * but we don't care.
1014 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1015 (unsigned int) GET_COMP_CODE(le32_to_cpu(event
->status
)));
1017 /* HW with the reset endpoint quirk needs to have a configure endpoint
1018 * command complete before the endpoint can be used. Queue that here
1019 * because the HW can't handle two commands being queued in a row.
1021 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1022 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1023 xhci_queue_configure_endpoint(xhci
,
1024 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1026 xhci_ring_cmd_db(xhci
);
1028 /* Clear our internal halted state and restart the ring(s) */
1029 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1030 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1034 /* Check to see if a command in the device's command queue matches this one.
1035 * Signal the completion or free the command, and return 1. Return 0 if the
1036 * completed command isn't at the head of the command list.
1038 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1039 struct xhci_virt_device
*virt_dev
,
1040 struct xhci_event_cmd
*event
)
1042 struct xhci_command
*command
;
1044 if (list_empty(&virt_dev
->cmd_list
))
1047 command
= list_entry(virt_dev
->cmd_list
.next
,
1048 struct xhci_command
, cmd_list
);
1049 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1052 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1053 list_del(&command
->cmd_list
);
1054 if (command
->completion
)
1055 complete(command
->completion
);
1057 xhci_free_command(xhci
, command
);
1061 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1062 struct xhci_event_cmd
*event
)
1064 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1066 dma_addr_t cmd_dequeue_dma
;
1067 struct xhci_input_control_ctx
*ctrl_ctx
;
1068 struct xhci_virt_device
*virt_dev
;
1069 unsigned int ep_index
;
1070 struct xhci_ring
*ep_ring
;
1071 unsigned int ep_state
;
1073 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1074 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1075 xhci
->cmd_ring
->dequeue
);
1076 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1077 if (cmd_dequeue_dma
== 0) {
1078 xhci
->error_bitmask
|= 1 << 4;
1081 /* Does the DMA address match our internal dequeue pointer address? */
1082 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1083 xhci
->error_bitmask
|= 1 << 5;
1086 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1087 & TRB_TYPE_BITMASK
) {
1088 case TRB_TYPE(TRB_ENABLE_SLOT
):
1089 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1090 xhci
->slot_id
= slot_id
;
1093 complete(&xhci
->addr_dev
);
1095 case TRB_TYPE(TRB_DISABLE_SLOT
):
1096 if (xhci
->devs
[slot_id
])
1097 xhci_free_virt_device(xhci
, slot_id
);
1099 case TRB_TYPE(TRB_CONFIG_EP
):
1100 virt_dev
= xhci
->devs
[slot_id
];
1101 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1104 * Configure endpoint commands can come from the USB core
1105 * configuration or alt setting changes, or because the HW
1106 * needed an extra configure endpoint command after a reset
1107 * endpoint command or streams were being configured.
1108 * If the command was for a halted endpoint, the xHCI driver
1109 * is not waiting on the configure endpoint command.
1111 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1113 /* Input ctx add_flags are the endpoint index plus one */
1114 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1115 /* A usb_set_interface() call directly after clearing a halted
1116 * condition may race on this quirky hardware. Not worth
1117 * worrying about, since this is prototype hardware. Not sure
1118 * if this will work for streams, but streams support was
1119 * untested on this prototype.
1121 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1122 ep_index
!= (unsigned int) -1 &&
1123 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1124 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1125 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1126 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1127 if (!(ep_state
& EP_HALTED
))
1128 goto bandwidth_change
;
1129 xhci_dbg(xhci
, "Completed config ep cmd - "
1130 "last ep index = %d, state = %d\n",
1131 ep_index
, ep_state
);
1132 /* Clear internal halted state and restart ring(s) */
1133 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1135 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1139 xhci_dbg(xhci
, "Completed config ep cmd\n");
1140 xhci
->devs
[slot_id
]->cmd_status
=
1141 GET_COMP_CODE(le32_to_cpu(event
->status
));
1142 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1144 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1145 virt_dev
= xhci
->devs
[slot_id
];
1146 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1148 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1149 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1151 case TRB_TYPE(TRB_ADDR_DEV
):
1152 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1153 complete(&xhci
->addr_dev
);
1155 case TRB_TYPE(TRB_STOP_RING
):
1156 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1158 case TRB_TYPE(TRB_SET_DEQ
):
1159 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1161 case TRB_TYPE(TRB_CMD_NOOP
):
1163 case TRB_TYPE(TRB_RESET_EP
):
1164 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1166 case TRB_TYPE(TRB_RESET_DEV
):
1167 xhci_dbg(xhci
, "Completed reset device command.\n");
1168 slot_id
= TRB_TO_SLOT_ID(
1169 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1170 virt_dev
= xhci
->devs
[slot_id
];
1172 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1174 xhci_warn(xhci
, "Reset device command completion "
1175 "for disabled slot %u\n", slot_id
);
1177 case TRB_TYPE(TRB_NEC_GET_FW
):
1178 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1179 xhci
->error_bitmask
|= 1 << 6;
1182 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1183 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1184 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1187 /* Skip over unknown commands on the event ring */
1188 xhci
->error_bitmask
|= 1 << 6;
1191 inc_deq(xhci
, xhci
->cmd_ring
, false);
1194 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1195 union xhci_trb
*event
)
1199 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1200 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1201 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1202 handle_cmd_completion(xhci
, &event
->event_cmd
);
1205 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1206 * port registers -- USB 3.0 and USB 2.0).
1208 * Returns a zero-based port number, which is suitable for indexing into each of
1209 * the split roothubs' port arrays and bus state arrays.
1211 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1212 struct xhci_hcd
*xhci
, u32 port_id
)
1215 unsigned int num_similar_speed_ports
= 0;
1217 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1218 * and usb2_ports are 0-based indexes. Count the number of similar
1219 * speed ports, up to 1 port before this port.
1221 for (i
= 0; i
< (port_id
- 1); i
++) {
1222 u8 port_speed
= xhci
->port_array
[i
];
1225 * Skip ports that don't have known speeds, or have duplicate
1226 * Extended Capabilities port speed entries.
1228 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1232 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1233 * 1.1 ports are under the USB 2.0 hub. If the port speed
1234 * matches the device speed, it's a similar speed port.
1236 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1237 num_similar_speed_ports
++;
1239 return num_similar_speed_ports
;
1242 static void handle_port_status(struct xhci_hcd
*xhci
,
1243 union xhci_trb
*event
)
1245 struct usb_hcd
*hcd
;
1250 unsigned int faked_port_index
;
1252 struct xhci_bus_state
*bus_state
;
1253 __le32 __iomem
**port_array
;
1254 bool bogus_port_status
= false;
1256 /* Port status change events always have a successful completion code */
1257 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1258 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1259 xhci
->error_bitmask
|= 1 << 8;
1261 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1262 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1264 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1265 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1266 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1267 bogus_port_status
= true;
1271 /* Figure out which usb_hcd this port is attached to:
1272 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1274 major_revision
= xhci
->port_array
[port_id
- 1];
1275 if (major_revision
== 0) {
1276 xhci_warn(xhci
, "Event for port %u not in "
1277 "Extended Capabilities, ignoring.\n",
1279 bogus_port_status
= true;
1282 if (major_revision
== DUPLICATE_ENTRY
) {
1283 xhci_warn(xhci
, "Event for port %u duplicated in"
1284 "Extended Capabilities, ignoring.\n",
1286 bogus_port_status
= true;
1291 * Hardware port IDs reported by a Port Status Change Event include USB
1292 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1293 * resume event, but we first need to translate the hardware port ID
1294 * into the index into the ports on the correct split roothub, and the
1295 * correct bus_state structure.
1297 /* Find the right roothub. */
1298 hcd
= xhci_to_hcd(xhci
);
1299 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1300 hcd
= xhci
->shared_hcd
;
1301 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1302 if (hcd
->speed
== HCD_USB3
)
1303 port_array
= xhci
->usb3_ports
;
1305 port_array
= xhci
->usb2_ports
;
1306 /* Find the faked port hub number */
1307 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1310 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1311 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1312 xhci_dbg(xhci
, "resume root hub\n");
1313 usb_hcd_resume_root_hub(hcd
);
1316 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1317 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1319 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1320 if (!(temp1
& CMD_RUN
)) {
1321 xhci_warn(xhci
, "xHC is not running.\n");
1325 if (DEV_SUPERSPEED(temp
)) {
1326 xhci_dbg(xhci
, "resume SS port %d\n", port_id
);
1327 temp
= xhci_port_state_to_neutral(temp
);
1328 temp
&= ~PORT_PLS_MASK
;
1329 temp
|= PORT_LINK_STROBE
| XDEV_U0
;
1330 xhci_writel(xhci
, temp
, port_array
[faked_port_index
]);
1331 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1334 xhci_dbg(xhci
, "slot_id is zero\n");
1337 xhci_ring_device(xhci
, slot_id
);
1338 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1339 /* Clear PORT_PLC */
1340 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1341 temp
= xhci_port_state_to_neutral(temp
);
1343 xhci_writel(xhci
, temp
, port_array
[faked_port_index
]);
1345 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1346 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1347 msecs_to_jiffies(20);
1348 mod_timer(&hcd
->rh_timer
,
1349 bus_state
->resume_done
[faked_port_index
]);
1350 /* Do the rest in GetPortStatus */
1355 /* Update event ring dequeue pointer before dropping the lock */
1356 inc_deq(xhci
, xhci
->event_ring
, true);
1358 /* Don't make the USB core poll the roothub if we got a bad port status
1359 * change event. Besides, at that point we can't tell which roothub
1360 * (USB 2.0 or USB 3.0) to kick.
1362 if (bogus_port_status
)
1365 spin_unlock(&xhci
->lock
);
1366 /* Pass this up to the core */
1367 usb_hcd_poll_rh_status(hcd
);
1368 spin_lock(&xhci
->lock
);
1372 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1373 * at end_trb, which may be in another segment. If the suspect DMA address is a
1374 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1377 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1378 union xhci_trb
*start_trb
,
1379 union xhci_trb
*end_trb
,
1380 dma_addr_t suspect_dma
)
1382 dma_addr_t start_dma
;
1383 dma_addr_t end_seg_dma
;
1384 dma_addr_t end_trb_dma
;
1385 struct xhci_segment
*cur_seg
;
1387 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1388 cur_seg
= start_seg
;
1393 /* We may get an event for a Link TRB in the middle of a TD */
1394 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1395 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1396 /* If the end TRB isn't in this segment, this is set to 0 */
1397 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1399 if (end_trb_dma
> 0) {
1400 /* The end TRB is in this segment, so suspect should be here */
1401 if (start_dma
<= end_trb_dma
) {
1402 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1405 /* Case for one segment with
1406 * a TD wrapped around to the top
1408 if ((suspect_dma
>= start_dma
&&
1409 suspect_dma
<= end_seg_dma
) ||
1410 (suspect_dma
>= cur_seg
->dma
&&
1411 suspect_dma
<= end_trb_dma
))
1416 /* Might still be somewhere in this segment */
1417 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1420 cur_seg
= cur_seg
->next
;
1421 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1422 } while (cur_seg
!= start_seg
);
1427 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1428 unsigned int slot_id
, unsigned int ep_index
,
1429 unsigned int stream_id
,
1430 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1432 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1433 ep
->ep_state
|= EP_HALTED
;
1434 ep
->stopped_td
= td
;
1435 ep
->stopped_trb
= event_trb
;
1436 ep
->stopped_stream
= stream_id
;
1438 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1439 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1441 ep
->stopped_td
= NULL
;
1442 ep
->stopped_trb
= NULL
;
1443 ep
->stopped_stream
= 0;
1445 xhci_ring_cmd_db(xhci
);
1448 /* Check if an error has halted the endpoint ring. The class driver will
1449 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1450 * However, a babble and other errors also halt the endpoint ring, and the class
1451 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1452 * Ring Dequeue Pointer command manually.
1454 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1455 struct xhci_ep_ctx
*ep_ctx
,
1456 unsigned int trb_comp_code
)
1458 /* TRB completion codes that may require a manual halt cleanup */
1459 if (trb_comp_code
== COMP_TX_ERR
||
1460 trb_comp_code
== COMP_BABBLE
||
1461 trb_comp_code
== COMP_SPLIT_ERR
)
1462 /* The 0.96 spec says a babbling control endpoint
1463 * is not halted. The 0.96 spec says it is. Some HW
1464 * claims to be 0.95 compliant, but it halts the control
1465 * endpoint anyway. Check if a babble halted the
1468 if ((le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) == EP_STATE_HALTED
)
1474 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1476 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1477 /* Vendor defined "informational" completion code,
1478 * treat as not-an-error.
1480 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1482 xhci_dbg(xhci
, "Treating code as success.\n");
1489 * Finish the td processing, remove the td from td list;
1490 * Return 1 if the urb can be given back.
1492 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1493 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1494 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1496 struct xhci_virt_device
*xdev
;
1497 struct xhci_ring
*ep_ring
;
1498 unsigned int slot_id
;
1500 struct urb
*urb
= NULL
;
1501 struct xhci_ep_ctx
*ep_ctx
;
1503 struct urb_priv
*urb_priv
;
1506 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1507 xdev
= xhci
->devs
[slot_id
];
1508 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1509 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1510 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1511 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1516 if (trb_comp_code
== COMP_STOP_INVAL
||
1517 trb_comp_code
== COMP_STOP
) {
1518 /* The Endpoint Stop Command completion will take care of any
1519 * stopped TDs. A stopped TD may be restarted, so don't update
1520 * the ring dequeue pointer or take this TD off any lists yet.
1522 ep
->stopped_td
= td
;
1523 ep
->stopped_trb
= event_trb
;
1526 if (trb_comp_code
== COMP_STALL
) {
1527 /* The transfer is completed from the driver's
1528 * perspective, but we need to issue a set dequeue
1529 * command for this stalled endpoint to move the dequeue
1530 * pointer past the TD. We can't do that here because
1531 * the halt condition must be cleared first. Let the
1532 * USB class driver clear the stall later.
1534 ep
->stopped_td
= td
;
1535 ep
->stopped_trb
= event_trb
;
1536 ep
->stopped_stream
= ep_ring
->stream_id
;
1537 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1538 ep_ctx
, trb_comp_code
)) {
1539 /* Other types of errors halt the endpoint, but the
1540 * class driver doesn't call usb_reset_endpoint() unless
1541 * the error is -EPIPE. Clear the halted status in the
1542 * xHCI hardware manually.
1544 xhci_cleanup_halted_endpoint(xhci
,
1545 slot_id
, ep_index
, ep_ring
->stream_id
,
1548 /* Update ring dequeue pointer */
1549 while (ep_ring
->dequeue
!= td
->last_trb
)
1550 inc_deq(xhci
, ep_ring
, false);
1551 inc_deq(xhci
, ep_ring
, false);
1555 /* Clean up the endpoint's TD list */
1557 urb_priv
= urb
->hcpriv
;
1559 /* Do one last check of the actual transfer length.
1560 * If the host controller said we transferred more data than
1561 * the buffer length, urb->actual_length will be a very big
1562 * number (since it's unsigned). Play it safe and say we didn't
1563 * transfer anything.
1565 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1566 xhci_warn(xhci
, "URB transfer length is wrong, "
1567 "xHC issue? req. len = %u, "
1569 urb
->transfer_buffer_length
,
1570 urb
->actual_length
);
1571 urb
->actual_length
= 0;
1572 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1573 *status
= -EREMOTEIO
;
1577 list_del(&td
->td_list
);
1578 /* Was this TD slated to be cancelled but completed anyway? */
1579 if (!list_empty(&td
->cancelled_td_list
))
1580 list_del(&td
->cancelled_td_list
);
1583 /* Giveback the urb when all the tds are completed */
1584 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1586 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1587 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1588 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1590 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1591 usb_amd_quirk_pll_enable();
1601 * Process control tds, update urb status and actual_length.
1603 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1604 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1605 struct xhci_virt_ep
*ep
, int *status
)
1607 struct xhci_virt_device
*xdev
;
1608 struct xhci_ring
*ep_ring
;
1609 unsigned int slot_id
;
1611 struct xhci_ep_ctx
*ep_ctx
;
1614 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1615 xdev
= xhci
->devs
[slot_id
];
1616 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1617 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1618 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1619 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1621 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1622 switch (trb_comp_code
) {
1624 if (event_trb
== ep_ring
->dequeue
) {
1625 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1626 "without IOC set??\n");
1627 *status
= -ESHUTDOWN
;
1628 } else if (event_trb
!= td
->last_trb
) {
1629 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1630 "without IOC set??\n");
1631 *status
= -ESHUTDOWN
;
1633 xhci_dbg(xhci
, "Successful control transfer!\n");
1638 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1639 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1640 *status
= -EREMOTEIO
;
1644 case COMP_STOP_INVAL
:
1646 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1648 if (!xhci_requires_manual_halt_cleanup(xhci
,
1649 ep_ctx
, trb_comp_code
))
1651 xhci_dbg(xhci
, "TRB error code %u, "
1652 "halted endpoint index = %u\n",
1653 trb_comp_code
, ep_index
);
1654 /* else fall through */
1656 /* Did we transfer part of the data (middle) phase? */
1657 if (event_trb
!= ep_ring
->dequeue
&&
1658 event_trb
!= td
->last_trb
)
1659 td
->urb
->actual_length
=
1660 td
->urb
->transfer_buffer_length
1661 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1663 td
->urb
->actual_length
= 0;
1665 xhci_cleanup_halted_endpoint(xhci
,
1666 slot_id
, ep_index
, 0, td
, event_trb
);
1667 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1670 * Did we transfer any data, despite the errors that might have
1671 * happened? I.e. did we get past the setup stage?
1673 if (event_trb
!= ep_ring
->dequeue
) {
1674 /* The event was for the status stage */
1675 if (event_trb
== td
->last_trb
) {
1676 if (td
->urb
->actual_length
!= 0) {
1677 /* Don't overwrite a previously set error code
1679 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1680 (td
->urb
->transfer_flags
1681 & URB_SHORT_NOT_OK
))
1682 /* Did we already see a short data
1684 *status
= -EREMOTEIO
;
1686 td
->urb
->actual_length
=
1687 td
->urb
->transfer_buffer_length
;
1690 /* Maybe the event was for the data stage? */
1691 td
->urb
->actual_length
=
1692 td
->urb
->transfer_buffer_length
-
1693 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1694 xhci_dbg(xhci
, "Waiting for status "
1700 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1704 * Process isochronous tds, update urb packet status and actual_length.
1706 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1707 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1708 struct xhci_virt_ep
*ep
, int *status
)
1710 struct xhci_ring
*ep_ring
;
1711 struct urb_priv
*urb_priv
;
1714 union xhci_trb
*cur_trb
;
1715 struct xhci_segment
*cur_seg
;
1716 struct usb_iso_packet_descriptor
*frame
;
1718 bool skip_td
= false;
1720 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1721 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1722 urb_priv
= td
->urb
->hcpriv
;
1723 idx
= urb_priv
->td_cnt
;
1724 frame
= &td
->urb
->iso_frame_desc
[idx
];
1726 /* handle completion code */
1727 switch (trb_comp_code
) {
1730 xhci_dbg(xhci
, "Successful isoc transfer!\n");
1733 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1737 frame
->status
= -ECOMM
;
1740 case COMP_BUFF_OVER
:
1742 frame
->status
= -EOVERFLOW
;
1746 frame
->status
= -EPROTO
;
1750 case COMP_STOP_INVAL
:
1757 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1758 frame
->actual_length
= frame
->length
;
1759 td
->urb
->actual_length
+= frame
->length
;
1761 for (cur_trb
= ep_ring
->dequeue
,
1762 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1763 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1764 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) &
1765 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1766 (le32_to_cpu(cur_trb
->generic
.field
[3]) &
1767 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1768 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1770 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1771 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1773 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1774 frame
->actual_length
= len
;
1775 td
->urb
->actual_length
+= len
;
1779 if ((idx
== urb_priv
->length
- 1) && *status
== -EINPROGRESS
)
1782 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1785 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1786 struct xhci_transfer_event
*event
,
1787 struct xhci_virt_ep
*ep
, int *status
)
1789 struct xhci_ring
*ep_ring
;
1790 struct urb_priv
*urb_priv
;
1791 struct usb_iso_packet_descriptor
*frame
;
1794 ep_ring
= xhci_dma_to_transfer_ring(ep
, event
->buffer
);
1795 urb_priv
= td
->urb
->hcpriv
;
1796 idx
= urb_priv
->td_cnt
;
1797 frame
= &td
->urb
->iso_frame_desc
[idx
];
1799 /* The transfer is partly done */
1801 frame
->status
= -EXDEV
;
1803 /* calc actual length */
1804 frame
->actual_length
= 0;
1806 /* Update ring dequeue pointer */
1807 while (ep_ring
->dequeue
!= td
->last_trb
)
1808 inc_deq(xhci
, ep_ring
, false);
1809 inc_deq(xhci
, ep_ring
, false);
1811 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1815 * Process bulk and interrupt tds, update urb status and actual_length.
1817 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1818 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1819 struct xhci_virt_ep
*ep
, int *status
)
1821 struct xhci_ring
*ep_ring
;
1822 union xhci_trb
*cur_trb
;
1823 struct xhci_segment
*cur_seg
;
1826 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1827 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1829 switch (trb_comp_code
) {
1831 /* Double check that the HW transferred everything. */
1832 if (event_trb
!= td
->last_trb
) {
1833 xhci_warn(xhci
, "WARN Successful completion "
1835 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1836 *status
= -EREMOTEIO
;
1840 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1841 xhci_dbg(xhci
, "Successful bulk "
1844 xhci_dbg(xhci
, "Successful interrupt "
1850 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1851 *status
= -EREMOTEIO
;
1856 /* Others already handled above */
1859 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1860 "%d bytes untransferred\n",
1861 td
->urb
->ep
->desc
.bEndpointAddress
,
1862 td
->urb
->transfer_buffer_length
,
1863 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1864 /* Fast path - was this the last TRB in the TD for this URB? */
1865 if (event_trb
== td
->last_trb
) {
1866 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1867 td
->urb
->actual_length
=
1868 td
->urb
->transfer_buffer_length
-
1869 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1870 if (td
->urb
->transfer_buffer_length
<
1871 td
->urb
->actual_length
) {
1872 xhci_warn(xhci
, "HC gave bad length "
1873 "of %d bytes left\n",
1874 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1875 td
->urb
->actual_length
= 0;
1876 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1877 *status
= -EREMOTEIO
;
1881 /* Don't overwrite a previously set error code */
1882 if (*status
== -EINPROGRESS
) {
1883 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1884 *status
= -EREMOTEIO
;
1889 td
->urb
->actual_length
=
1890 td
->urb
->transfer_buffer_length
;
1891 /* Ignore a short packet completion if the
1892 * untransferred length was zero.
1894 if (*status
== -EREMOTEIO
)
1898 /* Slow path - walk the list, starting from the dequeue
1899 * pointer, to get the actual length transferred.
1901 td
->urb
->actual_length
= 0;
1902 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1903 cur_trb
!= event_trb
;
1904 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1905 if ((le32_to_cpu(cur_trb
->generic
.field
[3]) &
1906 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_TR_NOOP
) &&
1907 (le32_to_cpu(cur_trb
->generic
.field
[3]) &
1908 TRB_TYPE_BITMASK
) != TRB_TYPE(TRB_LINK
))
1909 td
->urb
->actual_length
+=
1910 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1912 /* If the ring didn't stop on a Link or No-op TRB, add
1913 * in the actual bytes transferred from the Normal TRB
1915 if (trb_comp_code
!= COMP_STOP_INVAL
)
1916 td
->urb
->actual_length
+=
1917 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1918 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1921 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1925 * If this function returns an error condition, it means it got a Transfer
1926 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1927 * At this point, the host controller is probably hosed and should be reset.
1929 static int handle_tx_event(struct xhci_hcd
*xhci
,
1930 struct xhci_transfer_event
*event
)
1932 struct xhci_virt_device
*xdev
;
1933 struct xhci_virt_ep
*ep
;
1934 struct xhci_ring
*ep_ring
;
1935 unsigned int slot_id
;
1937 struct xhci_td
*td
= NULL
;
1938 dma_addr_t event_dma
;
1939 struct xhci_segment
*event_seg
;
1940 union xhci_trb
*event_trb
;
1941 struct urb
*urb
= NULL
;
1942 int status
= -EINPROGRESS
;
1943 struct urb_priv
*urb_priv
;
1944 struct xhci_ep_ctx
*ep_ctx
;
1948 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1949 xdev
= xhci
->devs
[slot_id
];
1951 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1955 /* Endpoint ID is 1 based, our index is zero based */
1956 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1957 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
1958 ep
= &xdev
->eps
[ep_index
];
1959 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1960 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1962 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
1963 EP_STATE_DISABLED
) {
1964 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1965 "or incorrect stream ring\n");
1969 event_dma
= le64_to_cpu(event
->buffer
);
1970 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1971 /* Look for common error cases */
1972 switch (trb_comp_code
) {
1973 /* Skip codes that require special handling depending on
1980 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1982 case COMP_STOP_INVAL
:
1983 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1986 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1987 ep
->ep_state
|= EP_HALTED
;
1991 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1994 case COMP_SPLIT_ERR
:
1996 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
2000 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
2001 status
= -EOVERFLOW
;
2004 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2008 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2010 case COMP_BUFF_OVER
:
2011 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2015 * When the Isoch ring is empty, the xHC will generate
2016 * a Ring Overrun Event for IN Isoch endpoint or Ring
2017 * Underrun Event for OUT Isoch endpoint.
2019 xhci_dbg(xhci
, "underrun event on endpoint\n");
2020 if (!list_empty(&ep_ring
->td_list
))
2021 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2022 "still with TDs queued?\n",
2023 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2027 xhci_dbg(xhci
, "overrun event on endpoint\n");
2028 if (!list_empty(&ep_ring
->td_list
))
2029 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2030 "still with TDs queued?\n",
2031 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2034 case COMP_MISSED_INT
:
2036 * When encounter missed service error, one or more isoc tds
2037 * may be missed by xHC.
2038 * Set skip flag of the ep_ring; Complete the missed tds as
2039 * short transfer when process the ep_ring next time.
2042 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2045 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2049 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2055 /* This TRB should be in the TD at the head of this ring's
2058 if (list_empty(&ep_ring
->td_list
)) {
2059 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2060 "with no TDs queued?\n",
2061 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2063 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2064 (unsigned int) (le32_to_cpu(event
->flags
)
2065 & TRB_TYPE_BITMASK
)>>10);
2066 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2069 xhci_dbg(xhci
, "td_list is empty while skip "
2070 "flag set. Clear skip flag.\n");
2076 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2078 /* Is this a TRB in the currently executing TD? */
2079 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2080 td
->last_trb
, event_dma
);
2083 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2084 /* HC is busted, give up! */
2086 "ERROR Transfer event TRB DMA ptr not "
2087 "part of current TD\n");
2091 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2096 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2100 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2101 sizeof(*event_trb
)];
2103 * No-op TRB should not trigger interrupts.
2104 * If event_trb is a no-op TRB, it means the
2105 * corresponding TD has been cancelled. Just ignore
2108 if ((le32_to_cpu(event_trb
->generic
.field
[3])
2110 == TRB_TYPE(TRB_TR_NOOP
)) {
2112 "event_trb is a no-op TRB. Skip it\n");
2116 /* Now update the urb's actual_length and give back to
2119 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2120 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2122 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2123 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2126 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2131 * Do not update event ring dequeue pointer if ep->skip is set.
2132 * Will roll back to continue process missed tds.
2134 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2135 inc_deq(xhci
, xhci
->event_ring
, true);
2140 urb_priv
= urb
->hcpriv
;
2141 /* Leave the TD around for the reset endpoint function
2142 * to use(but only if it's not a control endpoint,
2143 * since we already queued the Set TR dequeue pointer
2144 * command for stalled control endpoints).
2146 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2147 (trb_comp_code
!= COMP_STALL
&&
2148 trb_comp_code
!= COMP_BABBLE
))
2149 xhci_urb_free_priv(xhci
, urb_priv
);
2151 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2152 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2154 urb
, urb
->actual_length
, status
);
2155 spin_unlock(&xhci
->lock
);
2156 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2157 spin_lock(&xhci
->lock
);
2161 * If ep->skip is set, it means there are missed tds on the
2162 * endpoint ring need to take care of.
2163 * Process them as short transfer until reach the td pointed by
2166 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2172 * This function handles all OS-owned events on the event ring. It may drop
2173 * xhci->lock between event processing (e.g. to pass up port status changes).
2174 * Returns >0 for "possibly more events to process" (caller should call again),
2175 * otherwise 0 if done. In future, <0 returns should indicate error code.
2177 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2179 union xhci_trb
*event
;
2180 int update_ptrs
= 1;
2183 xhci_dbg(xhci
, "In %s\n", __func__
);
2184 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2185 xhci
->error_bitmask
|= 1 << 1;
2189 event
= xhci
->event_ring
->dequeue
;
2190 /* Does the HC or OS own the TRB? */
2191 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2192 xhci
->event_ring
->cycle_state
) {
2193 xhci
->error_bitmask
|= 1 << 2;
2196 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
2199 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2200 * speculative reads of the event's flags/data below.
2203 /* FIXME: Handle more event types. */
2204 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2205 case TRB_TYPE(TRB_COMPLETION
):
2206 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
2207 handle_cmd_completion(xhci
, &event
->event_cmd
);
2208 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
2210 case TRB_TYPE(TRB_PORT_STATUS
):
2211 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
2212 handle_port_status(xhci
, event
);
2213 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
2216 case TRB_TYPE(TRB_TRANSFER
):
2217 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
2218 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2219 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
2221 xhci
->error_bitmask
|= 1 << 9;
2226 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2228 handle_vendor_event(xhci
, event
);
2230 xhci
->error_bitmask
|= 1 << 3;
2232 /* Any of the above functions may drop and re-acquire the lock, so check
2233 * to make sure a watchdog timer didn't mark the host as non-responsive.
2235 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2236 xhci_dbg(xhci
, "xHCI host dying, returning from "
2237 "event handler.\n");
2242 /* Update SW event ring dequeue pointer */
2243 inc_deq(xhci
, xhci
->event_ring
, true);
2245 /* Are there more items on the event ring? Caller will call us again to
2252 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2253 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2254 * indicators of an event TRB error, but we check the status *first* to be safe.
2256 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2258 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2260 union xhci_trb
*trb
;
2262 union xhci_trb
*event_ring_deq
;
2265 spin_lock(&xhci
->lock
);
2266 trb
= xhci
->event_ring
->dequeue
;
2267 /* Check if the xHC generated the interrupt, or the irq is shared */
2268 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2269 if (status
== 0xffffffff)
2272 if (!(status
& STS_EINT
)) {
2273 spin_unlock(&xhci
->lock
);
2276 xhci_dbg(xhci
, "op reg status = %08x\n", status
);
2277 xhci_dbg(xhci
, "Event ring dequeue ptr:\n");
2278 xhci_dbg(xhci
, "@%llx %08x %08x %08x %08x\n",
2279 (unsigned long long)
2280 xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
, trb
),
2281 lower_32_bits(le64_to_cpu(trb
->link
.segment_ptr
)),
2282 upper_32_bits(le64_to_cpu(trb
->link
.segment_ptr
)),
2283 (unsigned int) le32_to_cpu(trb
->link
.intr_target
),
2284 (unsigned int) le32_to_cpu(trb
->link
.control
));
2286 if (status
& STS_FATAL
) {
2287 xhci_warn(xhci
, "WARNING: Host System Error\n");
2290 spin_unlock(&xhci
->lock
);
2295 * Clear the op reg interrupt status first,
2296 * so we can receive interrupts from other MSI-X interrupters.
2297 * Write 1 to clear the interrupt status.
2300 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2301 /* FIXME when MSI-X is supported and there are multiple vectors */
2302 /* Clear the MSI-X event interrupt status */
2304 if (hcd
->irq
!= -1) {
2306 /* Acknowledge the PCI interrupt */
2307 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2309 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2312 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2313 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2314 "Shouldn't IRQs be disabled?\n");
2315 /* Clear the event handler busy flag (RW1C);
2316 * the event ring should be empty.
2318 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2319 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2320 &xhci
->ir_set
->erst_dequeue
);
2321 spin_unlock(&xhci
->lock
);
2326 event_ring_deq
= xhci
->event_ring
->dequeue
;
2327 /* FIXME this should be a delayed service routine
2328 * that clears the EHB.
2330 while (xhci_handle_event(xhci
) > 0) {}
2332 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2333 /* If necessary, update the HW's version of the event ring deq ptr. */
2334 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2335 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2336 xhci
->event_ring
->dequeue
);
2338 xhci_warn(xhci
, "WARN something wrong with SW event "
2339 "ring dequeue ptr.\n");
2340 /* Update HC event ring dequeue pointer */
2341 temp_64
&= ERST_PTR_MASK
;
2342 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2345 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2346 temp_64
|= ERST_EHB
;
2347 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2349 spin_unlock(&xhci
->lock
);
2354 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2357 struct xhci_hcd
*xhci
;
2359 xhci
= hcd_to_xhci(hcd
);
2360 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
2361 if (xhci
->shared_hcd
)
2362 set_bit(HCD_FLAG_SAW_IRQ
, &xhci
->shared_hcd
->flags
);
2364 ret
= xhci_irq(hcd
);
2369 /**** Endpoint Ring Operations ****/
2372 * Generic function for queueing a TRB on a ring.
2373 * The caller must have checked to make sure there's room on the ring.
2375 * @more_trbs_coming: Will you enqueue more TRBs before calling
2376 * prepare_transfer()?
2378 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2379 bool consumer
, bool more_trbs_coming
,
2380 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2382 struct xhci_generic_trb
*trb
;
2384 trb
= &ring
->enqueue
->generic
;
2385 trb
->field
[0] = cpu_to_le32(field1
);
2386 trb
->field
[1] = cpu_to_le32(field2
);
2387 trb
->field
[2] = cpu_to_le32(field3
);
2388 trb
->field
[3] = cpu_to_le32(field4
);
2389 inc_enq(xhci
, ring
, consumer
, more_trbs_coming
);
2393 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2394 * FIXME allocate segments if the ring is full.
2396 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2397 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2399 /* Make sure the endpoint has been added to xHC schedule */
2400 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
2402 case EP_STATE_DISABLED
:
2404 * USB core changed config/interfaces without notifying us,
2405 * or hardware is reporting the wrong state.
2407 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2409 case EP_STATE_ERROR
:
2410 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2411 /* FIXME event handling code for error needs to clear it */
2412 /* XXX not sure if this should be -ENOENT or not */
2414 case EP_STATE_HALTED
:
2415 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2416 case EP_STATE_STOPPED
:
2417 case EP_STATE_RUNNING
:
2420 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2422 * FIXME issue Configure Endpoint command to try to get the HC
2423 * back into a known state.
2427 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
2428 /* FIXME allocate more room */
2429 xhci_err(xhci
, "ERROR no room on ep ring\n");
2433 if (enqueue_is_link_trb(ep_ring
)) {
2434 struct xhci_ring
*ring
= ep_ring
;
2435 union xhci_trb
*next
;
2437 xhci_dbg(xhci
, "prepare_ring: pointing to link trb\n");
2438 next
= ring
->enqueue
;
2440 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2441 /* If we're not dealing with 0.95 hardware,
2442 * clear the chain bit.
2444 if (!xhci_link_trb_quirk(xhci
))
2445 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2447 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2450 next
->link
.control
^= cpu_to_le32((u32
) TRB_CYCLE
);
2452 /* Toggle the cycle bit after the last ring segment. */
2453 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2454 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2455 if (!in_interrupt()) {
2456 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
2457 "state for ring %p = %i\n",
2458 ring
, (unsigned int)ring
->cycle_state
);
2461 ring
->enq_seg
= ring
->enq_seg
->next
;
2462 ring
->enqueue
= ring
->enq_seg
->trbs
;
2463 next
= ring
->enqueue
;
2470 static int prepare_transfer(struct xhci_hcd
*xhci
,
2471 struct xhci_virt_device
*xdev
,
2472 unsigned int ep_index
,
2473 unsigned int stream_id
,
2474 unsigned int num_trbs
,
2476 unsigned int td_index
,
2480 struct urb_priv
*urb_priv
;
2482 struct xhci_ring
*ep_ring
;
2483 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2485 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2487 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2492 ret
= prepare_ring(xhci
, ep_ring
,
2493 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2494 num_trbs
, mem_flags
);
2498 urb_priv
= urb
->hcpriv
;
2499 td
= urb_priv
->td
[td_index
];
2501 INIT_LIST_HEAD(&td
->td_list
);
2502 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2504 if (td_index
== 0) {
2505 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2506 if (unlikely(ret
)) {
2507 xhci_urb_free_priv(xhci
, urb_priv
);
2514 /* Add this TD to the tail of the endpoint ring's TD list */
2515 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2516 td
->start_seg
= ep_ring
->enq_seg
;
2517 td
->first_trb
= ep_ring
->enqueue
;
2519 urb_priv
->td
[td_index
] = td
;
2524 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2526 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2527 struct scatterlist
*sg
;
2530 num_sgs
= urb
->num_sgs
;
2531 temp
= urb
->transfer_buffer_length
;
2533 xhci_dbg(xhci
, "count sg list trbs: \n");
2535 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2536 unsigned int previous_total_trbs
= num_trbs
;
2537 unsigned int len
= sg_dma_len(sg
);
2539 /* Scatter gather list entries may cross 64KB boundaries */
2540 running_total
= TRB_MAX_BUFF_SIZE
-
2541 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2542 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2543 if (running_total
!= 0)
2546 /* How many more 64KB chunks to transfer, how many more TRBs? */
2547 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2549 running_total
+= TRB_MAX_BUFF_SIZE
;
2551 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2552 i
, (unsigned long long)sg_dma_address(sg
),
2553 len
, len
, num_trbs
- previous_total_trbs
);
2555 len
= min_t(int, len
, temp
);
2560 xhci_dbg(xhci
, "\n");
2561 if (!in_interrupt())
2562 xhci_dbg(xhci
, "ep %#x - urb len = %d, sglist used, "
2564 urb
->ep
->desc
.bEndpointAddress
,
2565 urb
->transfer_buffer_length
,
2570 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2573 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2574 "TRBs, %d left\n", __func__
,
2575 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2576 if (running_total
!= urb
->transfer_buffer_length
)
2577 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2578 "queued %#x (%d), asked for %#x (%d)\n",
2580 urb
->ep
->desc
.bEndpointAddress
,
2581 running_total
, running_total
,
2582 urb
->transfer_buffer_length
,
2583 urb
->transfer_buffer_length
);
2586 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2587 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2588 struct xhci_generic_trb
*start_trb
)
2591 * Pass all the TRBs to the hardware at once and make sure this write
2596 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2598 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2599 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2603 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2604 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2605 * (comprised of sg list entries) can take several service intervals to
2608 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2609 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2611 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2612 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2616 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2617 ep_interval
= urb
->interval
;
2618 /* Convert to microframes */
2619 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2620 urb
->dev
->speed
== USB_SPEED_FULL
)
2622 /* FIXME change this to a warning and a suggestion to use the new API
2623 * to set the polling interval (once the API is added).
2625 if (xhci_interval
!= ep_interval
) {
2626 if (printk_ratelimit())
2627 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2628 " (%d microframe%s) than xHCI "
2629 "(%d microframe%s)\n",
2631 ep_interval
== 1 ? "" : "s",
2633 xhci_interval
== 1 ? "" : "s");
2634 urb
->interval
= xhci_interval
;
2635 /* Convert back to frames for LS/FS devices */
2636 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2637 urb
->dev
->speed
== USB_SPEED_FULL
)
2640 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
2644 * The TD size is the number of bytes remaining in the TD (including this TRB),
2645 * right shifted by 10.
2646 * It must fit in bits 21:17, so it can't be bigger than 31.
2648 static u32
xhci_td_remainder(unsigned int remainder
)
2650 u32 max
= (1 << (21 - 17 + 1)) - 1;
2652 if ((remainder
>> 10) >= max
)
2655 return (remainder
>> 10) << 17;
2659 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2660 * the TD (*not* including this TRB).
2662 * Total TD packet count = total_packet_count =
2663 * roundup(TD size in bytes / wMaxPacketSize)
2665 * Packets transferred up to and including this TRB = packets_transferred =
2666 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2668 * TD size = total_packet_count - packets_transferred
2670 * It must fit in bits 21:17, so it can't be bigger than 31.
2673 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2674 unsigned int total_packet_count
, struct urb
*urb
)
2676 int packets_transferred
;
2678 /* All the TRB queueing functions don't count the current TRB in
2681 packets_transferred
= (running_total
+ trb_buff_len
) /
2682 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
);
2684 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2687 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2688 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2690 struct xhci_ring
*ep_ring
;
2691 unsigned int num_trbs
;
2692 struct urb_priv
*urb_priv
;
2694 struct scatterlist
*sg
;
2696 int trb_buff_len
, this_sg_len
, running_total
;
2697 unsigned int total_packet_count
;
2700 bool more_trbs_coming
;
2702 struct xhci_generic_trb
*start_trb
;
2705 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2709 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2710 num_sgs
= urb
->num_sgs
;
2711 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2712 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
2714 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2715 ep_index
, urb
->stream_id
,
2716 num_trbs
, urb
, 0, mem_flags
);
2717 if (trb_buff_len
< 0)
2718 return trb_buff_len
;
2720 urb_priv
= urb
->hcpriv
;
2721 td
= urb_priv
->td
[0];
2724 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2725 * until we've finished creating all the other TRBs. The ring's cycle
2726 * state may change as we enqueue the other TRBs, so save it too.
2728 start_trb
= &ep_ring
->enqueue
->generic
;
2729 start_cycle
= ep_ring
->cycle_state
;
2733 * How much data is in the first TRB?
2735 * There are three forces at work for TRB buffer pointers and lengths:
2736 * 1. We don't want to walk off the end of this sg-list entry buffer.
2737 * 2. The transfer length that the driver requested may be smaller than
2738 * the amount of memory allocated for this scatter-gather list.
2739 * 3. TRBs buffers can't cross 64KB boundaries.
2742 addr
= (u64
) sg_dma_address(sg
);
2743 this_sg_len
= sg_dma_len(sg
);
2744 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2745 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2746 if (trb_buff_len
> urb
->transfer_buffer_length
)
2747 trb_buff_len
= urb
->transfer_buffer_length
;
2748 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2752 /* Queue the first TRB, even if it's zero-length */
2755 u32 length_field
= 0;
2758 /* Don't change the cycle bit of the first TRB until later */
2761 if (start_cycle
== 0)
2764 field
|= ep_ring
->cycle_state
;
2766 /* Chain all the TRBs together; clear the chain bit in the last
2767 * TRB to indicate it's the last TRB in the chain.
2772 /* FIXME - add check for ZERO_PACKET flag before this */
2773 td
->last_trb
= ep_ring
->enqueue
;
2777 /* Only set interrupt on short packet for IN endpoints */
2778 if (usb_urb_dir_in(urb
))
2781 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2782 "64KB boundary at %#x, end dma = %#x\n",
2783 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2784 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2785 (unsigned int) addr
+ trb_buff_len
);
2786 if (TRB_MAX_BUFF_SIZE
-
2787 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2788 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2789 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2790 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2791 (unsigned int) addr
+ trb_buff_len
);
2794 /* Set the TRB length, TD size, and interrupter fields. */
2795 if (xhci
->hci_version
< 0x100) {
2796 remainder
= xhci_td_remainder(
2797 urb
->transfer_buffer_length
-
2800 remainder
= xhci_v1_0_td_remainder(running_total
,
2801 trb_buff_len
, total_packet_count
, urb
);
2803 length_field
= TRB_LEN(trb_buff_len
) |
2808 more_trbs_coming
= true;
2810 more_trbs_coming
= false;
2811 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2812 lower_32_bits(addr
),
2813 upper_32_bits(addr
),
2815 field
| TRB_TYPE(TRB_NORMAL
));
2817 running_total
+= trb_buff_len
;
2819 /* Calculate length for next transfer --
2820 * Are we done queueing all the TRBs for this sg entry?
2822 this_sg_len
-= trb_buff_len
;
2823 if (this_sg_len
== 0) {
2828 addr
= (u64
) sg_dma_address(sg
);
2829 this_sg_len
= sg_dma_len(sg
);
2831 addr
+= trb_buff_len
;
2834 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2835 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2836 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2837 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2839 urb
->transfer_buffer_length
- running_total
;
2840 } while (running_total
< urb
->transfer_buffer_length
);
2842 check_trb_math(urb
, num_trbs
, running_total
);
2843 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2844 start_cycle
, start_trb
);
2848 /* This is very similar to what ehci-q.c qtd_fill() does */
2849 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2850 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2852 struct xhci_ring
*ep_ring
;
2853 struct urb_priv
*urb_priv
;
2856 struct xhci_generic_trb
*start_trb
;
2858 bool more_trbs_coming
;
2860 u32 field
, length_field
;
2862 int running_total
, trb_buff_len
, ret
;
2863 unsigned int total_packet_count
;
2867 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2869 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2874 /* How much data is (potentially) left before the 64KB boundary? */
2875 running_total
= TRB_MAX_BUFF_SIZE
-
2876 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2877 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2879 /* If there's some data on this 64KB chunk, or we have to send a
2880 * zero-length transfer, we need at least one TRB
2882 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2884 /* How many more 64KB chunks to transfer, how many more TRBs? */
2885 while (running_total
< urb
->transfer_buffer_length
) {
2887 running_total
+= TRB_MAX_BUFF_SIZE
;
2889 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2891 if (!in_interrupt())
2892 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d), "
2893 "addr = %#llx, num_trbs = %d\n",
2894 urb
->ep
->desc
.bEndpointAddress
,
2895 urb
->transfer_buffer_length
,
2896 urb
->transfer_buffer_length
,
2897 (unsigned long long)urb
->transfer_dma
,
2900 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2901 ep_index
, urb
->stream_id
,
2902 num_trbs
, urb
, 0, mem_flags
);
2906 urb_priv
= urb
->hcpriv
;
2907 td
= urb_priv
->td
[0];
2910 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2911 * until we've finished creating all the other TRBs. The ring's cycle
2912 * state may change as we enqueue the other TRBs, so save it too.
2914 start_trb
= &ep_ring
->enqueue
->generic
;
2915 start_cycle
= ep_ring
->cycle_state
;
2918 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2919 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
2920 /* How much data is in the first TRB? */
2921 addr
= (u64
) urb
->transfer_dma
;
2922 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2923 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2924 if (trb_buff_len
> urb
->transfer_buffer_length
)
2925 trb_buff_len
= urb
->transfer_buffer_length
;
2929 /* Queue the first TRB, even if it's zero-length */
2934 /* Don't change the cycle bit of the first TRB until later */
2937 if (start_cycle
== 0)
2940 field
|= ep_ring
->cycle_state
;
2942 /* Chain all the TRBs together; clear the chain bit in the last
2943 * TRB to indicate it's the last TRB in the chain.
2948 /* FIXME - add check for ZERO_PACKET flag before this */
2949 td
->last_trb
= ep_ring
->enqueue
;
2953 /* Only set interrupt on short packet for IN endpoints */
2954 if (usb_urb_dir_in(urb
))
2957 /* Set the TRB length, TD size, and interrupter fields. */
2958 if (xhci
->hci_version
< 0x100) {
2959 remainder
= xhci_td_remainder(
2960 urb
->transfer_buffer_length
-
2963 remainder
= xhci_v1_0_td_remainder(running_total
,
2964 trb_buff_len
, total_packet_count
, urb
);
2966 length_field
= TRB_LEN(trb_buff_len
) |
2971 more_trbs_coming
= true;
2973 more_trbs_coming
= false;
2974 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
2975 lower_32_bits(addr
),
2976 upper_32_bits(addr
),
2978 field
| TRB_TYPE(TRB_NORMAL
));
2980 running_total
+= trb_buff_len
;
2982 /* Calculate length for next transfer */
2983 addr
+= trb_buff_len
;
2984 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
2985 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
2986 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
2987 } while (running_total
< urb
->transfer_buffer_length
);
2989 check_trb_math(urb
, num_trbs
, running_total
);
2990 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2991 start_cycle
, start_trb
);
2995 /* Caller must have locked xhci->lock */
2996 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2997 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2999 struct xhci_ring
*ep_ring
;
3002 struct usb_ctrlrequest
*setup
;
3003 struct xhci_generic_trb
*start_trb
;
3005 u32 field
, length_field
;
3006 struct urb_priv
*urb_priv
;
3009 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3014 * Need to copy setup packet into setup TRB, so we can't use the setup
3017 if (!urb
->setup_packet
)
3020 if (!in_interrupt())
3021 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
3023 /* 1 TRB for setup, 1 for status */
3026 * Don't need to check if we need additional event data and normal TRBs,
3027 * since data in control transfers will never get bigger than 16MB
3028 * XXX: can we get a buffer that crosses 64KB boundaries?
3030 if (urb
->transfer_buffer_length
> 0)
3032 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3033 ep_index
, urb
->stream_id
,
3034 num_trbs
, urb
, 0, mem_flags
);
3038 urb_priv
= urb
->hcpriv
;
3039 td
= urb_priv
->td
[0];
3042 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3043 * until we've finished creating all the other TRBs. The ring's cycle
3044 * state may change as we enqueue the other TRBs, so save it too.
3046 start_trb
= &ep_ring
->enqueue
->generic
;
3047 start_cycle
= ep_ring
->cycle_state
;
3049 /* Queue setup TRB - see section 6.4.1.2.1 */
3050 /* FIXME better way to translate setup_packet into two u32 fields? */
3051 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3053 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3054 if (start_cycle
== 0)
3057 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3058 if (xhci
->hci_version
== 0x100) {
3059 if (urb
->transfer_buffer_length
> 0) {
3060 if (setup
->bRequestType
& USB_DIR_IN
)
3061 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3063 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3067 queue_trb(xhci
, ep_ring
, false, true,
3068 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3069 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3070 TRB_LEN(8) | TRB_INTR_TARGET(0),
3071 /* Immediate data in pointer */
3074 /* If there's data, queue data TRBs */
3075 /* Only set interrupt on short packet for IN endpoints */
3076 if (usb_urb_dir_in(urb
))
3077 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3079 field
= TRB_TYPE(TRB_DATA
);
3081 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3082 xhci_td_remainder(urb
->transfer_buffer_length
) |
3084 if (urb
->transfer_buffer_length
> 0) {
3085 if (setup
->bRequestType
& USB_DIR_IN
)
3086 field
|= TRB_DIR_IN
;
3087 queue_trb(xhci
, ep_ring
, false, true,
3088 lower_32_bits(urb
->transfer_dma
),
3089 upper_32_bits(urb
->transfer_dma
),
3091 field
| ep_ring
->cycle_state
);
3094 /* Save the DMA address of the last TRB in the TD */
3095 td
->last_trb
= ep_ring
->enqueue
;
3097 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3098 /* If the device sent data, the status stage is an OUT transfer */
3099 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3103 queue_trb(xhci
, ep_ring
, false, false,
3107 /* Event on completion */
3108 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3110 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3111 start_cycle
, start_trb
);
3115 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3116 struct urb
*urb
, int i
)
3119 u64 addr
, td_len
, running_total
;
3121 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3122 td_len
= urb
->iso_frame_desc
[i
].length
;
3124 running_total
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3125 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3126 if (running_total
!= 0)
3129 while (running_total
< td_len
) {
3131 running_total
+= TRB_MAX_BUFF_SIZE
;
3138 * The transfer burst count field of the isochronous TRB defines the number of
3139 * bursts that are required to move all packets in this TD. Only SuperSpeed
3140 * devices can burst up to bMaxBurst number of packets per service interval.
3141 * This field is zero based, meaning a value of zero in the field means one
3142 * burst. Basically, for everything but SuperSpeed devices, this field will be
3143 * zero. Only xHCI 1.0 host controllers support this field.
3145 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3146 struct usb_device
*udev
,
3147 struct urb
*urb
, unsigned int total_packet_count
)
3149 unsigned int max_burst
;
3151 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3154 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3155 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3159 * Returns the number of packets in the last "burst" of packets. This field is
3160 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3161 * the last burst packet count is equal to the total number of packets in the
3162 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3163 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3164 * contain 1 to (bMaxBurst + 1) packets.
3166 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3167 struct usb_device
*udev
,
3168 struct urb
*urb
, unsigned int total_packet_count
)
3170 unsigned int max_burst
;
3171 unsigned int residue
;
3173 if (xhci
->hci_version
< 0x100)
3176 switch (udev
->speed
) {
3177 case USB_SPEED_SUPER
:
3178 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3179 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3180 residue
= total_packet_count
% (max_burst
+ 1);
3181 /* If residue is zero, the last burst contains (max_burst + 1)
3182 * number of packets, but the TLBPC field is zero-based.
3188 if (total_packet_count
== 0)
3190 return total_packet_count
- 1;
3194 /* This is for isoc transfer */
3195 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3196 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3198 struct xhci_ring
*ep_ring
;
3199 struct urb_priv
*urb_priv
;
3201 int num_tds
, trbs_per_td
;
3202 struct xhci_generic_trb
*start_trb
;
3205 u32 field
, length_field
;
3206 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3207 u64 start_addr
, addr
;
3209 bool more_trbs_coming
;
3211 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3213 num_tds
= urb
->number_of_packets
;
3215 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3219 if (!in_interrupt())
3220 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d),"
3221 " addr = %#llx, num_tds = %d\n",
3222 urb
->ep
->desc
.bEndpointAddress
,
3223 urb
->transfer_buffer_length
,
3224 urb
->transfer_buffer_length
,
3225 (unsigned long long)urb
->transfer_dma
,
3228 start_addr
= (u64
) urb
->transfer_dma
;
3229 start_trb
= &ep_ring
->enqueue
->generic
;
3230 start_cycle
= ep_ring
->cycle_state
;
3232 /* Queue the first TRB, even if it's zero-length */
3233 for (i
= 0; i
< num_tds
; i
++) {
3234 unsigned int total_packet_count
;
3235 unsigned int burst_count
;
3236 unsigned int residue
;
3240 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3241 td_len
= urb
->iso_frame_desc
[i
].length
;
3242 td_remain_len
= td_len
;
3243 /* FIXME: Ignoring zero-length packets, can those happen? */
3244 total_packet_count
= roundup(td_len
,
3245 le16_to_cpu(urb
->ep
->desc
.wMaxPacketSize
));
3246 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3247 total_packet_count
);
3248 residue
= xhci_get_last_burst_packet_count(xhci
,
3249 urb
->dev
, urb
, total_packet_count
);
3251 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3253 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3254 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3258 urb_priv
= urb
->hcpriv
;
3259 td
= urb_priv
->td
[i
];
3261 for (j
= 0; j
< trbs_per_td
; j
++) {
3263 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3266 /* Queue the isoc TRB */
3267 field
|= TRB_TYPE(TRB_ISOC
);
3268 /* Assume URB_ISO_ASAP is set */
3271 if (start_cycle
== 0)
3274 field
|= ep_ring
->cycle_state
;
3277 /* Queue other normal TRBs */
3278 field
|= TRB_TYPE(TRB_NORMAL
);
3279 field
|= ep_ring
->cycle_state
;
3282 /* Only set interrupt on short packet for IN EPs */
3283 if (usb_urb_dir_in(urb
))
3286 /* Chain all the TRBs together; clear the chain bit in
3287 * the last TRB to indicate it's the last TRB in the
3290 if (j
< trbs_per_td
- 1) {
3292 more_trbs_coming
= true;
3294 td
->last_trb
= ep_ring
->enqueue
;
3296 if (xhci
->hci_version
== 0x100) {
3297 /* Set BEI bit except for the last td */
3298 if (i
< num_tds
- 1)
3301 more_trbs_coming
= false;
3304 /* Calculate TRB length */
3305 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3306 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3307 if (trb_buff_len
> td_remain_len
)
3308 trb_buff_len
= td_remain_len
;
3310 /* Set the TRB length, TD size, & interrupter fields. */
3311 if (xhci
->hci_version
< 0x100) {
3312 remainder
= xhci_td_remainder(
3313 td_len
- running_total
);
3315 remainder
= xhci_v1_0_td_remainder(
3316 running_total
, trb_buff_len
,
3317 total_packet_count
, urb
);
3319 length_field
= TRB_LEN(trb_buff_len
) |
3323 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
,
3324 lower_32_bits(addr
),
3325 upper_32_bits(addr
),
3328 running_total
+= trb_buff_len
;
3330 addr
+= trb_buff_len
;
3331 td_remain_len
-= trb_buff_len
;
3334 /* Check TD length */
3335 if (running_total
!= td_len
) {
3336 xhci_err(xhci
, "ISOC TD length unmatch\n");
3341 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3342 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3343 usb_amd_quirk_pll_disable();
3345 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3347 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3348 start_cycle
, start_trb
);
3353 * Check transfer ring to guarantee there is enough room for the urb.
3354 * Update ISO URB start_frame and interval.
3355 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3356 * update the urb->start_frame by now.
3357 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3359 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3360 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3362 struct xhci_virt_device
*xdev
;
3363 struct xhci_ring
*ep_ring
;
3364 struct xhci_ep_ctx
*ep_ctx
;
3368 int num_tds
, num_trbs
, i
;
3371 xdev
= xhci
->devs
[slot_id
];
3372 ep_ring
= xdev
->eps
[ep_index
].ring
;
3373 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3376 num_tds
= urb
->number_of_packets
;
3377 for (i
= 0; i
< num_tds
; i
++)
3378 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3380 /* Check the ring to guarantee there is enough room for the whole urb.
3381 * Do not insert any td of the urb to the ring if the check failed.
3383 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3384 num_trbs
, mem_flags
);
3388 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3389 start_frame
&= 0x3fff;
3391 urb
->start_frame
= start_frame
;
3392 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3393 urb
->dev
->speed
== USB_SPEED_FULL
)
3394 urb
->start_frame
>>= 3;
3396 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3397 ep_interval
= urb
->interval
;
3398 /* Convert to microframes */
3399 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3400 urb
->dev
->speed
== USB_SPEED_FULL
)
3402 /* FIXME change this to a warning and a suggestion to use the new API
3403 * to set the polling interval (once the API is added).
3405 if (xhci_interval
!= ep_interval
) {
3406 if (printk_ratelimit())
3407 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3408 " (%d microframe%s) than xHCI "
3409 "(%d microframe%s)\n",
3411 ep_interval
== 1 ? "" : "s",
3413 xhci_interval
== 1 ? "" : "s");
3414 urb
->interval
= xhci_interval
;
3415 /* Convert back to frames for LS/FS devices */
3416 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3417 urb
->dev
->speed
== USB_SPEED_FULL
)
3420 return xhci_queue_isoc_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
3423 /**** Command Ring Operations ****/
3425 /* Generic function for queueing a command TRB on the command ring.
3426 * Check to make sure there's room on the command ring for one command TRB.
3427 * Also check that there's room reserved for commands that must not fail.
3428 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3429 * then only check for the number of reserved spots.
3430 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3431 * because the command event handler may want to resubmit a failed command.
3433 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3434 u32 field3
, u32 field4
, bool command_must_succeed
)
3436 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3439 if (!command_must_succeed
)
3442 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3443 reserved_trbs
, GFP_ATOMIC
);
3445 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3446 if (command_must_succeed
)
3447 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3448 "unfailable commands failed.\n");
3451 queue_trb(xhci
, xhci
->cmd_ring
, false, false, field1
, field2
, field3
,
3452 field4
| xhci
->cmd_ring
->cycle_state
);
3456 /* Queue a slot enable or disable request on the command ring */
3457 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3459 return queue_command(xhci
, 0, 0, 0,
3460 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3463 /* Queue an address device command TRB */
3464 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3467 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3468 upper_32_bits(in_ctx_ptr
), 0,
3469 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3473 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3474 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3476 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3479 /* Queue a reset device command TRB */
3480 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3482 return queue_command(xhci
, 0, 0, 0,
3483 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3487 /* Queue a configure endpoint command TRB */
3488 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3489 u32 slot_id
, bool command_must_succeed
)
3491 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3492 upper_32_bits(in_ctx_ptr
), 0,
3493 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3494 command_must_succeed
);
3497 /* Queue an evaluate context command TRB */
3498 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3501 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3502 upper_32_bits(in_ctx_ptr
), 0,
3503 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3508 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3509 * activity on an endpoint that is about to be suspended.
3511 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3512 unsigned int ep_index
, int suspend
)
3514 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3515 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3516 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3517 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3519 return queue_command(xhci
, 0, 0, 0,
3520 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3523 /* Set Transfer Ring Dequeue Pointer command.
3524 * This should not be used for endpoints that have streams enabled.
3526 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3527 unsigned int ep_index
, unsigned int stream_id
,
3528 struct xhci_segment
*deq_seg
,
3529 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3532 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3533 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3534 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3535 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3536 struct xhci_virt_ep
*ep
;
3538 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3540 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3541 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3545 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3546 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3547 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3548 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3551 ep
->queued_deq_seg
= deq_seg
;
3552 ep
->queued_deq_ptr
= deq_ptr
;
3553 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3554 upper_32_bits(addr
), trb_stream_id
,
3555 trb_slot_id
| trb_ep_index
| type
, false);
3558 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3559 unsigned int ep_index
)
3561 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3562 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3563 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3565 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,