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Documentation: configfs examples crash fix
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / dma / dw_dmac.c
blob2a2e2fa00e91427434286e5f3267defff300ff24
1 /*
2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
3 * AVR32 systems.)
4 *
5 * Copyright (C) 2007-2008 Atmel Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/mm.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22
23 #include "dw_dmac_regs.h"
24
25 /*
26 * This supports the Synopsys "DesignWare AHB Central DMA Controller",
27 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
28 * of which use ARM any more). See the "Databook" from Synopsys for
29 * information beyond what licensees probably provide.
30 *
31 * The driver has currently been tested only with the Atmel AT32AP7000,
32 * which does not support descriptor writeback.
33 */
34
35 #define DWC_DEFAULT_CTLLO(private) ({ \
36 struct dw_dma_slave *__slave = (private); \
37 int dms = __slave ? __slave->dst_master : 0; \
38 int sms = __slave ? __slave->src_master : 1; \
39 u8 smsize = __slave ? __slave->src_msize : DW_DMA_MSIZE_16; \
40 u8 dmsize = __slave ? __slave->dst_msize : DW_DMA_MSIZE_16; \
41 \
42 (DWC_CTLL_DST_MSIZE(dmsize) \
43 | DWC_CTLL_SRC_MSIZE(smsize) \
44 | DWC_CTLL_LLP_D_EN \
45 | DWC_CTLL_LLP_S_EN \
46 | DWC_CTLL_DMS(dms) \
47 | DWC_CTLL_SMS(sms)); \
48 })
49
50 /*
51 * This is configuration-dependent and usually a funny size like 4095.
52 *
53 * Note that this is a transfer count, i.e. if we transfer 32-bit
54 * words, we can do 16380 bytes per descriptor.
55 *
56 * This parameter is also system-specific.
57 */
58 #define DWC_MAX_COUNT 4095U
59
60 /*
61 * Number of descriptors to allocate for each channel. This should be
62 * made configurable somehow; preferably, the clients (at least the
63 * ones using slave transfers) should be able to give us a hint.
64 */
65 #define NR_DESCS_PER_CHANNEL 64
66
67 /*----------------------------------------------------------------------*/
68
69 /*
70 * Because we're not relying on writeback from the controller (it may not
71 * even be configured into the core!) we don't need to use dma_pool. These
72 * descriptors -- and associated data -- are cacheable. We do need to make
73 * sure their dcache entries are written back before handing them off to
74 * the controller, though.
75 */
76
77 static struct device *chan2dev(struct dma_chan *chan)
78 {
79 return &chan->dev->device;
80 }
81 static struct device *chan2parent(struct dma_chan *chan)
82 {
83 return chan->dev->device.parent;
84 }
85
86 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
87 {
88 return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
89 }
90
91 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
92 {
93 struct dw_desc *desc, *_desc;
94 struct dw_desc *ret = NULL;
95 unsigned int i = 0;
96
97 spin_lock_bh(&dwc->lock);
98 list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
99 if (async_tx_test_ack(&desc->txd)) {
100 list_del(&desc->desc_node);
101 ret = desc;
102 break;
103 }
104 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
105 i++;
106 }
107 spin_unlock_bh(&dwc->lock);
108
109 dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
110
111 return ret;
112 }
113
114 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
115 {
116 struct dw_desc *child;
117
118 list_for_each_entry(child, &desc->tx_list, desc_node)
119 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
120 child->txd.phys, sizeof(child->lli),
121 DMA_TO_DEVICE);
122 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
123 desc->txd.phys, sizeof(desc->lli),
124 DMA_TO_DEVICE);
125 }
126
127 /*
128 * Move a descriptor, including any children, to the free list.
129 * `desc' must not be on any lists.
130 */
131 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
132 {
133 if (desc) {
134 struct dw_desc *child;
135
136 dwc_sync_desc_for_cpu(dwc, desc);
137
138 spin_lock_bh(&dwc->lock);
139 list_for_each_entry(child, &desc->tx_list, desc_node)
140 dev_vdbg(chan2dev(&dwc->chan),
141 "moving child desc %p to freelist\n",
142 child);
143 list_splice_init(&desc->tx_list, &dwc->free_list);
144 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
145 list_add(&desc->desc_node, &dwc->free_list);
146 spin_unlock_bh(&dwc->lock);
147 }
148 }
149
150 /* Called with dwc->lock held and bh disabled */
151 static dma_cookie_t
152 dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
153 {
154 dma_cookie_t cookie = dwc->chan.cookie;
155
156 if (++cookie < 0)
157 cookie = 1;
158
159 dwc->chan.cookie = cookie;
160 desc->txd.cookie = cookie;
161
162 return cookie;
163 }
164
165 /*----------------------------------------------------------------------*/
166
167 /* Called with dwc->lock held and bh disabled */
168 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
169 {
170 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
171
172 /* ASSERT: channel is idle */
173 if (dma_readl(dw, CH_EN) & dwc->mask) {
174 dev_err(chan2dev(&dwc->chan),
175 "BUG: Attempted to start non-idle channel\n");
176 dev_err(chan2dev(&dwc->chan),
177 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
178 channel_readl(dwc, SAR),
179 channel_readl(dwc, DAR),
180 channel_readl(dwc, LLP),
181 channel_readl(dwc, CTL_HI),
182 channel_readl(dwc, CTL_LO));
183
184 /* The tasklet will hopefully advance the queue... */
185 return;
186 }
187
188 channel_writel(dwc, LLP, first->txd.phys);
189 channel_writel(dwc, CTL_LO,
190 DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
191 channel_writel(dwc, CTL_HI, 0);
192 channel_set_bit(dw, CH_EN, dwc->mask);
193 }
194
195 /*----------------------------------------------------------------------*/
196
197 static void
198 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc)
199 {
200 dma_async_tx_callback callback;
201 void *param;
202 struct dma_async_tx_descriptor *txd = &desc->txd;
203 struct dw_desc *child;
204
205 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
206
207 dwc->completed = txd->cookie;
208 callback = txd->callback;
209 param = txd->callback_param;
210
211 dwc_sync_desc_for_cpu(dwc, desc);
212
213 /* async_tx_ack */
214 list_for_each_entry(child, &desc->tx_list, desc_node)
215 async_tx_ack(&child->txd);
216 async_tx_ack(&desc->txd);
217
218 list_splice_init(&desc->tx_list, &dwc->free_list);
219 list_move(&desc->desc_node, &dwc->free_list);
220
221 if (!dwc->chan.private) {
222 struct device *parent = chan2parent(&dwc->chan);
223 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
224 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
225 dma_unmap_single(parent, desc->lli.dar,
226 desc->len, DMA_FROM_DEVICE);
227 else
228 dma_unmap_page(parent, desc->lli.dar,
229 desc->len, DMA_FROM_DEVICE);
230 }
231 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
232 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
233 dma_unmap_single(parent, desc->lli.sar,
234 desc->len, DMA_TO_DEVICE);
235 else
236 dma_unmap_page(parent, desc->lli.sar,
237 desc->len, DMA_TO_DEVICE);
238 }
239 }
240
241 /*
242 * The API requires that no submissions are done from a
243 * callback, so we don't need to drop the lock here
244 */
245 if (callback)
246 callback(param);
247 }
248
249 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
250 {
251 struct dw_desc *desc, *_desc;
252 LIST_HEAD(list);
253
254 if (dma_readl(dw, CH_EN) & dwc->mask) {
255 dev_err(chan2dev(&dwc->chan),
256 "BUG: XFER bit set, but channel not idle!\n");
257
258 /* Try to continue after resetting the channel... */
259 channel_clear_bit(dw, CH_EN, dwc->mask);
260 while (dma_readl(dw, CH_EN) & dwc->mask)
261 cpu_relax();
262 }
263
264 /*
265 * Submit queued descriptors ASAP, i.e. before we go through
266 * the completed ones.
267 */
268 list_splice_init(&dwc->active_list, &list);
269 if (!list_empty(&dwc->queue)) {
270 list_move(dwc->queue.next, &dwc->active_list);
271 dwc_dostart(dwc, dwc_first_active(dwc));
272 }
273
274 list_for_each_entry_safe(desc, _desc, &list, desc_node)
275 dwc_descriptor_complete(dwc, desc);
276 }
277
278 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
279 {
280 dma_addr_t llp;
281 struct dw_desc *desc, *_desc;
282 struct dw_desc *child;
283 u32 status_xfer;
284
285 /*
286 * Clear block interrupt flag before scanning so that we don't
287 * miss any, and read LLP before RAW_XFER to ensure it is
288 * valid if we decide to scan the list.
289 */
290 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
291 llp = channel_readl(dwc, LLP);
292 status_xfer = dma_readl(dw, RAW.XFER);
293
294 if (status_xfer & dwc->mask) {
295 /* Everything we've submitted is done */
296 dma_writel(dw, CLEAR.XFER, dwc->mask);
297 dwc_complete_all(dw, dwc);
298 return;
299 }
300
301 if (list_empty(&dwc->active_list))
302 return;
303
304 dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
305
306 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
307 if (desc->lli.llp == llp)
308 /* This one is currently in progress */
309 return;
310
311 list_for_each_entry(child, &desc->tx_list, desc_node)
312 if (child->lli.llp == llp)
313 /* Currently in progress */
314 return;
315
316 /*
317 * No descriptors so far seem to be in progress, i.e.
318 * this one must be done.
319 */
320 dwc_descriptor_complete(dwc, desc);
321 }
322
323 dev_err(chan2dev(&dwc->chan),
324 "BUG: All descriptors done, but channel not idle!\n");
325
326 /* Try to continue after resetting the channel... */
327 channel_clear_bit(dw, CH_EN, dwc->mask);
328 while (dma_readl(dw, CH_EN) & dwc->mask)
329 cpu_relax();
330
331 if (!list_empty(&dwc->queue)) {
332 list_move(dwc->queue.next, &dwc->active_list);
333 dwc_dostart(dwc, dwc_first_active(dwc));
334 }
335 }
336
337 static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
338 {
339 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
340 " desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
341 lli->sar, lli->dar, lli->llp,
342 lli->ctlhi, lli->ctllo);
343 }
344
345 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
346 {
347 struct dw_desc *bad_desc;
348 struct dw_desc *child;
349
350 dwc_scan_descriptors(dw, dwc);
351
352 /*
353 * The descriptor currently at the head of the active list is
354 * borked. Since we don't have any way to report errors, we'll
355 * just have to scream loudly and try to carry on.
356 */
357 bad_desc = dwc_first_active(dwc);
358 list_del_init(&bad_desc->desc_node);
359 list_move(dwc->queue.next, dwc->active_list.prev);
360
361 /* Clear the error flag and try to restart the controller */
362 dma_writel(dw, CLEAR.ERROR, dwc->mask);
363 if (!list_empty(&dwc->active_list))
364 dwc_dostart(dwc, dwc_first_active(dwc));
365
366 /*
367 * KERN_CRITICAL may seem harsh, but since this only happens
368 * when someone submits a bad physical address in a
369 * descriptor, we should consider ourselves lucky that the
370 * controller flagged an error instead of scribbling over
371 * random memory locations.
372 */
373 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
374 "Bad descriptor submitted for DMA!\n");
375 dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
376 " cookie: %d\n", bad_desc->txd.cookie);
377 dwc_dump_lli(dwc, &bad_desc->lli);
378 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
379 dwc_dump_lli(dwc, &child->lli);
380
381 /* Pretend the descriptor completed successfully */
382 dwc_descriptor_complete(dwc, bad_desc);
383 }
384
385 /* --------------------- Cyclic DMA API extensions -------------------- */
386
387 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
388 {
389 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
390 return channel_readl(dwc, SAR);
391 }
392 EXPORT_SYMBOL(dw_dma_get_src_addr);
393
394 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
395 {
396 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
397 return channel_readl(dwc, DAR);
398 }
399 EXPORT_SYMBOL(dw_dma_get_dst_addr);
400
401 /* called with dwc->lock held and all DMAC interrupts disabled */
402 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
403 u32 status_block, u32 status_err, u32 status_xfer)
404 {
405 if (status_block & dwc->mask) {
406 void (*callback)(void *param);
407 void *callback_param;
408
409 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
410 channel_readl(dwc, LLP));
411 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
412
413 callback = dwc->cdesc->period_callback;
414 callback_param = dwc->cdesc->period_callback_param;
415 if (callback) {
416 spin_unlock(&dwc->lock);
417 callback(callback_param);
418 spin_lock(&dwc->lock);
419 }
420 }
421
422 /*
423 * Error and transfer complete are highly unlikely, and will most
424 * likely be due to a configuration error by the user.
425 */
426 if (unlikely(status_err & dwc->mask) ||
427 unlikely(status_xfer & dwc->mask)) {
428 int i;
429
430 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
431 "interrupt, stopping DMA transfer\n",
432 status_xfer ? "xfer" : "error");
433 dev_err(chan2dev(&dwc->chan),
434 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
435 channel_readl(dwc, SAR),
436 channel_readl(dwc, DAR),
437 channel_readl(dwc, LLP),
438 channel_readl(dwc, CTL_HI),
439 channel_readl(dwc, CTL_LO));
440
441 channel_clear_bit(dw, CH_EN, dwc->mask);
442 while (dma_readl(dw, CH_EN) & dwc->mask)
443 cpu_relax();
444
445 /* make sure DMA does not restart by loading a new list */
446 channel_writel(dwc, LLP, 0);
447 channel_writel(dwc, CTL_LO, 0);
448 channel_writel(dwc, CTL_HI, 0);
449
450 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
451 dma_writel(dw, CLEAR.ERROR, dwc->mask);
452 dma_writel(dw, CLEAR.XFER, dwc->mask);
453
454 for (i = 0; i < dwc->cdesc->periods; i++)
455 dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
456 }
457 }
458
459 /* ------------------------------------------------------------------------- */
460
461 static void dw_dma_tasklet(unsigned long data)
462 {
463 struct dw_dma *dw = (struct dw_dma *)data;
464 struct dw_dma_chan *dwc;
465 u32 status_block;
466 u32 status_xfer;
467 u32 status_err;
468 int i;
469
470 status_block = dma_readl(dw, RAW.BLOCK);
471 status_xfer = dma_readl(dw, RAW.XFER);
472 status_err = dma_readl(dw, RAW.ERROR);
473
474 dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
475 status_block, status_err);
476
477 for (i = 0; i < dw->dma.chancnt; i++) {
478 dwc = &dw->chan[i];
479 spin_lock(&dwc->lock);
480 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
481 dwc_handle_cyclic(dw, dwc, status_block, status_err,
482 status_xfer);
483 else if (status_err & (1 << i))
484 dwc_handle_error(dw, dwc);
485 else if ((status_block | status_xfer) & (1 << i))
486 dwc_scan_descriptors(dw, dwc);
487 spin_unlock(&dwc->lock);
488 }
489
490 /*
491 * Re-enable interrupts. Block Complete interrupts are only
492 * enabled if the INT_EN bit in the descriptor is set. This
493 * will trigger a scan before the whole list is done.
494 */
495 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
496 channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
497 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
498 }
499
500 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
501 {
502 struct dw_dma *dw = dev_id;
503 u32 status;
504
505 dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
506 dma_readl(dw, STATUS_INT));
507
508 /*
509 * Just disable the interrupts. We'll turn them back on in the
510 * softirq handler.
511 */
512 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
513 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
514 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
515
516 status = dma_readl(dw, STATUS_INT);
517 if (status) {
518 dev_err(dw->dma.dev,
519 "BUG: Unexpected interrupts pending: 0x%x\n",
520 status);
521
522 /* Try to recover */
523 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
524 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
525 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
526 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
527 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
528 }
529
530 tasklet_schedule(&dw->tasklet);
531
532 return IRQ_HANDLED;
533 }
534
535 /*----------------------------------------------------------------------*/
536
537 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
538 {
539 struct dw_desc *desc = txd_to_dw_desc(tx);
540 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan);
541 dma_cookie_t cookie;
542
543 spin_lock_bh(&dwc->lock);
544 cookie = dwc_assign_cookie(dwc, desc);
545
546 /*
547 * REVISIT: We should attempt to chain as many descriptors as
548 * possible, perhaps even appending to those already submitted
549 * for DMA. But this is hard to do in a race-free manner.
550 */
551 if (list_empty(&dwc->active_list)) {
552 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
553 desc->txd.cookie);
554 list_add_tail(&desc->desc_node, &dwc->active_list);
555 dwc_dostart(dwc, dwc_first_active(dwc));
556 } else {
557 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
558 desc->txd.cookie);
559
560 list_add_tail(&desc->desc_node, &dwc->queue);
561 }
562
563 spin_unlock_bh(&dwc->lock);
564
565 return cookie;
566 }
567
568 static struct dma_async_tx_descriptor *
569 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
570 size_t len, unsigned long flags)
571 {
572 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
573 struct dw_desc *desc;
574 struct dw_desc *first;
575 struct dw_desc *prev;
576 size_t xfer_count;
577 size_t offset;
578 unsigned int src_width;
579 unsigned int dst_width;
580 u32 ctllo;
581
582 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
583 dest, src, len, flags);
584
585 if (unlikely(!len)) {
586 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
587 return NULL;
588 }
589
590 /*
591 * We can be a lot more clever here, but this should take care
592 * of the most common optimization.
593 */
594 if (!((src | dest | len) & 7))
595 src_width = dst_width = 3;
596 else if (!((src | dest | len) & 3))
597 src_width = dst_width = 2;
598 else if (!((src | dest | len) & 1))
599 src_width = dst_width = 1;
600 else
601 src_width = dst_width = 0;
602
603 ctllo = DWC_DEFAULT_CTLLO(chan->private)
604 | DWC_CTLL_DST_WIDTH(dst_width)
605 | DWC_CTLL_SRC_WIDTH(src_width)
606 | DWC_CTLL_DST_INC
607 | DWC_CTLL_SRC_INC
608 | DWC_CTLL_FC_M2M;
609 prev = first = NULL;
610
611 for (offset = 0; offset < len; offset += xfer_count << src_width) {
612 xfer_count = min_t(size_t, (len - offset) >> src_width,
613 DWC_MAX_COUNT);
614
615 desc = dwc_desc_get(dwc);
616 if (!desc)
617 goto err_desc_get;
618
619 desc->lli.sar = src + offset;
620 desc->lli.dar = dest + offset;
621 desc->lli.ctllo = ctllo;
622 desc->lli.ctlhi = xfer_count;
623
624 if (!first) {
625 first = desc;
626 } else {
627 prev->lli.llp = desc->txd.phys;
628 dma_sync_single_for_device(chan2parent(chan),
629 prev->txd.phys, sizeof(prev->lli),
630 DMA_TO_DEVICE);
631 list_add_tail(&desc->desc_node,
632 &first->tx_list);
633 }
634 prev = desc;
635 }
636
637
638 if (flags & DMA_PREP_INTERRUPT)
639 /* Trigger interrupt after last block */
640 prev->lli.ctllo |= DWC_CTLL_INT_EN;
641
642 prev->lli.llp = 0;
643 dma_sync_single_for_device(chan2parent(chan),
644 prev->txd.phys, sizeof(prev->lli),
645 DMA_TO_DEVICE);
646
647 first->txd.flags = flags;
648 first->len = len;
649
650 return &first->txd;
651
652 err_desc_get:
653 dwc_desc_put(dwc, first);
654 return NULL;
655 }
656
657 static struct dma_async_tx_descriptor *
658 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
659 unsigned int sg_len, enum dma_data_direction direction,
660 unsigned long flags)
661 {
662 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
663 struct dw_dma_slave *dws = chan->private;
664 struct dw_desc *prev;
665 struct dw_desc *first;
666 u32 ctllo;
667 dma_addr_t reg;
668 unsigned int reg_width;
669 unsigned int mem_width;
670 unsigned int i;
671 struct scatterlist *sg;
672 size_t total_len = 0;
673
674 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
675
676 if (unlikely(!dws || !sg_len))
677 return NULL;
678
679 reg_width = dws->reg_width;
680 prev = first = NULL;
681
682 switch (direction) {
683 case DMA_TO_DEVICE:
684 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
685 | DWC_CTLL_DST_WIDTH(reg_width)
686 | DWC_CTLL_DST_FIX
687 | DWC_CTLL_SRC_INC
688 | DWC_CTLL_FC(dws->fc));
689 reg = dws->tx_reg;
690 for_each_sg(sgl, sg, sg_len, i) {
691 struct dw_desc *desc;
692 u32 len;
693 u32 mem;
694
695 desc = dwc_desc_get(dwc);
696 if (!desc) {
697 dev_err(chan2dev(chan),
698 "not enough descriptors available\n");
699 goto err_desc_get;
700 }
701
702 mem = sg_phys(sg);
703 len = sg_dma_len(sg);
704 mem_width = 2;
705 if (unlikely(mem & 3 || len & 3))
706 mem_width = 0;
707
708 desc->lli.sar = mem;
709 desc->lli.dar = reg;
710 desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
711 desc->lli.ctlhi = len >> mem_width;
712
713 if (!first) {
714 first = desc;
715 } else {
716 prev->lli.llp = desc->txd.phys;
717 dma_sync_single_for_device(chan2parent(chan),
718 prev->txd.phys,
719 sizeof(prev->lli),
720 DMA_TO_DEVICE);
721 list_add_tail(&desc->desc_node,
722 &first->tx_list);
723 }
724 prev = desc;
725 total_len += len;
726 }
727 break;
728 case DMA_FROM_DEVICE:
729 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
730 | DWC_CTLL_SRC_WIDTH(reg_width)
731 | DWC_CTLL_DST_INC
732 | DWC_CTLL_SRC_FIX
733 | DWC_CTLL_FC(dws->fc));
734
735 reg = dws->rx_reg;
736 for_each_sg(sgl, sg, sg_len, i) {
737 struct dw_desc *desc;
738 u32 len;
739 u32 mem;
740
741 desc = dwc_desc_get(dwc);
742 if (!desc) {
743 dev_err(chan2dev(chan),
744 "not enough descriptors available\n");
745 goto err_desc_get;
746 }
747
748 mem = sg_phys(sg);
749 len = sg_dma_len(sg);
750 mem_width = 2;
751 if (unlikely(mem & 3 || len & 3))
752 mem_width = 0;
753
754 desc->lli.sar = reg;
755 desc->lli.dar = mem;
756 desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
757 desc->lli.ctlhi = len >> reg_width;
758
759 if (!first) {
760 first = desc;
761 } else {
762 prev->lli.llp = desc->txd.phys;
763 dma_sync_single_for_device(chan2parent(chan),
764 prev->txd.phys,
765 sizeof(prev->lli),
766 DMA_TO_DEVICE);
767 list_add_tail(&desc->desc_node,
768 &first->tx_list);
769 }
770 prev = desc;
771 total_len += len;
772 }
773 break;
774 default:
775 return NULL;
776 }
777
778 if (flags & DMA_PREP_INTERRUPT)
779 /* Trigger interrupt after last block */
780 prev->lli.ctllo |= DWC_CTLL_INT_EN;
781
782 prev->lli.llp = 0;
783 dma_sync_single_for_device(chan2parent(chan),
784 prev->txd.phys, sizeof(prev->lli),
785 DMA_TO_DEVICE);
786
787 first->len = total_len;
788
789 return &first->txd;
790
791 err_desc_get:
792 dwc_desc_put(dwc, first);
793 return NULL;
794 }
795
796 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
797 unsigned long arg)
798 {
799 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
800 struct dw_dma *dw = to_dw_dma(chan->device);
801 struct dw_desc *desc, *_desc;
802 LIST_HEAD(list);
803
804 /* Only supports DMA_TERMINATE_ALL */
805 if (cmd != DMA_TERMINATE_ALL)
806 return -ENXIO;
807
808 /*
809 * This is only called when something went wrong elsewhere, so
810 * we don't really care about the data. Just disable the
811 * channel. We still have to poll the channel enable bit due
812 * to AHB/HSB limitations.
813 */
814 spin_lock_bh(&dwc->lock);
815
816 channel_clear_bit(dw, CH_EN, dwc->mask);
817
818 while (dma_readl(dw, CH_EN) & dwc->mask)
819 cpu_relax();
820
821 /* active_list entries will end up before queued entries */
822 list_splice_init(&dwc->queue, &list);
823 list_splice_init(&dwc->active_list, &list);
824
825 spin_unlock_bh(&dwc->lock);
826
827 /* Flush all pending and queued descriptors */
828 list_for_each_entry_safe(desc, _desc, &list, desc_node)
829 dwc_descriptor_complete(dwc, desc);
830
831 return 0;
832 }
833
834 static enum dma_status
835 dwc_tx_status(struct dma_chan *chan,
836 dma_cookie_t cookie,
837 struct dma_tx_state *txstate)
838 {
839 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
840 dma_cookie_t last_used;
841 dma_cookie_t last_complete;
842 int ret;
843
844 last_complete = dwc->completed;
845 last_used = chan->cookie;
846
847 ret = dma_async_is_complete(cookie, last_complete, last_used);
848 if (ret != DMA_SUCCESS) {
849 spin_lock_bh(&dwc->lock);
850 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
851 spin_unlock_bh(&dwc->lock);
852
853 last_complete = dwc->completed;
854 last_used = chan->cookie;
855
856 ret = dma_async_is_complete(cookie, last_complete, last_used);
857 }
858
859 dma_set_tx_state(txstate, last_complete, last_used, 0);
860
861 return ret;
862 }
863
864 static void dwc_issue_pending(struct dma_chan *chan)
865 {
866 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
867
868 spin_lock_bh(&dwc->lock);
869 if (!list_empty(&dwc->queue))
870 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
871 spin_unlock_bh(&dwc->lock);
872 }
873
874 static int dwc_alloc_chan_resources(struct dma_chan *chan)
875 {
876 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
877 struct dw_dma *dw = to_dw_dma(chan->device);
878 struct dw_desc *desc;
879 struct dw_dma_slave *dws;
880 int i;
881 u32 cfghi;
882 u32 cfglo;
883
884 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
885
886 /* ASSERT: channel is idle */
887 if (dma_readl(dw, CH_EN) & dwc->mask) {
888 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
889 return -EIO;
890 }
891
892 dwc->completed = chan->cookie = 1;
893
894 cfghi = DWC_CFGH_FIFO_MODE;
895 cfglo = 0;
896
897 dws = chan->private;
898 if (dws) {
899 /*
900 * We need controller-specific data to set up slave
901 * transfers.
902 */
903 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
904
905 cfghi = dws->cfg_hi;
906 cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
907 }
908
909 cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
910
911 channel_writel(dwc, CFG_LO, cfglo);
912 channel_writel(dwc, CFG_HI, cfghi);
913
914 /*
915 * NOTE: some controllers may have additional features that we
916 * need to initialize here, like "scatter-gather" (which
917 * doesn't mean what you think it means), and status writeback.
918 */
919
920 spin_lock_bh(&dwc->lock);
921 i = dwc->descs_allocated;
922 while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
923 spin_unlock_bh(&dwc->lock);
924
925 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
926 if (!desc) {
927 dev_info(chan2dev(chan),
928 "only allocated %d descriptors\n", i);
929 spin_lock_bh(&dwc->lock);
930 break;
931 }
932
933 INIT_LIST_HEAD(&desc->tx_list);
934 dma_async_tx_descriptor_init(&desc->txd, chan);
935 desc->txd.tx_submit = dwc_tx_submit;
936 desc->txd.flags = DMA_CTRL_ACK;
937 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
938 sizeof(desc->lli), DMA_TO_DEVICE);
939 dwc_desc_put(dwc, desc);
940
941 spin_lock_bh(&dwc->lock);
942 i = ++dwc->descs_allocated;
943 }
944
945 /* Enable interrupts */
946 channel_set_bit(dw, MASK.XFER, dwc->mask);
947 channel_set_bit(dw, MASK.BLOCK, dwc->mask);
948 channel_set_bit(dw, MASK.ERROR, dwc->mask);
949
950 spin_unlock_bh(&dwc->lock);
951
952 dev_dbg(chan2dev(chan),
953 "alloc_chan_resources allocated %d descriptors\n", i);
954
955 return i;
956 }
957
958 static void dwc_free_chan_resources(struct dma_chan *chan)
959 {
960 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
961 struct dw_dma *dw = to_dw_dma(chan->device);
962 struct dw_desc *desc, *_desc;
963 LIST_HEAD(list);
964
965 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
966 dwc->descs_allocated);
967
968 /* ASSERT: channel is idle */
969 BUG_ON(!list_empty(&dwc->active_list));
970 BUG_ON(!list_empty(&dwc->queue));
971 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
972
973 spin_lock_bh(&dwc->lock);
974 list_splice_init(&dwc->free_list, &list);
975 dwc->descs_allocated = 0;
976
977 /* Disable interrupts */
978 channel_clear_bit(dw, MASK.XFER, dwc->mask);
979 channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
980 channel_clear_bit(dw, MASK.ERROR, dwc->mask);
981
982 spin_unlock_bh(&dwc->lock);
983
984 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
985 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
986 dma_unmap_single(chan2parent(chan), desc->txd.phys,
987 sizeof(desc->lli), DMA_TO_DEVICE);
988 kfree(desc);
989 }
990
991 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
992 }
993
994 /* --------------------- Cyclic DMA API extensions -------------------- */
995
996 /**
997 * dw_dma_cyclic_start - start the cyclic DMA transfer
998 * @chan: the DMA channel to start
999 *
1000 * Must be called with soft interrupts disabled. Returns zero on success or
1001 * -errno on failure.
1002 */
1003 int dw_dma_cyclic_start(struct dma_chan *chan)
1004 {
1005 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1006 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1007
1008 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1009 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1010 return -ENODEV;
1011 }
1012
1013 spin_lock(&dwc->lock);
1014
1015 /* assert channel is idle */
1016 if (dma_readl(dw, CH_EN) & dwc->mask) {
1017 dev_err(chan2dev(&dwc->chan),
1018 "BUG: Attempted to start non-idle channel\n");
1019 dev_err(chan2dev(&dwc->chan),
1020 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1021 channel_readl(dwc, SAR),
1022 channel_readl(dwc, DAR),
1023 channel_readl(dwc, LLP),
1024 channel_readl(dwc, CTL_HI),
1025 channel_readl(dwc, CTL_LO));
1026 spin_unlock(&dwc->lock);
1027 return -EBUSY;
1028 }
1029
1030 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1031 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1032 dma_writel(dw, CLEAR.XFER, dwc->mask);
1033
1034 /* setup DMAC channel registers */
1035 channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1036 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1037 channel_writel(dwc, CTL_HI, 0);
1038
1039 channel_set_bit(dw, CH_EN, dwc->mask);
1040
1041 spin_unlock(&dwc->lock);
1042
1043 return 0;
1044 }
1045 EXPORT_SYMBOL(dw_dma_cyclic_start);
1046
1047 /**
1048 * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1049 * @chan: the DMA channel to stop
1050 *
1051 * Must be called with soft interrupts disabled.
1052 */
1053 void dw_dma_cyclic_stop(struct dma_chan *chan)
1054 {
1055 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1056 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1057
1058 spin_lock(&dwc->lock);
1059
1060 channel_clear_bit(dw, CH_EN, dwc->mask);
1061 while (dma_readl(dw, CH_EN) & dwc->mask)
1062 cpu_relax();
1063
1064 spin_unlock(&dwc->lock);
1065 }
1066 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1067
1068 /**
1069 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1070 * @chan: the DMA channel to prepare
1071 * @buf_addr: physical DMA address where the buffer starts
1072 * @buf_len: total number of bytes for the entire buffer
1073 * @period_len: number of bytes for each period
1074 * @direction: transfer direction, to or from device
1075 *
1076 * Must be called before trying to start the transfer. Returns a valid struct
1077 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1078 */
1079 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1080 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1081 enum dma_data_direction direction)
1082 {
1083 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1084 struct dw_cyclic_desc *cdesc;
1085 struct dw_cyclic_desc *retval = NULL;
1086 struct dw_desc *desc;
1087 struct dw_desc *last = NULL;
1088 struct dw_dma_slave *dws = chan->private;
1089 unsigned long was_cyclic;
1090 unsigned int reg_width;
1091 unsigned int periods;
1092 unsigned int i;
1093
1094 spin_lock_bh(&dwc->lock);
1095 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1096 spin_unlock_bh(&dwc->lock);
1097 dev_dbg(chan2dev(&dwc->chan),
1098 "queue and/or active list are not empty\n");
1099 return ERR_PTR(-EBUSY);
1100 }
1101
1102 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1103 spin_unlock_bh(&dwc->lock);
1104 if (was_cyclic) {
1105 dev_dbg(chan2dev(&dwc->chan),
1106 "channel already prepared for cyclic DMA\n");
1107 return ERR_PTR(-EBUSY);
1108 }
1109
1110 retval = ERR_PTR(-EINVAL);
1111 reg_width = dws->reg_width;
1112 periods = buf_len / period_len;
1113
1114 /* Check for too big/unaligned periods and unaligned DMA buffer. */
1115 if (period_len > (DWC_MAX_COUNT << reg_width))
1116 goto out_err;
1117 if (unlikely(period_len & ((1 << reg_width) - 1)))
1118 goto out_err;
1119 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1120 goto out_err;
1121 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
1122 goto out_err;
1123
1124 retval = ERR_PTR(-ENOMEM);
1125
1126 if (periods > NR_DESCS_PER_CHANNEL)
1127 goto out_err;
1128
1129 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1130 if (!cdesc)
1131 goto out_err;
1132
1133 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1134 if (!cdesc->desc)
1135 goto out_err_alloc;
1136
1137 for (i = 0; i < periods; i++) {
1138 desc = dwc_desc_get(dwc);
1139 if (!desc)
1140 goto out_err_desc_get;
1141
1142 switch (direction) {
1143 case DMA_TO_DEVICE:
1144 desc->lli.dar = dws->tx_reg;
1145 desc->lli.sar = buf_addr + (period_len * i);
1146 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1147 | DWC_CTLL_DST_WIDTH(reg_width)
1148 | DWC_CTLL_SRC_WIDTH(reg_width)
1149 | DWC_CTLL_DST_FIX
1150 | DWC_CTLL_SRC_INC
1151 | DWC_CTLL_FC(dws->fc)
1152 | DWC_CTLL_INT_EN);
1153 break;
1154 case DMA_FROM_DEVICE:
1155 desc->lli.dar = buf_addr + (period_len * i);
1156 desc->lli.sar = dws->rx_reg;
1157 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1158 | DWC_CTLL_SRC_WIDTH(reg_width)
1159 | DWC_CTLL_DST_WIDTH(reg_width)
1160 | DWC_CTLL_DST_INC
1161 | DWC_CTLL_SRC_FIX
1162 | DWC_CTLL_FC(dws->fc)
1163 | DWC_CTLL_INT_EN);
1164 break;
1165 default:
1166 break;
1167 }
1168
1169 desc->lli.ctlhi = (period_len >> reg_width);
1170 cdesc->desc[i] = desc;
1171
1172 if (last) {
1173 last->lli.llp = desc->txd.phys;
1174 dma_sync_single_for_device(chan2parent(chan),
1175 last->txd.phys, sizeof(last->lli),
1176 DMA_TO_DEVICE);
1177 }
1178
1179 last = desc;
1180 }
1181
1182 /* lets make a cyclic list */
1183 last->lli.llp = cdesc->desc[0]->txd.phys;
1184 dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1185 sizeof(last->lli), DMA_TO_DEVICE);
1186
1187 dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
1188 "period %zu periods %d\n", buf_addr, buf_len,
1189 period_len, periods);
1190
1191 cdesc->periods = periods;
1192 dwc->cdesc = cdesc;
1193
1194 return cdesc;
1195
1196 out_err_desc_get:
1197 while (i--)
1198 dwc_desc_put(dwc, cdesc->desc[i]);
1199 out_err_alloc:
1200 kfree(cdesc);
1201 out_err:
1202 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1203 return (struct dw_cyclic_desc *)retval;
1204 }
1205 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1206
1207 /**
1208 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1209 * @chan: the DMA channel to free
1210 */
1211 void dw_dma_cyclic_free(struct dma_chan *chan)
1212 {
1213 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1214 struct dw_dma *dw = to_dw_dma(dwc->chan.device);
1215 struct dw_cyclic_desc *cdesc = dwc->cdesc;
1216 int i;
1217
1218 dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
1219
1220 if (!cdesc)
1221 return;
1222
1223 spin_lock_bh(&dwc->lock);
1224
1225 channel_clear_bit(dw, CH_EN, dwc->mask);
1226 while (dma_readl(dw, CH_EN) & dwc->mask)
1227 cpu_relax();
1228
1229 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1230 dma_writel(dw, CLEAR.ERROR, dwc->mask);
1231 dma_writel(dw, CLEAR.XFER, dwc->mask);
1232
1233 spin_unlock_bh(&dwc->lock);
1234
1235 for (i = 0; i < cdesc->periods; i++)
1236 dwc_desc_put(dwc, cdesc->desc[i]);
1237
1238 kfree(cdesc->desc);
1239 kfree(cdesc);
1240
1241 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1242 }
1243 EXPORT_SYMBOL(dw_dma_cyclic_free);
1244
1245 /*----------------------------------------------------------------------*/
1246
1247 static void dw_dma_off(struct dw_dma *dw)
1248 {
1249 dma_writel(dw, CFG, 0);
1250
1251 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1252 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1253 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1254 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1255 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1256
1257 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1258 cpu_relax();
1259 }
1260
1261 static int __init dw_probe(struct platform_device *pdev)
1262 {
1263 struct dw_dma_platform_data *pdata;
1264 struct resource *io;
1265 struct dw_dma *dw;
1266 size_t size;
1267 int irq;
1268 int err;
1269 int i;
1270
1271 pdata = pdev->dev.platform_data;
1272 if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1273 return -EINVAL;
1274
1275 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1276 if (!io)
1277 return -EINVAL;
1278
1279 irq = platform_get_irq(pdev, 0);
1280 if (irq < 0)
1281 return irq;
1282
1283 size = sizeof(struct dw_dma);
1284 size += pdata->nr_channels * sizeof(struct dw_dma_chan);
1285 dw = kzalloc(size, GFP_KERNEL);
1286 if (!dw)
1287 return -ENOMEM;
1288
1289 if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
1290 err = -EBUSY;
1291 goto err_kfree;
1292 }
1293
1294 dw->regs = ioremap(io->start, DW_REGLEN);
1295 if (!dw->regs) {
1296 err = -ENOMEM;
1297 goto err_release_r;
1298 }
1299
1300 dw->clk = clk_get(&pdev->dev, "hclk");
1301 if (IS_ERR(dw->clk)) {
1302 err = PTR_ERR(dw->clk);
1303 goto err_clk;
1304 }
1305 clk_enable(dw->clk);
1306
1307 /* force dma off, just in case */
1308 dw_dma_off(dw);
1309
1310 err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
1311 if (err)
1312 goto err_irq;
1313
1314 platform_set_drvdata(pdev, dw);
1315
1316 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1317
1318 dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1319
1320 INIT_LIST_HEAD(&dw->dma.channels);
1321 for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
1322 struct dw_dma_chan *dwc = &dw->chan[i];
1323
1324 dwc->chan.device = &dw->dma;
1325 dwc->chan.cookie = dwc->completed = 1;
1326 dwc->chan.chan_id = i;
1327 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1328 list_add_tail(&dwc->chan.device_node,
1329 &dw->dma.channels);
1330 else
1331 list_add(&dwc->chan.device_node, &dw->dma.channels);
1332
1333 /* 7 is highest priority & 0 is lowest. */
1334 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1335 dwc->priority = 7 - i;
1336 else
1337 dwc->priority = i;
1338
1339 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1340 spin_lock_init(&dwc->lock);
1341 dwc->mask = 1 << i;
1342
1343 INIT_LIST_HEAD(&dwc->active_list);
1344 INIT_LIST_HEAD(&dwc->queue);
1345 INIT_LIST_HEAD(&dwc->free_list);
1346
1347 channel_clear_bit(dw, CH_EN, dwc->mask);
1348 }
1349
1350 /* Clear/disable all interrupts on all channels. */
1351 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1352 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1353 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1354 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1355 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1356
1357 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1358 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1359 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1360 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1361 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1362
1363 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1364 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1365 if (pdata->is_private)
1366 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1367 dw->dma.dev = &pdev->dev;
1368 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1369 dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1370
1371 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1372
1373 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1374 dw->dma.device_control = dwc_control;
1375
1376 dw->dma.device_tx_status = dwc_tx_status;
1377 dw->dma.device_issue_pending = dwc_issue_pending;
1378
1379 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1380
1381 printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1382 dev_name(&pdev->dev), dw->dma.chancnt);
1383
1384 dma_async_device_register(&dw->dma);
1385
1386 return 0;
1387
1388 err_irq:
1389 clk_disable(dw->clk);
1390 clk_put(dw->clk);
1391 err_clk:
1392 iounmap(dw->regs);
1393 dw->regs = NULL;
1394 err_release_r:
1395 release_resource(io);
1396 err_kfree:
1397 kfree(dw);
1398 return err;
1399 }
1400
1401 static int __exit dw_remove(struct platform_device *pdev)
1402 {
1403 struct dw_dma *dw = platform_get_drvdata(pdev);
1404 struct dw_dma_chan *dwc, *_dwc;
1405 struct resource *io;
1406
1407 dw_dma_off(dw);
1408 dma_async_device_unregister(&dw->dma);
1409
1410 free_irq(platform_get_irq(pdev, 0), dw);
1411 tasklet_kill(&dw->tasklet);
1412
1413 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1414 chan.device_node) {
1415 list_del(&dwc->chan.device_node);
1416 channel_clear_bit(dw, CH_EN, dwc->mask);
1417 }
1418
1419 clk_disable(dw->clk);
1420 clk_put(dw->clk);
1421
1422 iounmap(dw->regs);
1423 dw->regs = NULL;
1424
1425 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1426 release_mem_region(io->start, DW_REGLEN);
1427
1428 kfree(dw);
1429
1430 return 0;
1431 }
1432
1433 static void dw_shutdown(struct platform_device *pdev)
1434 {
1435 struct dw_dma *dw = platform_get_drvdata(pdev);
1436
1437 dw_dma_off(platform_get_drvdata(pdev));
1438 clk_disable(dw->clk);
1439 }
1440
1441 static int dw_suspend_noirq(struct device *dev)
1442 {
1443 struct platform_device *pdev = to_platform_device(dev);
1444 struct dw_dma *dw = platform_get_drvdata(pdev);
1445
1446 dw_dma_off(platform_get_drvdata(pdev));
1447 clk_disable(dw->clk);
1448 return 0;
1449 }
1450
1451 static int dw_resume_noirq(struct device *dev)
1452 {
1453 struct platform_device *pdev = to_platform_device(dev);
1454 struct dw_dma *dw = platform_get_drvdata(pdev);
1455
1456 clk_enable(dw->clk);
1457 dma_writel(dw, CFG, DW_CFG_DMA_EN);
1458 return 0;
1459 }
1460
1461 static const struct dev_pm_ops dw_dev_pm_ops = {
1462 .suspend_noirq = dw_suspend_noirq,
1463 .resume_noirq = dw_resume_noirq,
1464 };
1465
1466 static struct platform_driver dw_driver = {
1467 .remove = __exit_p(dw_remove),
1468 .shutdown = dw_shutdown,
1469 .driver = {
1470 .name = "dw_dmac",
1471 .pm = &dw_dev_pm_ops,
1472 },
1473 };
1474
1475 static int __init dw_init(void)
1476 {
1477 return platform_driver_probe(&dw_driver, dw_probe);
1478 }
1479 subsys_initcall(dw_init);
1480
1481 static void __exit dw_exit(void)
1482 {
1483 platform_driver_unregister(&dw_driver);
1484 }
1485 module_exit(dw_exit);
1486
1487 MODULE_LICENSE("GPL v2");
1488 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1489 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree