1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
29 static const char *const version
=
30 DRV_NAME
".c:v" DRV_VERSION
" " DRV_RELDATE
" tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
54 #include <asm/uaccess.h>
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 static struct pci_device_id pcnet32_pci_tbl
[] = {
61 { PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE_HOME
,
62 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
63 { PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_LANCE
,
64 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
67 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
68 * the incorrect vendor id.
70 { PCI_VENDOR_ID_TRIDENT
, PCI_DEVICE_ID_AMD_LANCE
,
71 PCI_ANY_ID
, PCI_ANY_ID
,
72 PCI_CLASS_NETWORK_ETHERNET
<< 8, 0xffff00, 0},
74 { } /* terminate list */
77 MODULE_DEVICE_TABLE(pci
, pcnet32_pci_tbl
);
79 static int cards_found
;
84 static unsigned int pcnet32_portlist
[] __initdata
=
85 { 0x300, 0x320, 0x340, 0x360, 0 };
87 static int pcnet32_debug
= 0;
88 static int tx_start
= 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
89 static int pcnet32vlb
; /* check for VLB cards ? */
91 static struct net_device
*pcnet32_dev
;
93 static int max_interrupt_work
= 2;
94 static int rx_copybreak
= 200;
96 #define PCNET32_PORT_AUI 0x00
97 #define PCNET32_PORT_10BT 0x01
98 #define PCNET32_PORT_GPSI 0x02
99 #define PCNET32_PORT_MII 0x03
101 #define PCNET32_PORT_PORTSEL 0x03
102 #define PCNET32_PORT_ASEL 0x04
103 #define PCNET32_PORT_100 0x40
104 #define PCNET32_PORT_FD 0x80
106 #define PCNET32_DMA_MASK 0xffffffff
108 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
109 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
112 * table to translate option values from tulip
113 * to internal options
115 static const unsigned char options_mapping
[] = {
116 PCNET32_PORT_ASEL
, /* 0 Auto-select */
117 PCNET32_PORT_AUI
, /* 1 BNC/AUI */
118 PCNET32_PORT_AUI
, /* 2 AUI/BNC */
119 PCNET32_PORT_ASEL
, /* 3 not supported */
120 PCNET32_PORT_10BT
| PCNET32_PORT_FD
, /* 4 10baseT-FD */
121 PCNET32_PORT_ASEL
, /* 5 not supported */
122 PCNET32_PORT_ASEL
, /* 6 not supported */
123 PCNET32_PORT_ASEL
, /* 7 not supported */
124 PCNET32_PORT_ASEL
, /* 8 not supported */
125 PCNET32_PORT_MII
, /* 9 MII 10baseT */
126 PCNET32_PORT_MII
| PCNET32_PORT_FD
, /* 10 MII 10baseT-FD */
127 PCNET32_PORT_MII
, /* 11 MII (autosel) */
128 PCNET32_PORT_10BT
, /* 12 10BaseT */
129 PCNET32_PORT_MII
| PCNET32_PORT_100
, /* 13 MII 100BaseTx */
130 /* 14 MII 100BaseTx-FD */
131 PCNET32_PORT_MII
| PCNET32_PORT_100
| PCNET32_PORT_FD
,
132 PCNET32_PORT_ASEL
/* 15 not supported */
135 static const char pcnet32_gstrings_test
[][ETH_GSTRING_LEN
] = {
136 "Loopback test (offline)"
139 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141 #define PCNET32_NUM_REGS 136
143 #define MAX_UNITS 8 /* More are supported, limit only on options */
144 static int options
[MAX_UNITS
];
145 static int full_duplex
[MAX_UNITS
];
146 static int homepna
[MAX_UNITS
];
149 * Theory of Operation
151 * This driver uses the same software structure as the normal lance
152 * driver. So look for a verbose description in lance.c. The differences
153 * to the normal lance driver is the use of the 32bit mode of PCnet32
154 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
155 * 16MB limitation and we don't need bounce buffers.
159 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
160 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
161 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 #ifndef PCNET32_LOG_TX_BUFFERS
164 #define PCNET32_LOG_TX_BUFFERS 4
165 #define PCNET32_LOG_RX_BUFFERS 5
166 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
167 #define PCNET32_LOG_MAX_RX_BUFFERS 9
170 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
171 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
174 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176 #define PKT_BUF_SZ 1544
178 /* Offsets from base I/O address. */
179 #define PCNET32_WIO_RDP 0x10
180 #define PCNET32_WIO_RAP 0x12
181 #define PCNET32_WIO_RESET 0x14
182 #define PCNET32_WIO_BDP 0x16
184 #define PCNET32_DWIO_RDP 0x10
185 #define PCNET32_DWIO_RAP 0x14
186 #define PCNET32_DWIO_RESET 0x18
187 #define PCNET32_DWIO_BDP 0x1C
189 #define PCNET32_TOTAL_SIZE 0x20
191 /* The PCNET32 Rx and Tx ring descriptors. */
192 struct pcnet32_rx_head
{
200 struct pcnet32_tx_head
{
208 /* The PCNET32 32-Bit initialization block, described in databook. */
209 struct pcnet32_init_block
{
215 /* Receive and transmit ring base, along with extra bits. */
220 /* PCnet32 access functions */
221 struct pcnet32_access
{
222 u16 (*read_csr
) (unsigned long, int);
223 void (*write_csr
) (unsigned long, int, u16
);
224 u16 (*read_bcr
) (unsigned long, int);
225 void (*write_bcr
) (unsigned long, int, u16
);
226 u16 (*read_rap
) (unsigned long);
227 void (*write_rap
) (unsigned long, u16
);
228 void (*reset
) (unsigned long);
232 * The first field of pcnet32_private is read by the ethernet device
233 * so the structure should be allocated using pci_alloc_consistent().
235 struct pcnet32_private
{
236 struct pcnet32_init_block init_block
;
237 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
238 struct pcnet32_rx_head
*rx_ring
;
239 struct pcnet32_tx_head
*tx_ring
;
240 dma_addr_t dma_addr
;/* DMA address of beginning of this
241 object, returned by pci_alloc_consistent */
242 struct pci_dev
*pci_dev
;
244 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
245 struct sk_buff
**tx_skbuff
;
246 struct sk_buff
**rx_skbuff
;
247 dma_addr_t
*tx_dma_addr
;
248 dma_addr_t
*rx_dma_addr
;
249 struct pcnet32_access a
;
250 spinlock_t lock
; /* Guard lock */
251 unsigned int cur_rx
, cur_tx
; /* The next free ring entry */
252 unsigned int rx_ring_size
; /* current rx ring size */
253 unsigned int tx_ring_size
; /* current tx ring size */
254 unsigned int rx_mod_mask
; /* rx ring modular mask */
255 unsigned int tx_mod_mask
; /* tx ring modular mask */
256 unsigned short rx_len_bits
;
257 unsigned short tx_len_bits
;
258 dma_addr_t rx_ring_dma_addr
;
259 dma_addr_t tx_ring_dma_addr
;
260 unsigned int dirty_rx
, /* ring entries to be freed. */
263 struct net_device_stats stats
;
265 char phycount
; /* number of phys found */
267 unsigned int shared_irq
:1, /* shared irq possible */
268 dxsuflo
:1, /* disable transmit stop on uflo */
269 mii
:1; /* mii port available */
270 struct net_device
*next
;
271 struct mii_if_info mii_if
;
272 struct timer_list watchdog_timer
;
273 struct timer_list blink_timer
;
274 u32 msg_enable
; /* debug message level */
276 /* each bit indicates an available PHY */
280 static int pcnet32_probe_pci(struct pci_dev
*, const struct pci_device_id
*);
281 static int pcnet32_probe1(unsigned long, int, struct pci_dev
*);
282 static int pcnet32_open(struct net_device
*);
283 static int pcnet32_init_ring(struct net_device
*);
284 static int pcnet32_start_xmit(struct sk_buff
*, struct net_device
*);
285 static int pcnet32_rx(struct net_device
*);
286 static void pcnet32_tx_timeout(struct net_device
*dev
);
287 static irqreturn_t
pcnet32_interrupt(int, void *, struct pt_regs
*);
288 static int pcnet32_close(struct net_device
*);
289 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*);
290 static void pcnet32_load_multicast(struct net_device
*dev
);
291 static void pcnet32_set_multicast_list(struct net_device
*);
292 static int pcnet32_ioctl(struct net_device
*, struct ifreq
*, int);
293 static void pcnet32_watchdog(struct net_device
*);
294 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
);
295 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
,
297 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
);
298 static void pcnet32_ethtool_test(struct net_device
*dev
,
299 struct ethtool_test
*eth_test
, u64
* data
);
300 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
);
301 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
);
302 static void pcnet32_led_blink_callback(struct net_device
*dev
);
303 static int pcnet32_get_regs_len(struct net_device
*dev
);
304 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
306 static void pcnet32_purge_tx_ring(struct net_device
*dev
);
307 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
);
308 static void pcnet32_free_ring(struct net_device
*dev
);
309 static void pcnet32_check_media(struct net_device
*dev
, int verbose
);
311 static u16
pcnet32_wio_read_csr(unsigned long addr
, int index
)
313 outw(index
, addr
+ PCNET32_WIO_RAP
);
314 return inw(addr
+ PCNET32_WIO_RDP
);
317 static void pcnet32_wio_write_csr(unsigned long addr
, int index
, u16 val
)
319 outw(index
, addr
+ PCNET32_WIO_RAP
);
320 outw(val
, addr
+ PCNET32_WIO_RDP
);
323 static u16
pcnet32_wio_read_bcr(unsigned long addr
, int index
)
325 outw(index
, addr
+ PCNET32_WIO_RAP
);
326 return inw(addr
+ PCNET32_WIO_BDP
);
329 static void pcnet32_wio_write_bcr(unsigned long addr
, int index
, u16 val
)
331 outw(index
, addr
+ PCNET32_WIO_RAP
);
332 outw(val
, addr
+ PCNET32_WIO_BDP
);
335 static u16
pcnet32_wio_read_rap(unsigned long addr
)
337 return inw(addr
+ PCNET32_WIO_RAP
);
340 static void pcnet32_wio_write_rap(unsigned long addr
, u16 val
)
342 outw(val
, addr
+ PCNET32_WIO_RAP
);
345 static void pcnet32_wio_reset(unsigned long addr
)
347 inw(addr
+ PCNET32_WIO_RESET
);
350 static int pcnet32_wio_check(unsigned long addr
)
352 outw(88, addr
+ PCNET32_WIO_RAP
);
353 return (inw(addr
+ PCNET32_WIO_RAP
) == 88);
356 static struct pcnet32_access pcnet32_wio
= {
357 .read_csr
= pcnet32_wio_read_csr
,
358 .write_csr
= pcnet32_wio_write_csr
,
359 .read_bcr
= pcnet32_wio_read_bcr
,
360 .write_bcr
= pcnet32_wio_write_bcr
,
361 .read_rap
= pcnet32_wio_read_rap
,
362 .write_rap
= pcnet32_wio_write_rap
,
363 .reset
= pcnet32_wio_reset
366 static u16
pcnet32_dwio_read_csr(unsigned long addr
, int index
)
368 outl(index
, addr
+ PCNET32_DWIO_RAP
);
369 return (inl(addr
+ PCNET32_DWIO_RDP
) & 0xffff);
372 static void pcnet32_dwio_write_csr(unsigned long addr
, int index
, u16 val
)
374 outl(index
, addr
+ PCNET32_DWIO_RAP
);
375 outl(val
, addr
+ PCNET32_DWIO_RDP
);
378 static u16
pcnet32_dwio_read_bcr(unsigned long addr
, int index
)
380 outl(index
, addr
+ PCNET32_DWIO_RAP
);
381 return (inl(addr
+ PCNET32_DWIO_BDP
) & 0xffff);
384 static void pcnet32_dwio_write_bcr(unsigned long addr
, int index
, u16 val
)
386 outl(index
, addr
+ PCNET32_DWIO_RAP
);
387 outl(val
, addr
+ PCNET32_DWIO_BDP
);
390 static u16
pcnet32_dwio_read_rap(unsigned long addr
)
392 return (inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff);
395 static void pcnet32_dwio_write_rap(unsigned long addr
, u16 val
)
397 outl(val
, addr
+ PCNET32_DWIO_RAP
);
400 static void pcnet32_dwio_reset(unsigned long addr
)
402 inl(addr
+ PCNET32_DWIO_RESET
);
405 static int pcnet32_dwio_check(unsigned long addr
)
407 outl(88, addr
+ PCNET32_DWIO_RAP
);
408 return ((inl(addr
+ PCNET32_DWIO_RAP
) & 0xffff) == 88);
411 static struct pcnet32_access pcnet32_dwio
= {
412 .read_csr
= pcnet32_dwio_read_csr
,
413 .write_csr
= pcnet32_dwio_write_csr
,
414 .read_bcr
= pcnet32_dwio_read_bcr
,
415 .write_bcr
= pcnet32_dwio_write_bcr
,
416 .read_rap
= pcnet32_dwio_read_rap
,
417 .write_rap
= pcnet32_dwio_write_rap
,
418 .reset
= pcnet32_dwio_reset
421 #ifdef CONFIG_NET_POLL_CONTROLLER
422 static void pcnet32_poll_controller(struct net_device
*dev
)
424 disable_irq(dev
->irq
);
425 pcnet32_interrupt(0, dev
, NULL
);
426 enable_irq(dev
->irq
);
430 static int pcnet32_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
432 struct pcnet32_private
*lp
= dev
->priv
;
437 spin_lock_irqsave(&lp
->lock
, flags
);
438 mii_ethtool_gset(&lp
->mii_if
, cmd
);
439 spin_unlock_irqrestore(&lp
->lock
, flags
);
445 static int pcnet32_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
447 struct pcnet32_private
*lp
= dev
->priv
;
452 spin_lock_irqsave(&lp
->lock
, flags
);
453 r
= mii_ethtool_sset(&lp
->mii_if
, cmd
);
454 spin_unlock_irqrestore(&lp
->lock
, flags
);
459 static void pcnet32_get_drvinfo(struct net_device
*dev
,
460 struct ethtool_drvinfo
*info
)
462 struct pcnet32_private
*lp
= dev
->priv
;
464 strcpy(info
->driver
, DRV_NAME
);
465 strcpy(info
->version
, DRV_VERSION
);
467 strcpy(info
->bus_info
, pci_name(lp
->pci_dev
));
469 sprintf(info
->bus_info
, "VLB 0x%lx", dev
->base_addr
);
472 static u32
pcnet32_get_link(struct net_device
*dev
)
474 struct pcnet32_private
*lp
= dev
->priv
;
478 spin_lock_irqsave(&lp
->lock
, flags
);
480 r
= mii_link_ok(&lp
->mii_if
);
482 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
483 r
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
485 spin_unlock_irqrestore(&lp
->lock
, flags
);
490 static u32
pcnet32_get_msglevel(struct net_device
*dev
)
492 struct pcnet32_private
*lp
= dev
->priv
;
493 return lp
->msg_enable
;
496 static void pcnet32_set_msglevel(struct net_device
*dev
, u32 value
)
498 struct pcnet32_private
*lp
= dev
->priv
;
499 lp
->msg_enable
= value
;
502 static int pcnet32_nway_reset(struct net_device
*dev
)
504 struct pcnet32_private
*lp
= dev
->priv
;
509 spin_lock_irqsave(&lp
->lock
, flags
);
510 r
= mii_nway_restart(&lp
->mii_if
);
511 spin_unlock_irqrestore(&lp
->lock
, flags
);
516 static void pcnet32_get_ringparam(struct net_device
*dev
,
517 struct ethtool_ringparam
*ering
)
519 struct pcnet32_private
*lp
= dev
->priv
;
521 ering
->tx_max_pending
= TX_MAX_RING_SIZE
- 1;
522 ering
->tx_pending
= lp
->tx_ring_size
- 1;
523 ering
->rx_max_pending
= RX_MAX_RING_SIZE
- 1;
524 ering
->rx_pending
= lp
->rx_ring_size
- 1;
527 static int pcnet32_set_ringparam(struct net_device
*dev
,
528 struct ethtool_ringparam
*ering
)
530 struct pcnet32_private
*lp
= dev
->priv
;
534 if (ering
->rx_mini_pending
|| ering
->rx_jumbo_pending
)
537 if (netif_running(dev
))
540 spin_lock_irqsave(&lp
->lock
, flags
);
541 pcnet32_free_ring(dev
);
543 min(ering
->tx_pending
, (unsigned int)TX_MAX_RING_SIZE
);
545 min(ering
->rx_pending
, (unsigned int)RX_MAX_RING_SIZE
);
547 /* set the minimum ring size to 4, to allow the loopback test to work
550 for (i
= 2; i
<= PCNET32_LOG_MAX_TX_BUFFERS
; i
++) {
551 if (lp
->tx_ring_size
<= (1 << i
))
554 lp
->tx_ring_size
= (1 << i
);
555 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
556 lp
->tx_len_bits
= (i
<< 12);
558 for (i
= 2; i
<= PCNET32_LOG_MAX_RX_BUFFERS
; i
++) {
559 if (lp
->rx_ring_size
<= (1 << i
))
562 lp
->rx_ring_size
= (1 << i
);
563 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
564 lp
->rx_len_bits
= (i
<< 4);
566 if (pcnet32_alloc_ring(dev
, dev
->name
)) {
567 pcnet32_free_ring(dev
);
568 spin_unlock_irqrestore(&lp
->lock
, flags
);
572 spin_unlock_irqrestore(&lp
->lock
, flags
);
574 if (pcnet32_debug
& NETIF_MSG_DRV
)
576 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev
->name
,
577 lp
->rx_ring_size
, lp
->tx_ring_size
);
579 if (netif_running(dev
))
585 static void pcnet32_get_strings(struct net_device
*dev
, u32 stringset
,
588 memcpy(data
, pcnet32_gstrings_test
, sizeof(pcnet32_gstrings_test
));
591 static int pcnet32_self_test_count(struct net_device
*dev
)
593 return PCNET32_TEST_LEN
;
596 static void pcnet32_ethtool_test(struct net_device
*dev
,
597 struct ethtool_test
*test
, u64
* data
)
599 struct pcnet32_private
*lp
= dev
->priv
;
602 if (test
->flags
== ETH_TEST_FL_OFFLINE
) {
603 rc
= pcnet32_loopback_test(dev
, data
);
605 if (netif_msg_hw(lp
))
606 printk(KERN_DEBUG
"%s: Loopback test failed.\n",
608 test
->flags
|= ETH_TEST_FL_FAILED
;
609 } else if (netif_msg_hw(lp
))
610 printk(KERN_DEBUG
"%s: Loopback test passed.\n",
612 } else if (netif_msg_hw(lp
))
614 "%s: No tests to run (specify 'Offline' on ethtool).",
616 } /* end pcnet32_ethtool_test */
618 static int pcnet32_loopback_test(struct net_device
*dev
, uint64_t * data1
)
620 struct pcnet32_private
*lp
= dev
->priv
;
621 struct pcnet32_access
*a
= &lp
->a
; /* access to registers */
622 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
623 struct sk_buff
*skb
; /* sk buff */
624 int x
, i
; /* counters */
625 int numbuffs
= 4; /* number of TX/RX buffers and descs */
626 u16 status
= 0x8300; /* TX ring status */
627 u16 teststatus
; /* test of ring status */
628 int rc
; /* return code */
629 int size
; /* size of packets */
630 unsigned char *packet
; /* source packet data */
631 static const int data_len
= 60; /* length of source packets */
635 *data1
= 1; /* status of test, default to fail */
636 rc
= 1; /* default to fail */
638 if (netif_running(dev
))
641 spin_lock_irqsave(&lp
->lock
, flags
);
643 /* Reset the PCNET32 */
646 /* switch pcnet32 to 32bit mode */
647 lp
->a
.write_bcr(ioaddr
, 20, 2);
649 lp
->init_block
.mode
=
650 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
651 lp
->init_block
.filter
[0] = 0;
652 lp
->init_block
.filter
[1] = 0;
654 /* purge & init rings but don't actually restart */
655 pcnet32_restart(dev
, 0x0000);
657 lp
->a
.write_csr(ioaddr
, 0, 0x0004); /* Set STOP bit */
659 /* Initialize Transmit buffers. */
660 size
= data_len
+ 15;
661 for (x
= 0; x
< numbuffs
; x
++) {
662 if (!(skb
= dev_alloc_skb(size
))) {
663 if (netif_msg_hw(lp
))
665 "%s: Cannot allocate skb at line: %d!\n",
666 dev
->name
, __LINE__
);
670 skb_put(skb
, size
); /* create space for data */
671 lp
->tx_skbuff
[x
] = skb
;
672 lp
->tx_ring
[x
].length
= le16_to_cpu(-skb
->len
);
673 lp
->tx_ring
[x
].misc
= 0;
675 /* put DA and SA into the skb */
676 for (i
= 0; i
< 6; i
++)
677 *packet
++ = dev
->dev_addr
[i
];
678 for (i
= 0; i
< 6; i
++)
679 *packet
++ = dev
->dev_addr
[i
];
685 /* fill packet with data */
686 for (i
= 0; i
< data_len
; i
++)
690 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
,
692 lp
->tx_ring
[x
].base
=
693 (u32
) le32_to_cpu(lp
->tx_dma_addr
[x
]);
694 wmb(); /* Make sure owner changes after all others are visible */
695 lp
->tx_ring
[x
].status
= le16_to_cpu(status
);
699 x
= a
->read_bcr(ioaddr
, 32); /* set internal loopback in BSR32 */
701 a
->write_bcr(ioaddr
, 32, x
);
703 lp
->a
.write_csr(ioaddr
, 15, 0x0044); /* set int loopback in CSR15 */
705 teststatus
= le16_to_cpu(0x8000);
706 lp
->a
.write_csr(ioaddr
, 0, 0x0002); /* Set STRT bit */
708 /* Check status of descriptors */
709 for (x
= 0; x
< numbuffs
; x
++) {
712 while ((lp
->rx_ring
[x
].status
& teststatus
) && (ticks
< 200)) {
713 spin_unlock_irqrestore(&lp
->lock
, flags
);
715 spin_lock_irqsave(&lp
->lock
, flags
);
720 if (netif_msg_hw(lp
))
721 printk("%s: Desc %d failed to reset!\n",
727 lp
->a
.write_csr(ioaddr
, 0, 0x0004); /* Set STOP bit */
729 if (netif_msg_hw(lp
) && netif_msg_pktdata(lp
)) {
730 printk(KERN_DEBUG
"%s: RX loopback packets:\n", dev
->name
);
732 for (x
= 0; x
< numbuffs
; x
++) {
733 printk(KERN_DEBUG
"%s: Packet %d:\n", dev
->name
, x
);
734 skb
= lp
->rx_skbuff
[x
];
735 for (i
= 0; i
< size
; i
++) {
736 printk("%02x ", *(skb
->data
+ i
));
744 while (x
< numbuffs
&& !rc
) {
745 skb
= lp
->rx_skbuff
[x
];
746 packet
= lp
->tx_skbuff
[x
]->data
;
747 for (i
= 0; i
< size
; i
++) {
748 if (*(skb
->data
+ i
) != packet
[i
]) {
749 if (netif_msg_hw(lp
))
751 "%s: Error in compare! %2x - %02x %02x\n",
752 dev
->name
, i
, *(skb
->data
+ i
),
765 pcnet32_purge_tx_ring(dev
);
766 x
= a
->read_csr(ioaddr
, 15) & 0xFFFF;
767 a
->write_csr(ioaddr
, 15, (x
& ~0x0044)); /* reset bits 6 and 2 */
769 x
= a
->read_bcr(ioaddr
, 32); /* reset internal loopback */
771 a
->write_bcr(ioaddr
, 32, x
);
773 spin_unlock_irqrestore(&lp
->lock
, flags
);
775 if (netif_running(dev
)) {
778 lp
->a
.write_bcr(ioaddr
, 20, 4); /* return to 16bit mode */
782 } /* end pcnet32_loopback_test */
784 static void pcnet32_led_blink_callback(struct net_device
*dev
)
786 struct pcnet32_private
*lp
= dev
->priv
;
787 struct pcnet32_access
*a
= &lp
->a
;
788 ulong ioaddr
= dev
->base_addr
;
792 spin_lock_irqsave(&lp
->lock
, flags
);
793 for (i
= 4; i
< 8; i
++) {
794 a
->write_bcr(ioaddr
, i
, a
->read_bcr(ioaddr
, i
) ^ 0x4000);
796 spin_unlock_irqrestore(&lp
->lock
, flags
);
798 mod_timer(&lp
->blink_timer
, PCNET32_BLINK_TIMEOUT
);
801 static int pcnet32_phys_id(struct net_device
*dev
, u32 data
)
803 struct pcnet32_private
*lp
= dev
->priv
;
804 struct pcnet32_access
*a
= &lp
->a
;
805 ulong ioaddr
= dev
->base_addr
;
809 if (!lp
->blink_timer
.function
) {
810 init_timer(&lp
->blink_timer
);
811 lp
->blink_timer
.function
= (void *)pcnet32_led_blink_callback
;
812 lp
->blink_timer
.data
= (unsigned long)dev
;
815 /* Save the current value of the bcrs */
816 spin_lock_irqsave(&lp
->lock
, flags
);
817 for (i
= 4; i
< 8; i
++) {
818 regs
[i
- 4] = a
->read_bcr(ioaddr
, i
);
820 spin_unlock_irqrestore(&lp
->lock
, flags
);
822 mod_timer(&lp
->blink_timer
, jiffies
);
823 set_current_state(TASK_INTERRUPTIBLE
);
825 if ((!data
) || (data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
)))
826 data
= (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
);
828 msleep_interruptible(data
* 1000);
829 del_timer_sync(&lp
->blink_timer
);
831 /* Restore the original value of the bcrs */
832 spin_lock_irqsave(&lp
->lock
, flags
);
833 for (i
= 4; i
< 8; i
++) {
834 a
->write_bcr(ioaddr
, i
, regs
[i
- 4]);
836 spin_unlock_irqrestore(&lp
->lock
, flags
);
841 #define PCNET32_REGS_PER_PHY 32
842 #define PCNET32_MAX_PHYS 32
843 static int pcnet32_get_regs_len(struct net_device
*dev
)
845 struct pcnet32_private
*lp
= dev
->priv
;
846 int j
= lp
->phycount
* PCNET32_REGS_PER_PHY
;
848 return ((PCNET32_NUM_REGS
+ j
) * sizeof(u16
));
851 static void pcnet32_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
856 struct pcnet32_private
*lp
= dev
->priv
;
857 struct pcnet32_access
*a
= &lp
->a
;
858 ulong ioaddr
= dev
->base_addr
;
862 spin_lock_irqsave(&lp
->lock
, flags
);
864 csr0
= a
->read_csr(ioaddr
, 0);
865 if (!(csr0
& 0x0004)) { /* If not stopped */
866 /* set SUSPEND (SPND) - CSR5 bit 0 */
867 a
->write_csr(ioaddr
, 5, 0x0001);
869 /* poll waiting for bit to be set */
871 while (!(a
->read_csr(ioaddr
, 5) & 0x0001)) {
872 spin_unlock_irqrestore(&lp
->lock
, flags
);
874 spin_lock_irqsave(&lp
->lock
, flags
);
877 if (netif_msg_hw(lp
))
879 "%s: Error getting into suspend!\n",
886 /* read address PROM */
887 for (i
= 0; i
< 16; i
+= 2)
888 *buff
++ = inw(ioaddr
+ i
);
890 /* read control and status registers */
891 for (i
= 0; i
< 90; i
++) {
892 *buff
++ = a
->read_csr(ioaddr
, i
);
895 *buff
++ = a
->read_csr(ioaddr
, 112);
896 *buff
++ = a
->read_csr(ioaddr
, 114);
898 /* read bus configuration registers */
899 for (i
= 0; i
< 30; i
++) {
900 *buff
++ = a
->read_bcr(ioaddr
, i
);
902 *buff
++ = 0; /* skip bcr30 so as not to hang 79C976 */
903 for (i
= 31; i
< 36; i
++) {
904 *buff
++ = a
->read_bcr(ioaddr
, i
);
907 /* read mii phy registers */
910 for (j
= 0; j
< PCNET32_MAX_PHYS
; j
++) {
911 if (lp
->phymask
& (1 << j
)) {
912 for (i
= 0; i
< PCNET32_REGS_PER_PHY
; i
++) {
913 lp
->a
.write_bcr(ioaddr
, 33,
915 *buff
++ = lp
->a
.read_bcr(ioaddr
, 34);
921 if (!(csr0
& 0x0004)) { /* If not stopped */
922 /* clear SUSPEND (SPND) - CSR5 bit 0 */
923 a
->write_csr(ioaddr
, 5, 0x0000);
926 spin_unlock_irqrestore(&lp
->lock
, flags
);
929 static struct ethtool_ops pcnet32_ethtool_ops
= {
930 .get_settings
= pcnet32_get_settings
,
931 .set_settings
= pcnet32_set_settings
,
932 .get_drvinfo
= pcnet32_get_drvinfo
,
933 .get_msglevel
= pcnet32_get_msglevel
,
934 .set_msglevel
= pcnet32_set_msglevel
,
935 .nway_reset
= pcnet32_nway_reset
,
936 .get_link
= pcnet32_get_link
,
937 .get_ringparam
= pcnet32_get_ringparam
,
938 .set_ringparam
= pcnet32_set_ringparam
,
939 .get_tx_csum
= ethtool_op_get_tx_csum
,
940 .get_sg
= ethtool_op_get_sg
,
941 .get_tso
= ethtool_op_get_tso
,
942 .get_strings
= pcnet32_get_strings
,
943 .self_test_count
= pcnet32_self_test_count
,
944 .self_test
= pcnet32_ethtool_test
,
945 .phys_id
= pcnet32_phys_id
,
946 .get_regs_len
= pcnet32_get_regs_len
,
947 .get_regs
= pcnet32_get_regs
,
948 .get_perm_addr
= ethtool_op_get_perm_addr
,
951 /* only probes for non-PCI devices, the rest are handled by
952 * pci_register_driver via pcnet32_probe_pci */
954 static void __devinit
pcnet32_probe_vlbus(unsigned int *pcnet32_portlist
)
956 unsigned int *port
, ioaddr
;
958 /* search for PCnet32 VLB cards at known addresses */
959 for (port
= pcnet32_portlist
; (ioaddr
= *port
); port
++) {
961 (ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_vlbus")) {
962 /* check if there is really a pcnet chip on that ioaddr */
963 if ((inb(ioaddr
+ 14) == 0x57)
964 && (inb(ioaddr
+ 15) == 0x57)) {
965 pcnet32_probe1(ioaddr
, 0, NULL
);
967 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
974 pcnet32_probe_pci(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
976 unsigned long ioaddr
;
979 err
= pci_enable_device(pdev
);
981 if (pcnet32_debug
& NETIF_MSG_PROBE
)
983 "failed to enable device -- err=%d\n", err
);
986 pci_set_master(pdev
);
988 ioaddr
= pci_resource_start(pdev
, 0);
990 if (pcnet32_debug
& NETIF_MSG_PROBE
)
992 "card has no PCI IO resources, aborting\n");
996 if (!pci_dma_supported(pdev
, PCNET32_DMA_MASK
)) {
997 if (pcnet32_debug
& NETIF_MSG_PROBE
)
999 "architecture does not support 32bit PCI busmaster DMA\n");
1002 if (request_region(ioaddr
, PCNET32_TOTAL_SIZE
, "pcnet32_probe_pci") ==
1004 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1006 "io address range already allocated\n");
1010 err
= pcnet32_probe1(ioaddr
, 1, pdev
);
1012 pci_disable_device(pdev
);
1018 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1019 * pdev will be NULL when called from pcnet32_probe_vlbus.
1021 static int __devinit
1022 pcnet32_probe1(unsigned long ioaddr
, int shared
, struct pci_dev
*pdev
)
1024 struct pcnet32_private
*lp
;
1025 dma_addr_t lp_dma_addr
;
1027 int fdx
, mii
, fset
, dxsuflo
;
1030 struct net_device
*dev
;
1031 struct pcnet32_access
*a
= NULL
;
1035 /* reset the chip */
1036 pcnet32_wio_reset(ioaddr
);
1038 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1039 if (pcnet32_wio_read_csr(ioaddr
, 0) == 4 && pcnet32_wio_check(ioaddr
)) {
1042 pcnet32_dwio_reset(ioaddr
);
1043 if (pcnet32_dwio_read_csr(ioaddr
, 0) == 4
1044 && pcnet32_dwio_check(ioaddr
)) {
1047 goto err_release_region
;
1051 a
->read_csr(ioaddr
, 88) | (a
->read_csr(ioaddr
, 89) << 16);
1052 if ((pcnet32_debug
& NETIF_MSG_PROBE
) && (pcnet32_debug
& NETIF_MSG_HW
))
1053 printk(KERN_INFO
" PCnet chip version is %#x.\n",
1055 if ((chip_version
& 0xfff) != 0x003) {
1056 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1057 printk(KERN_INFO PFX
"Unsupported chip version.\n");
1058 goto err_release_region
;
1061 /* initialize variables */
1062 fdx
= mii
= fset
= dxsuflo
= 0;
1063 chip_version
= (chip_version
>> 12) & 0xffff;
1065 switch (chip_version
) {
1067 chipname
= "PCnet/PCI 79C970"; /* PCI */
1071 chipname
= "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1073 chipname
= "PCnet/32 79C965"; /* 486/VL bus */
1076 chipname
= "PCnet/PCI II 79C970A"; /* PCI */
1080 chipname
= "PCnet/FAST 79C971"; /* PCI */
1086 chipname
= "PCnet/FAST+ 79C972"; /* PCI */
1092 chipname
= "PCnet/FAST III 79C973"; /* PCI */
1097 chipname
= "PCnet/Home 79C978"; /* PCI */
1100 * This is based on specs published at www.amd.com. This section
1101 * assumes that a card with a 79C978 wants to go into standard
1102 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1103 * and the module option homepna=1 can select this instead.
1105 media
= a
->read_bcr(ioaddr
, 49);
1106 media
&= ~3; /* default to 10Mb ethernet */
1107 if (cards_found
< MAX_UNITS
&& homepna
[cards_found
])
1108 media
|= 1; /* switch to home wiring mode */
1109 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1110 printk(KERN_DEBUG PFX
"media set to %sMbit mode.\n",
1111 (media
& 1) ? "1" : "10");
1112 a
->write_bcr(ioaddr
, 49, media
);
1115 chipname
= "PCnet/FAST III 79C975"; /* PCI */
1120 chipname
= "PCnet/PRO 79C976";
1125 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1126 printk(KERN_INFO PFX
1127 "PCnet version %#x, no PCnet32 chip.\n",
1129 goto err_release_region
;
1133 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1134 * starting until the packet is loaded. Strike one for reliability, lose
1135 * one for latency - although on PCI this isnt a big loss. Older chips
1136 * have FIFO's smaller than a packet, so you can't do this.
1137 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1141 a
->write_bcr(ioaddr
, 18, (a
->read_bcr(ioaddr
, 18) | 0x0860));
1142 a
->write_csr(ioaddr
, 80,
1143 (a
->read_csr(ioaddr
, 80) & 0x0C00) | 0x0c00);
1147 dev
= alloc_etherdev(0);
1149 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1150 printk(KERN_ERR PFX
"Memory allocation failed.\n");
1152 goto err_release_region
;
1154 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1156 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1157 printk(KERN_INFO PFX
"%s at %#3lx,", chipname
, ioaddr
);
1159 /* In most chips, after a chip reset, the ethernet address is read from the
1160 * station address PROM at the base address and programmed into the
1161 * "Physical Address Registers" CSR12-14.
1162 * As a precautionary measure, we read the PROM values and complain if
1163 * they disagree with the CSRs. If they miscompare, and the PROM addr
1164 * is valid, then the PROM addr is used.
1166 for (i
= 0; i
< 3; i
++) {
1168 val
= a
->read_csr(ioaddr
, i
+ 12) & 0x0ffff;
1169 /* There may be endianness issues here. */
1170 dev
->dev_addr
[2 * i
] = val
& 0x0ff;
1171 dev
->dev_addr
[2 * i
+ 1] = (val
>> 8) & 0x0ff;
1174 /* read PROM address and compare with CSR address */
1175 for (i
= 0; i
< 6; i
++)
1176 promaddr
[i
] = inb(ioaddr
+ i
);
1178 if (memcmp(promaddr
, dev
->dev_addr
, 6)
1179 || !is_valid_ether_addr(dev
->dev_addr
)) {
1180 if (is_valid_ether_addr(promaddr
)) {
1181 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1182 printk(" warning: CSR address invalid,\n");
1184 " using instead PROM address of");
1186 memcpy(dev
->dev_addr
, promaddr
, 6);
1189 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
1191 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1192 if (!is_valid_ether_addr(dev
->perm_addr
))
1193 memset(dev
->dev_addr
, 0, sizeof(dev
->dev_addr
));
1195 if (pcnet32_debug
& NETIF_MSG_PROBE
) {
1196 for (i
= 0; i
< 6; i
++)
1197 printk(" %2.2x", dev
->dev_addr
[i
]);
1199 /* Version 0x2623 and 0x2624 */
1200 if (((chip_version
+ 1) & 0xfffe) == 0x2624) {
1201 i
= a
->read_csr(ioaddr
, 80) & 0x0C00; /* Check tx_start_pt */
1202 printk("\n" KERN_INFO
" tx_start_pt(0x%04x):", i
);
1205 printk(" 20 bytes,");
1208 printk(" 64 bytes,");
1211 printk(" 128 bytes,");
1214 printk("~220 bytes,");
1217 i
= a
->read_bcr(ioaddr
, 18); /* Check Burst/Bus control */
1218 printk(" BCR18(%x):", i
& 0xffff);
1220 printk("BurstWrEn ");
1222 printk("BurstRdEn ");
1227 i
= a
->read_bcr(ioaddr
, 25);
1228 printk("\n" KERN_INFO
" SRAMSIZE=0x%04x,", i
<< 8);
1229 i
= a
->read_bcr(ioaddr
, 26);
1230 printk(" SRAM_BND=0x%04x,", i
<< 8);
1231 i
= a
->read_bcr(ioaddr
, 27);
1237 dev
->base_addr
= ioaddr
;
1238 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1240 pci_alloc_consistent(pdev
, sizeof(*lp
), &lp_dma_addr
)) == NULL
) {
1241 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1243 "Consistent memory allocation failed.\n");
1245 goto err_free_netdev
;
1248 memset(lp
, 0, sizeof(*lp
));
1249 lp
->dma_addr
= lp_dma_addr
;
1252 spin_lock_init(&lp
->lock
);
1254 SET_MODULE_OWNER(dev
);
1255 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1257 lp
->name
= chipname
;
1258 lp
->shared_irq
= shared
;
1259 lp
->tx_ring_size
= TX_RING_SIZE
; /* default tx ring size */
1260 lp
->rx_ring_size
= RX_RING_SIZE
; /* default rx ring size */
1261 lp
->tx_mod_mask
= lp
->tx_ring_size
- 1;
1262 lp
->rx_mod_mask
= lp
->rx_ring_size
- 1;
1263 lp
->tx_len_bits
= (PCNET32_LOG_TX_BUFFERS
<< 12);
1264 lp
->rx_len_bits
= (PCNET32_LOG_RX_BUFFERS
<< 4);
1265 lp
->mii_if
.full_duplex
= fdx
;
1266 lp
->mii_if
.phy_id_mask
= 0x1f;
1267 lp
->mii_if
.reg_num_mask
= 0x1f;
1268 lp
->dxsuflo
= dxsuflo
;
1270 lp
->msg_enable
= pcnet32_debug
;
1271 if ((cards_found
>= MAX_UNITS
)
1272 || (options
[cards_found
] > sizeof(options_mapping
)))
1273 lp
->options
= PCNET32_PORT_ASEL
;
1275 lp
->options
= options_mapping
[options
[cards_found
]];
1276 lp
->mii_if
.dev
= dev
;
1277 lp
->mii_if
.mdio_read
= mdio_read
;
1278 lp
->mii_if
.mdio_write
= mdio_write
;
1280 if (fdx
&& !(lp
->options
& PCNET32_PORT_ASEL
) &&
1281 ((cards_found
>= MAX_UNITS
) || full_duplex
[cards_found
]))
1282 lp
->options
|= PCNET32_PORT_FD
;
1285 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1286 printk(KERN_ERR PFX
"No access methods\n");
1288 goto err_free_consistent
;
1292 /* prior to register_netdev, dev->name is not yet correct */
1293 if (pcnet32_alloc_ring(dev
, pci_name(lp
->pci_dev
))) {
1297 /* detect special T1/E1 WAN card by checking for MAC address */
1298 if (dev
->dev_addr
[0] == 0x00 && dev
->dev_addr
[1] == 0xe0
1299 && dev
->dev_addr
[2] == 0x75)
1300 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_GPSI
;
1302 lp
->init_block
.mode
= le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1303 lp
->init_block
.tlen_rlen
=
1304 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1305 for (i
= 0; i
< 6; i
++)
1306 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
1307 lp
->init_block
.filter
[0] = 0x00000000;
1308 lp
->init_block
.filter
[1] = 0x00000000;
1309 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1310 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1312 /* switch pcnet32 to 32bit mode */
1313 a
->write_bcr(ioaddr
, 20, 2);
1315 a
->write_csr(ioaddr
, 1, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1316 init_block
)) & 0xffff);
1317 a
->write_csr(ioaddr
, 2, (lp
->dma_addr
+ offsetof(struct pcnet32_private
,
1318 init_block
)) >> 16);
1320 if (pdev
) { /* use the IRQ provided by PCI */
1321 dev
->irq
= pdev
->irq
;
1322 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1323 printk(" assigned IRQ %d.\n", dev
->irq
);
1325 unsigned long irq_mask
= probe_irq_on();
1328 * To auto-IRQ we enable the initialization-done and DMA error
1329 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1332 /* Trigger an initialization just for the interrupt. */
1333 a
->write_csr(ioaddr
, 0, 0x41);
1336 dev
->irq
= probe_irq_off(irq_mask
);
1338 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1339 printk(", failed to detect IRQ line.\n");
1343 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1344 printk(", probed IRQ %d.\n", dev
->irq
);
1347 /* Set the mii phy_id so that we can query the link state */
1349 /* lp->phycount and lp->phymask are set to 0 by memset above */
1351 lp
->mii_if
.phy_id
= ((lp
->a
.read_bcr(ioaddr
, 33)) >> 5) & 0x1f;
1353 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1354 unsigned short id1
, id2
;
1356 id1
= mdio_read(dev
, i
, MII_PHYSID1
);
1359 id2
= mdio_read(dev
, i
, MII_PHYSID2
);
1362 if (i
== 31 && ((chip_version
+ 1) & 0xfffe) == 0x2624)
1363 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1365 lp
->phymask
|= (1 << i
);
1366 lp
->mii_if
.phy_id
= i
;
1367 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1368 printk(KERN_INFO PFX
1369 "Found PHY %04x:%04x at address %d.\n",
1372 lp
->a
.write_bcr(ioaddr
, 33, (lp
->mii_if
.phy_id
) << 5);
1373 if (lp
->phycount
> 1) {
1374 lp
->options
|= PCNET32_PORT_MII
;
1378 init_timer(&lp
->watchdog_timer
);
1379 lp
->watchdog_timer
.data
= (unsigned long)dev
;
1380 lp
->watchdog_timer
.function
= (void *)&pcnet32_watchdog
;
1382 /* The PCNET32-specific entries in the device structure. */
1383 dev
->open
= &pcnet32_open
;
1384 dev
->hard_start_xmit
= &pcnet32_start_xmit
;
1385 dev
->stop
= &pcnet32_close
;
1386 dev
->get_stats
= &pcnet32_get_stats
;
1387 dev
->set_multicast_list
= &pcnet32_set_multicast_list
;
1388 dev
->do_ioctl
= &pcnet32_ioctl
;
1389 dev
->ethtool_ops
= &pcnet32_ethtool_ops
;
1390 dev
->tx_timeout
= pcnet32_tx_timeout
;
1391 dev
->watchdog_timeo
= (5 * HZ
);
1393 #ifdef CONFIG_NET_POLL_CONTROLLER
1394 dev
->poll_controller
= pcnet32_poll_controller
;
1397 /* Fill in the generic fields of the device structure. */
1398 if (register_netdev(dev
))
1402 pci_set_drvdata(pdev
, dev
);
1404 lp
->next
= pcnet32_dev
;
1408 if (pcnet32_debug
& NETIF_MSG_PROBE
)
1409 printk(KERN_INFO
"%s: registered as %s\n", dev
->name
, lp
->name
);
1412 /* enable LED writes */
1413 a
->write_bcr(ioaddr
, 2, a
->read_bcr(ioaddr
, 2) | 0x1000);
1418 pcnet32_free_ring(dev
);
1419 err_free_consistent
:
1420 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
1424 release_region(ioaddr
, PCNET32_TOTAL_SIZE
);
1428 /* if any allocation fails, caller must also call pcnet32_free_ring */
1429 static int pcnet32_alloc_ring(struct net_device
*dev
, char *name
)
1431 struct pcnet32_private
*lp
= dev
->priv
;
1433 lp
->tx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1434 sizeof(struct pcnet32_tx_head
) *
1436 &lp
->tx_ring_dma_addr
);
1437 if (lp
->tx_ring
== NULL
) {
1438 if (pcnet32_debug
& NETIF_MSG_DRV
)
1439 printk("\n" KERN_ERR PFX
1440 "%s: Consistent memory allocation failed.\n",
1445 lp
->rx_ring
= pci_alloc_consistent(lp
->pci_dev
,
1446 sizeof(struct pcnet32_rx_head
) *
1448 &lp
->rx_ring_dma_addr
);
1449 if (lp
->rx_ring
== NULL
) {
1450 if (pcnet32_debug
& NETIF_MSG_DRV
)
1451 printk("\n" KERN_ERR PFX
1452 "%s: Consistent memory allocation failed.\n",
1457 lp
->tx_dma_addr
= kmalloc(sizeof(dma_addr_t
) * lp
->tx_ring_size
,
1459 if (!lp
->tx_dma_addr
) {
1460 if (pcnet32_debug
& NETIF_MSG_DRV
)
1461 printk("\n" KERN_ERR PFX
1462 "%s: Memory allocation failed.\n", name
);
1465 memset(lp
->tx_dma_addr
, 0, sizeof(dma_addr_t
) * lp
->tx_ring_size
);
1467 lp
->rx_dma_addr
= kmalloc(sizeof(dma_addr_t
) * lp
->rx_ring_size
,
1469 if (!lp
->rx_dma_addr
) {
1470 if (pcnet32_debug
& NETIF_MSG_DRV
)
1471 printk("\n" KERN_ERR PFX
1472 "%s: Memory allocation failed.\n", name
);
1475 memset(lp
->rx_dma_addr
, 0, sizeof(dma_addr_t
) * lp
->rx_ring_size
);
1477 lp
->tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * lp
->tx_ring_size
,
1479 if (!lp
->tx_skbuff
) {
1480 if (pcnet32_debug
& NETIF_MSG_DRV
)
1481 printk("\n" KERN_ERR PFX
1482 "%s: Memory allocation failed.\n", name
);
1485 memset(lp
->tx_skbuff
, 0, sizeof(struct sk_buff
*) * lp
->tx_ring_size
);
1487 lp
->rx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * lp
->rx_ring_size
,
1489 if (!lp
->rx_skbuff
) {
1490 if (pcnet32_debug
& NETIF_MSG_DRV
)
1491 printk("\n" KERN_ERR PFX
1492 "%s: Memory allocation failed.\n", name
);
1495 memset(lp
->rx_skbuff
, 0, sizeof(struct sk_buff
*) * lp
->rx_ring_size
);
1500 static void pcnet32_free_ring(struct net_device
*dev
)
1502 struct pcnet32_private
*lp
= dev
->priv
;
1504 kfree(lp
->tx_skbuff
);
1505 lp
->tx_skbuff
= NULL
;
1507 kfree(lp
->rx_skbuff
);
1508 lp
->rx_skbuff
= NULL
;
1510 kfree(lp
->tx_dma_addr
);
1511 lp
->tx_dma_addr
= NULL
;
1513 kfree(lp
->rx_dma_addr
);
1514 lp
->rx_dma_addr
= NULL
;
1517 pci_free_consistent(lp
->pci_dev
,
1518 sizeof(struct pcnet32_tx_head
) *
1519 lp
->tx_ring_size
, lp
->tx_ring
,
1520 lp
->tx_ring_dma_addr
);
1525 pci_free_consistent(lp
->pci_dev
,
1526 sizeof(struct pcnet32_rx_head
) *
1527 lp
->rx_ring_size
, lp
->rx_ring
,
1528 lp
->rx_ring_dma_addr
);
1533 static int pcnet32_open(struct net_device
*dev
)
1535 struct pcnet32_private
*lp
= dev
->priv
;
1536 unsigned long ioaddr
= dev
->base_addr
;
1540 unsigned long flags
;
1542 if (request_irq(dev
->irq
, &pcnet32_interrupt
,
1543 lp
->shared_irq
? IRQF_SHARED
: 0, dev
->name
,
1548 spin_lock_irqsave(&lp
->lock
, flags
);
1549 /* Check for a valid station address */
1550 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1555 /* Reset the PCNET32 */
1556 lp
->a
.reset(ioaddr
);
1558 /* switch pcnet32 to 32bit mode */
1559 lp
->a
.write_bcr(ioaddr
, 20, 2);
1561 if (netif_msg_ifup(lp
))
1563 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1564 dev
->name
, dev
->irq
, (u32
) (lp
->tx_ring_dma_addr
),
1565 (u32
) (lp
->rx_ring_dma_addr
),
1566 (u32
) (lp
->dma_addr
+
1567 offsetof(struct pcnet32_private
, init_block
)));
1569 /* set/reset autoselect bit */
1570 val
= lp
->a
.read_bcr(ioaddr
, 2) & ~2;
1571 if (lp
->options
& PCNET32_PORT_ASEL
)
1573 lp
->a
.write_bcr(ioaddr
, 2, val
);
1575 /* handle full duplex setting */
1576 if (lp
->mii_if
.full_duplex
) {
1577 val
= lp
->a
.read_bcr(ioaddr
, 9) & ~3;
1578 if (lp
->options
& PCNET32_PORT_FD
) {
1580 if (lp
->options
== (PCNET32_PORT_FD
| PCNET32_PORT_AUI
))
1582 } else if (lp
->options
& PCNET32_PORT_ASEL
) {
1583 /* workaround of xSeries250, turn on for 79C975 only */
1584 i
= ((lp
->a
.read_csr(ioaddr
, 88) |
1586 read_csr(ioaddr
, 89) << 16)) >> 12) & 0xffff;
1590 lp
->a
.write_bcr(ioaddr
, 9, val
);
1593 /* set/reset GPSI bit in test register */
1594 val
= lp
->a
.read_csr(ioaddr
, 124) & ~0x10;
1595 if ((lp
->options
& PCNET32_PORT_PORTSEL
) == PCNET32_PORT_GPSI
)
1597 lp
->a
.write_csr(ioaddr
, 124, val
);
1599 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1600 if (lp
->pci_dev
->subsystem_vendor
== PCI_VENDOR_ID_AT
&&
1601 (lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2700FX
||
1602 lp
->pci_dev
->subsystem_device
== PCI_SUBDEVICE_ID_AT_2701FX
)) {
1603 if (lp
->options
& PCNET32_PORT_ASEL
) {
1604 lp
->options
= PCNET32_PORT_FD
| PCNET32_PORT_100
;
1605 if (netif_msg_link(lp
))
1607 "%s: Setting 100Mb-Full Duplex.\n",
1611 if (lp
->phycount
< 2) {
1613 * 24 Jun 2004 according AMD, in order to change the PHY,
1614 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1615 * duplex, and/or enable auto negotiation, and clear DANAS
1617 if (lp
->mii
&& !(lp
->options
& PCNET32_PORT_ASEL
)) {
1618 lp
->a
.write_bcr(ioaddr
, 32,
1619 lp
->a
.read_bcr(ioaddr
, 32) | 0x0080);
1620 /* disable Auto Negotiation, set 10Mpbs, HD */
1621 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0xb8;
1622 if (lp
->options
& PCNET32_PORT_FD
)
1624 if (lp
->options
& PCNET32_PORT_100
)
1626 lp
->a
.write_bcr(ioaddr
, 32, val
);
1628 if (lp
->options
& PCNET32_PORT_ASEL
) {
1629 lp
->a
.write_bcr(ioaddr
, 32,
1630 lp
->a
.read_bcr(ioaddr
,
1632 /* enable auto negotiate, setup, disable fd */
1633 val
= lp
->a
.read_bcr(ioaddr
, 32) & ~0x98;
1635 lp
->a
.write_bcr(ioaddr
, 32, val
);
1642 struct ethtool_cmd ecmd
;
1645 * There is really no good other way to handle multiple PHYs
1646 * other than turning off all automatics
1648 val
= lp
->a
.read_bcr(ioaddr
, 2);
1649 lp
->a
.write_bcr(ioaddr
, 2, val
& ~2);
1650 val
= lp
->a
.read_bcr(ioaddr
, 32);
1651 lp
->a
.write_bcr(ioaddr
, 32, val
& ~(1 << 7)); /* stop MII manager */
1653 if (!(lp
->options
& PCNET32_PORT_ASEL
)) {
1655 ecmd
.port
= PORT_MII
;
1656 ecmd
.transceiver
= XCVR_INTERNAL
;
1657 ecmd
.autoneg
= AUTONEG_DISABLE
;
1660 options
& PCNET32_PORT_100
? SPEED_100
: SPEED_10
;
1661 bcr9
= lp
->a
.read_bcr(ioaddr
, 9);
1663 if (lp
->options
& PCNET32_PORT_FD
) {
1664 ecmd
.duplex
= DUPLEX_FULL
;
1667 ecmd
.duplex
= DUPLEX_HALF
;
1670 lp
->a
.write_bcr(ioaddr
, 9, bcr9
);
1673 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
1674 if (lp
->phymask
& (1 << i
)) {
1675 /* isolate all but the first PHY */
1676 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
1677 if (first_phy
== -1) {
1679 mdio_write(dev
, i
, MII_BMCR
,
1680 bmcr
& ~BMCR_ISOLATE
);
1682 mdio_write(dev
, i
, MII_BMCR
,
1683 bmcr
| BMCR_ISOLATE
);
1685 /* use mii_ethtool_sset to setup PHY */
1686 lp
->mii_if
.phy_id
= i
;
1687 ecmd
.phy_address
= i
;
1688 if (lp
->options
& PCNET32_PORT_ASEL
) {
1689 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
1690 ecmd
.autoneg
= AUTONEG_ENABLE
;
1692 mii_ethtool_sset(&lp
->mii_if
, &ecmd
);
1695 lp
->mii_if
.phy_id
= first_phy
;
1696 if (netif_msg_link(lp
))
1697 printk(KERN_INFO
"%s: Using PHY number %d.\n",
1698 dev
->name
, first_phy
);
1702 if (lp
->dxsuflo
) { /* Disable transmit stop on underflow */
1703 val
= lp
->a
.read_csr(ioaddr
, 3);
1705 lp
->a
.write_csr(ioaddr
, 3, val
);
1709 lp
->init_block
.mode
=
1710 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
1711 pcnet32_load_multicast(dev
);
1713 if (pcnet32_init_ring(dev
)) {
1718 /* Re-initialize the PCNET32, and start it when done. */
1719 lp
->a
.write_csr(ioaddr
, 1, (lp
->dma_addr
+
1720 offsetof(struct pcnet32_private
,
1721 init_block
)) & 0xffff);
1722 lp
->a
.write_csr(ioaddr
, 2,
1724 offsetof(struct pcnet32_private
, init_block
)) >> 16);
1726 lp
->a
.write_csr(ioaddr
, 4, 0x0915);
1727 lp
->a
.write_csr(ioaddr
, 0, 0x0001);
1729 netif_start_queue(dev
);
1731 /* Print the link status and start the watchdog */
1732 pcnet32_check_media(dev
, 1);
1733 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
1737 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0100)
1740 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1741 * reports that doing so triggers a bug in the '974.
1743 lp
->a
.write_csr(ioaddr
, 0, 0x0042);
1745 if (netif_msg_ifup(lp
))
1747 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1749 (u32
) (lp
->dma_addr
+
1750 offsetof(struct pcnet32_private
, init_block
)),
1751 lp
->a
.read_csr(ioaddr
, 0));
1753 spin_unlock_irqrestore(&lp
->lock
, flags
);
1755 return 0; /* Always succeed */
1758 /* free any allocated skbuffs */
1759 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
1760 lp
->rx_ring
[i
].status
= 0;
1761 if (lp
->rx_skbuff
[i
]) {
1762 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
1763 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
1764 dev_kfree_skb(lp
->rx_skbuff
[i
]);
1766 lp
->rx_skbuff
[i
] = NULL
;
1767 lp
->rx_dma_addr
[i
] = 0;
1771 * Switch back to 16bit mode to avoid problems with dumb
1772 * DOS packet driver after a warm reboot
1774 lp
->a
.write_bcr(ioaddr
, 20, 4);
1777 spin_unlock_irqrestore(&lp
->lock
, flags
);
1778 free_irq(dev
->irq
, dev
);
1783 * The LANCE has been halted for one reason or another (busmaster memory
1784 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1785 * etc.). Modern LANCE variants always reload their ring-buffer
1786 * configuration when restarted, so we must reinitialize our ring
1787 * context before restarting. As part of this reinitialization,
1788 * find all packets still on the Tx ring and pretend that they had been
1789 * sent (in effect, drop the packets on the floor) - the higher-level
1790 * protocols will time out and retransmit. It'd be better to shuffle
1791 * these skbs to a temp list and then actually re-Tx them after
1792 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1795 static void pcnet32_purge_tx_ring(struct net_device
*dev
)
1797 struct pcnet32_private
*lp
= dev
->priv
;
1800 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
1801 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
1802 wmb(); /* Make sure adapter sees owner change */
1803 if (lp
->tx_skbuff
[i
]) {
1804 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
1805 lp
->tx_skbuff
[i
]->len
,
1807 dev_kfree_skb_any(lp
->tx_skbuff
[i
]);
1809 lp
->tx_skbuff
[i
] = NULL
;
1810 lp
->tx_dma_addr
[i
] = 0;
1814 /* Initialize the PCNET32 Rx and Tx rings. */
1815 static int pcnet32_init_ring(struct net_device
*dev
)
1817 struct pcnet32_private
*lp
= dev
->priv
;
1821 lp
->cur_rx
= lp
->cur_tx
= 0;
1822 lp
->dirty_rx
= lp
->dirty_tx
= 0;
1824 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
1825 struct sk_buff
*rx_skbuff
= lp
->rx_skbuff
[i
];
1826 if (rx_skbuff
== NULL
) {
1828 (rx_skbuff
= lp
->rx_skbuff
[i
] =
1829 dev_alloc_skb(PKT_BUF_SZ
))) {
1830 /* there is not much, we can do at this point */
1831 if (pcnet32_debug
& NETIF_MSG_DRV
)
1833 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1837 skb_reserve(rx_skbuff
, 2);
1841 if (lp
->rx_dma_addr
[i
] == 0)
1842 lp
->rx_dma_addr
[i
] =
1843 pci_map_single(lp
->pci_dev
, rx_skbuff
->data
,
1844 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
1845 lp
->rx_ring
[i
].base
= (u32
) le32_to_cpu(lp
->rx_dma_addr
[i
]);
1846 lp
->rx_ring
[i
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
1847 wmb(); /* Make sure owner changes after all others are visible */
1848 lp
->rx_ring
[i
].status
= le16_to_cpu(0x8000);
1850 /* The Tx buffer address is filled in as needed, but we do need to clear
1851 * the upper ownership bit. */
1852 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
1853 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
1854 wmb(); /* Make sure adapter sees owner change */
1855 lp
->tx_ring
[i
].base
= 0;
1856 lp
->tx_dma_addr
[i
] = 0;
1859 lp
->init_block
.tlen_rlen
=
1860 le16_to_cpu(lp
->tx_len_bits
| lp
->rx_len_bits
);
1861 for (i
= 0; i
< 6; i
++)
1862 lp
->init_block
.phys_addr
[i
] = dev
->dev_addr
[i
];
1863 lp
->init_block
.rx_ring
= (u32
) le32_to_cpu(lp
->rx_ring_dma_addr
);
1864 lp
->init_block
.tx_ring
= (u32
) le32_to_cpu(lp
->tx_ring_dma_addr
);
1865 wmb(); /* Make sure all changes are visible */
1869 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1870 * then flush the pending transmit operations, re-initialize the ring,
1871 * and tell the chip to initialize.
1873 static void pcnet32_restart(struct net_device
*dev
, unsigned int csr0_bits
)
1875 struct pcnet32_private
*lp
= dev
->priv
;
1876 unsigned long ioaddr
= dev
->base_addr
;
1880 for (i
= 0; i
< 100; i
++)
1881 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0004)
1884 if (i
>= 100 && netif_msg_drv(lp
))
1886 "%s: pcnet32_restart timed out waiting for stop.\n",
1889 pcnet32_purge_tx_ring(dev
);
1890 if (pcnet32_init_ring(dev
))
1894 lp
->a
.write_csr(ioaddr
, 0, 1);
1897 if (lp
->a
.read_csr(ioaddr
, 0) & 0x0100)
1900 lp
->a
.write_csr(ioaddr
, 0, csr0_bits
);
1903 static void pcnet32_tx_timeout(struct net_device
*dev
)
1905 struct pcnet32_private
*lp
= dev
->priv
;
1906 unsigned long ioaddr
= dev
->base_addr
, flags
;
1908 spin_lock_irqsave(&lp
->lock
, flags
);
1909 /* Transmitter timeout, serious problems. */
1910 if (pcnet32_debug
& NETIF_MSG_DRV
)
1912 "%s: transmit timed out, status %4.4x, resetting.\n",
1913 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
1914 lp
->a
.write_csr(ioaddr
, 0, 0x0004);
1915 lp
->stats
.tx_errors
++;
1916 if (netif_msg_tx_err(lp
)) {
1919 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1920 lp
->dirty_tx
, lp
->cur_tx
, lp
->tx_full
? " (full)" : "",
1922 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
1923 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
1924 le32_to_cpu(lp
->rx_ring
[i
].base
),
1925 (-le16_to_cpu(lp
->rx_ring
[i
].buf_length
)) &
1926 0xffff, le32_to_cpu(lp
->rx_ring
[i
].msg_length
),
1927 le16_to_cpu(lp
->rx_ring
[i
].status
));
1928 for (i
= 0; i
< lp
->tx_ring_size
; i
++)
1929 printk("%s %08x %04x %08x %04x", i
& 1 ? "" : "\n ",
1930 le32_to_cpu(lp
->tx_ring
[i
].base
),
1931 (-le16_to_cpu(lp
->tx_ring
[i
].length
)) & 0xffff,
1932 le32_to_cpu(lp
->tx_ring
[i
].misc
),
1933 le16_to_cpu(lp
->tx_ring
[i
].status
));
1936 pcnet32_restart(dev
, 0x0042);
1938 dev
->trans_start
= jiffies
;
1939 netif_wake_queue(dev
);
1941 spin_unlock_irqrestore(&lp
->lock
, flags
);
1944 static int pcnet32_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1946 struct pcnet32_private
*lp
= dev
->priv
;
1947 unsigned long ioaddr
= dev
->base_addr
;
1950 unsigned long flags
;
1952 spin_lock_irqsave(&lp
->lock
, flags
);
1954 if (netif_msg_tx_queued(lp
)) {
1956 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1957 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
1960 /* Default status -- will not enable Successful-TxDone
1961 * interrupt when that option is available to us.
1965 /* Fill in a Tx ring entry */
1967 /* Mask to ring buffer boundary. */
1968 entry
= lp
->cur_tx
& lp
->tx_mod_mask
;
1970 /* Caution: the write order is important here, set the status
1971 * with the "ownership" bits last. */
1973 lp
->tx_ring
[entry
].length
= le16_to_cpu(-skb
->len
);
1975 lp
->tx_ring
[entry
].misc
= 0x00000000;
1977 lp
->tx_skbuff
[entry
] = skb
;
1978 lp
->tx_dma_addr
[entry
] =
1979 pci_map_single(lp
->pci_dev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
1980 lp
->tx_ring
[entry
].base
= (u32
) le32_to_cpu(lp
->tx_dma_addr
[entry
]);
1981 wmb(); /* Make sure owner changes after all others are visible */
1982 lp
->tx_ring
[entry
].status
= le16_to_cpu(status
);
1985 lp
->stats
.tx_bytes
+= skb
->len
;
1987 /* Trigger an immediate send poll. */
1988 lp
->a
.write_csr(ioaddr
, 0, 0x0048);
1990 dev
->trans_start
= jiffies
;
1992 if (lp
->tx_ring
[(entry
+ 1) & lp
->tx_mod_mask
].base
!= 0) {
1994 netif_stop_queue(dev
);
1996 spin_unlock_irqrestore(&lp
->lock
, flags
);
2000 /* The PCNET32 interrupt handler. */
2002 pcnet32_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2004 struct net_device
*dev
= dev_id
;
2005 struct pcnet32_private
*lp
;
2006 unsigned long ioaddr
;
2008 int boguscnt
= max_interrupt_work
;
2012 if (pcnet32_debug
& NETIF_MSG_INTR
)
2013 printk(KERN_DEBUG
"%s(): irq %d for unknown device\n",
2018 ioaddr
= dev
->base_addr
;
2021 spin_lock(&lp
->lock
);
2023 rap
= lp
->a
.read_rap(ioaddr
);
2024 while ((csr0
= lp
->a
.read_csr(ioaddr
, 0)) & 0x8f00 && --boguscnt
>= 0) {
2025 if (csr0
== 0xffff) {
2026 break; /* PCMCIA remove happened */
2028 /* Acknowledge all of the current interrupt sources ASAP. */
2029 lp
->a
.write_csr(ioaddr
, 0, csr0
& ~0x004f);
2033 if (netif_msg_intr(lp
))
2035 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2036 dev
->name
, csr0
, lp
->a
.read_csr(ioaddr
, 0));
2038 if (csr0
& 0x0400) /* Rx interrupt */
2041 if (csr0
& 0x0200) { /* Tx-done interrupt */
2042 unsigned int dirty_tx
= lp
->dirty_tx
;
2045 while (dirty_tx
!= lp
->cur_tx
) {
2046 int entry
= dirty_tx
& lp
->tx_mod_mask
;
2048 (short)le16_to_cpu(lp
->tx_ring
[entry
].
2052 break; /* It still hasn't been Txed */
2054 lp
->tx_ring
[entry
].base
= 0;
2056 if (status
& 0x4000) {
2057 /* There was an major error, log it. */
2059 le32_to_cpu(lp
->tx_ring
[entry
].
2061 lp
->stats
.tx_errors
++;
2062 if (netif_msg_tx_err(lp
))
2064 "%s: Tx error status=%04x err_status=%08x\n",
2067 if (err_status
& 0x04000000)
2068 lp
->stats
.tx_aborted_errors
++;
2069 if (err_status
& 0x08000000)
2070 lp
->stats
.tx_carrier_errors
++;
2071 if (err_status
& 0x10000000)
2072 lp
->stats
.tx_window_errors
++;
2074 if (err_status
& 0x40000000) {
2075 lp
->stats
.tx_fifo_errors
++;
2076 /* Ackk! On FIFO errors the Tx unit is turned off! */
2077 /* Remove this verbosity later! */
2078 if (netif_msg_tx_err(lp
))
2080 "%s: Tx FIFO error! CSR0=%4.4x\n",
2085 if (err_status
& 0x40000000) {
2086 lp
->stats
.tx_fifo_errors
++;
2087 if (!lp
->dxsuflo
) { /* If controller doesn't recover ... */
2088 /* Ackk! On FIFO errors the Tx unit is turned off! */
2089 /* Remove this verbosity later! */
2090 if (netif_msg_tx_err
2093 "%s: Tx FIFO error! CSR0=%4.4x\n",
2102 if (status
& 0x1800)
2103 lp
->stats
.collisions
++;
2104 lp
->stats
.tx_packets
++;
2107 /* We must free the original skb */
2108 if (lp
->tx_skbuff
[entry
]) {
2109 pci_unmap_single(lp
->pci_dev
,
2110 lp
->tx_dma_addr
[entry
],
2111 lp
->tx_skbuff
[entry
]->
2112 len
, PCI_DMA_TODEVICE
);
2113 dev_kfree_skb_irq(lp
->tx_skbuff
[entry
]);
2114 lp
->tx_skbuff
[entry
] = NULL
;
2115 lp
->tx_dma_addr
[entry
] = 0;
2121 (lp
->cur_tx
- dirty_tx
) & (lp
->tx_mod_mask
+
2123 if (delta
> lp
->tx_ring_size
) {
2124 if (netif_msg_drv(lp
))
2126 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2127 dev
->name
, dirty_tx
, lp
->cur_tx
,
2129 dirty_tx
+= lp
->tx_ring_size
;
2130 delta
-= lp
->tx_ring_size
;
2134 netif_queue_stopped(dev
) &&
2135 delta
< lp
->tx_ring_size
- 2) {
2136 /* The ring is no longer full, clear tbusy. */
2138 netif_wake_queue(dev
);
2140 lp
->dirty_tx
= dirty_tx
;
2143 /* Log misc errors. */
2145 lp
->stats
.tx_errors
++; /* Tx babble. */
2146 if (csr0
& 0x1000) {
2148 * this happens when our receive ring is full. This shouldn't
2149 * be a problem as we will see normal rx interrupts for the frames
2150 * in the receive ring. But there are some PCI chipsets (I can
2151 * reproduce this on SP3G with Intel saturn chipset) which have
2152 * sometimes problems and will fill up the receive ring with
2153 * error descriptors. In this situation we don't get a rx
2154 * interrupt, but a missed frame interrupt sooner or later.
2155 * So we try to clean up our receive ring here.
2158 lp
->stats
.rx_errors
++; /* Missed a Rx frame. */
2160 if (csr0
& 0x0800) {
2161 if (netif_msg_drv(lp
))
2163 "%s: Bus master arbitration failure, status %4.4x.\n",
2165 /* unlike for the lance, there is no restart needed */
2169 /* reset the chip to clear the error condition, then restart */
2170 lp
->a
.reset(ioaddr
);
2171 lp
->a
.write_csr(ioaddr
, 4, 0x0915);
2172 pcnet32_restart(dev
, 0x0002);
2173 netif_wake_queue(dev
);
2177 /* Set interrupt enable. */
2178 lp
->a
.write_csr(ioaddr
, 0, 0x0040);
2179 lp
->a
.write_rap(ioaddr
, rap
);
2181 if (netif_msg_intr(lp
))
2182 printk(KERN_DEBUG
"%s: exiting interrupt, csr0=%#4.4x.\n",
2183 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2185 spin_unlock(&lp
->lock
);
2190 static int pcnet32_rx(struct net_device
*dev
)
2192 struct pcnet32_private
*lp
= dev
->priv
;
2193 int entry
= lp
->cur_rx
& lp
->rx_mod_mask
;
2194 int boguscnt
= lp
->rx_ring_size
/ 2;
2196 /* If we own the next entry, it's a new packet. Send it up. */
2197 while ((short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >= 0) {
2198 int status
= (short)le16_to_cpu(lp
->rx_ring
[entry
].status
) >> 8;
2200 if (status
!= 0x03) { /* There was an error. */
2202 * There is a tricky error noted by John Murphy,
2203 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2204 * buffers it's possible for a jabber packet to use two
2205 * buffers, with only the last correctly noting the error.
2207 if (status
& 0x01) /* Only count a general error at the */
2208 lp
->stats
.rx_errors
++; /* end of a packet. */
2210 lp
->stats
.rx_frame_errors
++;
2212 lp
->stats
.rx_over_errors
++;
2214 lp
->stats
.rx_crc_errors
++;
2216 lp
->stats
.rx_fifo_errors
++;
2217 lp
->rx_ring
[entry
].status
&= le16_to_cpu(0x03ff);
2219 /* Malloc up new buffer, compatible with net-2e. */
2221 (le32_to_cpu(lp
->rx_ring
[entry
].msg_length
) & 0xfff)
2223 struct sk_buff
*skb
;
2225 /* Discard oversize frames. */
2226 if (unlikely(pkt_len
> PKT_BUF_SZ
- 2)) {
2227 if (netif_msg_drv(lp
))
2229 "%s: Impossible packet size %d!\n",
2230 dev
->name
, pkt_len
);
2231 lp
->stats
.rx_errors
++;
2232 } else if (pkt_len
< 60) {
2233 if (netif_msg_rx_err(lp
))
2234 printk(KERN_ERR
"%s: Runt packet!\n",
2236 lp
->stats
.rx_errors
++;
2238 int rx_in_place
= 0;
2240 if (pkt_len
> rx_copybreak
) {
2241 struct sk_buff
*newskb
;
2244 dev_alloc_skb(PKT_BUF_SZ
))) {
2245 skb_reserve(newskb
, 2);
2246 skb
= lp
->rx_skbuff
[entry
];
2247 pci_unmap_single(lp
->pci_dev
,
2252 PCI_DMA_FROMDEVICE
);
2253 skb_put(skb
, pkt_len
);
2254 lp
->rx_skbuff
[entry
] = newskb
;
2256 lp
->rx_dma_addr
[entry
] =
2257 pci_map_single(lp
->pci_dev
,
2261 PCI_DMA_FROMDEVICE
);
2262 lp
->rx_ring
[entry
].base
=
2270 skb
= dev_alloc_skb(pkt_len
+ 2);
2275 if (netif_msg_drv(lp
))
2277 "%s: Memory squeeze, deferring packet.\n",
2279 for (i
= 0; i
< lp
->rx_ring_size
; i
++)
2289 if (i
> lp
->rx_ring_size
- 2) {
2290 lp
->stats
.rx_dropped
++;
2291 lp
->rx_ring
[entry
].status
|=
2292 le16_to_cpu(0x8000);
2293 wmb(); /* Make sure adapter sees owner change */
2300 skb_reserve(skb
, 2); /* 16 byte align */
2301 skb_put(skb
, pkt_len
); /* Make room */
2302 pci_dma_sync_single_for_cpu(lp
->pci_dev
,
2308 PCI_DMA_FROMDEVICE
);
2309 eth_copy_and_sum(skb
,
2310 (unsigned char *)(lp
->
2315 pci_dma_sync_single_for_device(lp
->
2322 PCI_DMA_FROMDEVICE
);
2324 lp
->stats
.rx_bytes
+= skb
->len
;
2325 skb
->protocol
= eth_type_trans(skb
, dev
);
2327 dev
->last_rx
= jiffies
;
2328 lp
->stats
.rx_packets
++;
2332 * The docs say that the buffer length isn't touched, but Andrew Boyd
2333 * of QNX reports that some revs of the 79C965 clear it.
2335 lp
->rx_ring
[entry
].buf_length
= le16_to_cpu(2 - PKT_BUF_SZ
);
2336 wmb(); /* Make sure owner changes after all others are visible */
2337 lp
->rx_ring
[entry
].status
|= le16_to_cpu(0x8000);
2338 entry
= (++lp
->cur_rx
) & lp
->rx_mod_mask
;
2339 if (--boguscnt
<= 0)
2340 break; /* don't stay in loop forever */
2346 static int pcnet32_close(struct net_device
*dev
)
2348 unsigned long ioaddr
= dev
->base_addr
;
2349 struct pcnet32_private
*lp
= dev
->priv
;
2351 unsigned long flags
;
2353 del_timer_sync(&lp
->watchdog_timer
);
2355 netif_stop_queue(dev
);
2357 spin_lock_irqsave(&lp
->lock
, flags
);
2359 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2361 if (netif_msg_ifdown(lp
))
2363 "%s: Shutting down ethercard, status was %2.2x.\n",
2364 dev
->name
, lp
->a
.read_csr(ioaddr
, 0));
2366 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2367 lp
->a
.write_csr(ioaddr
, 0, 0x0004);
2370 * Switch back to 16bit mode to avoid problems with dumb
2371 * DOS packet driver after a warm reboot
2373 lp
->a
.write_bcr(ioaddr
, 20, 4);
2375 spin_unlock_irqrestore(&lp
->lock
, flags
);
2377 free_irq(dev
->irq
, dev
);
2379 spin_lock_irqsave(&lp
->lock
, flags
);
2381 /* free all allocated skbuffs */
2382 for (i
= 0; i
< lp
->rx_ring_size
; i
++) {
2383 lp
->rx_ring
[i
].status
= 0;
2384 wmb(); /* Make sure adapter sees owner change */
2385 if (lp
->rx_skbuff
[i
]) {
2386 pci_unmap_single(lp
->pci_dev
, lp
->rx_dma_addr
[i
],
2387 PKT_BUF_SZ
- 2, PCI_DMA_FROMDEVICE
);
2388 dev_kfree_skb(lp
->rx_skbuff
[i
]);
2390 lp
->rx_skbuff
[i
] = NULL
;
2391 lp
->rx_dma_addr
[i
] = 0;
2394 for (i
= 0; i
< lp
->tx_ring_size
; i
++) {
2395 lp
->tx_ring
[i
].status
= 0; /* CPU owns buffer */
2396 wmb(); /* Make sure adapter sees owner change */
2397 if (lp
->tx_skbuff
[i
]) {
2398 pci_unmap_single(lp
->pci_dev
, lp
->tx_dma_addr
[i
],
2399 lp
->tx_skbuff
[i
]->len
,
2401 dev_kfree_skb(lp
->tx_skbuff
[i
]);
2403 lp
->tx_skbuff
[i
] = NULL
;
2404 lp
->tx_dma_addr
[i
] = 0;
2407 spin_unlock_irqrestore(&lp
->lock
, flags
);
2412 static struct net_device_stats
*pcnet32_get_stats(struct net_device
*dev
)
2414 struct pcnet32_private
*lp
= dev
->priv
;
2415 unsigned long ioaddr
= dev
->base_addr
;
2417 unsigned long flags
;
2419 spin_lock_irqsave(&lp
->lock
, flags
);
2420 saved_addr
= lp
->a
.read_rap(ioaddr
);
2421 lp
->stats
.rx_missed_errors
= lp
->a
.read_csr(ioaddr
, 112);
2422 lp
->a
.write_rap(ioaddr
, saved_addr
);
2423 spin_unlock_irqrestore(&lp
->lock
, flags
);
2428 /* taken from the sunlance driver, which it took from the depca driver */
2429 static void pcnet32_load_multicast(struct net_device
*dev
)
2431 struct pcnet32_private
*lp
= dev
->priv
;
2432 volatile struct pcnet32_init_block
*ib
= &lp
->init_block
;
2433 volatile u16
*mcast_table
= (u16
*) & ib
->filter
;
2434 struct dev_mc_list
*dmi
= dev
->mc_list
;
2439 /* set all multicast bits */
2440 if (dev
->flags
& IFF_ALLMULTI
) {
2441 ib
->filter
[0] = 0xffffffff;
2442 ib
->filter
[1] = 0xffffffff;
2445 /* clear the multicast filter */
2450 for (i
= 0; i
< dev
->mc_count
; i
++) {
2451 addrs
= dmi
->dmi_addr
;
2454 /* multicast address? */
2458 crc
= ether_crc_le(6, addrs
);
2460 mcast_table
[crc
>> 4] =
2461 le16_to_cpu(le16_to_cpu(mcast_table
[crc
>> 4]) |
2462 (1 << (crc
& 0xf)));
2468 * Set or clear the multicast filter for this adaptor.
2470 static void pcnet32_set_multicast_list(struct net_device
*dev
)
2472 unsigned long ioaddr
= dev
->base_addr
, flags
;
2473 struct pcnet32_private
*lp
= dev
->priv
;
2475 spin_lock_irqsave(&lp
->lock
, flags
);
2476 if (dev
->flags
& IFF_PROMISC
) {
2477 /* Log any net taps. */
2478 if (netif_msg_hw(lp
))
2479 printk(KERN_INFO
"%s: Promiscuous mode enabled.\n",
2481 lp
->init_block
.mode
=
2482 le16_to_cpu(0x8000 | (lp
->options
& PCNET32_PORT_PORTSEL
) <<
2485 lp
->init_block
.mode
=
2486 le16_to_cpu((lp
->options
& PCNET32_PORT_PORTSEL
) << 7);
2487 pcnet32_load_multicast(dev
);
2490 lp
->a
.write_csr(ioaddr
, 0, 0x0004); /* Temporarily stop the lance. */
2491 pcnet32_restart(dev
, 0x0042); /* Resume normal operation */
2492 netif_wake_queue(dev
);
2494 spin_unlock_irqrestore(&lp
->lock
, flags
);
2497 /* This routine assumes that the lp->lock is held */
2498 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
2500 struct pcnet32_private
*lp
= dev
->priv
;
2501 unsigned long ioaddr
= dev
->base_addr
;
2507 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2508 val_out
= lp
->a
.read_bcr(ioaddr
, 34);
2513 /* This routine assumes that the lp->lock is held */
2514 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
2516 struct pcnet32_private
*lp
= dev
->priv
;
2517 unsigned long ioaddr
= dev
->base_addr
;
2522 lp
->a
.write_bcr(ioaddr
, 33, ((phy_id
& 0x1f) << 5) | (reg_num
& 0x1f));
2523 lp
->a
.write_bcr(ioaddr
, 34, val
);
2526 static int pcnet32_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2528 struct pcnet32_private
*lp
= dev
->priv
;
2530 unsigned long flags
;
2532 /* SIOC[GS]MIIxxx ioctls */
2534 spin_lock_irqsave(&lp
->lock
, flags
);
2535 rc
= generic_mii_ioctl(&lp
->mii_if
, if_mii(rq
), cmd
, NULL
);
2536 spin_unlock_irqrestore(&lp
->lock
, flags
);
2544 static int pcnet32_check_otherphy(struct net_device
*dev
)
2546 struct pcnet32_private
*lp
= dev
->priv
;
2547 struct mii_if_info mii
= lp
->mii_if
;
2551 for (i
= 0; i
< PCNET32_MAX_PHYS
; i
++) {
2552 if (i
== lp
->mii_if
.phy_id
)
2553 continue; /* skip active phy */
2554 if (lp
->phymask
& (1 << i
)) {
2556 if (mii_link_ok(&mii
)) {
2557 /* found PHY with active link */
2558 if (netif_msg_link(lp
))
2560 "%s: Using PHY number %d.\n",
2563 /* isolate inactive phy */
2565 mdio_read(dev
, lp
->mii_if
.phy_id
, MII_BMCR
);
2566 mdio_write(dev
, lp
->mii_if
.phy_id
, MII_BMCR
,
2567 bmcr
| BMCR_ISOLATE
);
2569 /* de-isolate new phy */
2570 bmcr
= mdio_read(dev
, i
, MII_BMCR
);
2571 mdio_write(dev
, i
, MII_BMCR
,
2572 bmcr
& ~BMCR_ISOLATE
);
2574 /* set new phy address */
2575 lp
->mii_if
.phy_id
= i
;
2584 * Show the status of the media. Similar to mii_check_media however it
2585 * correctly shows the link speed for all (tested) pcnet32 variants.
2586 * Devices with no mii just report link state without speed.
2588 * Caller is assumed to hold and release the lp->lock.
2591 static void pcnet32_check_media(struct net_device
*dev
, int verbose
)
2593 struct pcnet32_private
*lp
= dev
->priv
;
2595 int prev_link
= netif_carrier_ok(dev
) ? 1 : 0;
2599 curr_link
= mii_link_ok(&lp
->mii_if
);
2601 ulong ioaddr
= dev
->base_addr
; /* card base I/O address */
2602 curr_link
= (lp
->a
.read_bcr(ioaddr
, 4) != 0xc0);
2605 if (prev_link
|| verbose
) {
2606 netif_carrier_off(dev
);
2607 if (netif_msg_link(lp
))
2608 printk(KERN_INFO
"%s: link down\n", dev
->name
);
2610 if (lp
->phycount
> 1) {
2611 curr_link
= pcnet32_check_otherphy(dev
);
2614 } else if (verbose
|| !prev_link
) {
2615 netif_carrier_on(dev
);
2617 if (netif_msg_link(lp
)) {
2618 struct ethtool_cmd ecmd
;
2619 mii_ethtool_gset(&lp
->mii_if
, &ecmd
);
2621 "%s: link up, %sMbps, %s-duplex\n",
2623 (ecmd
.speed
== SPEED_100
) ? "100" : "10",
2625 DUPLEX_FULL
) ? "full" : "half");
2627 bcr9
= lp
->a
.read_bcr(dev
->base_addr
, 9);
2628 if ((bcr9
& (1 << 0)) != lp
->mii_if
.full_duplex
) {
2629 if (lp
->mii_if
.full_duplex
)
2633 lp
->a
.write_bcr(dev
->base_addr
, 9, bcr9
);
2636 if (netif_msg_link(lp
))
2637 printk(KERN_INFO
"%s: link up\n", dev
->name
);
2643 * Check for loss of link and link establishment.
2644 * Can not use mii_check_media because it does nothing if mode is forced.
2647 static void pcnet32_watchdog(struct net_device
*dev
)
2649 struct pcnet32_private
*lp
= dev
->priv
;
2650 unsigned long flags
;
2652 /* Print the link status if it has changed */
2653 spin_lock_irqsave(&lp
->lock
, flags
);
2654 pcnet32_check_media(dev
, 0);
2655 spin_unlock_irqrestore(&lp
->lock
, flags
);
2657 mod_timer(&(lp
->watchdog_timer
), PCNET32_WATCHDOG_TIMEOUT
);
2660 static void __devexit
pcnet32_remove_one(struct pci_dev
*pdev
)
2662 struct net_device
*dev
= pci_get_drvdata(pdev
);
2665 struct pcnet32_private
*lp
= dev
->priv
;
2667 unregister_netdev(dev
);
2668 pcnet32_free_ring(dev
);
2669 release_region(dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2670 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2672 pci_disable_device(pdev
);
2673 pci_set_drvdata(pdev
, NULL
);
2677 static struct pci_driver pcnet32_driver
= {
2679 .probe
= pcnet32_probe_pci
,
2680 .remove
= __devexit_p(pcnet32_remove_one
),
2681 .id_table
= pcnet32_pci_tbl
,
2684 /* An additional parameter that may be passed in... */
2685 static int debug
= -1;
2686 static int tx_start_pt
= -1;
2687 static int pcnet32_have_pci
;
2689 module_param(debug
, int, 0);
2690 MODULE_PARM_DESC(debug
, DRV_NAME
" debug level");
2691 module_param(max_interrupt_work
, int, 0);
2692 MODULE_PARM_DESC(max_interrupt_work
,
2693 DRV_NAME
" maximum events handled per interrupt");
2694 module_param(rx_copybreak
, int, 0);
2695 MODULE_PARM_DESC(rx_copybreak
,
2696 DRV_NAME
" copy breakpoint for copy-only-tiny-frames");
2697 module_param(tx_start_pt
, int, 0);
2698 MODULE_PARM_DESC(tx_start_pt
, DRV_NAME
" transmit start point (0-3)");
2699 module_param(pcnet32vlb
, int, 0);
2700 MODULE_PARM_DESC(pcnet32vlb
, DRV_NAME
" Vesa local bus (VLB) support (0/1)");
2701 module_param_array(options
, int, NULL
, 0);
2702 MODULE_PARM_DESC(options
, DRV_NAME
" initial option setting(s) (0-15)");
2703 module_param_array(full_duplex
, int, NULL
, 0);
2704 MODULE_PARM_DESC(full_duplex
, DRV_NAME
" full duplex setting(s) (1)");
2705 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2706 module_param_array(homepna
, int, NULL
, 0);
2707 MODULE_PARM_DESC(homepna
,
2709 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2711 MODULE_AUTHOR("Thomas Bogendoerfer");
2712 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2713 MODULE_LICENSE("GPL");
2715 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2717 static int __init
pcnet32_init_module(void)
2719 printk(KERN_INFO
"%s", version
);
2721 pcnet32_debug
= netif_msg_init(debug
, PCNET32_MSG_DEFAULT
);
2723 if ((tx_start_pt
>= 0) && (tx_start_pt
<= 3))
2724 tx_start
= tx_start_pt
;
2726 /* find the PCI devices */
2727 if (!pci_module_init(&pcnet32_driver
))
2728 pcnet32_have_pci
= 1;
2730 /* should we find any remaining VLbus devices ? */
2732 pcnet32_probe_vlbus(pcnet32_portlist
);
2734 if (cards_found
&& (pcnet32_debug
& NETIF_MSG_PROBE
))
2735 printk(KERN_INFO PFX
"%d cards_found.\n", cards_found
);
2737 return (pcnet32_have_pci
+ cards_found
) ? 0 : -ENODEV
;
2740 static void __exit
pcnet32_cleanup_module(void)
2742 struct net_device
*next_dev
;
2744 while (pcnet32_dev
) {
2745 struct pcnet32_private
*lp
= pcnet32_dev
->priv
;
2746 next_dev
= lp
->next
;
2747 unregister_netdev(pcnet32_dev
);
2748 pcnet32_free_ring(pcnet32_dev
);
2749 release_region(pcnet32_dev
->base_addr
, PCNET32_TOTAL_SIZE
);
2750 pci_free_consistent(lp
->pci_dev
, sizeof(*lp
), lp
, lp
->dma_addr
);
2751 free_netdev(pcnet32_dev
);
2752 pcnet32_dev
= next_dev
;
2755 if (pcnet32_have_pci
)
2756 pci_unregister_driver(&pcnet32_driver
);
2759 module_init(pcnet32_init_module
);
2760 module_exit(pcnet32_cleanup_module
);