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Linux 2.6.16.40
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / ata_piix.c
blobfc3ca051ceed36dd431bcd0dab1dcf29dbc36cd9
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.05"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
105 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
106 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
107
108 /* combined mode. if set, PATA is channel 0.
109 * if clear, PATA is channel 1.
110 */
111 PIIX_COMB_PATA_P0 = (1 << 1),
112 PIIX_COMB = (1 << 2), /* combined mode enabled? */
113
114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
120 ich5_pata = 0,
121 ich5_sata = 1,
122 piix4_pata = 2,
123 ich6_sata = 3,
124 ich6_sata_ahci = 4,
125
126 PIIX_AHCI_DEVICE = 6,
127 };
128
129 static int piix_init_one (struct pci_dev *pdev,
130 const struct pci_device_id *ent);
131
132 static void piix_pata_phy_reset(struct ata_port *ap);
133 static void piix_sata_phy_reset(struct ata_port *ap);
134 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
135 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
136
137 static unsigned int in_module_init = 1;
138
139 static const struct pci_device_id piix_pci_tbl[] = {
140 #ifdef ATA_ENABLE_PATA
141 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
142 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
143 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
144 #endif
145
146 /* NOTE: The following PCI ids must be kept in sync with the
147 * list in drivers/pci/quirks.c.
148 */
149
150 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
151 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
152 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
153 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
154 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
155 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
156 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
157 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
158 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
159 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
160 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
161 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
162 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
163
164 { } /* terminate list */
165 };
166
167 static struct pci_driver piix_pci_driver = {
168 .name = DRV_NAME,
169 .id_table = piix_pci_tbl,
170 .probe = piix_init_one,
171 .remove = ata_pci_remove_one,
172 .suspend = ata_pci_device_suspend,
173 .resume = ata_pci_device_resume,
174 };
175
176 static struct scsi_host_template piix_sht = {
177 .module = THIS_MODULE,
178 .name = DRV_NAME,
179 .ioctl = ata_scsi_ioctl,
180 .queuecommand = ata_scsi_queuecmd,
181 .eh_strategy_handler = ata_scsi_error,
182 .can_queue = ATA_DEF_QUEUE,
183 .this_id = ATA_SHT_THIS_ID,
184 .sg_tablesize = LIBATA_MAX_PRD,
185 .max_sectors = ATA_MAX_SECTORS,
186 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
187 .emulated = ATA_SHT_EMULATED,
188 .use_clustering = ATA_SHT_USE_CLUSTERING,
189 .proc_name = DRV_NAME,
190 .dma_boundary = ATA_DMA_BOUNDARY,
191 .slave_configure = ata_scsi_slave_config,
192 .bios_param = ata_std_bios_param,
193 .resume = ata_scsi_device_resume,
194 .suspend = ata_scsi_device_suspend,
195 };
196
197 static const struct ata_port_operations piix_pata_ops = {
198 .port_disable = ata_port_disable,
199 .set_piomode = piix_set_piomode,
200 .set_dmamode = piix_set_dmamode,
201
202 .tf_load = ata_tf_load,
203 .tf_read = ata_tf_read,
204 .check_status = ata_check_status,
205 .exec_command = ata_exec_command,
206 .dev_select = ata_std_dev_select,
207
208 .phy_reset = piix_pata_phy_reset,
209
210 .bmdma_setup = ata_bmdma_setup,
211 .bmdma_start = ata_bmdma_start,
212 .bmdma_stop = ata_bmdma_stop,
213 .bmdma_status = ata_bmdma_status,
214 .qc_prep = ata_qc_prep,
215 .qc_issue = ata_qc_issue_prot,
216
217 .eng_timeout = ata_eng_timeout,
218
219 .irq_handler = ata_interrupt,
220 .irq_clear = ata_bmdma_irq_clear,
221
222 .port_start = ata_port_start,
223 .port_stop = ata_port_stop,
224 .host_stop = ata_host_stop,
225 };
226
227 static const struct ata_port_operations piix_sata_ops = {
228 .port_disable = ata_port_disable,
229
230 .tf_load = ata_tf_load,
231 .tf_read = ata_tf_read,
232 .check_status = ata_check_status,
233 .exec_command = ata_exec_command,
234 .dev_select = ata_std_dev_select,
235
236 .phy_reset = piix_sata_phy_reset,
237
238 .bmdma_setup = ata_bmdma_setup,
239 .bmdma_start = ata_bmdma_start,
240 .bmdma_stop = ata_bmdma_stop,
241 .bmdma_status = ata_bmdma_status,
242 .qc_prep = ata_qc_prep,
243 .qc_issue = ata_qc_issue_prot,
244
245 .eng_timeout = ata_eng_timeout,
246
247 .irq_handler = ata_interrupt,
248 .irq_clear = ata_bmdma_irq_clear,
249
250 .port_start = ata_port_start,
251 .port_stop = ata_port_stop,
252 .host_stop = ata_host_stop,
253 };
254
255 static struct ata_port_info piix_port_info[] = {
256 /* ich5_pata */
257 {
258 .sht = &piix_sht,
259 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
260 PIIX_FLAG_CHECKINTR,
261 .pio_mask = 0x1f, /* pio0-4 */
262 #if 0
263 .mwdma_mask = 0x06, /* mwdma1-2 */
264 #else
265 .mwdma_mask = 0x00, /* mwdma broken */
266 #endif
267 .udma_mask = 0x3f, /* udma0-5 */
268 .port_ops = &piix_pata_ops,
269 },
270
271 /* ich5_sata */
272 {
273 .sht = &piix_sht,
274 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
275 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
276 .pio_mask = 0x1f, /* pio0-4 */
277 .mwdma_mask = 0x07, /* mwdma0-2 */
278 .udma_mask = 0x7f, /* udma0-6 */
279 .port_ops = &piix_sata_ops,
280 },
281
282 /* piix4_pata */
283 {
284 .sht = &piix_sht,
285 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
286 .pio_mask = 0x1f, /* pio0-4 */
287 #if 0
288 .mwdma_mask = 0x06, /* mwdma1-2 */
289 #else
290 .mwdma_mask = 0x00, /* mwdma broken */
291 #endif
292 .udma_mask = ATA_UDMA_MASK_40C,
293 .port_ops = &piix_pata_ops,
294 },
295
296 /* ich6_sata */
297 {
298 .sht = &piix_sht,
299 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
300 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
301 ATA_FLAG_SLAVE_POSS,
302 .pio_mask = 0x1f, /* pio0-4 */
303 .mwdma_mask = 0x07, /* mwdma0-2 */
304 .udma_mask = 0x7f, /* udma0-6 */
305 .port_ops = &piix_sata_ops,
306 },
307
308 /* ich6_sata_ahci */
309 {
310 .sht = &piix_sht,
311 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
312 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
313 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
314 .pio_mask = 0x1f, /* pio0-4 */
315 .mwdma_mask = 0x07, /* mwdma0-2 */
316 .udma_mask = 0x7f, /* udma0-6 */
317 .port_ops = &piix_sata_ops,
318 },
319 };
320
321 static struct pci_bits piix_enable_bits[] = {
322 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
323 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
324 };
325
326 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
327 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
328 MODULE_LICENSE("GPL");
329 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
330 MODULE_VERSION(DRV_VERSION);
331
332 /**
333 * piix_pata_cbl_detect - Probe host controller cable detect info
334 * @ap: Port for which cable detect info is desired
335 *
336 * Read 80c cable indicator from ATA PCI device's PCI config
337 * register. This register is normally set by firmware (BIOS).
338 *
339 * LOCKING:
340 * None (inherited from caller).
341 */
342 static void piix_pata_cbl_detect(struct ata_port *ap)
343 {
344 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
345 u8 tmp, mask;
346
347 /* no 80c support in host controller? */
348 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
349 goto cbl40;
350
351 /* check BIOS cable detect results */
352 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
353 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
354 if ((tmp & mask) == 0)
355 goto cbl40;
356
357 ap->cbl = ATA_CBL_PATA80;
358 return;
359
360 cbl40:
361 ap->cbl = ATA_CBL_PATA40;
362 ap->udma_mask &= ATA_UDMA_MASK_40C;
363 }
364
365 /**
366 * piix_pata_phy_reset - Probe specified port on PATA host controller
367 * @ap: Port to probe
368 *
369 * Probe PATA phy.
370 *
371 * LOCKING:
372 * None (inherited from caller).
373 */
374
375 static void piix_pata_phy_reset(struct ata_port *ap)
376 {
377 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
378
379 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
380 ata_port_disable(ap);
381 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
382 return;
383 }
384
385 piix_pata_cbl_detect(ap);
386
387 ata_port_probe(ap);
388
389 ata_bus_reset(ap);
390 }
391
392 /**
393 * piix_sata_probe - Probe PCI device for present SATA devices
394 * @ap: Port associated with the PCI device we wish to probe
395 *
396 * Reads SATA PCI device's PCI config register Port Configuration
397 * and Status (PCS) to determine port and device availability.
398 *
399 * LOCKING:
400 * None (inherited from caller).
401 *
402 * RETURNS:
403 * Non-zero if port is enabled, it may or may not have a device
404 * attached in that case (PRESENT bit would only be set if BIOS probe
405 * was done). Zero is returned if port is disabled.
406 */
407 static int piix_sata_probe (struct ata_port *ap)
408 {
409 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
410 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
411 int orig_mask, mask, i;
412 u8 pcs;
413
414 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
415 (PIIX_PORT_ENABLED << ap->hard_port_no);
416
417 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
418 orig_mask = (int) pcs & 0xff;
419
420 /* TODO: this is vaguely wrong for ICH6 combined mode,
421 * where only two of the four SATA ports are mapped
422 * onto a single ATA channel. It is also vaguely inaccurate
423 * for ICH5, which has only two ports. However, this is ok,
424 * as further device presence detection code will handle
425 * any false positives produced here.
426 */
427
428 for (i = 0; i < 4; i++) {
429 mask = (PIIX_PORT_ENABLED << i);
430
431 if ((orig_mask & mask) == mask)
432 if (combined || (i == ap->hard_port_no))
433 return 1;
434 }
435
436 return 0;
437 }
438
439 /**
440 * piix_sata_phy_reset - Probe specified port on SATA host controller
441 * @ap: Port to probe
442 *
443 * Probe SATA phy.
444 *
445 * LOCKING:
446 * None (inherited from caller).
447 */
448
449 static void piix_sata_phy_reset(struct ata_port *ap)
450 {
451 if (!piix_sata_probe(ap)) {
452 ata_port_disable(ap);
453 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
454 return;
455 }
456
457 ap->cbl = ATA_CBL_SATA;
458
459 ata_port_probe(ap);
460
461 ata_bus_reset(ap);
462 }
463
464 /**
465 * piix_set_piomode - Initialize host controller PATA PIO timings
466 * @ap: Port whose timings we are configuring
467 * @adev: um
468 *
469 * Set PIO mode for device, in host controller PCI config space.
470 *
471 * LOCKING:
472 * None (inherited from caller).
473 */
474
475 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
476 {
477 unsigned int pio = adev->pio_mode - XFER_PIO_0;
478 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
479 unsigned int is_slave = (adev->devno != 0);
480 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
481 unsigned int slave_port = 0x44;
482 u16 master_data;
483 u8 slave_data;
484
485 static const /* ISP RTC */
486 u8 timings[][2] = { { 0, 0 },
487 { 0, 0 },
488 { 1, 0 },
489 { 2, 1 },
490 { 2, 3 }, };
491
492 pci_read_config_word(dev, master_port, &master_data);
493 if (is_slave) {
494 master_data |= 0x4000;
495 /* enable PPE, IE and TIME */
496 master_data |= 0x0070;
497 pci_read_config_byte(dev, slave_port, &slave_data);
498 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
499 slave_data |=
500 (timings[pio][0] << 2) |
501 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
502 } else {
503 master_data &= 0xccf8;
504 /* enable PPE, IE and TIME */
505 master_data |= 0x0007;
506 master_data |=
507 (timings[pio][0] << 12) |
508 (timings[pio][1] << 8);
509 }
510 pci_write_config_word(dev, master_port, master_data);
511 if (is_slave)
512 pci_write_config_byte(dev, slave_port, slave_data);
513 }
514
515 /**
516 * piix_set_dmamode - Initialize host controller PATA PIO timings
517 * @ap: Port whose timings we are configuring
518 * @adev: um
519 * @udma: udma mode, 0 - 6
520 *
521 * Set UDMA mode for device, in host controller PCI config space.
522 *
523 * LOCKING:
524 * None (inherited from caller).
525 */
526
527 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
528 {
529 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
530 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
531 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
532 u8 speed = udma;
533 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
534 int a_speed = 3 << (drive_dn * 4);
535 int u_flag = 1 << drive_dn;
536 int v_flag = 0x01 << drive_dn;
537 int w_flag = 0x10 << drive_dn;
538 int u_speed = 0;
539 int sitre;
540 u16 reg4042, reg4a;
541 u8 reg48, reg54, reg55;
542
543 pci_read_config_word(dev, maslave, &reg4042);
544 DPRINTK("reg4042 = 0x%04x\n", reg4042);
545 sitre = (reg4042 & 0x4000) ? 1 : 0;
546 pci_read_config_byte(dev, 0x48, &reg48);
547 pci_read_config_word(dev, 0x4a, &reg4a);
548 pci_read_config_byte(dev, 0x54, &reg54);
549 pci_read_config_byte(dev, 0x55, &reg55);
550
551 switch(speed) {
552 case XFER_UDMA_4:
553 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
554 case XFER_UDMA_6:
555 case XFER_UDMA_5:
556 case XFER_UDMA_3:
557 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
558 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
559 case XFER_MW_DMA_2:
560 case XFER_MW_DMA_1: break;
561 default:
562 BUG();
563 return;
564 }
565
566 if (speed >= XFER_UDMA_0) {
567 if (!(reg48 & u_flag))
568 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
569 if (speed == XFER_UDMA_5) {
570 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
571 } else {
572 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
573 }
574 if ((reg4a & a_speed) != u_speed)
575 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
576 if (speed > XFER_UDMA_2) {
577 if (!(reg54 & v_flag))
578 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
579 } else
580 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
581 } else {
582 if (reg48 & u_flag)
583 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
584 if (reg4a & a_speed)
585 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
586 if (reg54 & v_flag)
587 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
588 if (reg55 & w_flag)
589 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
590 }
591 }
592
593 #define AHCI_PCI_BAR 5
594 #define AHCI_GLOBAL_CTL 0x04
595 #define AHCI_ENABLE (1 << 31)
596 static int piix_disable_ahci(struct pci_dev *pdev)
597 {
598 void __iomem *mmio;
599 u32 tmp;
600 int rc = 0;
601
602 /* BUG: pci_enable_device has not yet been called. This
603 * works because this device is usually set up by BIOS.
604 */
605
606 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
607 !pci_resource_len(pdev, AHCI_PCI_BAR))
608 return 0;
609
610 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
611 if (!mmio)
612 return -ENOMEM;
613
614 tmp = readl(mmio + AHCI_GLOBAL_CTL);
615 if (tmp & AHCI_ENABLE) {
616 tmp &= ~AHCI_ENABLE;
617 writel(tmp, mmio + AHCI_GLOBAL_CTL);
618
619 tmp = readl(mmio + AHCI_GLOBAL_CTL);
620 if (tmp & AHCI_ENABLE)
621 rc = -EIO;
622 }
623
624 pci_iounmap(pdev, mmio);
625 return rc;
626 }
627
628 /**
629 * piix_check_450nx_errata - Check for problem 450NX setup
630 *
631 * Check for the present of 450NX errata #19 and errata #25. If
632 * they are found return an error code so we can turn off DMA
633 */
634
635 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
636 {
637 struct pci_dev *pdev = NULL;
638 u16 cfg;
639 u8 rev;
640 int no_piix_dma = 0;
641
642 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
643 {
644 /* Look for 450NX PXB. Check for problem configurations
645 A PCI quirk checks bit 6 already */
646 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
647 pci_read_config_word(pdev, 0x41, &cfg);
648 /* Only on the original revision: IDE DMA can hang */
649 if(rev == 0x00)
650 no_piix_dma = 1;
651 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
652 else if(cfg & (1<<14) && rev < 5)
653 no_piix_dma = 2;
654 }
655 if(no_piix_dma)
656 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
657 if(no_piix_dma == 2)
658 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
659 return no_piix_dma;
660 }
661
662 /**
663 * piix_init_one - Register PIIX ATA PCI device with kernel services
664 * @pdev: PCI device to register
665 * @ent: Entry in piix_pci_tbl matching with @pdev
666 *
667 * Called from kernel PCI layer. We probe for combined mode (sigh),
668 * and then hand over control to libata, for it to do the rest.
669 *
670 * LOCKING:
671 * Inherited from PCI layer (may sleep).
672 *
673 * RETURNS:
674 * Zero on success, or -ERRNO value.
675 */
676
677 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
678 {
679 static int printed_version;
680 struct ata_port_info *port_info[2];
681 unsigned int combined = 0;
682 unsigned int pata_chan = 0, sata_chan = 0;
683
684 if (!printed_version++)
685 dev_printk(KERN_DEBUG, &pdev->dev,
686 "version " DRV_VERSION "\n");
687
688 /* no hotplugging support (FIXME) */
689 if (!in_module_init)
690 return -ENODEV;
691
692 port_info[0] = &piix_port_info[ent->driver_data];
693 port_info[1] = &piix_port_info[ent->driver_data];
694
695 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
696 u8 tmp;
697 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
698 if (tmp == PIIX_AHCI_DEVICE) {
699 int rc = piix_disable_ahci(pdev);
700 if (rc)
701 return rc;
702 }
703 }
704
705 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
706 u8 tmp;
707 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
708
709 if (tmp & PIIX_COMB) {
710 combined = 1;
711 if (tmp & PIIX_COMB_PATA_P0)
712 sata_chan = 1;
713 else
714 pata_chan = 1;
715 }
716 }
717
718 /* On ICH5, some BIOSen disable the interrupt using the
719 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
720 * On ICH6, this bit has the same effect, but only when
721 * MSI is disabled (and it is disabled, as we don't use
722 * message-signalled interrupts currently).
723 */
724 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
725 pci_intx(pdev, 1);
726
727 if (combined) {
728 port_info[sata_chan] = &piix_port_info[ent->driver_data];
729 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
730 port_info[pata_chan] = &piix_port_info[ich5_pata];
731
732 dev_printk(KERN_WARNING, &pdev->dev,
733 "combined mode detected (p=%u, s=%u)\n",
734 pata_chan, sata_chan);
735 }
736 if (piix_check_450nx_errata(pdev)) {
737 /* This writes into the master table but it does not
738 really matter for this errata as we will apply it to
739 all the PIIX devices on the board */
740 port_info[0]->mwdma_mask = 0;
741 port_info[0]->udma_mask = 0;
742 port_info[1]->mwdma_mask = 0;
743 port_info[1]->udma_mask = 0;
744 }
745 return ata_pci_init_one(pdev, port_info, 2);
746 }
747
748 static int __init piix_init(void)
749 {
750 int rc;
751
752 DPRINTK("pci_module_init\n");
753 rc = pci_module_init(&piix_pci_driver);
754 if (rc)
755 return rc;
756
757 in_module_init = 0;
758
759 DPRINTK("done\n");
760 return 0;
761 }
762
763 static void __exit piix_exit(void)
764 {
765 pci_unregister_driver(&piix_pci_driver);
766 }
767
768 module_init(piix_init);
769 module_exit(piix_exit);
770
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree