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packet: Add fanout support.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / 8139too.c
blobed6355cc52612953a8f33fde4f15ed3b4185e60a
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
93
94 #define DRV_NAME "8139too"
95 #define DRV_VERSION "0.9.28"
96
97
98 #include <linux/module.h>
99 #include <linux/kernel.h>
100 #include <linux/compiler.h>
101 #include <linux/pci.h>
102 #include <linux/init.h>
103 #include <linux/interrupt.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/rtnetlink.h>
107 #include <linux/delay.h>
108 #include <linux/ethtool.h>
109 #include <linux/mii.h>
110 #include <linux/completion.h>
111 #include <linux/crc32.h>
112 #include <linux/io.h>
113 #include <linux/uaccess.h>
114 #include <linux/gfp.h>
115 #include <asm/irq.h>
116
117 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* define to 1, 2 or 3 to enable copious debugging info */
126 #define RTL8139_DEBUG 0
127
128 /* define to 1 to disable lightweight runtime debugging checks */
129 #undef RTL8139_NDEBUG
130
131
132 #ifdef RTL8139_NDEBUG
133 # define assert(expr) do {} while (0)
134 #else
135 # define assert(expr) \
136 if (unlikely(!(expr))) { \
137 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
138 #expr, __FILE__, __func__, __LINE__); \
139 }
140 #endif
141
142
143 /* A few user-configurable values. */
144 /* media options */
145 #define MAX_UNITS 8
146 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
147 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
148
149 /* Whether to use MMIO or PIO. Default to MMIO. */
150 #ifdef CONFIG_8139TOO_PIO
151 static int use_io = 1;
152 #else
153 static int use_io = 0;
154 #endif
155
156 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
157 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
158 static int multicast_filter_limit = 32;
159
160 /* bitmapped message enable number */
161 static int debug = -1;
162
163 /*
164 * Receive ring size
165 * Warning: 64K ring has hardware issues and may lock up.
166 */
167 #if defined(CONFIG_SH_DREAMCAST)
168 #define RX_BUF_IDX 0 /* 8K ring */
169 #else
170 #define RX_BUF_IDX 2 /* 32K ring */
171 #endif
172 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
173 #define RX_BUF_PAD 16
174 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
175
176 #if RX_BUF_LEN == 65536
177 #define RX_BUF_TOT_LEN RX_BUF_LEN
178 #else
179 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
180 #endif
181
182 /* Number of Tx descriptor registers. */
183 #define NUM_TX_DESC 4
184
185 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
186 #define MAX_ETH_FRAME_SIZE 1536
187
188 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
189 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
190 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
191
192 /* PCI Tuning Parameters
193 Threshold is bytes transferred to chip before transmission starts. */
194 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
195
196 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
197 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
198 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
199 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
200 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
201
202 /* Operational parameters that usually are not changed. */
203 /* Time in jiffies before concluding the transmitter is hung. */
204 #define TX_TIMEOUT (6*HZ)
205
206
207 enum {
208 HAS_MII_XCVR = 0x010000,
209 HAS_CHIP_XCVR = 0x020000,
210 HAS_LNK_CHNG = 0x040000,
211 };
212
213 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
214 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
215 #define RTL_MIN_IO_SIZE 0x80
216 #define RTL8139B_IO_SIZE 256
217
218 #define RTL8129_CAPS HAS_MII_XCVR
219 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG)
220
221 typedef enum {
222 RTL8139 = 0,
223 RTL8129,
224 } board_t;
225
226
227 /* indexed by board_t, above */
228 static const struct {
229 const char *name;
230 u32 hw_flags;
231 } board_info[] __devinitdata = {
232 { "RealTek RTL8139", RTL8139_CAPS },
233 { "RealTek RTL8129", RTL8129_CAPS },
234 };
235
236
237 static DEFINE_PCI_DEVICE_TABLE(rtl8139_pci_tbl) = {
238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257
258 #ifdef CONFIG_SH_SECUREEDGE5410
259 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
260 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 #endif
262 #ifdef CONFIG_8139TOO_8129
263 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
264 #endif
265
266 /* some crazy cards report invalid vendor ids like
267 * 0x0001 here. The other ids are valid and constant,
268 * so we simply don't match on the main vendor id.
269 */
270 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
271 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
272 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
273
274 {0,}
275 };
276 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
277
278 static struct {
279 const char str[ETH_GSTRING_LEN];
280 } ethtool_stats_keys[] = {
281 { "early_rx" },
282 { "tx_buf_mapped" },
283 { "tx_timeouts" },
284 { "rx_lost_in_ring" },
285 };
286
287 /* The rest of these values should never change. */
288
289 /* Symbolic offsets to registers. */
290 enum RTL8139_registers {
291 MAC0 = 0, /* Ethernet hardware address. */
292 MAR0 = 8, /* Multicast filter. */
293 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
294 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
295 RxBuf = 0x30,
296 ChipCmd = 0x37,
297 RxBufPtr = 0x38,
298 RxBufAddr = 0x3A,
299 IntrMask = 0x3C,
300 IntrStatus = 0x3E,
301 TxConfig = 0x40,
302 RxConfig = 0x44,
303 Timer = 0x48, /* A general-purpose counter. */
304 RxMissed = 0x4C, /* 24 bits valid, write clears. */
305 Cfg9346 = 0x50,
306 Config0 = 0x51,
307 Config1 = 0x52,
308 TimerInt = 0x54,
309 MediaStatus = 0x58,
310 Config3 = 0x59,
311 Config4 = 0x5A, /* absent on RTL-8139A */
312 HltClk = 0x5B,
313 MultiIntr = 0x5C,
314 TxSummary = 0x60,
315 BasicModeCtrl = 0x62,
316 BasicModeStatus = 0x64,
317 NWayAdvert = 0x66,
318 NWayLPAR = 0x68,
319 NWayExpansion = 0x6A,
320 /* Undocumented registers, but required for proper operation. */
321 FIFOTMS = 0x70, /* FIFO Control and test. */
322 CSCR = 0x74, /* Chip Status and Configuration Register. */
323 PARA78 = 0x78,
324 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */
325 PARA7c = 0x7c, /* Magic transceiver parameter register. */
326 Config5 = 0xD8, /* absent on RTL-8139A */
327 };
328
329 enum ClearBitMasks {
330 MultiIntrClear = 0xF000,
331 ChipCmdClear = 0xE2,
332 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
333 };
334
335 enum ChipCmdBits {
336 CmdReset = 0x10,
337 CmdRxEnb = 0x08,
338 CmdTxEnb = 0x04,
339 RxBufEmpty = 0x01,
340 };
341
342 /* Interrupt register bits, using my own meaningful names. */
343 enum IntrStatusBits {
344 PCIErr = 0x8000,
345 PCSTimeout = 0x4000,
346 RxFIFOOver = 0x40,
347 RxUnderrun = 0x20,
348 RxOverflow = 0x10,
349 TxErr = 0x08,
350 TxOK = 0x04,
351 RxErr = 0x02,
352 RxOK = 0x01,
353
354 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
355 };
356
357 enum TxStatusBits {
358 TxHostOwns = 0x2000,
359 TxUnderrun = 0x4000,
360 TxStatOK = 0x8000,
361 TxOutOfWindow = 0x20000000,
362 TxAborted = 0x40000000,
363 TxCarrierLost = 0x80000000,
364 };
365 enum RxStatusBits {
366 RxMulticast = 0x8000,
367 RxPhysical = 0x4000,
368 RxBroadcast = 0x2000,
369 RxBadSymbol = 0x0020,
370 RxRunt = 0x0010,
371 RxTooLong = 0x0008,
372 RxCRCErr = 0x0004,
373 RxBadAlign = 0x0002,
374 RxStatusOK = 0x0001,
375 };
376
377 /* Bits in RxConfig. */
378 enum rx_mode_bits {
379 AcceptErr = 0x20,
380 AcceptRunt = 0x10,
381 AcceptBroadcast = 0x08,
382 AcceptMulticast = 0x04,
383 AcceptMyPhys = 0x02,
384 AcceptAllPhys = 0x01,
385 };
386
387 /* Bits in TxConfig. */
388 enum tx_config_bits {
389 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
390 TxIFGShift = 24,
391 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
392 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
393 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
394 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
395
396 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
397 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */
398 TxClearAbt = (1 << 0), /* Clear abort (WO) */
399 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */
400 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */
401
402 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
403 };
404
405 /* Bits in Config1 */
406 enum Config1Bits {
407 Cfg1_PM_Enable = 0x01,
408 Cfg1_VPD_Enable = 0x02,
409 Cfg1_PIO = 0x04,
410 Cfg1_MMIO = 0x08,
411 LWAKE = 0x10, /* not on 8139, 8139A */
412 Cfg1_Driver_Load = 0x20,
413 Cfg1_LED0 = 0x40,
414 Cfg1_LED1 = 0x80,
415 SLEEP = (1 << 1), /* only on 8139, 8139A */
416 PWRDN = (1 << 0), /* only on 8139, 8139A */
417 };
418
419 /* Bits in Config3 */
420 enum Config3Bits {
421 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
422 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
423 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
424 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
425 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
426 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
427 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
428 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
429 };
430
431 /* Bits in Config4 */
432 enum Config4Bits {
433 LWPTN = (1 << 2), /* not on 8139, 8139A */
434 };
435
436 /* Bits in Config5 */
437 enum Config5Bits {
438 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
439 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
440 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
441 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
442 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
443 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
444 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
445 };
446
447 enum RxConfigBits {
448 /* rx fifo threshold */
449 RxCfgFIFOShift = 13,
450 RxCfgFIFONone = (7 << RxCfgFIFOShift),
451
452 /* Max DMA burst */
453 RxCfgDMAShift = 8,
454 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
455
456 /* rx ring buffer length */
457 RxCfgRcv8K = 0,
458 RxCfgRcv16K = (1 << 11),
459 RxCfgRcv32K = (1 << 12),
460 RxCfgRcv64K = (1 << 11) | (1 << 12),
461
462 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
463 RxNoWrap = (1 << 7),
464 };
465
466 /* Twister tuning parameters from RealTek.
467 Completely undocumented, but required to tune bad links on some boards. */
468 enum CSCRBits {
469 CSCR_LinkOKBit = 0x0400,
470 CSCR_LinkChangeBit = 0x0800,
471 CSCR_LinkStatusBits = 0x0f000,
472 CSCR_LinkDownOffCmd = 0x003c0,
473 CSCR_LinkDownCmd = 0x0f3c0,
474 };
475
476 enum Cfg9346Bits {
477 Cfg9346_Lock = 0x00,
478 Cfg9346_Unlock = 0xC0,
479 };
480
481 typedef enum {
482 CH_8139 = 0,
483 CH_8139_K,
484 CH_8139A,
485 CH_8139A_G,
486 CH_8139B,
487 CH_8130,
488 CH_8139C,
489 CH_8100,
490 CH_8100B_8139D,
491 CH_8101,
492 } chip_t;
493
494 enum chip_flags {
495 HasHltClk = (1 << 0),
496 HasLWake = (1 << 1),
497 };
498
499 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
500 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
501 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
502
503 /* directly indexed by chip_t, above */
504 static const struct {
505 const char *name;
506 u32 version; /* from RTL8139C/RTL8139D docs */
507 u32 flags;
508 } rtl_chip_info[] = {
509 { "RTL-8139",
510 HW_REVID(1, 0, 0, 0, 0, 0, 0),
511 HasHltClk,
512 },
513
514 { "RTL-8139 rev K",
515 HW_REVID(1, 1, 0, 0, 0, 0, 0),
516 HasHltClk,
517 },
518
519 { "RTL-8139A",
520 HW_REVID(1, 1, 1, 0, 0, 0, 0),
521 HasHltClk, /* XXX undocumented? */
522 },
523
524 { "RTL-8139A rev G",
525 HW_REVID(1, 1, 1, 0, 0, 1, 0),
526 HasHltClk, /* XXX undocumented? */
527 },
528
529 { "RTL-8139B",
530 HW_REVID(1, 1, 1, 1, 0, 0, 0),
531 HasLWake,
532 },
533
534 { "RTL-8130",
535 HW_REVID(1, 1, 1, 1, 1, 0, 0),
536 HasLWake,
537 },
538
539 { "RTL-8139C",
540 HW_REVID(1, 1, 1, 0, 1, 0, 0),
541 HasLWake,
542 },
543
544 { "RTL-8100",
545 HW_REVID(1, 1, 1, 1, 0, 1, 0),
546 HasLWake,
547 },
548
549 { "RTL-8100B/8139D",
550 HW_REVID(1, 1, 1, 0, 1, 0, 1),
551 HasHltClk /* XXX undocumented? */
552 | HasLWake,
553 },
554
555 { "RTL-8101",
556 HW_REVID(1, 1, 1, 0, 1, 1, 1),
557 HasLWake,
558 },
559 };
560
561 struct rtl_extra_stats {
562 unsigned long early_rx;
563 unsigned long tx_buf_mapped;
564 unsigned long tx_timeouts;
565 unsigned long rx_lost_in_ring;
566 };
567
568 struct rtl8139_private {
569 void __iomem *mmio_addr;
570 int drv_flags;
571 struct pci_dev *pci_dev;
572 u32 msg_enable;
573 struct napi_struct napi;
574 struct net_device *dev;
575
576 unsigned char *rx_ring;
577 unsigned int cur_rx; /* RX buf index of next pkt */
578 dma_addr_t rx_ring_dma;
579
580 unsigned int tx_flag;
581 unsigned long cur_tx;
582 unsigned long dirty_tx;
583 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
584 unsigned char *tx_bufs; /* Tx bounce buffer region. */
585 dma_addr_t tx_bufs_dma;
586
587 signed char phys[4]; /* MII device addresses. */
588
589 /* Twister tune state. */
590 char twistie, twist_row, twist_col;
591
592 unsigned int watchdog_fired : 1;
593 unsigned int default_port : 4; /* Last dev->if_port value. */
594 unsigned int have_thread : 1;
595
596 spinlock_t lock;
597 spinlock_t rx_lock;
598
599 chip_t chipset;
600 u32 rx_config;
601 struct rtl_extra_stats xstats;
602
603 struct delayed_work thread;
604
605 struct mii_if_info mii;
606 unsigned int regs_len;
607 unsigned long fifo_copy_timeout;
608 };
609
610 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
611 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
612 MODULE_LICENSE("GPL");
613 MODULE_VERSION(DRV_VERSION);
614
615 module_param(use_io, int, 0);
616 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
617 module_param(multicast_filter_limit, int, 0);
618 module_param_array(media, int, NULL, 0);
619 module_param_array(full_duplex, int, NULL, 0);
620 module_param(debug, int, 0);
621 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
622 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
623 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
624 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
625
626 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
627 static int rtl8139_open (struct net_device *dev);
628 static int mdio_read (struct net_device *dev, int phy_id, int location);
629 static void mdio_write (struct net_device *dev, int phy_id, int location,
630 int val);
631 static void rtl8139_start_thread(struct rtl8139_private *tp);
632 static void rtl8139_tx_timeout (struct net_device *dev);
633 static void rtl8139_init_ring (struct net_device *dev);
634 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
635 struct net_device *dev);
636 #ifdef CONFIG_NET_POLL_CONTROLLER
637 static void rtl8139_poll_controller(struct net_device *dev);
638 #endif
639 static int rtl8139_set_mac_address(struct net_device *dev, void *p);
640 static int rtl8139_poll(struct napi_struct *napi, int budget);
641 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
642 static int rtl8139_close (struct net_device *dev);
643 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
644 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
645 static void rtl8139_set_rx_mode (struct net_device *dev);
646 static void __set_rx_mode (struct net_device *dev);
647 static void rtl8139_hw_start (struct net_device *dev);
648 static void rtl8139_thread (struct work_struct *work);
649 static void rtl8139_tx_timeout_task(struct work_struct *work);
650 static const struct ethtool_ops rtl8139_ethtool_ops;
651
652 /* write MMIO register, with flush */
653 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
654 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
655 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
656 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
657
658 /* write MMIO register */
659 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
660 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
661 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
662
663 /* read MMIO register */
664 #define RTL_R8(reg) ioread8 (ioaddr + (reg))
665 #define RTL_R16(reg) ioread16 (ioaddr + (reg))
666 #define RTL_R32(reg) ioread32 (ioaddr + (reg))
667
668
669 static const u16 rtl8139_intr_mask =
670 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
671 TxErr | TxOK | RxErr | RxOK;
672
673 static const u16 rtl8139_norx_intr_mask =
674 PCIErr | PCSTimeout | RxUnderrun |
675 TxErr | TxOK | RxErr ;
676
677 #if RX_BUF_IDX == 0
678 static const unsigned int rtl8139_rx_config =
679 RxCfgRcv8K | RxNoWrap |
680 (RX_FIFO_THRESH << RxCfgFIFOShift) |
681 (RX_DMA_BURST << RxCfgDMAShift);
682 #elif RX_BUF_IDX == 1
683 static const unsigned int rtl8139_rx_config =
684 RxCfgRcv16K | RxNoWrap |
685 (RX_FIFO_THRESH << RxCfgFIFOShift) |
686 (RX_DMA_BURST << RxCfgDMAShift);
687 #elif RX_BUF_IDX == 2
688 static const unsigned int rtl8139_rx_config =
689 RxCfgRcv32K | RxNoWrap |
690 (RX_FIFO_THRESH << RxCfgFIFOShift) |
691 (RX_DMA_BURST << RxCfgDMAShift);
692 #elif RX_BUF_IDX == 3
693 static const unsigned int rtl8139_rx_config =
694 RxCfgRcv64K |
695 (RX_FIFO_THRESH << RxCfgFIFOShift) |
696 (RX_DMA_BURST << RxCfgDMAShift);
697 #else
698 #error "Invalid configuration for 8139_RXBUF_IDX"
699 #endif
700
701 static const unsigned int rtl8139_tx_config =
702 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
703
704 static void __rtl8139_cleanup_dev (struct net_device *dev)
705 {
706 struct rtl8139_private *tp = netdev_priv(dev);
707 struct pci_dev *pdev;
708
709 assert (dev != NULL);
710 assert (tp->pci_dev != NULL);
711 pdev = tp->pci_dev;
712
713 if (tp->mmio_addr)
714 pci_iounmap (pdev, tp->mmio_addr);
715
716 /* it's ok to call this even if we have no regions to free */
717 pci_release_regions (pdev);
718
719 free_netdev(dev);
720 pci_set_drvdata (pdev, NULL);
721 }
722
723
724 static void rtl8139_chip_reset (void __iomem *ioaddr)
725 {
726 int i;
727
728 /* Soft reset the chip. */
729 RTL_W8 (ChipCmd, CmdReset);
730
731 /* Check that the chip has finished the reset. */
732 for (i = 1000; i > 0; i--) {
733 barrier();
734 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
735 break;
736 udelay (10);
737 }
738 }
739
740
741 static __devinit struct net_device * rtl8139_init_board (struct pci_dev *pdev)
742 {
743 void __iomem *ioaddr;
744 struct net_device *dev;
745 struct rtl8139_private *tp;
746 u8 tmp8;
747 int rc, disable_dev_on_err = 0;
748 unsigned int i;
749 unsigned long pio_start, pio_end, pio_flags, pio_len;
750 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
751 u32 version;
752
753 assert (pdev != NULL);
754
755 /* dev and priv zeroed in alloc_etherdev */
756 dev = alloc_etherdev (sizeof (*tp));
757 if (dev == NULL) {
758 dev_err(&pdev->dev, "Unable to alloc new net device\n");
759 return ERR_PTR(-ENOMEM);
760 }
761 SET_NETDEV_DEV(dev, &pdev->dev);
762
763 tp = netdev_priv(dev);
764 tp->pci_dev = pdev;
765
766 /* enable device (incl. PCI PM wakeup and hotplug setup) */
767 rc = pci_enable_device (pdev);
768 if (rc)
769 goto err_out;
770
771 pio_start = pci_resource_start (pdev, 0);
772 pio_end = pci_resource_end (pdev, 0);
773 pio_flags = pci_resource_flags (pdev, 0);
774 pio_len = pci_resource_len (pdev, 0);
775
776 mmio_start = pci_resource_start (pdev, 1);
777 mmio_end = pci_resource_end (pdev, 1);
778 mmio_flags = pci_resource_flags (pdev, 1);
779 mmio_len = pci_resource_len (pdev, 1);
780
781 /* set this immediately, we need to know before
782 * we talk to the chip directly */
783 pr_debug("PIO region size == 0x%02lX\n", pio_len);
784 pr_debug("MMIO region size == 0x%02lX\n", mmio_len);
785
786 retry:
787 if (use_io) {
788 /* make sure PCI base addr 0 is PIO */
789 if (!(pio_flags & IORESOURCE_IO)) {
790 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
791 rc = -ENODEV;
792 goto err_out;
793 }
794 /* check for weird/broken PCI region reporting */
795 if (pio_len < RTL_MIN_IO_SIZE) {
796 dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
797 rc = -ENODEV;
798 goto err_out;
799 }
800 } else {
801 /* make sure PCI base addr 1 is MMIO */
802 if (!(mmio_flags & IORESOURCE_MEM)) {
803 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
804 rc = -ENODEV;
805 goto err_out;
806 }
807 if (mmio_len < RTL_MIN_IO_SIZE) {
808 dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
809 rc = -ENODEV;
810 goto err_out;
811 }
812 }
813
814 rc = pci_request_regions (pdev, DRV_NAME);
815 if (rc)
816 goto err_out;
817 disable_dev_on_err = 1;
818
819 /* enable PCI bus-mastering */
820 pci_set_master (pdev);
821
822 if (use_io) {
823 ioaddr = pci_iomap(pdev, 0, 0);
824 if (!ioaddr) {
825 dev_err(&pdev->dev, "cannot map PIO, aborting\n");
826 rc = -EIO;
827 goto err_out;
828 }
829 dev->base_addr = pio_start;
830 tp->regs_len = pio_len;
831 } else {
832 /* ioremap MMIO region */
833 ioaddr = pci_iomap(pdev, 1, 0);
834 if (ioaddr == NULL) {
835 dev_err(&pdev->dev, "cannot remap MMIO, trying PIO\n");
836 pci_release_regions(pdev);
837 use_io = 1;
838 goto retry;
839 }
840 dev->base_addr = (long) ioaddr;
841 tp->regs_len = mmio_len;
842 }
843 tp->mmio_addr = ioaddr;
844
845 /* Bring old chips out of low-power mode. */
846 RTL_W8 (HltClk, 'R');
847
848 /* check for missing/broken hardware */
849 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
850 dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
851 rc = -EIO;
852 goto err_out;
853 }
854
855 /* identify chip attached to board */
856 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
857 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
858 if (version == rtl_chip_info[i].version) {
859 tp->chipset = i;
860 goto match;
861 }
862
863 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
864 i = 0;
865 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
866 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
867 tp->chipset = 0;
868
869 match:
870 pr_debug("chipset id (%d) == index %d, '%s'\n",
871 version, i, rtl_chip_info[i].name);
872
873 if (tp->chipset >= CH_8139B) {
874 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
875 pr_debug("PCI PM wakeup\n");
876 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
877 (tmp8 & LWAKE))
878 new_tmp8 &= ~LWAKE;
879 new_tmp8 |= Cfg1_PM_Enable;
880 if (new_tmp8 != tmp8) {
881 RTL_W8 (Cfg9346, Cfg9346_Unlock);
882 RTL_W8 (Config1, tmp8);
883 RTL_W8 (Cfg9346, Cfg9346_Lock);
884 }
885 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
886 tmp8 = RTL_R8 (Config4);
887 if (tmp8 & LWPTN) {
888 RTL_W8 (Cfg9346, Cfg9346_Unlock);
889 RTL_W8 (Config4, tmp8 & ~LWPTN);
890 RTL_W8 (Cfg9346, Cfg9346_Lock);
891 }
892 }
893 } else {
894 pr_debug("Old chip wakeup\n");
895 tmp8 = RTL_R8 (Config1);
896 tmp8 &= ~(SLEEP | PWRDN);
897 RTL_W8 (Config1, tmp8);
898 }
899
900 rtl8139_chip_reset (ioaddr);
901
902 return dev;
903
904 err_out:
905 __rtl8139_cleanup_dev (dev);
906 if (disable_dev_on_err)
907 pci_disable_device (pdev);
908 return ERR_PTR(rc);
909 }
910
911 static const struct net_device_ops rtl8139_netdev_ops = {
912 .ndo_open = rtl8139_open,
913 .ndo_stop = rtl8139_close,
914 .ndo_get_stats = rtl8139_get_stats,
915 .ndo_change_mtu = eth_change_mtu,
916 .ndo_validate_addr = eth_validate_addr,
917 .ndo_set_mac_address = rtl8139_set_mac_address,
918 .ndo_start_xmit = rtl8139_start_xmit,
919 .ndo_set_multicast_list = rtl8139_set_rx_mode,
920 .ndo_do_ioctl = netdev_ioctl,
921 .ndo_tx_timeout = rtl8139_tx_timeout,
922 #ifdef CONFIG_NET_POLL_CONTROLLER
923 .ndo_poll_controller = rtl8139_poll_controller,
924 #endif
925 };
926
927 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
928 const struct pci_device_id *ent)
929 {
930 struct net_device *dev = NULL;
931 struct rtl8139_private *tp;
932 int i, addr_len, option;
933 void __iomem *ioaddr;
934 static int board_idx = -1;
935
936 assert (pdev != NULL);
937 assert (ent != NULL);
938
939 board_idx++;
940
941 /* when we're built into the kernel, the driver version message
942 * is only printed if at least one 8139 board has been found
943 */
944 #ifndef MODULE
945 {
946 static int printed_version;
947 if (!printed_version++)
948 pr_info(RTL8139_DRIVER_NAME "\n");
949 }
950 #endif
951
952 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
953 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
954 dev_info(&pdev->dev,
955 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
956 pdev->vendor, pdev->device, pdev->revision);
957 return -ENODEV;
958 }
959
960 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
961 pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
962 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
963 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
964 pr_info("OQO Model 2 detected. Forcing PIO\n");
965 use_io = 1;
966 }
967
968 dev = rtl8139_init_board (pdev);
969 if (IS_ERR(dev))
970 return PTR_ERR(dev);
971
972 assert (dev != NULL);
973 tp = netdev_priv(dev);
974 tp->dev = dev;
975
976 ioaddr = tp->mmio_addr;
977 assert (ioaddr != NULL);
978
979 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
980 for (i = 0; i < 3; i++)
981 ((__le16 *) (dev->dev_addr))[i] =
982 cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
983 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
984
985 /* The Rtl8139-specific entries in the device structure. */
986 dev->netdev_ops = &rtl8139_netdev_ops;
987 dev->ethtool_ops = &rtl8139_ethtool_ops;
988 dev->watchdog_timeo = TX_TIMEOUT;
989 netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
990
991 /* note: the hardware is not capable of sg/csum/highdma, however
992 * through the use of skb_copy_and_csum_dev we enable these
993 * features
994 */
995 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
996
997 dev->irq = pdev->irq;
998
999 /* tp zeroed and aligned in alloc_etherdev */
1000 tp = netdev_priv(dev);
1001
1002 /* note: tp->chipset set in rtl8139_init_board */
1003 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1004 tp->mmio_addr = ioaddr;
1005 tp->msg_enable =
1006 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1007 spin_lock_init (&tp->lock);
1008 spin_lock_init (&tp->rx_lock);
1009 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1010 tp->mii.dev = dev;
1011 tp->mii.mdio_read = mdio_read;
1012 tp->mii.mdio_write = mdio_write;
1013 tp->mii.phy_id_mask = 0x3f;
1014 tp->mii.reg_num_mask = 0x1f;
1015
1016 /* dev is fully set up and ready to use now */
1017 pr_debug("about to register device named %s (%p)...\n",
1018 dev->name, dev);
1019 i = register_netdev (dev);
1020 if (i) goto err_out;
1021
1022 pci_set_drvdata (pdev, dev);
1023
1024 netdev_info(dev, "%s at 0x%lx, %pM, IRQ %d\n",
1025 board_info[ent->driver_data].name,
1026 dev->base_addr, dev->dev_addr, dev->irq);
1027
1028 netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1029 rtl_chip_info[tp->chipset].name);
1030
1031 /* Find the connected MII xcvrs.
1032 Doing this in open() would allow detecting external xcvrs later, but
1033 takes too much time. */
1034 #ifdef CONFIG_8139TOO_8129
1035 if (tp->drv_flags & HAS_MII_XCVR) {
1036 int phy, phy_idx = 0;
1037 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1038 int mii_status = mdio_read(dev, phy, 1);
1039 if (mii_status != 0xffff && mii_status != 0x0000) {
1040 u16 advertising = mdio_read(dev, phy, 4);
1041 tp->phys[phy_idx++] = phy;
1042 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1043 phy, mii_status, advertising);
1044 }
1045 }
1046 if (phy_idx == 0) {
1047 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1048 tp->phys[0] = 32;
1049 }
1050 } else
1051 #endif
1052 tp->phys[0] = 32;
1053 tp->mii.phy_id = tp->phys[0];
1054
1055 /* The lower four bits are the media type. */
1056 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1057 if (option > 0) {
1058 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1059 tp->default_port = option & 0xFF;
1060 if (tp->default_port)
1061 tp->mii.force_media = 1;
1062 }
1063 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1064 tp->mii.full_duplex = full_duplex[board_idx];
1065 if (tp->mii.full_duplex) {
1066 netdev_info(dev, "Media type forced to Full Duplex\n");
1067 /* Changing the MII-advertised media because might prevent
1068 re-connection. */
1069 tp->mii.force_media = 1;
1070 }
1071 if (tp->default_port) {
1072 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n",
1073 (option & 0x20 ? 100 : 10),
1074 (option & 0x10 ? "full" : "half"));
1075 mdio_write(dev, tp->phys[0], 0,
1076 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1077 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1078 }
1079
1080 /* Put the chip into low-power mode. */
1081 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1082 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1083
1084 return 0;
1085
1086 err_out:
1087 __rtl8139_cleanup_dev (dev);
1088 pci_disable_device (pdev);
1089 return i;
1090 }
1091
1092
1093 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1094 {
1095 struct net_device *dev = pci_get_drvdata (pdev);
1096 struct rtl8139_private *tp = netdev_priv(dev);
1097
1098 assert (dev != NULL);
1099
1100 cancel_delayed_work_sync(&tp->thread);
1101
1102 unregister_netdev (dev);
1103
1104 __rtl8139_cleanup_dev (dev);
1105 pci_disable_device (pdev);
1106 }
1107
1108
1109 /* Serial EEPROM section. */
1110
1111 /* EEPROM_Ctrl bits. */
1112 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1113 #define EE_CS 0x08 /* EEPROM chip select. */
1114 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1115 #define EE_WRITE_0 0x00
1116 #define EE_WRITE_1 0x02
1117 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1118 #define EE_ENB (0x80 | EE_CS)
1119
1120 /* Delay between EEPROM clock transitions.
1121 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1122 */
1123
1124 #define eeprom_delay() (void)RTL_R32(Cfg9346)
1125
1126 /* The EEPROM commands include the alway-set leading bit. */
1127 #define EE_WRITE_CMD (5)
1128 #define EE_READ_CMD (6)
1129 #define EE_ERASE_CMD (7)
1130
1131 static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1132 {
1133 int i;
1134 unsigned retval = 0;
1135 int read_cmd = location | (EE_READ_CMD << addr_len);
1136
1137 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1138 RTL_W8 (Cfg9346, EE_ENB);
1139 eeprom_delay ();
1140
1141 /* Shift the read command bits out. */
1142 for (i = 4 + addr_len; i >= 0; i--) {
1143 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1144 RTL_W8 (Cfg9346, EE_ENB | dataval);
1145 eeprom_delay ();
1146 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1147 eeprom_delay ();
1148 }
1149 RTL_W8 (Cfg9346, EE_ENB);
1150 eeprom_delay ();
1151
1152 for (i = 16; i > 0; i--) {
1153 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1154 eeprom_delay ();
1155 retval =
1156 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1157 0);
1158 RTL_W8 (Cfg9346, EE_ENB);
1159 eeprom_delay ();
1160 }
1161
1162 /* Terminate the EEPROM access. */
1163 RTL_W8 (Cfg9346, ~EE_CS);
1164 eeprom_delay ();
1165
1166 return retval;
1167 }
1168
1169 /* MII serial management: mostly bogus for now. */
1170 /* Read and write the MII management registers using software-generated
1171 serial MDIO protocol.
1172 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1173 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1174 "overclocking" issues. */
1175 #define MDIO_DIR 0x80
1176 #define MDIO_DATA_OUT 0x04
1177 #define MDIO_DATA_IN 0x02
1178 #define MDIO_CLK 0x01
1179 #define MDIO_WRITE0 (MDIO_DIR)
1180 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1181
1182 #define mdio_delay() RTL_R8(Config4)
1183
1184
1185 static const char mii_2_8139_map[8] = {
1186 BasicModeCtrl,
1187 BasicModeStatus,
1188 0,
1189 0,
1190 NWayAdvert,
1191 NWayLPAR,
1192 NWayExpansion,
1193 0
1194 };
1195
1196
1197 #ifdef CONFIG_8139TOO_8129
1198 /* Syncronize the MII management interface by shifting 32 one bits out. */
1199 static void mdio_sync (void __iomem *ioaddr)
1200 {
1201 int i;
1202
1203 for (i = 32; i >= 0; i--) {
1204 RTL_W8 (Config4, MDIO_WRITE1);
1205 mdio_delay ();
1206 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1207 mdio_delay ();
1208 }
1209 }
1210 #endif
1211
1212 static int mdio_read (struct net_device *dev, int phy_id, int location)
1213 {
1214 struct rtl8139_private *tp = netdev_priv(dev);
1215 int retval = 0;
1216 #ifdef CONFIG_8139TOO_8129
1217 void __iomem *ioaddr = tp->mmio_addr;
1218 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1219 int i;
1220 #endif
1221
1222 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1223 void __iomem *ioaddr = tp->mmio_addr;
1224 return location < 8 && mii_2_8139_map[location] ?
1225 RTL_R16 (mii_2_8139_map[location]) : 0;
1226 }
1227
1228 #ifdef CONFIG_8139TOO_8129
1229 mdio_sync (ioaddr);
1230 /* Shift the read command bits out. */
1231 for (i = 15; i >= 0; i--) {
1232 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1233
1234 RTL_W8 (Config4, MDIO_DIR | dataval);
1235 mdio_delay ();
1236 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1237 mdio_delay ();
1238 }
1239
1240 /* Read the two transition, 16 data, and wire-idle bits. */
1241 for (i = 19; i > 0; i--) {
1242 RTL_W8 (Config4, 0);
1243 mdio_delay ();
1244 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1245 RTL_W8 (Config4, MDIO_CLK);
1246 mdio_delay ();
1247 }
1248 #endif
1249
1250 return (retval >> 1) & 0xffff;
1251 }
1252
1253
1254 static void mdio_write (struct net_device *dev, int phy_id, int location,
1255 int value)
1256 {
1257 struct rtl8139_private *tp = netdev_priv(dev);
1258 #ifdef CONFIG_8139TOO_8129
1259 void __iomem *ioaddr = tp->mmio_addr;
1260 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1261 int i;
1262 #endif
1263
1264 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1265 void __iomem *ioaddr = tp->mmio_addr;
1266 if (location == 0) {
1267 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1268 RTL_W16 (BasicModeCtrl, value);
1269 RTL_W8 (Cfg9346, Cfg9346_Lock);
1270 } else if (location < 8 && mii_2_8139_map[location])
1271 RTL_W16 (mii_2_8139_map[location], value);
1272 return;
1273 }
1274
1275 #ifdef CONFIG_8139TOO_8129
1276 mdio_sync (ioaddr);
1277
1278 /* Shift the command bits out. */
1279 for (i = 31; i >= 0; i--) {
1280 int dataval =
1281 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1282 RTL_W8 (Config4, dataval);
1283 mdio_delay ();
1284 RTL_W8 (Config4, dataval | MDIO_CLK);
1285 mdio_delay ();
1286 }
1287 /* Clear out extra bits. */
1288 for (i = 2; i > 0; i--) {
1289 RTL_W8 (Config4, 0);
1290 mdio_delay ();
1291 RTL_W8 (Config4, MDIO_CLK);
1292 mdio_delay ();
1293 }
1294 #endif
1295 }
1296
1297
1298 static int rtl8139_open (struct net_device *dev)
1299 {
1300 struct rtl8139_private *tp = netdev_priv(dev);
1301 int retval;
1302 void __iomem *ioaddr = tp->mmio_addr;
1303
1304 retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1305 if (retval)
1306 return retval;
1307
1308 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1309 &tp->tx_bufs_dma, GFP_KERNEL);
1310 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1311 &tp->rx_ring_dma, GFP_KERNEL);
1312 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1313 free_irq(dev->irq, dev);
1314
1315 if (tp->tx_bufs)
1316 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1317 tp->tx_bufs, tp->tx_bufs_dma);
1318 if (tp->rx_ring)
1319 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1320 tp->rx_ring, tp->rx_ring_dma);
1321
1322 return -ENOMEM;
1323
1324 }
1325
1326 napi_enable(&tp->napi);
1327
1328 tp->mii.full_duplex = tp->mii.force_media;
1329 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1330
1331 rtl8139_init_ring (dev);
1332 rtl8139_hw_start (dev);
1333 netif_start_queue (dev);
1334
1335 netif_dbg(tp, ifup, dev,
1336 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1337 __func__,
1338 (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1339 dev->irq, RTL_R8 (MediaStatus),
1340 tp->mii.full_duplex ? "full" : "half");
1341
1342 rtl8139_start_thread(tp);
1343
1344 return 0;
1345 }
1346
1347
1348 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1349 {
1350 struct rtl8139_private *tp = netdev_priv(dev);
1351
1352 if (tp->phys[0] >= 0) {
1353 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1354 }
1355 }
1356
1357 /* Start the hardware at open or resume. */
1358 static void rtl8139_hw_start (struct net_device *dev)
1359 {
1360 struct rtl8139_private *tp = netdev_priv(dev);
1361 void __iomem *ioaddr = tp->mmio_addr;
1362 u32 i;
1363 u8 tmp;
1364
1365 /* Bring old chips out of low-power mode. */
1366 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1367 RTL_W8 (HltClk, 'R');
1368
1369 rtl8139_chip_reset (ioaddr);
1370
1371 /* unlock Config[01234] and BMCR register writes */
1372 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1373 /* Restore our idea of the MAC address. */
1374 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1375 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1376
1377 tp->cur_rx = 0;
1378
1379 /* init Rx ring buffer DMA address */
1380 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1381
1382 /* Must enable Tx/Rx before setting transfer thresholds! */
1383 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1384
1385 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1386 RTL_W32 (RxConfig, tp->rx_config);
1387 RTL_W32 (TxConfig, rtl8139_tx_config);
1388
1389 rtl_check_media (dev, 1);
1390
1391 if (tp->chipset >= CH_8139B) {
1392 /* Disable magic packet scanning, which is enabled
1393 * when PM is enabled in Config1. It can be reenabled
1394 * via ETHTOOL_SWOL if desired. */
1395 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1396 }
1397
1398 netdev_dbg(dev, "init buffer addresses\n");
1399
1400 /* Lock Config[01234] and BMCR register writes */
1401 RTL_W8 (Cfg9346, Cfg9346_Lock);
1402
1403 /* init Tx buffer DMA addresses */
1404 for (i = 0; i < NUM_TX_DESC; i++)
1405 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1406
1407 RTL_W32 (RxMissed, 0);
1408
1409 rtl8139_set_rx_mode (dev);
1410
1411 /* no early-rx interrupts */
1412 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1413
1414 /* make sure RxTx has started */
1415 tmp = RTL_R8 (ChipCmd);
1416 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1417 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1418
1419 /* Enable all known interrupts by setting the interrupt mask. */
1420 RTL_W16 (IntrMask, rtl8139_intr_mask);
1421 }
1422
1423
1424 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1425 static void rtl8139_init_ring (struct net_device *dev)
1426 {
1427 struct rtl8139_private *tp = netdev_priv(dev);
1428 int i;
1429
1430 tp->cur_rx = 0;
1431 tp->cur_tx = 0;
1432 tp->dirty_tx = 0;
1433
1434 for (i = 0; i < NUM_TX_DESC; i++)
1435 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1436 }
1437
1438
1439 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1440 static int next_tick = 3 * HZ;
1441
1442 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1443 static inline void rtl8139_tune_twister (struct net_device *dev,
1444 struct rtl8139_private *tp) {}
1445 #else
1446 enum TwisterParamVals {
1447 PARA78_default = 0x78fa8388,
1448 PARA7c_default = 0xcb38de43, /* param[0][3] */
1449 PARA7c_xxx = 0xcb38de43,
1450 };
1451
1452 static const unsigned long param[4][4] = {
1453 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1454 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1455 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1456 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1457 };
1458
1459 static void rtl8139_tune_twister (struct net_device *dev,
1460 struct rtl8139_private *tp)
1461 {
1462 int linkcase;
1463 void __iomem *ioaddr = tp->mmio_addr;
1464
1465 /* This is a complicated state machine to configure the "twister" for
1466 impedance/echos based on the cable length.
1467 All of this is magic and undocumented.
1468 */
1469 switch (tp->twistie) {
1470 case 1:
1471 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1472 /* We have link beat, let us tune the twister. */
1473 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1474 tp->twistie = 2; /* Change to state 2. */
1475 next_tick = HZ / 10;
1476 } else {
1477 /* Just put in some reasonable defaults for when beat returns. */
1478 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1479 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1480 RTL_W32 (PARA78, PARA78_default);
1481 RTL_W32 (PARA7c, PARA7c_default);
1482 tp->twistie = 0; /* Bail from future actions. */
1483 }
1484 break;
1485 case 2:
1486 /* Read how long it took to hear the echo. */
1487 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1488 if (linkcase == 0x7000)
1489 tp->twist_row = 3;
1490 else if (linkcase == 0x3000)
1491 tp->twist_row = 2;
1492 else if (linkcase == 0x1000)
1493 tp->twist_row = 1;
1494 else
1495 tp->twist_row = 0;
1496 tp->twist_col = 0;
1497 tp->twistie = 3; /* Change to state 2. */
1498 next_tick = HZ / 10;
1499 break;
1500 case 3:
1501 /* Put out four tuning parameters, one per 100msec. */
1502 if (tp->twist_col == 0)
1503 RTL_W16 (FIFOTMS, 0);
1504 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1505 [(int) tp->twist_col]);
1506 next_tick = HZ / 10;
1507 if (++tp->twist_col >= 4) {
1508 /* For short cables we are done.
1509 For long cables (row == 3) check for mistune. */
1510 tp->twistie =
1511 (tp->twist_row == 3) ? 4 : 0;
1512 }
1513 break;
1514 case 4:
1515 /* Special case for long cables: check for mistune. */
1516 if ((RTL_R16 (CSCR) &
1517 CSCR_LinkStatusBits) == 0x7000) {
1518 tp->twistie = 0;
1519 break;
1520 } else {
1521 RTL_W32 (PARA7c, 0xfb38de03);
1522 tp->twistie = 5;
1523 next_tick = HZ / 10;
1524 }
1525 break;
1526 case 5:
1527 /* Retune for shorter cable (column 2). */
1528 RTL_W32 (FIFOTMS, 0x20);
1529 RTL_W32 (PARA78, PARA78_default);
1530 RTL_W32 (PARA7c, PARA7c_default);
1531 RTL_W32 (FIFOTMS, 0x00);
1532 tp->twist_row = 2;
1533 tp->twist_col = 0;
1534 tp->twistie = 3;
1535 next_tick = HZ / 10;
1536 break;
1537
1538 default:
1539 /* do nothing */
1540 break;
1541 }
1542 }
1543 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1544
1545 static inline void rtl8139_thread_iter (struct net_device *dev,
1546 struct rtl8139_private *tp,
1547 void __iomem *ioaddr)
1548 {
1549 int mii_lpa;
1550
1551 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1552
1553 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1554 int duplex = ((mii_lpa & LPA_100FULL) ||
1555 (mii_lpa & 0x01C0) == 0x0040);
1556 if (tp->mii.full_duplex != duplex) {
1557 tp->mii.full_duplex = duplex;
1558
1559 if (mii_lpa) {
1560 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1561 tp->mii.full_duplex ? "full" : "half",
1562 tp->phys[0], mii_lpa);
1563 } else {
1564 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1565 }
1566 #if 0
1567 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1568 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1569 RTL_W8 (Cfg9346, Cfg9346_Lock);
1570 #endif
1571 }
1572 }
1573
1574 next_tick = HZ * 60;
1575
1576 rtl8139_tune_twister (dev, tp);
1577
1578 netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1579 RTL_R16(NWayLPAR));
1580 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1581 RTL_R16(IntrMask), RTL_R16(IntrStatus));
1582 netdev_dbg(dev, "Chip config %02x %02x\n",
1583 RTL_R8(Config0), RTL_R8(Config1));
1584 }
1585
1586 static void rtl8139_thread (struct work_struct *work)
1587 {
1588 struct rtl8139_private *tp =
1589 container_of(work, struct rtl8139_private, thread.work);
1590 struct net_device *dev = tp->mii.dev;
1591 unsigned long thr_delay = next_tick;
1592
1593 rtnl_lock();
1594
1595 if (!netif_running(dev))
1596 goto out_unlock;
1597
1598 if (tp->watchdog_fired) {
1599 tp->watchdog_fired = 0;
1600 rtl8139_tx_timeout_task(work);
1601 } else
1602 rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1603
1604 if (tp->have_thread)
1605 schedule_delayed_work(&tp->thread, thr_delay);
1606 out_unlock:
1607 rtnl_unlock ();
1608 }
1609
1610 static void rtl8139_start_thread(struct rtl8139_private *tp)
1611 {
1612 tp->twistie = 0;
1613 if (tp->chipset == CH_8139_K)
1614 tp->twistie = 1;
1615 else if (tp->drv_flags & HAS_LNK_CHNG)
1616 return;
1617
1618 tp->have_thread = 1;
1619 tp->watchdog_fired = 0;
1620
1621 schedule_delayed_work(&tp->thread, next_tick);
1622 }
1623
1624 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1625 {
1626 tp->cur_tx = 0;
1627 tp->dirty_tx = 0;
1628
1629 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1630 }
1631
1632 static void rtl8139_tx_timeout_task (struct work_struct *work)
1633 {
1634 struct rtl8139_private *tp =
1635 container_of(work, struct rtl8139_private, thread.work);
1636 struct net_device *dev = tp->mii.dev;
1637 void __iomem *ioaddr = tp->mmio_addr;
1638 int i;
1639 u8 tmp8;
1640
1641 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1642 RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1643 RTL_R16(IntrMask), RTL_R8(MediaStatus));
1644 /* Emit info to figure out what went wrong. */
1645 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n",
1646 tp->cur_tx, tp->dirty_tx);
1647 for (i = 0; i < NUM_TX_DESC; i++)
1648 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1649 i, RTL_R32(TxStatus0 + (i * 4)),
1650 i == tp->dirty_tx % NUM_TX_DESC ?
1651 " (queue head)" : "");
1652
1653 tp->xstats.tx_timeouts++;
1654
1655 /* disable Tx ASAP, if not already */
1656 tmp8 = RTL_R8 (ChipCmd);
1657 if (tmp8 & CmdTxEnb)
1658 RTL_W8 (ChipCmd, CmdRxEnb);
1659
1660 spin_lock_bh(&tp->rx_lock);
1661 /* Disable interrupts by clearing the interrupt mask. */
1662 RTL_W16 (IntrMask, 0x0000);
1663
1664 /* Stop a shared interrupt from scavenging while we are. */
1665 spin_lock_irq(&tp->lock);
1666 rtl8139_tx_clear (tp);
1667 spin_unlock_irq(&tp->lock);
1668
1669 /* ...and finally, reset everything */
1670 if (netif_running(dev)) {
1671 rtl8139_hw_start (dev);
1672 netif_wake_queue (dev);
1673 }
1674 spin_unlock_bh(&tp->rx_lock);
1675 }
1676
1677 static void rtl8139_tx_timeout (struct net_device *dev)
1678 {
1679 struct rtl8139_private *tp = netdev_priv(dev);
1680
1681 tp->watchdog_fired = 1;
1682 if (!tp->have_thread) {
1683 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1684 schedule_delayed_work(&tp->thread, next_tick);
1685 }
1686 }
1687
1688 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1689 struct net_device *dev)
1690 {
1691 struct rtl8139_private *tp = netdev_priv(dev);
1692 void __iomem *ioaddr = tp->mmio_addr;
1693 unsigned int entry;
1694 unsigned int len = skb->len;
1695 unsigned long flags;
1696
1697 /* Calculate the next Tx descriptor entry. */
1698 entry = tp->cur_tx % NUM_TX_DESC;
1699
1700 /* Note: the chip doesn't have auto-pad! */
1701 if (likely(len < TX_BUF_SIZE)) {
1702 if (len < ETH_ZLEN)
1703 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1704 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1705 dev_kfree_skb(skb);
1706 } else {
1707 dev_kfree_skb(skb);
1708 dev->stats.tx_dropped++;
1709 return NETDEV_TX_OK;
1710 }
1711
1712 spin_lock_irqsave(&tp->lock, flags);
1713 /*
1714 * Writing to TxStatus triggers a DMA transfer of the data
1715 * copied to tp->tx_buf[entry] above. Use a memory barrier
1716 * to make sure that the device sees the updated data.
1717 */
1718 wmb();
1719 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1720 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1721
1722 tp->cur_tx++;
1723
1724 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1725 netif_stop_queue (dev);
1726 spin_unlock_irqrestore(&tp->lock, flags);
1727
1728 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1729 len, entry);
1730
1731 return NETDEV_TX_OK;
1732 }
1733
1734
1735 static void rtl8139_tx_interrupt (struct net_device *dev,
1736 struct rtl8139_private *tp,
1737 void __iomem *ioaddr)
1738 {
1739 unsigned long dirty_tx, tx_left;
1740
1741 assert (dev != NULL);
1742 assert (ioaddr != NULL);
1743
1744 dirty_tx = tp->dirty_tx;
1745 tx_left = tp->cur_tx - dirty_tx;
1746 while (tx_left > 0) {
1747 int entry = dirty_tx % NUM_TX_DESC;
1748 int txstatus;
1749
1750 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1751
1752 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1753 break; /* It still hasn't been Txed */
1754
1755 /* Note: TxCarrierLost is always asserted at 100mbps. */
1756 if (txstatus & (TxOutOfWindow | TxAborted)) {
1757 /* There was an major error, log it. */
1758 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1759 txstatus);
1760 dev->stats.tx_errors++;
1761 if (txstatus & TxAborted) {
1762 dev->stats.tx_aborted_errors++;
1763 RTL_W32 (TxConfig, TxClearAbt);
1764 RTL_W16 (IntrStatus, TxErr);
1765 wmb();
1766 }
1767 if (txstatus & TxCarrierLost)
1768 dev->stats.tx_carrier_errors++;
1769 if (txstatus & TxOutOfWindow)
1770 dev->stats.tx_window_errors++;
1771 } else {
1772 if (txstatus & TxUnderrun) {
1773 /* Add 64 to the Tx FIFO threshold. */
1774 if (tp->tx_flag < 0x00300000)
1775 tp->tx_flag += 0x00020000;
1776 dev->stats.tx_fifo_errors++;
1777 }
1778 dev->stats.collisions += (txstatus >> 24) & 15;
1779 dev->stats.tx_bytes += txstatus & 0x7ff;
1780 dev->stats.tx_packets++;
1781 }
1782
1783 dirty_tx++;
1784 tx_left--;
1785 }
1786
1787 #ifndef RTL8139_NDEBUG
1788 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1789 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1790 dirty_tx, tp->cur_tx);
1791 dirty_tx += NUM_TX_DESC;
1792 }
1793 #endif /* RTL8139_NDEBUG */
1794
1795 /* only wake the queue if we did work, and the queue is stopped */
1796 if (tp->dirty_tx != dirty_tx) {
1797 tp->dirty_tx = dirty_tx;
1798 mb();
1799 netif_wake_queue (dev);
1800 }
1801 }
1802
1803
1804 /* TODO: clean this up! Rx reset need not be this intensive */
1805 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1806 struct rtl8139_private *tp, void __iomem *ioaddr)
1807 {
1808 u8 tmp8;
1809 #ifdef CONFIG_8139_OLD_RX_RESET
1810 int tmp_work;
1811 #endif
1812
1813 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1814 rx_status);
1815 dev->stats.rx_errors++;
1816 if (!(rx_status & RxStatusOK)) {
1817 if (rx_status & RxTooLong) {
1818 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1819 rx_status);
1820 /* A.C.: The chip hangs here. */
1821 }
1822 if (rx_status & (RxBadSymbol | RxBadAlign))
1823 dev->stats.rx_frame_errors++;
1824 if (rx_status & (RxRunt | RxTooLong))
1825 dev->stats.rx_length_errors++;
1826 if (rx_status & RxCRCErr)
1827 dev->stats.rx_crc_errors++;
1828 } else {
1829 tp->xstats.rx_lost_in_ring++;
1830 }
1831
1832 #ifndef CONFIG_8139_OLD_RX_RESET
1833 tmp8 = RTL_R8 (ChipCmd);
1834 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1835 RTL_W8 (ChipCmd, tmp8);
1836 RTL_W32 (RxConfig, tp->rx_config);
1837 tp->cur_rx = 0;
1838 #else
1839 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1840
1841 /* disable receive */
1842 RTL_W8_F (ChipCmd, CmdTxEnb);
1843 tmp_work = 200;
1844 while (--tmp_work > 0) {
1845 udelay(1);
1846 tmp8 = RTL_R8 (ChipCmd);
1847 if (!(tmp8 & CmdRxEnb))
1848 break;
1849 }
1850 if (tmp_work <= 0)
1851 netdev_warn(dev, "rx stop wait too long\n");
1852 /* restart receive */
1853 tmp_work = 200;
1854 while (--tmp_work > 0) {
1855 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1856 udelay(1);
1857 tmp8 = RTL_R8 (ChipCmd);
1858 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1859 break;
1860 }
1861 if (tmp_work <= 0)
1862 netdev_warn(dev, "tx/rx enable wait too long\n");
1863
1864 /* and reinitialize all rx related registers */
1865 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1866 /* Must enable Tx/Rx before setting transfer thresholds! */
1867 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1868
1869 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1870 RTL_W32 (RxConfig, tp->rx_config);
1871 tp->cur_rx = 0;
1872
1873 netdev_dbg(dev, "init buffer addresses\n");
1874
1875 /* Lock Config[01234] and BMCR register writes */
1876 RTL_W8 (Cfg9346, Cfg9346_Lock);
1877
1878 /* init Rx ring buffer DMA address */
1879 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1880
1881 /* A.C.: Reset the multicast list. */
1882 __set_rx_mode (dev);
1883 #endif
1884 }
1885
1886 #if RX_BUF_IDX == 3
1887 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1888 u32 offset, unsigned int size)
1889 {
1890 u32 left = RX_BUF_LEN - offset;
1891
1892 if (size > left) {
1893 skb_copy_to_linear_data(skb, ring + offset, left);
1894 skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1895 } else
1896 skb_copy_to_linear_data(skb, ring + offset, size);
1897 }
1898 #endif
1899
1900 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1901 {
1902 void __iomem *ioaddr = tp->mmio_addr;
1903 u16 status;
1904
1905 status = RTL_R16 (IntrStatus) & RxAckBits;
1906
1907 /* Clear out errors and receive interrupts */
1908 if (likely(status != 0)) {
1909 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1910 tp->dev->stats.rx_errors++;
1911 if (status & RxFIFOOver)
1912 tp->dev->stats.rx_fifo_errors++;
1913 }
1914 RTL_W16_F (IntrStatus, RxAckBits);
1915 }
1916 }
1917
1918 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1919 int budget)
1920 {
1921 void __iomem *ioaddr = tp->mmio_addr;
1922 int received = 0;
1923 unsigned char *rx_ring = tp->rx_ring;
1924 unsigned int cur_rx = tp->cur_rx;
1925 unsigned int rx_size = 0;
1926
1927 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1928 __func__, (u16)cur_rx,
1929 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1930
1931 while (netif_running(dev) && received < budget &&
1932 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1933 u32 ring_offset = cur_rx % RX_BUF_LEN;
1934 u32 rx_status;
1935 unsigned int pkt_size;
1936 struct sk_buff *skb;
1937
1938 rmb();
1939
1940 /* read size+status of next frame from DMA ring buffer */
1941 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1942 rx_size = rx_status >> 16;
1943 pkt_size = rx_size - 4;
1944
1945 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1946 __func__, rx_status, rx_size, cur_rx);
1947 #if RTL8139_DEBUG > 2
1948 print_hex_dump(KERN_DEBUG, "Frame contents: ",
1949 DUMP_PREFIX_OFFSET, 16, 1,
1950 &rx_ring[ring_offset], 70, true);
1951 #endif
1952
1953 /* Packet copy from FIFO still in progress.
1954 * Theoretically, this should never happen
1955 * since EarlyRx is disabled.
1956 */
1957 if (unlikely(rx_size == 0xfff0)) {
1958 if (!tp->fifo_copy_timeout)
1959 tp->fifo_copy_timeout = jiffies + 2;
1960 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1961 netdev_dbg(dev, "hung FIFO. Reset\n");
1962 rx_size = 0;
1963 goto no_early_rx;
1964 }
1965 netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1966 tp->xstats.early_rx++;
1967 break;
1968 }
1969
1970 no_early_rx:
1971 tp->fifo_copy_timeout = 0;
1972
1973 /* If Rx err or invalid rx_size/rx_status received
1974 * (which happens if we get lost in the ring),
1975 * Rx process gets reset, so we abort any further
1976 * Rx processing.
1977 */
1978 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1979 (rx_size < 8) ||
1980 (!(rx_status & RxStatusOK)))) {
1981 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
1982 received = -1;
1983 goto out;
1984 }
1985
1986 /* Malloc up new buffer, compatible with net-2e. */
1987 /* Omit the four octet CRC from the length. */
1988
1989 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
1990 if (likely(skb)) {
1991 #if RX_BUF_IDX == 3
1992 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
1993 #else
1994 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1995 #endif
1996 skb_put (skb, pkt_size);
1997
1998 skb->protocol = eth_type_trans (skb, dev);
1999
2000 dev->stats.rx_bytes += pkt_size;
2001 dev->stats.rx_packets++;
2002
2003 netif_receive_skb (skb);
2004 } else {
2005 if (net_ratelimit())
2006 netdev_warn(dev, "Memory squeeze, dropping packet\n");
2007 dev->stats.rx_dropped++;
2008 }
2009 received++;
2010
2011 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2012 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2013
2014 rtl8139_isr_ack(tp);
2015 }
2016
2017 if (unlikely(!received || rx_size == 0xfff0))
2018 rtl8139_isr_ack(tp);
2019
2020 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2021 __func__, cur_rx,
2022 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2023
2024 tp->cur_rx = cur_rx;
2025
2026 /*
2027 * The receive buffer should be mostly empty.
2028 * Tell NAPI to reenable the Rx irq.
2029 */
2030 if (tp->fifo_copy_timeout)
2031 received = budget;
2032
2033 out:
2034 return received;
2035 }
2036
2037
2038 static void rtl8139_weird_interrupt (struct net_device *dev,
2039 struct rtl8139_private *tp,
2040 void __iomem *ioaddr,
2041 int status, int link_changed)
2042 {
2043 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2044
2045 assert (dev != NULL);
2046 assert (tp != NULL);
2047 assert (ioaddr != NULL);
2048
2049 /* Update the error count. */
2050 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2051 RTL_W32 (RxMissed, 0);
2052
2053 if ((status & RxUnderrun) && link_changed &&
2054 (tp->drv_flags & HAS_LNK_CHNG)) {
2055 rtl_check_media(dev, 0);
2056 status &= ~RxUnderrun;
2057 }
2058
2059 if (status & (RxUnderrun | RxErr))
2060 dev->stats.rx_errors++;
2061
2062 if (status & PCSTimeout)
2063 dev->stats.rx_length_errors++;
2064 if (status & RxUnderrun)
2065 dev->stats.rx_fifo_errors++;
2066 if (status & PCIErr) {
2067 u16 pci_cmd_status;
2068 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2069 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2070
2071 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2072 }
2073 }
2074
2075 static int rtl8139_poll(struct napi_struct *napi, int budget)
2076 {
2077 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2078 struct net_device *dev = tp->dev;
2079 void __iomem *ioaddr = tp->mmio_addr;
2080 int work_done;
2081
2082 spin_lock(&tp->rx_lock);
2083 work_done = 0;
2084 if (likely(RTL_R16(IntrStatus) & RxAckBits))
2085 work_done += rtl8139_rx(dev, tp, budget);
2086
2087 if (work_done < budget) {
2088 unsigned long flags;
2089 /*
2090 * Order is important since data can get interrupted
2091 * again when we think we are done.
2092 */
2093 spin_lock_irqsave(&tp->lock, flags);
2094 __napi_complete(napi);
2095 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2096 spin_unlock_irqrestore(&tp->lock, flags);
2097 }
2098 spin_unlock(&tp->rx_lock);
2099
2100 return work_done;
2101 }
2102
2103 /* The interrupt handler does all of the Rx thread work and cleans up
2104 after the Tx thread. */
2105 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2106 {
2107 struct net_device *dev = (struct net_device *) dev_instance;
2108 struct rtl8139_private *tp = netdev_priv(dev);
2109 void __iomem *ioaddr = tp->mmio_addr;
2110 u16 status, ackstat;
2111 int link_changed = 0; /* avoid bogus "uninit" warning */
2112 int handled = 0;
2113
2114 spin_lock (&tp->lock);
2115 status = RTL_R16 (IntrStatus);
2116
2117 /* shared irq? */
2118 if (unlikely((status & rtl8139_intr_mask) == 0))
2119 goto out;
2120
2121 handled = 1;
2122
2123 /* h/w no longer present (hotplug?) or major error, bail */
2124 if (unlikely(status == 0xFFFF))
2125 goto out;
2126
2127 /* close possible race's with dev_close */
2128 if (unlikely(!netif_running(dev))) {
2129 RTL_W16 (IntrMask, 0);
2130 goto out;
2131 }
2132
2133 /* Acknowledge all of the current interrupt sources ASAP, but
2134 an first get an additional status bit from CSCR. */
2135 if (unlikely(status & RxUnderrun))
2136 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2137
2138 ackstat = status & ~(RxAckBits | TxErr);
2139 if (ackstat)
2140 RTL_W16 (IntrStatus, ackstat);
2141
2142 /* Receive packets are processed by poll routine.
2143 If not running start it now. */
2144 if (status & RxAckBits){
2145 if (napi_schedule_prep(&tp->napi)) {
2146 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2147 __napi_schedule(&tp->napi);
2148 }
2149 }
2150
2151 /* Check uncommon events with one test. */
2152 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2153 rtl8139_weird_interrupt (dev, tp, ioaddr,
2154 status, link_changed);
2155
2156 if (status & (TxOK | TxErr)) {
2157 rtl8139_tx_interrupt (dev, tp, ioaddr);
2158 if (status & TxErr)
2159 RTL_W16 (IntrStatus, TxErr);
2160 }
2161 out:
2162 spin_unlock (&tp->lock);
2163
2164 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2165 RTL_R16(IntrStatus));
2166 return IRQ_RETVAL(handled);
2167 }
2168
2169 #ifdef CONFIG_NET_POLL_CONTROLLER
2170 /*
2171 * Polling receive - used by netconsole and other diagnostic tools
2172 * to allow network i/o with interrupts disabled.
2173 */
2174 static void rtl8139_poll_controller(struct net_device *dev)
2175 {
2176 disable_irq(dev->irq);
2177 rtl8139_interrupt(dev->irq, dev);
2178 enable_irq(dev->irq);
2179 }
2180 #endif
2181
2182 static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2183 {
2184 struct rtl8139_private *tp = netdev_priv(dev);
2185 void __iomem *ioaddr = tp->mmio_addr;
2186 struct sockaddr *addr = p;
2187
2188 if (!is_valid_ether_addr(addr->sa_data))
2189 return -EADDRNOTAVAIL;
2190
2191 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2192
2193 spin_lock_irq(&tp->lock);
2194
2195 RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2196 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2197 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2198 RTL_W8_F(Cfg9346, Cfg9346_Lock);
2199
2200 spin_unlock_irq(&tp->lock);
2201
2202 return 0;
2203 }
2204
2205 static int rtl8139_close (struct net_device *dev)
2206 {
2207 struct rtl8139_private *tp = netdev_priv(dev);
2208 void __iomem *ioaddr = tp->mmio_addr;
2209 unsigned long flags;
2210
2211 netif_stop_queue(dev);
2212 napi_disable(&tp->napi);
2213
2214 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2215 RTL_R16(IntrStatus));
2216
2217 spin_lock_irqsave (&tp->lock, flags);
2218
2219 /* Stop the chip's Tx and Rx DMA processes. */
2220 RTL_W8 (ChipCmd, 0);
2221
2222 /* Disable interrupts by clearing the interrupt mask. */
2223 RTL_W16 (IntrMask, 0);
2224
2225 /* Update the error counts. */
2226 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2227 RTL_W32 (RxMissed, 0);
2228
2229 spin_unlock_irqrestore (&tp->lock, flags);
2230
2231 free_irq (dev->irq, dev);
2232
2233 rtl8139_tx_clear (tp);
2234
2235 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2236 tp->rx_ring, tp->rx_ring_dma);
2237 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2238 tp->tx_bufs, tp->tx_bufs_dma);
2239 tp->rx_ring = NULL;
2240 tp->tx_bufs = NULL;
2241
2242 /* Green! Put the chip in low-power mode. */
2243 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2244
2245 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2246 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2247
2248 return 0;
2249 }
2250
2251
2252 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2253 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2254 other threads or interrupts aren't messing with the 8139. */
2255 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2256 {
2257 struct rtl8139_private *tp = netdev_priv(dev);
2258 void __iomem *ioaddr = tp->mmio_addr;
2259
2260 spin_lock_irq(&tp->lock);
2261 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2262 u8 cfg3 = RTL_R8 (Config3);
2263 u8 cfg5 = RTL_R8 (Config5);
2264
2265 wol->supported = WAKE_PHY | WAKE_MAGIC
2266 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2267
2268 wol->wolopts = 0;
2269 if (cfg3 & Cfg3_LinkUp)
2270 wol->wolopts |= WAKE_PHY;
2271 if (cfg3 & Cfg3_Magic)
2272 wol->wolopts |= WAKE_MAGIC;
2273 /* (KON)FIXME: See how netdev_set_wol() handles the
2274 following constants. */
2275 if (cfg5 & Cfg5_UWF)
2276 wol->wolopts |= WAKE_UCAST;
2277 if (cfg5 & Cfg5_MWF)
2278 wol->wolopts |= WAKE_MCAST;
2279 if (cfg5 & Cfg5_BWF)
2280 wol->wolopts |= WAKE_BCAST;
2281 }
2282 spin_unlock_irq(&tp->lock);
2283 }
2284
2285
2286 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2287 that wol points to kernel memory and other threads or interrupts
2288 aren't messing with the 8139. */
2289 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2290 {
2291 struct rtl8139_private *tp = netdev_priv(dev);
2292 void __iomem *ioaddr = tp->mmio_addr;
2293 u32 support;
2294 u8 cfg3, cfg5;
2295
2296 support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2297 ? (WAKE_PHY | WAKE_MAGIC
2298 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2299 : 0);
2300 if (wol->wolopts & ~support)
2301 return -EINVAL;
2302
2303 spin_lock_irq(&tp->lock);
2304 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2305 if (wol->wolopts & WAKE_PHY)
2306 cfg3 |= Cfg3_LinkUp;
2307 if (wol->wolopts & WAKE_MAGIC)
2308 cfg3 |= Cfg3_Magic;
2309 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2310 RTL_W8 (Config3, cfg3);
2311 RTL_W8 (Cfg9346, Cfg9346_Lock);
2312
2313 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2314 /* (KON)FIXME: These are untested. We may have to set the
2315 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2316 documentation. */
2317 if (wol->wolopts & WAKE_UCAST)
2318 cfg5 |= Cfg5_UWF;
2319 if (wol->wolopts & WAKE_MCAST)
2320 cfg5 |= Cfg5_MWF;
2321 if (wol->wolopts & WAKE_BCAST)
2322 cfg5 |= Cfg5_BWF;
2323 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2324 spin_unlock_irq(&tp->lock);
2325
2326 return 0;
2327 }
2328
2329 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2330 {
2331 struct rtl8139_private *tp = netdev_priv(dev);
2332 strcpy(info->driver, DRV_NAME);
2333 strcpy(info->version, DRV_VERSION);
2334 strcpy(info->bus_info, pci_name(tp->pci_dev));
2335 info->regdump_len = tp->regs_len;
2336 }
2337
2338 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2339 {
2340 struct rtl8139_private *tp = netdev_priv(dev);
2341 spin_lock_irq(&tp->lock);
2342 mii_ethtool_gset(&tp->mii, cmd);
2343 spin_unlock_irq(&tp->lock);
2344 return 0;
2345 }
2346
2347 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2348 {
2349 struct rtl8139_private *tp = netdev_priv(dev);
2350 int rc;
2351 spin_lock_irq(&tp->lock);
2352 rc = mii_ethtool_sset(&tp->mii, cmd);
2353 spin_unlock_irq(&tp->lock);
2354 return rc;
2355 }
2356
2357 static int rtl8139_nway_reset(struct net_device *dev)
2358 {
2359 struct rtl8139_private *tp = netdev_priv(dev);
2360 return mii_nway_restart(&tp->mii);
2361 }
2362
2363 static u32 rtl8139_get_link(struct net_device *dev)
2364 {
2365 struct rtl8139_private *tp = netdev_priv(dev);
2366 return mii_link_ok(&tp->mii);
2367 }
2368
2369 static u32 rtl8139_get_msglevel(struct net_device *dev)
2370 {
2371 struct rtl8139_private *tp = netdev_priv(dev);
2372 return tp->msg_enable;
2373 }
2374
2375 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2376 {
2377 struct rtl8139_private *tp = netdev_priv(dev);
2378 tp->msg_enable = datum;
2379 }
2380
2381 static int rtl8139_get_regs_len(struct net_device *dev)
2382 {
2383 struct rtl8139_private *tp;
2384 /* TODO: we are too slack to do reg dumping for pio, for now */
2385 if (use_io)
2386 return 0;
2387 tp = netdev_priv(dev);
2388 return tp->regs_len;
2389 }
2390
2391 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2392 {
2393 struct rtl8139_private *tp;
2394
2395 /* TODO: we are too slack to do reg dumping for pio, for now */
2396 if (use_io)
2397 return;
2398 tp = netdev_priv(dev);
2399
2400 regs->version = RTL_REGS_VER;
2401
2402 spin_lock_irq(&tp->lock);
2403 memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2404 spin_unlock_irq(&tp->lock);
2405 }
2406
2407 static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2408 {
2409 switch (sset) {
2410 case ETH_SS_STATS:
2411 return RTL_NUM_STATS;
2412 default:
2413 return -EOPNOTSUPP;
2414 }
2415 }
2416
2417 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2418 {
2419 struct rtl8139_private *tp = netdev_priv(dev);
2420
2421 data[0] = tp->xstats.early_rx;
2422 data[1] = tp->xstats.tx_buf_mapped;
2423 data[2] = tp->xstats.tx_timeouts;
2424 data[3] = tp->xstats.rx_lost_in_ring;
2425 }
2426
2427 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2428 {
2429 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2430 }
2431
2432 static const struct ethtool_ops rtl8139_ethtool_ops = {
2433 .get_drvinfo = rtl8139_get_drvinfo,
2434 .get_settings = rtl8139_get_settings,
2435 .set_settings = rtl8139_set_settings,
2436 .get_regs_len = rtl8139_get_regs_len,
2437 .get_regs = rtl8139_get_regs,
2438 .nway_reset = rtl8139_nway_reset,
2439 .get_link = rtl8139_get_link,
2440 .get_msglevel = rtl8139_get_msglevel,
2441 .set_msglevel = rtl8139_set_msglevel,
2442 .get_wol = rtl8139_get_wol,
2443 .set_wol = rtl8139_set_wol,
2444 .get_strings = rtl8139_get_strings,
2445 .get_sset_count = rtl8139_get_sset_count,
2446 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2447 };
2448
2449 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2450 {
2451 struct rtl8139_private *tp = netdev_priv(dev);
2452 int rc;
2453
2454 if (!netif_running(dev))
2455 return -EINVAL;
2456
2457 spin_lock_irq(&tp->lock);
2458 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2459 spin_unlock_irq(&tp->lock);
2460
2461 return rc;
2462 }
2463
2464
2465 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2466 {
2467 struct rtl8139_private *tp = netdev_priv(dev);
2468 void __iomem *ioaddr = tp->mmio_addr;
2469 unsigned long flags;
2470
2471 if (netif_running(dev)) {
2472 spin_lock_irqsave (&tp->lock, flags);
2473 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2474 RTL_W32 (RxMissed, 0);
2475 spin_unlock_irqrestore (&tp->lock, flags);
2476 }
2477
2478 return &dev->stats;
2479 }
2480
2481 /* Set or clear the multicast filter for this adaptor.
2482 This routine is not state sensitive and need not be SMP locked. */
2483
2484 static void __set_rx_mode (struct net_device *dev)
2485 {
2486 struct rtl8139_private *tp = netdev_priv(dev);
2487 void __iomem *ioaddr = tp->mmio_addr;
2488 u32 mc_filter[2]; /* Multicast hash filter */
2489 int rx_mode;
2490 u32 tmp;
2491
2492 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2493 dev->flags, RTL_R32(RxConfig));
2494
2495 /* Note: do not reorder, GCC is clever about common statements. */
2496 if (dev->flags & IFF_PROMISC) {
2497 rx_mode =
2498 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2499 AcceptAllPhys;
2500 mc_filter[1] = mc_filter[0] = 0xffffffff;
2501 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2502 (dev->flags & IFF_ALLMULTI)) {
2503 /* Too many to filter perfectly -- accept all multicasts. */
2504 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2505 mc_filter[1] = mc_filter[0] = 0xffffffff;
2506 } else {
2507 struct netdev_hw_addr *ha;
2508 rx_mode = AcceptBroadcast | AcceptMyPhys;
2509 mc_filter[1] = mc_filter[0] = 0;
2510 netdev_for_each_mc_addr(ha, dev) {
2511 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2512
2513 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2514 rx_mode |= AcceptMulticast;
2515 }
2516 }
2517
2518 /* We can safely update without stopping the chip. */
2519 tmp = rtl8139_rx_config | rx_mode;
2520 if (tp->rx_config != tmp) {
2521 RTL_W32_F (RxConfig, tmp);
2522 tp->rx_config = tmp;
2523 }
2524 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2525 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2526 }
2527
2528 static void rtl8139_set_rx_mode (struct net_device *dev)
2529 {
2530 unsigned long flags;
2531 struct rtl8139_private *tp = netdev_priv(dev);
2532
2533 spin_lock_irqsave (&tp->lock, flags);
2534 __set_rx_mode(dev);
2535 spin_unlock_irqrestore (&tp->lock, flags);
2536 }
2537
2538 #ifdef CONFIG_PM
2539
2540 static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2541 {
2542 struct net_device *dev = pci_get_drvdata (pdev);
2543 struct rtl8139_private *tp = netdev_priv(dev);
2544 void __iomem *ioaddr = tp->mmio_addr;
2545 unsigned long flags;
2546
2547 pci_save_state (pdev);
2548
2549 if (!netif_running (dev))
2550 return 0;
2551
2552 netif_device_detach (dev);
2553
2554 spin_lock_irqsave (&tp->lock, flags);
2555
2556 /* Disable interrupts, stop Tx and Rx. */
2557 RTL_W16 (IntrMask, 0);
2558 RTL_W8 (ChipCmd, 0);
2559
2560 /* Update the error counts. */
2561 dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2562 RTL_W32 (RxMissed, 0);
2563
2564 spin_unlock_irqrestore (&tp->lock, flags);
2565
2566 pci_set_power_state (pdev, PCI_D3hot);
2567
2568 return 0;
2569 }
2570
2571
2572 static int rtl8139_resume (struct pci_dev *pdev)
2573 {
2574 struct net_device *dev = pci_get_drvdata (pdev);
2575
2576 pci_restore_state (pdev);
2577 if (!netif_running (dev))
2578 return 0;
2579 pci_set_power_state (pdev, PCI_D0);
2580 rtl8139_init_ring (dev);
2581 rtl8139_hw_start (dev);
2582 netif_device_attach (dev);
2583 return 0;
2584 }
2585
2586 #endif /* CONFIG_PM */
2587
2588
2589 static struct pci_driver rtl8139_pci_driver = {
2590 .name = DRV_NAME,
2591 .id_table = rtl8139_pci_tbl,
2592 .probe = rtl8139_init_one,
2593 .remove = __devexit_p(rtl8139_remove_one),
2594 #ifdef CONFIG_PM
2595 .suspend = rtl8139_suspend,
2596 .resume = rtl8139_resume,
2597 #endif /* CONFIG_PM */
2598 };
2599
2600
2601 static int __init rtl8139_init_module (void)
2602 {
2603 /* when we're a module, we always print a version message,
2604 * even if no 8139 board is found.
2605 */
2606 #ifdef MODULE
2607 pr_info(RTL8139_DRIVER_NAME "\n");
2608 #endif
2609
2610 return pci_register_driver(&rtl8139_pci_driver);
2611 }
2612
2613
2614 static void __exit rtl8139_cleanup_module (void)
2615 {
2616 pci_unregister_driver (&rtl8139_pci_driver);
2617 }
2618
2619
2620 module_init(rtl8139_init_module);
2621 module_exit(rtl8139_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree