5 #include <asm-generic/pci-dma-compat.h>
6 #include <asm-generic/pci-bridge.h>
8 #include <asm/mach/pci.h> /* for pci_sys_data */
9 #include <mach/hardware.h> /* for PCIBIOS_MIN_* */
11 static inline int pcibios_assign_all_busses(void)
13 return pci_has_flag(PCI_REASSIGN_ALL_RSRC
);
16 #ifdef CONFIG_PCI_DOMAINS
17 static inline int pci_domain_nr(struct pci_bus
*bus
)
19 struct pci_sys_data
*root
= bus
->sysdata
;
24 static inline int pci_proc_domain(struct pci_bus
*bus
)
26 return pci_domain_nr(bus
);
28 #endif /* CONFIG_PCI_DOMAINS */
30 #ifdef CONFIG_PCI_HOST_ITE8152
31 /* ITE bridge requires setting latency timer to avoid early bus access
32 termination by PIC bus mater devices
34 extern void pcibios_set_master(struct pci_dev
*dev
);
36 static inline void pcibios_set_master(struct pci_dev
*dev
)
38 /* No special bus mastering setup handling */
42 static inline void pcibios_penalize_isa_irq(int irq
, int active
)
44 /* We don't do dynamic PCI IRQ allocation */
48 * The PCI address space does equal the physical memory address space.
49 * The networking and block device layers use this boolean for bounce
52 #define PCI_DMA_BUS_IS_PHYS (1)
55 static inline void pci_dma_burst_advice(struct pci_dev
*pdev
,
56 enum pci_dma_burst_strategy
*strat
,
57 unsigned long *strategy_parameter
)
59 *strat
= PCI_DMA_BURST_INFINITY
;
60 *strategy_parameter
= ~0UL;
65 extern int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
66 enum pci_mmap_state mmap_state
, int write_combine
);
69 pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
70 struct resource
*res
);
73 pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
74 struct pci_bus_region
*region
);
77 * Dummy implementation; always return 0.
79 static inline int pci_get_legacy_ide_irq(struct pci_dev
*dev
, int channel
)
84 #endif /* __KERNEL__ */