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iwlwifi: make mac80211 ops a device config
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blob7921a910b34ab7f1f5459a368bdf744d10717d76
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <net/mac80211.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40
41 #include "iwl-eeprom.h"
42 #include "iwl-dev.h"
43 #include "iwl-core.h"
44 #include "iwl-io.h"
45 #include "iwl-helpers.h"
46 #include "iwl-agn-calib.h"
47 #include "iwl-sta.h"
48 #include "iwl-agn-led.h"
49 #include "iwl-agn.h"
50 #include "iwl-agn-debugfs.h"
51
52 static int iwl4965_send_tx_power(struct iwl_priv *priv);
53 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
54
55 /* Highest firmware API version supported */
56 #define IWL4965_UCODE_API_MAX 2
57
58 /* Lowest firmware API version supported */
59 #define IWL4965_UCODE_API_MIN 2
60
61 #define IWL4965_FW_PRE "iwlwifi-4965-"
62 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
63 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
64
65 /* check contents of special bootstrap uCode SRAM */
66 static int iwl4965_verify_bsm(struct iwl_priv *priv)
67 {
68 __le32 *image = priv->ucode_boot.v_addr;
69 u32 len = priv->ucode_boot.len;
70 u32 reg;
71 u32 val;
72
73 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
74
75 /* verify BSM SRAM contents */
76 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
77 for (reg = BSM_SRAM_LOWER_BOUND;
78 reg < BSM_SRAM_LOWER_BOUND + len;
79 reg += sizeof(u32), image++) {
80 val = iwl_read_prph(priv, reg);
81 if (val != le32_to_cpu(*image)) {
82 IWL_ERR(priv, "BSM uCode verification failed at "
83 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
84 BSM_SRAM_LOWER_BOUND,
85 reg - BSM_SRAM_LOWER_BOUND, len,
86 val, le32_to_cpu(*image));
87 return -EIO;
88 }
89 }
90
91 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
92
93 return 0;
94 }
95
96 /**
97 * iwl4965_load_bsm - Load bootstrap instructions
98 *
99 * BSM operation:
100 *
101 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
102 * in special SRAM that does not power down during RFKILL. When powering back
103 * up after power-saving sleeps (or during initial uCode load), the BSM loads
104 * the bootstrap program into the on-board processor, and starts it.
105 *
106 * The bootstrap program loads (via DMA) instructions and data for a new
107 * program from host DRAM locations indicated by the host driver in the
108 * BSM_DRAM_* registers. Once the new program is loaded, it starts
109 * automatically.
110 *
111 * When initializing the NIC, the host driver points the BSM to the
112 * "initialize" uCode image. This uCode sets up some internal data, then
113 * notifies host via "initialize alive" that it is complete.
114 *
115 * The host then replaces the BSM_DRAM_* pointer values to point to the
116 * normal runtime uCode instructions and a backup uCode data cache buffer
117 * (filled initially with starting data values for the on-board processor),
118 * then triggers the "initialize" uCode to load and launch the runtime uCode,
119 * which begins normal operation.
120 *
121 * When doing a power-save shutdown, runtime uCode saves data SRAM into
122 * the backup data cache in DRAM before SRAM is powered down.
123 *
124 * When powering back up, the BSM loads the bootstrap program. This reloads
125 * the runtime uCode instructions and the backup data cache into SRAM,
126 * and re-launches the runtime uCode from where it left off.
127 */
128 static int iwl4965_load_bsm(struct iwl_priv *priv)
129 {
130 __le32 *image = priv->ucode_boot.v_addr;
131 u32 len = priv->ucode_boot.len;
132 dma_addr_t pinst;
133 dma_addr_t pdata;
134 u32 inst_len;
135 u32 data_len;
136 int i;
137 u32 done;
138 u32 reg_offset;
139 int ret;
140
141 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
142
143 priv->ucode_type = UCODE_RT;
144
145 /* make sure bootstrap program is no larger than BSM's SRAM size */
146 if (len > IWL49_MAX_BSM_SIZE)
147 return -EINVAL;
148
149 /* Tell bootstrap uCode where to find the "Initialize" uCode
150 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
151 * NOTE: iwl_init_alive_start() will replace these values,
152 * after the "initialize" uCode has run, to point to
153 * runtime/protocol instructions and backup data cache.
154 */
155 pinst = priv->ucode_init.p_addr >> 4;
156 pdata = priv->ucode_init_data.p_addr >> 4;
157 inst_len = priv->ucode_init.len;
158 data_len = priv->ucode_init_data.len;
159
160 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
161 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
162 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
163 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
164
165 /* Fill BSM memory with bootstrap instructions */
166 for (reg_offset = BSM_SRAM_LOWER_BOUND;
167 reg_offset < BSM_SRAM_LOWER_BOUND + len;
168 reg_offset += sizeof(u32), image++)
169 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
170
171 ret = iwl4965_verify_bsm(priv);
172 if (ret)
173 return ret;
174
175 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
176 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
177 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
178 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
179
180 /* Load bootstrap code into instruction SRAM now,
181 * to prepare to load "initialize" uCode */
182 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
183
184 /* Wait for load of bootstrap uCode to finish */
185 for (i = 0; i < 100; i++) {
186 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
187 if (!(done & BSM_WR_CTRL_REG_BIT_START))
188 break;
189 udelay(10);
190 }
191 if (i < 100)
192 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
193 else {
194 IWL_ERR(priv, "BSM write did not complete!\n");
195 return -EIO;
196 }
197
198 /* Enable future boot loads whenever power management unit triggers it
199 * (e.g. when powering back up after power-save shutdown) */
200 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
201
202
203 return 0;
204 }
205
206 /**
207 * iwl4965_set_ucode_ptrs - Set uCode address location
208 *
209 * Tell initialization uCode where to find runtime uCode.
210 *
211 * BSM registers initially contain pointers to initialization uCode.
212 * We need to replace them to load runtime uCode inst and data,
213 * and to save runtime data when powering down.
214 */
215 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
216 {
217 dma_addr_t pinst;
218 dma_addr_t pdata;
219 int ret = 0;
220
221 /* bits 35:4 for 4965 */
222 pinst = priv->ucode_code.p_addr >> 4;
223 pdata = priv->ucode_data_backup.p_addr >> 4;
224
225 /* Tell bootstrap uCode where to find image to load */
226 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
227 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
228 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
229 priv->ucode_data.len);
230
231 /* Inst byte count must be last to set up, bit 31 signals uCode
232 * that all new ptr/size info is in place */
233 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
234 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
235 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
236
237 return ret;
238 }
239
240 /**
241 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
242 *
243 * Called after REPLY_ALIVE notification received from "initialize" uCode.
244 *
245 * The 4965 "initialize" ALIVE reply contains calibration data for:
246 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
247 * (3945 does not contain this data).
248 *
249 * Tell "initialize" uCode to go ahead and load the runtime uCode.
250 */
251 static void iwl4965_init_alive_start(struct iwl_priv *priv)
252 {
253 /* Check alive response for "valid" sign from uCode */
254 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
255 /* We had an error bringing up the hardware, so take it
256 * all the way back down so we can try again */
257 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
258 goto restart;
259 }
260
261 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
262 * This is a paranoid check, because we would not have gotten the
263 * "initialize" alive if code weren't properly loaded. */
264 if (iwl_verify_ucode(priv)) {
265 /* Runtime instruction load was bad;
266 * take it all the way back down so we can try again */
267 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
268 goto restart;
269 }
270
271 /* Calculate temperature */
272 priv->temperature = iwl4965_hw_get_temperature(priv);
273
274 /* Send pointers to protocol/runtime uCode image ... init code will
275 * load and launch runtime uCode, which will send us another "Alive"
276 * notification. */
277 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
278 if (iwl4965_set_ucode_ptrs(priv)) {
279 /* Runtime instruction load won't happen;
280 * take it all the way back down so we can try again */
281 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
282 goto restart;
283 }
284 return;
285
286 restart:
287 queue_work(priv->workqueue, &priv->restart);
288 }
289
290 static bool is_ht40_channel(__le32 rxon_flags)
291 {
292 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
293 >> RXON_FLG_CHANNEL_MODE_POS;
294 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
295 (chan_mod == CHANNEL_MODE_MIXED));
296 }
297
298 /*
299 * EEPROM handlers
300 */
301 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
302 {
303 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
304 }
305
306 /*
307 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
308 * must be called under priv->lock and mac access
309 */
310 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
311 {
312 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
313 }
314
315 static void iwl4965_nic_config(struct iwl_priv *priv)
316 {
317 unsigned long flags;
318 u16 radio_cfg;
319
320 spin_lock_irqsave(&priv->lock, flags);
321
322 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
323
324 /* write radio config values to register */
325 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
326 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
327 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
328 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
329 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
330
331 /* set CSR_HW_CONFIG_REG for uCode use */
332 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
333 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
334 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
335
336 priv->calib_info = (struct iwl_eeprom_calib_info *)
337 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
338
339 spin_unlock_irqrestore(&priv->lock, flags);
340 }
341
342 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
343 * Called after every association, but this runs only once!
344 * ... once chain noise is calibrated the first time, it's good forever. */
345 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
346 {
347 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
348
349 if ((data->state == IWL_CHAIN_NOISE_ALIVE) &&
350 iwl_is_any_associated(priv)) {
351 struct iwl_calib_diff_gain_cmd cmd;
352
353 /* clear data for chain noise calibration algorithm */
354 data->chain_noise_a = 0;
355 data->chain_noise_b = 0;
356 data->chain_noise_c = 0;
357 data->chain_signal_a = 0;
358 data->chain_signal_b = 0;
359 data->chain_signal_c = 0;
360 data->beacon_count = 0;
361
362 memset(&cmd, 0, sizeof(cmd));
363 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
364 cmd.diff_gain_a = 0;
365 cmd.diff_gain_b = 0;
366 cmd.diff_gain_c = 0;
367 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
368 sizeof(cmd), &cmd))
369 IWL_ERR(priv,
370 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
371 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
372 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
373 }
374 }
375
376 static void iwl4965_gain_computation(struct iwl_priv *priv,
377 u32 *average_noise,
378 u16 min_average_noise_antenna_i,
379 u32 min_average_noise,
380 u8 default_chain)
381 {
382 int i, ret;
383 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
384
385 data->delta_gain_code[min_average_noise_antenna_i] = 0;
386
387 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
388 s32 delta_g = 0;
389
390 if (!(data->disconn_array[i]) &&
391 (data->delta_gain_code[i] ==
392 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
393 delta_g = average_noise[i] - min_average_noise;
394 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
395 data->delta_gain_code[i] =
396 min(data->delta_gain_code[i],
397 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
398
399 data->delta_gain_code[i] =
400 (data->delta_gain_code[i] | (1 << 2));
401 } else {
402 data->delta_gain_code[i] = 0;
403 }
404 }
405 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
406 data->delta_gain_code[0],
407 data->delta_gain_code[1],
408 data->delta_gain_code[2]);
409
410 /* Differential gain gets sent to uCode only once */
411 if (!data->radio_write) {
412 struct iwl_calib_diff_gain_cmd cmd;
413 data->radio_write = 1;
414
415 memset(&cmd, 0, sizeof(cmd));
416 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
417 cmd.diff_gain_a = data->delta_gain_code[0];
418 cmd.diff_gain_b = data->delta_gain_code[1];
419 cmd.diff_gain_c = data->delta_gain_code[2];
420 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
421 sizeof(cmd), &cmd);
422 if (ret)
423 IWL_DEBUG_CALIB(priv, "fail sending cmd "
424 "REPLY_PHY_CALIBRATION_CMD\n");
425
426 /* TODO we might want recalculate
427 * rx_chain in rxon cmd */
428
429 /* Mark so we run this algo only once! */
430 data->state = IWL_CHAIN_NOISE_CALIBRATED;
431 }
432 }
433
434 static void iwl4965_bg_txpower_work(struct work_struct *work)
435 {
436 struct iwl_priv *priv = container_of(work, struct iwl_priv,
437 txpower_work);
438
439 /* If a scan happened to start before we got here
440 * then just return; the statistics notification will
441 * kick off another scheduled work to compensate for
442 * any temperature delta we missed here. */
443 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
444 test_bit(STATUS_SCANNING, &priv->status))
445 return;
446
447 mutex_lock(&priv->mutex);
448
449 /* Regardless of if we are associated, we must reconfigure the
450 * TX power since frames can be sent on non-radar channels while
451 * not associated */
452 iwl4965_send_tx_power(priv);
453
454 /* Update last_temperature to keep is_calib_needed from running
455 * when it isn't needed... */
456 priv->last_temperature = priv->temperature;
457
458 mutex_unlock(&priv->mutex);
459 }
460
461 /*
462 * Acquire priv->lock before calling this function !
463 */
464 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
465 {
466 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
467 (index & 0xff) | (txq_id << 8));
468 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
469 }
470
471 /**
472 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
473 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
474 * @scd_retry: (1) Indicates queue will be used in aggregation mode
475 *
476 * NOTE: Acquire priv->lock before calling this function !
477 */
478 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
479 struct iwl_tx_queue *txq,
480 int tx_fifo_id, int scd_retry)
481 {
482 int txq_id = txq->q.id;
483
484 /* Find out whether to activate Tx queue */
485 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
486
487 /* Set up and activate */
488 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
489 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
490 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
491 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
492 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
493 IWL49_SCD_QUEUE_STTS_REG_MSK);
494
495 txq->sched_retry = scd_retry;
496
497 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
498 active ? "Activate" : "Deactivate",
499 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
500 }
501
502 static const s8 default_queue_to_tx_fifo[] = {
503 IWL_TX_FIFO_VO,
504 IWL_TX_FIFO_VI,
505 IWL_TX_FIFO_BE,
506 IWL_TX_FIFO_BK,
507 IWL49_CMD_FIFO_NUM,
508 IWL_TX_FIFO_UNUSED,
509 IWL_TX_FIFO_UNUSED,
510 };
511
512 static int iwl4965_alive_notify(struct iwl_priv *priv)
513 {
514 u32 a;
515 unsigned long flags;
516 int i, chan;
517 u32 reg_val;
518
519 spin_lock_irqsave(&priv->lock, flags);
520
521 /* Clear 4965's internal Tx Scheduler data base */
522 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
523 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
524 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
525 iwl_write_targ_mem(priv, a, 0);
526 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
527 iwl_write_targ_mem(priv, a, 0);
528 for (; a < priv->scd_base_addr +
529 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
530 iwl_write_targ_mem(priv, a, 0);
531
532 /* Tel 4965 where to find Tx byte count tables */
533 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
534 priv->scd_bc_tbls.dma >> 10);
535
536 /* Enable DMA channel */
537 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
538 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
539 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
540 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
541
542 /* Update FH chicken bits */
543 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
544 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
545 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
546
547 /* Disable chain mode for all queues */
548 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
549
550 /* Initialize each Tx queue (including the command queue) */
551 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
552
553 /* TFD circular buffer read/write indexes */
554 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
555 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
556
557 /* Max Tx Window size for Scheduler-ACK mode */
558 iwl_write_targ_mem(priv, priv->scd_base_addr +
559 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
560 (SCD_WIN_SIZE <<
561 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
562 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
563
564 /* Frame limit */
565 iwl_write_targ_mem(priv, priv->scd_base_addr +
566 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
567 sizeof(u32),
568 (SCD_FRAME_LIMIT <<
569 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
570 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
571
572 }
573 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
574 (1 << priv->hw_params.max_txq_num) - 1);
575
576 /* Activate all Tx DMA/FIFO channels */
577 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
578
579 iwl4965_set_wr_ptrs(priv, IWL_DEFAULT_CMD_QUEUE_NUM, 0);
580
581 /* make sure all queue are not stopped */
582 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
583 for (i = 0; i < 4; i++)
584 atomic_set(&priv->queue_stop_count[i], 0);
585
586 /* reset to 0 to enable all the queue first */
587 priv->txq_ctx_active_msk = 0;
588 /* Map each Tx/cmd queue to its corresponding fifo */
589 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
590
591 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
592 int ac = default_queue_to_tx_fifo[i];
593
594 iwl_txq_ctx_activate(priv, i);
595
596 if (ac == IWL_TX_FIFO_UNUSED)
597 continue;
598
599 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
600 }
601
602 spin_unlock_irqrestore(&priv->lock, flags);
603
604 return 0;
605 }
606
607 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
608 .min_nrg_cck = 97,
609 .max_nrg_cck = 0, /* not used, set to 0 */
610
611 .auto_corr_min_ofdm = 85,
612 .auto_corr_min_ofdm_mrc = 170,
613 .auto_corr_min_ofdm_x1 = 105,
614 .auto_corr_min_ofdm_mrc_x1 = 220,
615
616 .auto_corr_max_ofdm = 120,
617 .auto_corr_max_ofdm_mrc = 210,
618 .auto_corr_max_ofdm_x1 = 140,
619 .auto_corr_max_ofdm_mrc_x1 = 270,
620
621 .auto_corr_min_cck = 125,
622 .auto_corr_max_cck = 200,
623 .auto_corr_min_cck_mrc = 200,
624 .auto_corr_max_cck_mrc = 400,
625
626 .nrg_th_cck = 100,
627 .nrg_th_ofdm = 100,
628
629 .barker_corr_th_min = 190,
630 .barker_corr_th_min_mrc = 390,
631 .nrg_th_cca = 62,
632 };
633
634 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
635 {
636 /* want Kelvin */
637 priv->hw_params.ct_kill_threshold =
638 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
639 }
640
641 /**
642 * iwl4965_hw_set_hw_params
643 *
644 * Called when initializing driver
645 */
646 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
647 {
648 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
649 priv->cfg->mod_params->num_of_queues <= IWL49_NUM_QUEUES)
650 priv->cfg->base_params->num_of_queues =
651 priv->cfg->mod_params->num_of_queues;
652
653 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
654 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
655 priv->hw_params.scd_bc_tbls_size =
656 priv->cfg->base_params->num_of_queues *
657 sizeof(struct iwl4965_scd_bc_tbl);
658 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
659 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
660 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL4965_BROADCAST_ID;
661 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
662 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
663 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
664 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
665
666 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
667
668 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
669 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
670 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
671 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
672
673 iwl4965_set_ct_threshold(priv);
674
675 priv->hw_params.sens = &iwl4965_sensitivity;
676 priv->hw_params.beacon_time_tsf_bits = IWLAGN_EXT_BEACON_TIME_POS;
677
678 return 0;
679 }
680
681 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
682 {
683 s32 sign = 1;
684
685 if (num < 0) {
686 sign = -sign;
687 num = -num;
688 }
689 if (denom < 0) {
690 sign = -sign;
691 denom = -denom;
692 }
693 *res = 1;
694 *res = ((num * 2 + denom) / (denom * 2)) * sign;
695
696 return 1;
697 }
698
699 /**
700 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
701 *
702 * Determines power supply voltage compensation for txpower calculations.
703 * Returns number of 1/2-dB steps to subtract from gain table index,
704 * to compensate for difference between power supply voltage during
705 * factory measurements, vs. current power supply voltage.
706 *
707 * Voltage indication is higher for lower voltage.
708 * Lower voltage requires more gain (lower gain table index).
709 */
710 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
711 s32 current_voltage)
712 {
713 s32 comp = 0;
714
715 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
716 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
717 return 0;
718
719 iwl4965_math_div_round(current_voltage - eeprom_voltage,
720 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
721
722 if (current_voltage > eeprom_voltage)
723 comp *= 2;
724 if ((comp < -2) || (comp > 2))
725 comp = 0;
726
727 return comp;
728 }
729
730 static s32 iwl4965_get_tx_atten_grp(u16 channel)
731 {
732 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
733 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
734 return CALIB_CH_GROUP_5;
735
736 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
737 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
738 return CALIB_CH_GROUP_1;
739
740 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
741 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
742 return CALIB_CH_GROUP_2;
743
744 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
745 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
746 return CALIB_CH_GROUP_3;
747
748 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
749 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
750 return CALIB_CH_GROUP_4;
751
752 return -1;
753 }
754
755 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
756 {
757 s32 b = -1;
758
759 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
760 if (priv->calib_info->band_info[b].ch_from == 0)
761 continue;
762
763 if ((channel >= priv->calib_info->band_info[b].ch_from)
764 && (channel <= priv->calib_info->band_info[b].ch_to))
765 break;
766 }
767
768 return b;
769 }
770
771 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
772 {
773 s32 val;
774
775 if (x2 == x1)
776 return y1;
777 else {
778 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
779 return val + y2;
780 }
781 }
782
783 /**
784 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
785 *
786 * Interpolates factory measurements from the two sample channels within a
787 * sub-band, to apply to channel of interest. Interpolation is proportional to
788 * differences in channel frequencies, which is proportional to differences
789 * in channel number.
790 */
791 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
792 struct iwl_eeprom_calib_ch_info *chan_info)
793 {
794 s32 s = -1;
795 u32 c;
796 u32 m;
797 const struct iwl_eeprom_calib_measure *m1;
798 const struct iwl_eeprom_calib_measure *m2;
799 struct iwl_eeprom_calib_measure *omeas;
800 u32 ch_i1;
801 u32 ch_i2;
802
803 s = iwl4965_get_sub_band(priv, channel);
804 if (s >= EEPROM_TX_POWER_BANDS) {
805 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
806 return -1;
807 }
808
809 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
810 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
811 chan_info->ch_num = (u8) channel;
812
813 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
814 channel, s, ch_i1, ch_i2);
815
816 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
817 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
818 m1 = &(priv->calib_info->band_info[s].ch1.
819 measurements[c][m]);
820 m2 = &(priv->calib_info->band_info[s].ch2.
821 measurements[c][m]);
822 omeas = &(chan_info->measurements[c][m]);
823
824 omeas->actual_pow =
825 (u8) iwl4965_interpolate_value(channel, ch_i1,
826 m1->actual_pow,
827 ch_i2,
828 m2->actual_pow);
829 omeas->gain_idx =
830 (u8) iwl4965_interpolate_value(channel, ch_i1,
831 m1->gain_idx, ch_i2,
832 m2->gain_idx);
833 omeas->temperature =
834 (u8) iwl4965_interpolate_value(channel, ch_i1,
835 m1->temperature,
836 ch_i2,
837 m2->temperature);
838 omeas->pa_det =
839 (s8) iwl4965_interpolate_value(channel, ch_i1,
840 m1->pa_det, ch_i2,
841 m2->pa_det);
842
843 IWL_DEBUG_TXPOWER(priv,
844 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
845 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
846 IWL_DEBUG_TXPOWER(priv,
847 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
848 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
849 IWL_DEBUG_TXPOWER(priv,
850 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
851 m1->pa_det, m2->pa_det, omeas->pa_det);
852 IWL_DEBUG_TXPOWER(priv,
853 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
854 m1->temperature, m2->temperature,
855 omeas->temperature);
856 }
857 }
858
859 return 0;
860 }
861
862 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
863 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
864 static s32 back_off_table[] = {
865 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
866 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
867 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
868 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
869 10 /* CCK */
870 };
871
872 /* Thermal compensation values for txpower for various frequency ranges ...
873 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
874 static struct iwl4965_txpower_comp_entry {
875 s32 degrees_per_05db_a;
876 s32 degrees_per_05db_a_denom;
877 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
878 {9, 2}, /* group 0 5.2, ch 34-43 */
879 {4, 1}, /* group 1 5.2, ch 44-70 */
880 {4, 1}, /* group 2 5.2, ch 71-124 */
881 {4, 1}, /* group 3 5.2, ch 125-200 */
882 {3, 1} /* group 4 2.4, ch all */
883 };
884
885 static s32 get_min_power_index(s32 rate_power_index, u32 band)
886 {
887 if (!band) {
888 if ((rate_power_index & 7) <= 4)
889 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
890 }
891 return MIN_TX_GAIN_INDEX;
892 }
893
894 struct gain_entry {
895 u8 dsp;
896 u8 radio;
897 };
898
899 static const struct gain_entry gain_table[2][108] = {
900 /* 5.2GHz power gain index table */
901 {
902 {123, 0x3F}, /* highest txpower */
903 {117, 0x3F},
904 {110, 0x3F},
905 {104, 0x3F},
906 {98, 0x3F},
907 {110, 0x3E},
908 {104, 0x3E},
909 {98, 0x3E},
910 {110, 0x3D},
911 {104, 0x3D},
912 {98, 0x3D},
913 {110, 0x3C},
914 {104, 0x3C},
915 {98, 0x3C},
916 {110, 0x3B},
917 {104, 0x3B},
918 {98, 0x3B},
919 {110, 0x3A},
920 {104, 0x3A},
921 {98, 0x3A},
922 {110, 0x39},
923 {104, 0x39},
924 {98, 0x39},
925 {110, 0x38},
926 {104, 0x38},
927 {98, 0x38},
928 {110, 0x37},
929 {104, 0x37},
930 {98, 0x37},
931 {110, 0x36},
932 {104, 0x36},
933 {98, 0x36},
934 {110, 0x35},
935 {104, 0x35},
936 {98, 0x35},
937 {110, 0x34},
938 {104, 0x34},
939 {98, 0x34},
940 {110, 0x33},
941 {104, 0x33},
942 {98, 0x33},
943 {110, 0x32},
944 {104, 0x32},
945 {98, 0x32},
946 {110, 0x31},
947 {104, 0x31},
948 {98, 0x31},
949 {110, 0x30},
950 {104, 0x30},
951 {98, 0x30},
952 {110, 0x25},
953 {104, 0x25},
954 {98, 0x25},
955 {110, 0x24},
956 {104, 0x24},
957 {98, 0x24},
958 {110, 0x23},
959 {104, 0x23},
960 {98, 0x23},
961 {110, 0x22},
962 {104, 0x18},
963 {98, 0x18},
964 {110, 0x17},
965 {104, 0x17},
966 {98, 0x17},
967 {110, 0x16},
968 {104, 0x16},
969 {98, 0x16},
970 {110, 0x15},
971 {104, 0x15},
972 {98, 0x15},
973 {110, 0x14},
974 {104, 0x14},
975 {98, 0x14},
976 {110, 0x13},
977 {104, 0x13},
978 {98, 0x13},
979 {110, 0x12},
980 {104, 0x08},
981 {98, 0x08},
982 {110, 0x07},
983 {104, 0x07},
984 {98, 0x07},
985 {110, 0x06},
986 {104, 0x06},
987 {98, 0x06},
988 {110, 0x05},
989 {104, 0x05},
990 {98, 0x05},
991 {110, 0x04},
992 {104, 0x04},
993 {98, 0x04},
994 {110, 0x03},
995 {104, 0x03},
996 {98, 0x03},
997 {110, 0x02},
998 {104, 0x02},
999 {98, 0x02},
1000 {110, 0x01},
1001 {104, 0x01},
1002 {98, 0x01},
1003 {110, 0x00},
1004 {104, 0x00},
1005 {98, 0x00},
1006 {93, 0x00},
1007 {88, 0x00},
1008 {83, 0x00},
1009 {78, 0x00},
1010 },
1011 /* 2.4GHz power gain index table */
1012 {
1013 {110, 0x3f}, /* highest txpower */
1014 {104, 0x3f},
1015 {98, 0x3f},
1016 {110, 0x3e},
1017 {104, 0x3e},
1018 {98, 0x3e},
1019 {110, 0x3d},
1020 {104, 0x3d},
1021 {98, 0x3d},
1022 {110, 0x3c},
1023 {104, 0x3c},
1024 {98, 0x3c},
1025 {110, 0x3b},
1026 {104, 0x3b},
1027 {98, 0x3b},
1028 {110, 0x3a},
1029 {104, 0x3a},
1030 {98, 0x3a},
1031 {110, 0x39},
1032 {104, 0x39},
1033 {98, 0x39},
1034 {110, 0x38},
1035 {104, 0x38},
1036 {98, 0x38},
1037 {110, 0x37},
1038 {104, 0x37},
1039 {98, 0x37},
1040 {110, 0x36},
1041 {104, 0x36},
1042 {98, 0x36},
1043 {110, 0x35},
1044 {104, 0x35},
1045 {98, 0x35},
1046 {110, 0x34},
1047 {104, 0x34},
1048 {98, 0x34},
1049 {110, 0x33},
1050 {104, 0x33},
1051 {98, 0x33},
1052 {110, 0x32},
1053 {104, 0x32},
1054 {98, 0x32},
1055 {110, 0x31},
1056 {104, 0x31},
1057 {98, 0x31},
1058 {110, 0x30},
1059 {104, 0x30},
1060 {98, 0x30},
1061 {110, 0x6},
1062 {104, 0x6},
1063 {98, 0x6},
1064 {110, 0x5},
1065 {104, 0x5},
1066 {98, 0x5},
1067 {110, 0x4},
1068 {104, 0x4},
1069 {98, 0x4},
1070 {110, 0x3},
1071 {104, 0x3},
1072 {98, 0x3},
1073 {110, 0x2},
1074 {104, 0x2},
1075 {98, 0x2},
1076 {110, 0x1},
1077 {104, 0x1},
1078 {98, 0x1},
1079 {110, 0x0},
1080 {104, 0x0},
1081 {98, 0x0},
1082 {97, 0},
1083 {96, 0},
1084 {95, 0},
1085 {94, 0},
1086 {93, 0},
1087 {92, 0},
1088 {91, 0},
1089 {90, 0},
1090 {89, 0},
1091 {88, 0},
1092 {87, 0},
1093 {86, 0},
1094 {85, 0},
1095 {84, 0},
1096 {83, 0},
1097 {82, 0},
1098 {81, 0},
1099 {80, 0},
1100 {79, 0},
1101 {78, 0},
1102 {77, 0},
1103 {76, 0},
1104 {75, 0},
1105 {74, 0},
1106 {73, 0},
1107 {72, 0},
1108 {71, 0},
1109 {70, 0},
1110 {69, 0},
1111 {68, 0},
1112 {67, 0},
1113 {66, 0},
1114 {65, 0},
1115 {64, 0},
1116 {63, 0},
1117 {62, 0},
1118 {61, 0},
1119 {60, 0},
1120 {59, 0},
1121 }
1122 };
1123
1124 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1125 u8 is_ht40, u8 ctrl_chan_high,
1126 struct iwl4965_tx_power_db *tx_power_tbl)
1127 {
1128 u8 saturation_power;
1129 s32 target_power;
1130 s32 user_target_power;
1131 s32 power_limit;
1132 s32 current_temp;
1133 s32 reg_limit;
1134 s32 current_regulatory;
1135 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1136 int i;
1137 int c;
1138 const struct iwl_channel_info *ch_info = NULL;
1139 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1140 const struct iwl_eeprom_calib_measure *measurement;
1141 s16 voltage;
1142 s32 init_voltage;
1143 s32 voltage_compensation;
1144 s32 degrees_per_05db_num;
1145 s32 degrees_per_05db_denom;
1146 s32 factory_temp;
1147 s32 temperature_comp[2];
1148 s32 factory_gain_index[2];
1149 s32 factory_actual_pwr[2];
1150 s32 power_index;
1151
1152 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1153 * are used for indexing into txpower table) */
1154 user_target_power = 2 * priv->tx_power_user_lmt;
1155
1156 /* Get current (RXON) channel, band, width */
1157 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1158 is_ht40);
1159
1160 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1161
1162 if (!is_channel_valid(ch_info))
1163 return -EINVAL;
1164
1165 /* get txatten group, used to select 1) thermal txpower adjustment
1166 * and 2) mimo txpower balance between Tx chains. */
1167 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1168 if (txatten_grp < 0) {
1169 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1170 channel);
1171 return -EINVAL;
1172 }
1173
1174 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1175 channel, txatten_grp);
1176
1177 if (is_ht40) {
1178 if (ctrl_chan_high)
1179 channel -= 2;
1180 else
1181 channel += 2;
1182 }
1183
1184 /* hardware txpower limits ...
1185 * saturation (clipping distortion) txpowers are in half-dBm */
1186 if (band)
1187 saturation_power = priv->calib_info->saturation_power24;
1188 else
1189 saturation_power = priv->calib_info->saturation_power52;
1190
1191 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1192 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1193 if (band)
1194 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1195 else
1196 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1197 }
1198
1199 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1200 * max_power_avg values are in dBm, convert * 2 */
1201 if (is_ht40)
1202 reg_limit = ch_info->ht40_max_power_avg * 2;
1203 else
1204 reg_limit = ch_info->max_power_avg * 2;
1205
1206 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1207 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1208 if (band)
1209 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1210 else
1211 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1212 }
1213
1214 /* Interpolate txpower calibration values for this channel,
1215 * based on factory calibration tests on spaced channels. */
1216 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1217
1218 /* calculate tx gain adjustment based on power supply voltage */
1219 voltage = le16_to_cpu(priv->calib_info->voltage);
1220 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1221 voltage_compensation =
1222 iwl4965_get_voltage_compensation(voltage, init_voltage);
1223
1224 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1225 init_voltage,
1226 voltage, voltage_compensation);
1227
1228 /* get current temperature (Celsius) */
1229 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1230 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1231 current_temp = KELVIN_TO_CELSIUS(current_temp);
1232
1233 /* select thermal txpower adjustment params, based on channel group
1234 * (same frequency group used for mimo txatten adjustment) */
1235 degrees_per_05db_num =
1236 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1237 degrees_per_05db_denom =
1238 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1239
1240 /* get per-chain txpower values from factory measurements */
1241 for (c = 0; c < 2; c++) {
1242 measurement = &ch_eeprom_info.measurements[c][1];
1243
1244 /* txgain adjustment (in half-dB steps) based on difference
1245 * between factory and current temperature */
1246 factory_temp = measurement->temperature;
1247 iwl4965_math_div_round((current_temp - factory_temp) *
1248 degrees_per_05db_denom,
1249 degrees_per_05db_num,
1250 &temperature_comp[c]);
1251
1252 factory_gain_index[c] = measurement->gain_idx;
1253 factory_actual_pwr[c] = measurement->actual_pow;
1254
1255 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1256 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1257 "curr tmp %d, comp %d steps\n",
1258 factory_temp, current_temp,
1259 temperature_comp[c]);
1260
1261 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1262 factory_gain_index[c],
1263 factory_actual_pwr[c]);
1264 }
1265
1266 /* for each of 33 bit-rates (including 1 for CCK) */
1267 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1268 u8 is_mimo_rate;
1269 union iwl4965_tx_power_dual_stream tx_power;
1270
1271 /* for mimo, reduce each chain's txpower by half
1272 * (3dB, 6 steps), so total output power is regulatory
1273 * compliant. */
1274 if (i & 0x8) {
1275 current_regulatory = reg_limit -
1276 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1277 is_mimo_rate = 1;
1278 } else {
1279 current_regulatory = reg_limit;
1280 is_mimo_rate = 0;
1281 }
1282
1283 /* find txpower limit, either hardware or regulatory */
1284 power_limit = saturation_power - back_off_table[i];
1285 if (power_limit > current_regulatory)
1286 power_limit = current_regulatory;
1287
1288 /* reduce user's txpower request if necessary
1289 * for this rate on this channel */
1290 target_power = user_target_power;
1291 if (target_power > power_limit)
1292 target_power = power_limit;
1293
1294 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1295 i, saturation_power - back_off_table[i],
1296 current_regulatory, user_target_power,
1297 target_power);
1298
1299 /* for each of 2 Tx chains (radio transmitters) */
1300 for (c = 0; c < 2; c++) {
1301 s32 atten_value;
1302
1303 if (is_mimo_rate)
1304 atten_value =
1305 (s32)le32_to_cpu(priv->card_alive_init.
1306 tx_atten[txatten_grp][c]);
1307 else
1308 atten_value = 0;
1309
1310 /* calculate index; higher index means lower txpower */
1311 power_index = (u8) (factory_gain_index[c] -
1312 (target_power -
1313 factory_actual_pwr[c]) -
1314 temperature_comp[c] -
1315 voltage_compensation +
1316 atten_value);
1317
1318 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1319 power_index); */
1320
1321 if (power_index < get_min_power_index(i, band))
1322 power_index = get_min_power_index(i, band);
1323
1324 /* adjust 5 GHz index to support negative indexes */
1325 if (!band)
1326 power_index += 9;
1327
1328 /* CCK, rate 32, reduce txpower for CCK */
1329 if (i == POWER_TABLE_CCK_ENTRY)
1330 power_index +=
1331 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1332
1333 /* stay within the table! */
1334 if (power_index > 107) {
1335 IWL_WARN(priv, "txpower index %d > 107\n",
1336 power_index);
1337 power_index = 107;
1338 }
1339 if (power_index < 0) {
1340 IWL_WARN(priv, "txpower index %d < 0\n",
1341 power_index);
1342 power_index = 0;
1343 }
1344
1345 /* fill txpower command for this rate/chain */
1346 tx_power.s.radio_tx_gain[c] =
1347 gain_table[band][power_index].radio;
1348 tx_power.s.dsp_predis_atten[c] =
1349 gain_table[band][power_index].dsp;
1350
1351 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1352 "gain 0x%02x dsp %d\n",
1353 c, atten_value, power_index,
1354 tx_power.s.radio_tx_gain[c],
1355 tx_power.s.dsp_predis_atten[c]);
1356 } /* for each chain */
1357
1358 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1359
1360 } /* for each rate */
1361
1362 return 0;
1363 }
1364
1365 /**
1366 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1367 *
1368 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1369 * The power limit is taken from priv->tx_power_user_lmt.
1370 */
1371 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1372 {
1373 struct iwl4965_txpowertable_cmd cmd = { 0 };
1374 int ret;
1375 u8 band = 0;
1376 bool is_ht40 = false;
1377 u8 ctrl_chan_high = 0;
1378 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1379
1380 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1381 "TX Power requested while scanning!\n"))
1382 return -EAGAIN;
1383
1384 band = priv->band == IEEE80211_BAND_2GHZ;
1385
1386 is_ht40 = is_ht40_channel(ctx->active.flags);
1387
1388 if (is_ht40 && (ctx->active.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1389 ctrl_chan_high = 1;
1390
1391 cmd.band = band;
1392 cmd.channel = ctx->active.channel;
1393
1394 ret = iwl4965_fill_txpower_tbl(priv, band,
1395 le16_to_cpu(ctx->active.channel),
1396 is_ht40, ctrl_chan_high, &cmd.tx_power);
1397 if (ret)
1398 goto out;
1399
1400 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1401
1402 out:
1403 return ret;
1404 }
1405
1406 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv,
1407 struct iwl_rxon_context *ctx)
1408 {
1409 int ret = 0;
1410 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1411 const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1412 const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1413
1414 if ((rxon1->flags == rxon2->flags) &&
1415 (rxon1->filter_flags == rxon2->filter_flags) &&
1416 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1417 (rxon1->ofdm_ht_single_stream_basic_rates ==
1418 rxon2->ofdm_ht_single_stream_basic_rates) &&
1419 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1420 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1421 (rxon1->rx_chain == rxon2->rx_chain) &&
1422 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1423 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1424 return 0;
1425 }
1426
1427 rxon_assoc.flags = ctx->staging.flags;
1428 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1429 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1430 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1431 rxon_assoc.reserved = 0;
1432 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1433 ctx->staging.ofdm_ht_single_stream_basic_rates;
1434 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1435 ctx->staging.ofdm_ht_dual_stream_basic_rates;
1436 rxon_assoc.rx_chain_select_flags = ctx->staging.rx_chain;
1437
1438 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1439 sizeof(rxon_assoc), &rxon_assoc, NULL);
1440 if (ret)
1441 return ret;
1442
1443 return ret;
1444 }
1445
1446 static int iwl4965_hw_channel_switch(struct iwl_priv *priv,
1447 struct ieee80211_channel_switch *ch_switch)
1448 {
1449 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1450 int rc;
1451 u8 band = 0;
1452 bool is_ht40 = false;
1453 u8 ctrl_chan_high = 0;
1454 struct iwl4965_channel_switch_cmd cmd;
1455 const struct iwl_channel_info *ch_info;
1456 u32 switch_time_in_usec, ucode_switch_time;
1457 u16 ch;
1458 u32 tsf_low;
1459 u8 switch_count;
1460 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
1461 struct ieee80211_vif *vif = ctx->vif;
1462 band = priv->band == IEEE80211_BAND_2GHZ;
1463
1464 is_ht40 = is_ht40_channel(ctx->staging.flags);
1465
1466 if (is_ht40 &&
1467 (ctx->staging.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1468 ctrl_chan_high = 1;
1469
1470 cmd.band = band;
1471 cmd.expect_beacon = 0;
1472 ch = ch_switch->channel->hw_value;
1473 cmd.channel = cpu_to_le16(ch);
1474 cmd.rxon_flags = ctx->staging.flags;
1475 cmd.rxon_filter_flags = ctx->staging.filter_flags;
1476 switch_count = ch_switch->count;
1477 tsf_low = ch_switch->timestamp & 0x0ffffffff;
1478 /*
1479 * calculate the ucode channel switch time
1480 * adding TSF as one of the factor for when to switch
1481 */
1482 if ((priv->ucode_beacon_time > tsf_low) && beacon_interval) {
1483 if (switch_count > ((priv->ucode_beacon_time - tsf_low) /
1484 beacon_interval)) {
1485 switch_count -= (priv->ucode_beacon_time -
1486 tsf_low) / beacon_interval;
1487 } else
1488 switch_count = 0;
1489 }
1490 if (switch_count <= 1)
1491 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1492 else {
1493 switch_time_in_usec =
1494 vif->bss_conf.beacon_int * switch_count * TIME_UNIT;
1495 ucode_switch_time = iwl_usecs_to_beacons(priv,
1496 switch_time_in_usec,
1497 beacon_interval);
1498 cmd.switch_time = iwl_add_beacon_time(priv,
1499 priv->ucode_beacon_time,
1500 ucode_switch_time,
1501 beacon_interval);
1502 }
1503 IWL_DEBUG_11H(priv, "uCode time for the switch is 0x%x\n",
1504 cmd.switch_time);
1505 ch_info = iwl_get_channel_info(priv, priv->band, ch);
1506 if (ch_info)
1507 cmd.expect_beacon = is_channel_radar(ch_info);
1508 else {
1509 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1510 ctx->active.channel, ch);
1511 return -EFAULT;
1512 }
1513
1514 rc = iwl4965_fill_txpower_tbl(priv, band, ch, is_ht40,
1515 ctrl_chan_high, &cmd.tx_power);
1516 if (rc) {
1517 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1518 return rc;
1519 }
1520
1521 priv->switch_rxon.channel = cmd.channel;
1522 priv->switch_rxon.switch_in_progress = true;
1523
1524 return iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1525 }
1526
1527 /**
1528 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1529 */
1530 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1531 struct iwl_tx_queue *txq,
1532 u16 byte_cnt)
1533 {
1534 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1535 int txq_id = txq->q.id;
1536 int write_ptr = txq->q.write_ptr;
1537 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1538 __le16 bc_ent;
1539
1540 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1541
1542 bc_ent = cpu_to_le16(len & 0xFFF);
1543 /* Set up byte count within first 256 entries */
1544 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1545
1546 /* If within first 64 entries, duplicate at end */
1547 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1548 scd_bc_tbl[txq_id].
1549 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1550 }
1551
1552 /**
1553 * sign_extend - Sign extend a value using specified bit as sign-bit
1554 *
1555 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1556 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1557 *
1558 * @param oper value to sign extend
1559 * @param index 0 based bit index (0<=index<32) to sign bit
1560 */
1561 static s32 sign_extend(u32 oper, int index)
1562 {
1563 u8 shift = 31 - index;
1564
1565 return (s32)(oper << shift) >> shift;
1566 }
1567
1568 /**
1569 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1570 * @statistics: Provides the temperature reading from the uCode
1571 *
1572 * A return of <0 indicates bogus data in the statistics
1573 */
1574 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1575 {
1576 s32 temperature;
1577 s32 vt;
1578 s32 R1, R2, R3;
1579 u32 R4;
1580
1581 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1582 (priv->_agn.statistics.flag &
1583 STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1584 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1585 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1586 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1587 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1588 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1589 } else {
1590 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1591 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1592 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1593 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1594 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1595 }
1596
1597 /*
1598 * Temperature is only 23 bits, so sign extend out to 32.
1599 *
1600 * NOTE If we haven't received a statistics notification yet
1601 * with an updated temperature, use R4 provided to us in the
1602 * "initialize" ALIVE response.
1603 */
1604 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1605 vt = sign_extend(R4, 23);
1606 else
1607 vt = sign_extend(le32_to_cpu(priv->_agn.statistics.
1608 general.common.temperature), 23);
1609
1610 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1611
1612 if (R3 == R1) {
1613 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1614 return -1;
1615 }
1616
1617 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1618 * Add offset to center the adjustment around 0 degrees Centigrade. */
1619 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1620 temperature /= (R3 - R1);
1621 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1622
1623 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1624 temperature, KELVIN_TO_CELSIUS(temperature));
1625
1626 return temperature;
1627 }
1628
1629 /* Adjust Txpower only if temperature variance is greater than threshold. */
1630 #define IWL_TEMPERATURE_THRESHOLD 3
1631
1632 /**
1633 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1634 *
1635 * If the temperature changed has changed sufficiently, then a recalibration
1636 * is needed.
1637 *
1638 * Assumes caller will replace priv->last_temperature once calibration
1639 * executed.
1640 */
1641 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1642 {
1643 int temp_diff;
1644
1645 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1646 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1647 return 0;
1648 }
1649
1650 temp_diff = priv->temperature - priv->last_temperature;
1651
1652 /* get absolute value */
1653 if (temp_diff < 0) {
1654 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d\n", temp_diff);
1655 temp_diff = -temp_diff;
1656 } else if (temp_diff == 0)
1657 IWL_DEBUG_POWER(priv, "Temperature unchanged\n");
1658 else
1659 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d\n", temp_diff);
1660
1661 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1662 IWL_DEBUG_POWER(priv, " => thermal txpower calib not needed\n");
1663 return 0;
1664 }
1665
1666 IWL_DEBUG_POWER(priv, " => thermal txpower calib needed\n");
1667
1668 return 1;
1669 }
1670
1671 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1672 {
1673 s32 temp;
1674
1675 temp = iwl4965_hw_get_temperature(priv);
1676 if (temp < 0)
1677 return;
1678
1679 if (priv->temperature != temp) {
1680 if (priv->temperature)
1681 IWL_DEBUG_TEMP(priv, "Temperature changed "
1682 "from %dC to %dC\n",
1683 KELVIN_TO_CELSIUS(priv->temperature),
1684 KELVIN_TO_CELSIUS(temp));
1685 else
1686 IWL_DEBUG_TEMP(priv, "Temperature "
1687 "initialized to %dC\n",
1688 KELVIN_TO_CELSIUS(temp));
1689 }
1690
1691 priv->temperature = temp;
1692 iwl_tt_handler(priv);
1693 set_bit(STATUS_TEMPERATURE, &priv->status);
1694
1695 if (!priv->disable_tx_power_cal &&
1696 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1697 iwl4965_is_temp_calib_needed(priv))
1698 queue_work(priv->workqueue, &priv->txpower_work);
1699 }
1700
1701 /**
1702 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1703 */
1704 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1705 u16 txq_id)
1706 {
1707 /* Simply stop the queue, but don't change any configuration;
1708 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1709 iwl_write_prph(priv,
1710 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1711 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1712 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1713 }
1714
1715 /**
1716 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1717 * priv->lock must be held by the caller
1718 */
1719 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1720 u16 ssn_idx, u8 tx_fifo)
1721 {
1722 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1723 (IWL49_FIRST_AMPDU_QUEUE +
1724 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
1725 IWL_WARN(priv,
1726 "queue number out of range: %d, must be %d to %d\n",
1727 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1728 IWL49_FIRST_AMPDU_QUEUE +
1729 priv->cfg->base_params->num_of_ampdu_queues - 1);
1730 return -EINVAL;
1731 }
1732
1733 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1734
1735 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1736
1737 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1738 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1739 /* supposes that ssn_idx is valid (!= 0xFFF) */
1740 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1741
1742 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1743 iwl_txq_ctx_deactivate(priv, txq_id);
1744 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1745
1746 return 0;
1747 }
1748
1749 /**
1750 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1751 */
1752 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1753 u16 txq_id)
1754 {
1755 u32 tbl_dw_addr;
1756 u32 tbl_dw;
1757 u16 scd_q2ratid;
1758
1759 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1760
1761 tbl_dw_addr = priv->scd_base_addr +
1762 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1763
1764 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1765
1766 if (txq_id & 0x1)
1767 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1768 else
1769 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1770
1771 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1772
1773 return 0;
1774 }
1775
1776
1777 /**
1778 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1779 *
1780 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1781 * i.e. it must be one of the higher queues used for aggregation
1782 */
1783 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1784 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1785 {
1786 unsigned long flags;
1787 u16 ra_tid;
1788 int ret;
1789
1790 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1791 (IWL49_FIRST_AMPDU_QUEUE +
1792 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
1793 IWL_WARN(priv,
1794 "queue number out of range: %d, must be %d to %d\n",
1795 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1796 IWL49_FIRST_AMPDU_QUEUE +
1797 priv->cfg->base_params->num_of_ampdu_queues - 1);
1798 return -EINVAL;
1799 }
1800
1801 ra_tid = BUILD_RAxTID(sta_id, tid);
1802
1803 /* Modify device's station table to Tx this TID */
1804 ret = iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1805 if (ret)
1806 return ret;
1807
1808 spin_lock_irqsave(&priv->lock, flags);
1809
1810 /* Stop this Tx queue before configuring it */
1811 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1812
1813 /* Map receiver-address / traffic-ID to this queue */
1814 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1815
1816 /* Set this queue as a chain-building queue */
1817 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1818
1819 /* Place first TFD at index corresponding to start sequence number.
1820 * Assumes that ssn_idx is valid (!= 0xFFF) */
1821 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1822 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1823 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1824
1825 /* Set up Tx window size and frame limit for this queue */
1826 iwl_write_targ_mem(priv,
1827 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1828 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1829 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1830
1831 iwl_write_targ_mem(priv, priv->scd_base_addr +
1832 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1833 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1834 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1835
1836 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1837
1838 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1839 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1840
1841 spin_unlock_irqrestore(&priv->lock, flags);
1842
1843 return 0;
1844 }
1845
1846
1847 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1848 {
1849 switch (cmd_id) {
1850 case REPLY_RXON:
1851 return (u16) sizeof(struct iwl4965_rxon_cmd);
1852 default:
1853 return len;
1854 }
1855 }
1856
1857 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1858 {
1859 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1860 addsta->mode = cmd->mode;
1861 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1862 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1863 addsta->station_flags = cmd->station_flags;
1864 addsta->station_flags_msk = cmd->station_flags_msk;
1865 addsta->tid_disable_tx = cmd->tid_disable_tx;
1866 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1867 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1868 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1869 addsta->sleep_tx_count = cmd->sleep_tx_count;
1870 addsta->reserved1 = cpu_to_le16(0);
1871 addsta->reserved2 = cpu_to_le16(0);
1872
1873 return (u16)sizeof(struct iwl4965_addsta_cmd);
1874 }
1875
1876 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1877 {
1878 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1879 }
1880
1881 /**
1882 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1883 */
1884 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1885 struct iwl_ht_agg *agg,
1886 struct iwl4965_tx_resp *tx_resp,
1887 int txq_id, u16 start_idx)
1888 {
1889 u16 status;
1890 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1891 struct ieee80211_tx_info *info = NULL;
1892 struct ieee80211_hdr *hdr = NULL;
1893 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1894 int i, sh, idx;
1895 u16 seq;
1896 if (agg->wait_for_ba)
1897 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1898
1899 agg->frame_count = tx_resp->frame_count;
1900 agg->start_idx = start_idx;
1901 agg->rate_n_flags = rate_n_flags;
1902 agg->bitmap = 0;
1903
1904 /* num frames attempted by Tx command */
1905 if (agg->frame_count == 1) {
1906 /* Only one frame was attempted; no block-ack will arrive */
1907 status = le16_to_cpu(frame_status[0].status);
1908 idx = start_idx;
1909
1910 /* FIXME: code repetition */
1911 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1912 agg->frame_count, agg->start_idx, idx);
1913
1914 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb);
1915 info->status.rates[0].count = tx_resp->failure_frame + 1;
1916 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1917 info->flags |= iwl_tx_status_to_mac80211(status);
1918 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
1919 /* FIXME: code repetition end */
1920
1921 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1922 status & 0xff, tx_resp->failure_frame);
1923 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1924
1925 agg->wait_for_ba = 0;
1926 } else {
1927 /* Two or more frames were attempted; expect block-ack */
1928 u64 bitmap = 0;
1929 int start = agg->start_idx;
1930
1931 /* Construct bit-map of pending frames within Tx window */
1932 for (i = 0; i < agg->frame_count; i++) {
1933 u16 sc;
1934 status = le16_to_cpu(frame_status[i].status);
1935 seq = le16_to_cpu(frame_status[i].sequence);
1936 idx = SEQ_TO_INDEX(seq);
1937 txq_id = SEQ_TO_QUEUE(seq);
1938
1939 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1940 AGG_TX_STATE_ABORT_MSK))
1941 continue;
1942
1943 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1944 agg->frame_count, txq_id, idx);
1945
1946 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1947 if (!hdr) {
1948 IWL_ERR(priv,
1949 "BUG_ON idx doesn't point to valid skb"
1950 " idx=%d, txq_id=%d\n", idx, txq_id);
1951 return -1;
1952 }
1953
1954 sc = le16_to_cpu(hdr->seq_ctrl);
1955 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1956 IWL_ERR(priv,
1957 "BUG_ON idx doesn't match seq control"
1958 " idx=%d, seq_idx=%d, seq=%d\n",
1959 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
1960 return -1;
1961 }
1962
1963 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1964 i, idx, SEQ_TO_SN(sc));
1965
1966 sh = idx - start;
1967 if (sh > 64) {
1968 sh = (start - idx) + 0xff;
1969 bitmap = bitmap << sh;
1970 sh = 0;
1971 start = idx;
1972 } else if (sh < -64)
1973 sh = 0xff - (start - idx);
1974 else if (sh < 0) {
1975 sh = start - idx;
1976 start = idx;
1977 bitmap = bitmap << sh;
1978 sh = 0;
1979 }
1980 bitmap |= 1ULL << sh;
1981 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1982 start, (unsigned long long)bitmap);
1983 }
1984
1985 agg->bitmap = bitmap;
1986 agg->start_idx = start;
1987 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1988 agg->frame_count, agg->start_idx,
1989 (unsigned long long)agg->bitmap);
1990
1991 if (bitmap)
1992 agg->wait_for_ba = 1;
1993 }
1994 return 0;
1995 }
1996
1997 static u8 iwl_find_station(struct iwl_priv *priv, const u8 *addr)
1998 {
1999 int i;
2000 int start = 0;
2001 int ret = IWL_INVALID_STATION;
2002 unsigned long flags;
2003
2004 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
2005 (priv->iw_mode == NL80211_IFTYPE_AP))
2006 start = IWL_STA_ID;
2007
2008 if (is_broadcast_ether_addr(addr))
2009 return priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2010
2011 spin_lock_irqsave(&priv->sta_lock, flags);
2012 for (i = start; i < priv->hw_params.max_stations; i++)
2013 if (priv->stations[i].used &&
2014 (!compare_ether_addr(priv->stations[i].sta.sta.addr,
2015 addr))) {
2016 ret = i;
2017 goto out;
2018 }
2019
2020 IWL_DEBUG_ASSOC_LIMIT(priv, "can not find STA %pM total %d\n",
2021 addr, priv->num_stations);
2022
2023 out:
2024 /*
2025 * It may be possible that more commands interacting with stations
2026 * arrive before we completed processing the adding of
2027 * station
2028 */
2029 if (ret != IWL_INVALID_STATION &&
2030 (!(priv->stations[ret].used & IWL_STA_UCODE_ACTIVE) ||
2031 ((priv->stations[ret].used & IWL_STA_UCODE_ACTIVE) &&
2032 (priv->stations[ret].used & IWL_STA_UCODE_INPROGRESS)))) {
2033 IWL_ERR(priv, "Requested station info for sta %d before ready.\n",
2034 ret);
2035 ret = IWL_INVALID_STATION;
2036 }
2037 spin_unlock_irqrestore(&priv->sta_lock, flags);
2038 return ret;
2039 }
2040
2041 static int iwl_get_ra_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
2042 {
2043 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
2044 return IWL_AP_ID;
2045 } else {
2046 u8 *da = ieee80211_get_DA(hdr);
2047 return iwl_find_station(priv, da);
2048 }
2049 }
2050
2051 /**
2052 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2053 */
2054 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2055 struct iwl_rx_mem_buffer *rxb)
2056 {
2057 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2058 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2059 int txq_id = SEQ_TO_QUEUE(sequence);
2060 int index = SEQ_TO_INDEX(sequence);
2061 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2062 struct ieee80211_hdr *hdr;
2063 struct ieee80211_tx_info *info;
2064 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2065 u32 status = le32_to_cpu(tx_resp->u.status);
2066 int uninitialized_var(tid);
2067 int sta_id;
2068 int freed;
2069 u8 *qc = NULL;
2070 unsigned long flags;
2071
2072 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2073 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2074 "is out of range [0-%d] %d %d\n", txq_id,
2075 index, txq->q.n_bd, txq->q.write_ptr,
2076 txq->q.read_ptr);
2077 return;
2078 }
2079
2080 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
2081 memset(&info->status, 0, sizeof(info->status));
2082
2083 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2084 if (ieee80211_is_data_qos(hdr->frame_control)) {
2085 qc = ieee80211_get_qos_ctl(hdr);
2086 tid = qc[0] & 0xf;
2087 }
2088
2089 sta_id = iwl_get_ra_sta_id(priv, hdr);
2090 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2091 IWL_ERR(priv, "Station not known\n");
2092 return;
2093 }
2094
2095 spin_lock_irqsave(&priv->sta_lock, flags);
2096 if (txq->sched_retry) {
2097 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2098 struct iwl_ht_agg *agg = NULL;
2099 WARN_ON(!qc);
2100
2101 agg = &priv->stations[sta_id].tid[tid].agg;
2102
2103 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2104
2105 /* check if BAR is needed */
2106 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2107 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2108
2109 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2110 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2111 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2112 "%d index %d\n", scd_ssn , index);
2113 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2114 if (qc)
2115 iwl_free_tfds_in_queue(priv, sta_id,
2116 tid, freed);
2117
2118 if (priv->mac80211_registered &&
2119 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2120 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2121 if (agg->state == IWL_AGG_OFF)
2122 iwl_wake_queue(priv, txq_id);
2123 else
2124 iwl_wake_queue(priv, txq->swq_id);
2125 }
2126 }
2127 } else {
2128 info->status.rates[0].count = tx_resp->failure_frame + 1;
2129 info->flags |= iwl_tx_status_to_mac80211(status);
2130 iwlagn_hwrate_to_tx_control(priv,
2131 le32_to_cpu(tx_resp->rate_n_flags),
2132 info);
2133
2134 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2135 "rate_n_flags 0x%x retries %d\n",
2136 txq_id,
2137 iwl_get_tx_fail_reason(status), status,
2138 le32_to_cpu(tx_resp->rate_n_flags),
2139 tx_resp->failure_frame);
2140
2141 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
2142 if (qc && likely(sta_id != IWL_INVALID_STATION))
2143 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
2144 else if (sta_id == IWL_INVALID_STATION)
2145 IWL_DEBUG_TX_REPLY(priv, "Station not known\n");
2146
2147 if (priv->mac80211_registered &&
2148 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2149 iwl_wake_queue(priv, txq_id);
2150 }
2151 if (qc && likely(sta_id != IWL_INVALID_STATION))
2152 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
2153
2154 iwl_check_abort_status(priv, tx_resp->frame_count, status);
2155
2156 spin_unlock_irqrestore(&priv->sta_lock, flags);
2157 }
2158
2159 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2160 struct iwl_rx_phy_res *rx_resp)
2161 {
2162 /* data from PHY/DSP regarding signal strength, etc.,
2163 * contents are always there, not configurable by host. */
2164 struct iwl4965_rx_non_cfg_phy *ncphy =
2165 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2166 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2167 >> IWL49_AGC_DB_POS;
2168
2169 u32 valid_antennae =
2170 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2171 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2172 u8 max_rssi = 0;
2173 u32 i;
2174
2175 /* Find max rssi among 3 possible receivers.
2176 * These values are measured by the digital signal processor (DSP).
2177 * They should stay fairly constant even as the signal strength varies,
2178 * if the radio's automatic gain control (AGC) is working right.
2179 * AGC value (see below) will provide the "interesting" info. */
2180 for (i = 0; i < 3; i++)
2181 if (valid_antennae & (1 << i))
2182 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2183
2184 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2185 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2186 max_rssi, agc);
2187
2188 /* dBm = max_rssi dB - agc dB - constant.
2189 * Higher AGC (higher radio gain) means lower signal. */
2190 return max_rssi - agc - IWLAGN_RSSI_OFFSET;
2191 }
2192
2193
2194 /* Set up 4965-specific Rx frame reply handlers */
2195 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2196 {
2197 /* Legacy Rx frames */
2198 priv->rx_handlers[REPLY_RX] = iwlagn_rx_reply_rx;
2199 /* Tx response */
2200 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2201 }
2202
2203 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2204 {
2205 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2206 }
2207
2208 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2209 {
2210 cancel_work_sync(&priv->txpower_work);
2211 }
2212
2213 static struct iwl_hcmd_ops iwl4965_hcmd = {
2214 .rxon_assoc = iwl4965_send_rxon_assoc,
2215 .commit_rxon = iwlagn_commit_rxon,
2216 .set_rxon_chain = iwlagn_set_rxon_chain,
2217 .send_bt_config = iwl_send_bt_config,
2218 };
2219
2220 static void iwl4965_post_scan(struct iwl_priv *priv)
2221 {
2222 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2223
2224 /*
2225 * Since setting the RXON may have been deferred while
2226 * performing the scan, fire one off if needed
2227 */
2228 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
2229 iwlcore_commit_rxon(priv, ctx);
2230 }
2231
2232 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2233 .get_hcmd_size = iwl4965_get_hcmd_size,
2234 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2235 .chain_noise_reset = iwl4965_chain_noise_reset,
2236 .gain_computation = iwl4965_gain_computation,
2237 .tx_cmd_protection = iwlcore_tx_cmd_protection,
2238 .calc_rssi = iwl4965_calc_rssi,
2239 .request_scan = iwlagn_request_scan,
2240 .post_scan = iwl4965_post_scan,
2241 };
2242
2243 static struct iwl_lib_ops iwl4965_lib = {
2244 .set_hw_params = iwl4965_hw_set_hw_params,
2245 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2246 .txq_set_sched = iwl4965_txq_set_sched,
2247 .txq_agg_enable = iwl4965_txq_agg_enable,
2248 .txq_agg_disable = iwl4965_txq_agg_disable,
2249 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2250 .txq_free_tfd = iwl_hw_txq_free_tfd,
2251 .txq_init = iwl_hw_tx_queue_init,
2252 .rx_handler_setup = iwl4965_rx_handler_setup,
2253 .setup_deferred_work = iwl4965_setup_deferred_work,
2254 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2255 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2256 .alive_notify = iwl4965_alive_notify,
2257 .init_alive_start = iwl4965_init_alive_start,
2258 .load_ucode = iwl4965_load_bsm,
2259 .dump_nic_event_log = iwl_dump_nic_event_log,
2260 .dump_nic_error_log = iwl_dump_nic_error_log,
2261 .dump_fh = iwl_dump_fh,
2262 .set_channel_switch = iwl4965_hw_channel_switch,
2263 .apm_ops = {
2264 .init = iwl_apm_init,
2265 .config = iwl4965_nic_config,
2266 },
2267 .eeprom_ops = {
2268 .regulatory_bands = {
2269 EEPROM_REGULATORY_BAND_1_CHANNELS,
2270 EEPROM_REGULATORY_BAND_2_CHANNELS,
2271 EEPROM_REGULATORY_BAND_3_CHANNELS,
2272 EEPROM_REGULATORY_BAND_4_CHANNELS,
2273 EEPROM_REGULATORY_BAND_5_CHANNELS,
2274 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2275 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2276 },
2277 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2278 .release_semaphore = iwlcore_eeprom_release_semaphore,
2279 .calib_version = iwl4965_eeprom_calib_version,
2280 .query_addr = iwlcore_eeprom_query_addr,
2281 },
2282 .send_tx_power = iwl4965_send_tx_power,
2283 .update_chain_flags = iwl_update_chain_flags,
2284 .post_associate = iwl_post_associate,
2285 .config_ap = iwl_config_ap,
2286 .isr = iwl_isr_legacy,
2287 .temp_ops = {
2288 .temperature = iwl4965_temperature_calib,
2289 },
2290 .manage_ibss_station = iwlagn_manage_ibss_station,
2291 .update_bcast_stations = iwl_update_bcast_stations,
2292 .debugfs_ops = {
2293 .rx_stats_read = iwl_ucode_rx_stats_read,
2294 .tx_stats_read = iwl_ucode_tx_stats_read,
2295 .general_stats_read = iwl_ucode_general_stats_read,
2296 .bt_stats_read = iwl_ucode_bt_stats_read,
2297 .reply_tx_error = iwl_reply_tx_error_read,
2298 },
2299 .recover_from_tx_stall = iwl_bg_monitor_recover,
2300 .check_plcp_health = iwl_good_plcp_health,
2301 };
2302
2303 static const struct iwl_ops iwl4965_ops = {
2304 .lib = &iwl4965_lib,
2305 .hcmd = &iwl4965_hcmd,
2306 .utils = &iwl4965_hcmd_utils,
2307 .led = &iwlagn_led_ops,
2308 .ieee80211_ops = &iwlagn_hw_ops,
2309 };
2310
2311 static struct iwl_base_params iwl4965_base_params = {
2312 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2313 .num_of_queues = IWL49_NUM_QUEUES,
2314 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
2315 .pll_cfg_val = 0,
2316 .set_l0s = true,
2317 .use_bsm = true,
2318 .use_isr_legacy = true,
2319 .broken_powersave = true,
2320 .led_compensation = 61,
2321 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2322 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2323 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
2324 .temperature_kelvin = true,
2325 .max_event_log_size = 512,
2326 .tx_power_by_driver = true,
2327 .ucode_tracing = true,
2328 .sensitivity_calib_by_driver = true,
2329 .chain_noise_calib_by_driver = true,
2330 };
2331
2332 struct iwl_cfg iwl4965_agn_cfg = {
2333 .name = "Intel(R) Wireless WiFi Link 4965AGN",
2334 .fw_name_pre = IWL4965_FW_PRE,
2335 .ucode_api_max = IWL4965_UCODE_API_MAX,
2336 .ucode_api_min = IWL4965_UCODE_API_MIN,
2337 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2338 .valid_tx_ant = ANT_AB,
2339 .valid_rx_ant = ANT_ABC,
2340 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2341 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2342 .ops = &iwl4965_ops,
2343 .mod_params = &iwlagn_mod_params,
2344 .base_params = &iwl4965_base_params,
2345 /*
2346 * Force use of chains B and C for scan RX on 5 GHz band
2347 * because the device has off-channel reception on chain A.
2348 */
2349 .scan_rx_antennas[IEEE80211_BAND_5GHZ] = ANT_BC,
2350 };
2351
2352 /* Module firmware */
2353 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2354
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree