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x86: remove 32-bit versions of readq()/writeq()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / qla4xxx / ql4_nx.c
blob03e522b2fe0be6f70f9bc4838ff109a789e1c0c1
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7 #include <linux/delay.h>
8 #include <linux/io.h>
9 #include <linux/pci.h>
10 #include "ql4_def.h"
11 #include "ql4_glbl.h"
12
13 #define MASK(n) DMA_BIT_MASK(n)
14 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
15 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
16 #define MS_WIN(addr) (addr & 0x0ffc0000)
17 #define QLA82XX_PCI_MN_2M (0)
18 #define QLA82XX_PCI_MS_2M (0x80000)
19 #define QLA82XX_PCI_OCM0_2M (0xc0000)
20 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
21 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
22
23 /* CRB window related */
24 #define CRB_BLK(off) ((off >> 20) & 0x3f)
25 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
26 #define CRB_WINDOW_2M (0x130060)
27 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
28 ((off) & 0xf0000))
29 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
30 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
31 #define CRB_INDIRECT_2M (0x1e0000UL)
32
33 static inline void __iomem *
34 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
35 {
36 if ((off < ha->first_page_group_end) &&
37 (off >= ha->first_page_group_start))
38 return (void __iomem *)(ha->nx_pcibase + off);
39
40 return NULL;
41 }
42
43 #define MAX_CRB_XFORM 60
44 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
45 static int qla4_8xxx_crb_table_initialized;
46
47 #define qla4_8xxx_crb_addr_transform(name) \
48 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
49 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
50 static void
51 qla4_8xxx_crb_addr_transform_setup(void)
52 {
53 qla4_8xxx_crb_addr_transform(XDMA);
54 qla4_8xxx_crb_addr_transform(TIMR);
55 qla4_8xxx_crb_addr_transform(SRE);
56 qla4_8xxx_crb_addr_transform(SQN3);
57 qla4_8xxx_crb_addr_transform(SQN2);
58 qla4_8xxx_crb_addr_transform(SQN1);
59 qla4_8xxx_crb_addr_transform(SQN0);
60 qla4_8xxx_crb_addr_transform(SQS3);
61 qla4_8xxx_crb_addr_transform(SQS2);
62 qla4_8xxx_crb_addr_transform(SQS1);
63 qla4_8xxx_crb_addr_transform(SQS0);
64 qla4_8xxx_crb_addr_transform(RPMX7);
65 qla4_8xxx_crb_addr_transform(RPMX6);
66 qla4_8xxx_crb_addr_transform(RPMX5);
67 qla4_8xxx_crb_addr_transform(RPMX4);
68 qla4_8xxx_crb_addr_transform(RPMX3);
69 qla4_8xxx_crb_addr_transform(RPMX2);
70 qla4_8xxx_crb_addr_transform(RPMX1);
71 qla4_8xxx_crb_addr_transform(RPMX0);
72 qla4_8xxx_crb_addr_transform(ROMUSB);
73 qla4_8xxx_crb_addr_transform(SN);
74 qla4_8xxx_crb_addr_transform(QMN);
75 qla4_8xxx_crb_addr_transform(QMS);
76 qla4_8xxx_crb_addr_transform(PGNI);
77 qla4_8xxx_crb_addr_transform(PGND);
78 qla4_8xxx_crb_addr_transform(PGN3);
79 qla4_8xxx_crb_addr_transform(PGN2);
80 qla4_8xxx_crb_addr_transform(PGN1);
81 qla4_8xxx_crb_addr_transform(PGN0);
82 qla4_8xxx_crb_addr_transform(PGSI);
83 qla4_8xxx_crb_addr_transform(PGSD);
84 qla4_8xxx_crb_addr_transform(PGS3);
85 qla4_8xxx_crb_addr_transform(PGS2);
86 qla4_8xxx_crb_addr_transform(PGS1);
87 qla4_8xxx_crb_addr_transform(PGS0);
88 qla4_8xxx_crb_addr_transform(PS);
89 qla4_8xxx_crb_addr_transform(PH);
90 qla4_8xxx_crb_addr_transform(NIU);
91 qla4_8xxx_crb_addr_transform(I2Q);
92 qla4_8xxx_crb_addr_transform(EG);
93 qla4_8xxx_crb_addr_transform(MN);
94 qla4_8xxx_crb_addr_transform(MS);
95 qla4_8xxx_crb_addr_transform(CAS2);
96 qla4_8xxx_crb_addr_transform(CAS1);
97 qla4_8xxx_crb_addr_transform(CAS0);
98 qla4_8xxx_crb_addr_transform(CAM);
99 qla4_8xxx_crb_addr_transform(C2C1);
100 qla4_8xxx_crb_addr_transform(C2C0);
101 qla4_8xxx_crb_addr_transform(SMB);
102 qla4_8xxx_crb_addr_transform(OCM0);
103 qla4_8xxx_crb_addr_transform(I2C0);
104
105 qla4_8xxx_crb_table_initialized = 1;
106 }
107
108 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
109 {{{0, 0, 0, 0} } }, /* 0: PCI */
110 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
111 {1, 0x0110000, 0x0120000, 0x130000},
112 {1, 0x0120000, 0x0122000, 0x124000},
113 {1, 0x0130000, 0x0132000, 0x126000},
114 {1, 0x0140000, 0x0142000, 0x128000},
115 {1, 0x0150000, 0x0152000, 0x12a000},
116 {1, 0x0160000, 0x0170000, 0x110000},
117 {1, 0x0170000, 0x0172000, 0x12e000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x01e0000, 0x01e0800, 0x122000},
125 {0, 0x0000000, 0x0000000, 0x000000} } },
126 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
127 {{{0, 0, 0, 0} } }, /* 3: */
128 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
129 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
130 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
131 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
132 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x08f0000, 0x08f2000, 0x172000} } },
148 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x09f0000, 0x09f2000, 0x176000} } },
164 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
180 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
196 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
197 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
198 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
199 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
200 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
201 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
202 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
203 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
204 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
205 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
206 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
207 {{{0, 0, 0, 0} } }, /* 23: */
208 {{{0, 0, 0, 0} } }, /* 24: */
209 {{{0, 0, 0, 0} } }, /* 25: */
210 {{{0, 0, 0, 0} } }, /* 26: */
211 {{{0, 0, 0, 0} } }, /* 27: */
212 {{{0, 0, 0, 0} } }, /* 28: */
213 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
214 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
215 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
216 {{{0} } }, /* 32: PCI */
217 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
218 {1, 0x2110000, 0x2120000, 0x130000},
219 {1, 0x2120000, 0x2122000, 0x124000},
220 {1, 0x2130000, 0x2132000, 0x126000},
221 {1, 0x2140000, 0x2142000, 0x128000},
222 {1, 0x2150000, 0x2152000, 0x12a000},
223 {1, 0x2160000, 0x2170000, 0x110000},
224 {1, 0x2170000, 0x2172000, 0x12e000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000} } },
233 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
234 {{{0} } }, /* 35: */
235 {{{0} } }, /* 36: */
236 {{{0} } }, /* 37: */
237 {{{0} } }, /* 38: */
238 {{{0} } }, /* 39: */
239 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
240 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
241 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
242 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
243 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
244 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
245 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
246 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
247 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
248 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
249 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
250 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
251 {{{0} } }, /* 52: */
252 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
253 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
254 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
255 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
256 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
257 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
258 {{{0} } }, /* 59: I2C0 */
259 {{{0} } }, /* 60: I2C1 */
260 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
261 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
262 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
263 };
264
265 /*
266 * top 12 bits of crb internal address (hub, agent)
267 */
268 static unsigned qla4_8xxx_crb_hub_agt[64] = {
269 0,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
273 0,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
299 0,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
303 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
304 0,
305 0,
306 0,
307 0,
308 0,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
310 0,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
321 0,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
326 0,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
330 0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
332 0,
333 };
334
335 /* Device states */
336 static char *qdev_state[] = {
337 "Unknown",
338 "Cold",
339 "Initializing",
340 "Ready",
341 "Need Reset",
342 "Need Quiescent",
343 "Failed",
344 "Quiescent",
345 };
346
347 /*
348 * In: 'off' is offset from CRB space in 128M pci map
349 * Out: 'off' is 2M pci map addr
350 * side effect: lock crb window
351 */
352 static void
353 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
354 {
355 u32 win_read;
356
357 ha->crb_win = CRB_HI(*off);
358 writel(ha->crb_win,
359 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
360
361 /* Read back value to make sure write has gone through before trying
362 * to use it. */
363 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
364 if (win_read != ha->crb_win) {
365 DEBUG2(ql4_printk(KERN_INFO, ha,
366 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
367 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
368 }
369 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
370 }
371
372 void
373 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
374 {
375 unsigned long flags = 0;
376 int rv;
377
378 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
379
380 BUG_ON(rv == -1);
381
382 if (rv == 1) {
383 write_lock_irqsave(&ha->hw_lock, flags);
384 qla4_8xxx_crb_win_lock(ha);
385 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
386 }
387
388 writel(data, (void __iomem *)off);
389
390 if (rv == 1) {
391 qla4_8xxx_crb_win_unlock(ha);
392 write_unlock_irqrestore(&ha->hw_lock, flags);
393 }
394 }
395
396 int
397 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
398 {
399 unsigned long flags = 0;
400 int rv;
401 u32 data;
402
403 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
404
405 BUG_ON(rv == -1);
406
407 if (rv == 1) {
408 write_lock_irqsave(&ha->hw_lock, flags);
409 qla4_8xxx_crb_win_lock(ha);
410 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
411 }
412 data = readl((void __iomem *)off);
413
414 if (rv == 1) {
415 qla4_8xxx_crb_win_unlock(ha);
416 write_unlock_irqrestore(&ha->hw_lock, flags);
417 }
418 return data;
419 }
420
421 #define CRB_WIN_LOCK_TIMEOUT 100000000
422
423 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
424 {
425 int i;
426 int done = 0, timeout = 0;
427
428 while (!done) {
429 /* acquire semaphore3 from PCI HW block */
430 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
431 if (done == 1)
432 break;
433 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
434 return -1;
435
436 timeout++;
437
438 /* Yield CPU */
439 if (!in_interrupt())
440 schedule();
441 else {
442 for (i = 0; i < 20; i++)
443 cpu_relax(); /*This a nop instr on i386*/
444 }
445 }
446 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
447 return 0;
448 }
449
450 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
451 {
452 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
453 }
454
455 #define IDC_LOCK_TIMEOUT 100000000
456
457 /**
458 * qla4_8xxx_idc_lock - hw_lock
459 * @ha: pointer to adapter structure
460 *
461 * General purpose lock used to synchronize access to
462 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
463 **/
464 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
465 {
466 int i;
467 int done = 0, timeout = 0;
468
469 while (!done) {
470 /* acquire semaphore5 from PCI HW block */
471 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
472 if (done == 1)
473 break;
474 if (timeout >= IDC_LOCK_TIMEOUT)
475 return -1;
476
477 timeout++;
478
479 /* Yield CPU */
480 if (!in_interrupt())
481 schedule();
482 else {
483 for (i = 0; i < 20; i++)
484 cpu_relax(); /*This a nop instr on i386*/
485 }
486 }
487 return 0;
488 }
489
490 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
491 {
492 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
493 }
494
495 int
496 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
497 {
498 struct crb_128M_2M_sub_block_map *m;
499
500 if (*off >= QLA82XX_CRB_MAX)
501 return -1;
502
503 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
504 *off = (*off - QLA82XX_PCI_CAMQM) +
505 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
506 return 0;
507 }
508
509 if (*off < QLA82XX_PCI_CRBSPACE)
510 return -1;
511
512 *off -= QLA82XX_PCI_CRBSPACE;
513 /*
514 * Try direct map
515 */
516
517 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
518
519 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
520 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
521 return 0;
522 }
523
524 /*
525 * Not in direct map, use crb window
526 */
527 return 1;
528 }
529
530 /* PCI Windowing for DDR regions. */
531 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
532 (((addr) <= (high)) && ((addr) >= (low)))
533
534 /*
535 * check memory access boundary.
536 * used by test agent. support ddr access only for now
537 */
538 static unsigned long
539 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
540 unsigned long long addr, int size)
541 {
542 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
543 QLA82XX_ADDR_DDR_NET_MAX) ||
544 !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
545 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
546 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
547 return 0;
548 }
549 return 1;
550 }
551
552 static int qla4_8xxx_pci_set_window_warning_count;
553
554 static unsigned long
555 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
556 {
557 int window;
558 u32 win_read;
559
560 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
561 QLA82XX_ADDR_DDR_NET_MAX)) {
562 /* DDR network side */
563 window = MN_WIN(addr);
564 ha->ddr_mn_window = window;
565 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
566 QLA82XX_PCI_CRBSPACE, window);
567 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
568 QLA82XX_PCI_CRBSPACE);
569 if ((win_read << 17) != window) {
570 ql4_printk(KERN_WARNING, ha,
571 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
572 __func__, window, win_read);
573 }
574 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
575 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
576 QLA82XX_ADDR_OCM0_MAX)) {
577 unsigned int temp1;
578 /* if bits 19:18&17:11 are on */
579 if ((addr & 0x00ff800) == 0xff800) {
580 printk("%s: QM access not handled.\n", __func__);
581 addr = -1UL;
582 }
583
584 window = OCM_WIN(addr);
585 ha->ddr_mn_window = window;
586 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
587 QLA82XX_PCI_CRBSPACE, window);
588 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
589 QLA82XX_PCI_CRBSPACE);
590 temp1 = ((window & 0x1FF) << 7) |
591 ((window & 0x0FFFE0000) >> 17);
592 if (win_read != temp1) {
593 printk("%s: Written OCMwin (0x%x) != Read"
594 " OCMwin (0x%x)\n", __func__, temp1, win_read);
595 }
596 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
597
598 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
599 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
600 /* QDR network side */
601 window = MS_WIN(addr);
602 ha->qdr_sn_window = window;
603 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
604 QLA82XX_PCI_CRBSPACE, window);
605 win_read = qla4_8xxx_rd_32(ha,
606 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
607 if (win_read != window) {
608 printk("%s: Written MSwin (0x%x) != Read "
609 "MSwin (0x%x)\n", __func__, window, win_read);
610 }
611 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
612
613 } else {
614 /*
615 * peg gdb frequently accesses memory that doesn't exist,
616 * this limits the chit chat so debugging isn't slowed down.
617 */
618 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
619 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
620 printk("%s: Warning:%s Unknown address range!\n",
621 __func__, DRIVER_NAME);
622 }
623 addr = -1UL;
624 }
625 return addr;
626 }
627
628 /* check if address is in the same windows as the previous access */
629 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
630 unsigned long long addr)
631 {
632 int window;
633 unsigned long long qdr_max;
634
635 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
636
637 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
638 QLA82XX_ADDR_DDR_NET_MAX)) {
639 /* DDR network side */
640 BUG(); /* MN access can not come here */
641 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
642 QLA82XX_ADDR_OCM0_MAX)) {
643 return 1;
644 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
645 QLA82XX_ADDR_OCM1_MAX)) {
646 return 1;
647 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
648 qdr_max)) {
649 /* QDR network side */
650 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
651 if (ha->qdr_sn_window == window)
652 return 1;
653 }
654
655 return 0;
656 }
657
658 #ifndef readq
659 static inline __u64 readq(const volatile void __iomem *addr)
660 {
661 const volatile u32 __iomem *p = addr;
662 u32 low, high;
663
664 low = readl(p);
665 high = readl(p + 1);
666
667 return low + ((u64)high << 32);
668 }
669 #endif
670
671 #ifndef writeq
672 static inline void writeq(__u64 val, volatile void __iomem *addr)
673 {
674 writel(val, addr);
675 writel(val >> 32, addr+4);
676 }
677 #endif
678
679 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
680 u64 off, void *data, int size)
681 {
682 unsigned long flags;
683 void __iomem *addr;
684 int ret = 0;
685 u64 start;
686 void __iomem *mem_ptr = NULL;
687 unsigned long mem_base;
688 unsigned long mem_page;
689
690 write_lock_irqsave(&ha->hw_lock, flags);
691
692 /*
693 * If attempting to access unknown address or straddle hw windows,
694 * do not access.
695 */
696 start = qla4_8xxx_pci_set_window(ha, off);
697 if ((start == -1UL) ||
698 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
699 write_unlock_irqrestore(&ha->hw_lock, flags);
700 printk(KERN_ERR"%s out of bound pci memory access. "
701 "offset is 0x%llx\n", DRIVER_NAME, off);
702 return -1;
703 }
704
705 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
706 if (!addr) {
707 write_unlock_irqrestore(&ha->hw_lock, flags);
708 mem_base = pci_resource_start(ha->pdev, 0);
709 mem_page = start & PAGE_MASK;
710 /* Map two pages whenever user tries to access addresses in two
711 consecutive pages.
712 */
713 if (mem_page != ((start + size - 1) & PAGE_MASK))
714 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
715 else
716 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
717
718 if (mem_ptr == NULL) {
719 *(u8 *)data = 0;
720 return -1;
721 }
722 addr = mem_ptr;
723 addr += start & (PAGE_SIZE - 1);
724 write_lock_irqsave(&ha->hw_lock, flags);
725 }
726
727 switch (size) {
728 case 1:
729 *(u8 *)data = readb(addr);
730 break;
731 case 2:
732 *(u16 *)data = readw(addr);
733 break;
734 case 4:
735 *(u32 *)data = readl(addr);
736 break;
737 case 8:
738 *(u64 *)data = readq(addr);
739 break;
740 default:
741 ret = -1;
742 break;
743 }
744 write_unlock_irqrestore(&ha->hw_lock, flags);
745
746 if (mem_ptr)
747 iounmap(mem_ptr);
748 return ret;
749 }
750
751 static int
752 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
753 void *data, int size)
754 {
755 unsigned long flags;
756 void __iomem *addr;
757 int ret = 0;
758 u64 start;
759 void __iomem *mem_ptr = NULL;
760 unsigned long mem_base;
761 unsigned long mem_page;
762
763 write_lock_irqsave(&ha->hw_lock, flags);
764
765 /*
766 * If attempting to access unknown address or straddle hw windows,
767 * do not access.
768 */
769 start = qla4_8xxx_pci_set_window(ha, off);
770 if ((start == -1UL) ||
771 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
772 write_unlock_irqrestore(&ha->hw_lock, flags);
773 printk(KERN_ERR"%s out of bound pci memory access. "
774 "offset is 0x%llx\n", DRIVER_NAME, off);
775 return -1;
776 }
777
778 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
779 if (!addr) {
780 write_unlock_irqrestore(&ha->hw_lock, flags);
781 mem_base = pci_resource_start(ha->pdev, 0);
782 mem_page = start & PAGE_MASK;
783 /* Map two pages whenever user tries to access addresses in two
784 consecutive pages.
785 */
786 if (mem_page != ((start + size - 1) & PAGE_MASK))
787 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
788 else
789 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
790 if (mem_ptr == NULL)
791 return -1;
792
793 addr = mem_ptr;
794 addr += start & (PAGE_SIZE - 1);
795 write_lock_irqsave(&ha->hw_lock, flags);
796 }
797
798 switch (size) {
799 case 1:
800 writeb(*(u8 *)data, addr);
801 break;
802 case 2:
803 writew(*(u16 *)data, addr);
804 break;
805 case 4:
806 writel(*(u32 *)data, addr);
807 break;
808 case 8:
809 writeq(*(u64 *)data, addr);
810 break;
811 default:
812 ret = -1;
813 break;
814 }
815 write_unlock_irqrestore(&ha->hw_lock, flags);
816 if (mem_ptr)
817 iounmap(mem_ptr);
818 return ret;
819 }
820
821 #define MTU_FUDGE_FACTOR 100
822
823 static unsigned long
824 qla4_8xxx_decode_crb_addr(unsigned long addr)
825 {
826 int i;
827 unsigned long base_addr, offset, pci_base;
828
829 if (!qla4_8xxx_crb_table_initialized)
830 qla4_8xxx_crb_addr_transform_setup();
831
832 pci_base = ADDR_ERROR;
833 base_addr = addr & 0xfff00000;
834 offset = addr & 0x000fffff;
835
836 for (i = 0; i < MAX_CRB_XFORM; i++) {
837 if (crb_addr_xform[i] == base_addr) {
838 pci_base = i << 20;
839 break;
840 }
841 }
842 if (pci_base == ADDR_ERROR)
843 return pci_base;
844 else
845 return pci_base + offset;
846 }
847
848 static long rom_max_timeout = 100;
849 static long qla4_8xxx_rom_lock_timeout = 100;
850
851 static int
852 qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
853 {
854 int i;
855 int done = 0, timeout = 0;
856
857 while (!done) {
858 /* acquire semaphore2 from PCI HW block */
859
860 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
861 if (done == 1)
862 break;
863 if (timeout >= qla4_8xxx_rom_lock_timeout) {
864 ql4_printk(KERN_WARNING, ha,
865 "%s: Failed to acquire rom lock", __func__);
866 return -1;
867 }
868
869 timeout++;
870
871 /* Yield CPU */
872 if (!in_interrupt())
873 schedule();
874 else {
875 for (i = 0; i < 20; i++)
876 cpu_relax(); /*This a nop instr on i386*/
877 }
878 }
879 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
880 return 0;
881 }
882
883 static void
884 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
885 {
886 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
887 }
888
889 static int
890 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
891 {
892 long timeout = 0;
893 long done = 0 ;
894
895 while (done == 0) {
896 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
897 done &= 2;
898 timeout++;
899 if (timeout >= rom_max_timeout) {
900 printk("%s: Timeout reached waiting for rom done",
901 DRIVER_NAME);
902 return -1;
903 }
904 }
905 return 0;
906 }
907
908 static int
909 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
910 {
911 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
912 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
913 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
914 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
915 if (qla4_8xxx_wait_rom_done(ha)) {
916 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
917 return -1;
918 }
919 /* reset abyte_cnt and dummy_byte_cnt */
920 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
921 udelay(10);
922 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
923
924 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
925 return 0;
926 }
927
928 static int
929 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
930 {
931 int ret, loops = 0;
932
933 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
934 udelay(100);
935 loops++;
936 }
937 if (loops >= 50000) {
938 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
939 return -1;
940 }
941 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
942 qla4_8xxx_rom_unlock(ha);
943 return ret;
944 }
945
946 /**
947 * This routine does CRB initialize sequence
948 * to put the ISP into operational state
949 **/
950 static int
951 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
952 {
953 int addr, val;
954 int i ;
955 struct crb_addr_pair *buf;
956 unsigned long off;
957 unsigned offset, n;
958
959 struct crb_addr_pair {
960 long addr;
961 long data;
962 };
963
964 /* Halt all the indiviual PEGs and other blocks of the ISP */
965 qla4_8xxx_rom_lock(ha);
966
967 /* mask all niu interrupts */
968 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
969 /* disable xge rx/tx */
970 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
971 /* disable xg1 rx/tx */
972 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
973
974 /* halt sre */
975 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
976 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
977
978 /* halt epg */
979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
980
981 /* halt timers */
982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
983 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
984 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
985 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
986 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
987
988 /* halt pegs */
989 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
990 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
992 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
993 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
994
995 /* big hammer */
996 msleep(1000);
997 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
998 /* don't reset CAM block on reset */
999 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1000 else
1001 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1002
1003 /* reset ms */
1004 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1005 val |= (1 << 1);
1006 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1007
1008 msleep(20);
1009 /* unreset ms */
1010 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1011 val &= ~(1 << 1);
1012 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1013 msleep(20);
1014
1015 qla4_8xxx_rom_unlock(ha);
1016
1017 /* Read the signature value from the flash.
1018 * Offset 0: Contain signature (0xcafecafe)
1019 * Offset 4: Offset and number of addr/value pairs
1020 * that present in CRB initialize sequence
1021 */
1022 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1023 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
1024 ql4_printk(KERN_WARNING, ha,
1025 "[ERROR] Reading crb_init area: n: %08x\n", n);
1026 return -1;
1027 }
1028
1029 /* Offset in flash = lower 16 bits
1030 * Number of enteries = upper 16 bits
1031 */
1032 offset = n & 0xffffU;
1033 n = (n >> 16) & 0xffffU;
1034
1035 /* number of addr/value pair should not exceed 1024 enteries */
1036 if (n >= 1024) {
1037 ql4_printk(KERN_WARNING, ha,
1038 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1039 DRIVER_NAME, __func__, n);
1040 return -1;
1041 }
1042
1043 ql4_printk(KERN_INFO, ha,
1044 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1045
1046 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1047 if (buf == NULL) {
1048 ql4_printk(KERN_WARNING, ha,
1049 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1050 return -1;
1051 }
1052
1053 for (i = 0; i < n; i++) {
1054 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1055 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1056 0) {
1057 kfree(buf);
1058 return -1;
1059 }
1060
1061 buf[i].addr = addr;
1062 buf[i].data = val;
1063 }
1064
1065 for (i = 0; i < n; i++) {
1066 /* Translate internal CRB initialization
1067 * address to PCI bus address
1068 */
1069 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1070 QLA82XX_PCI_CRBSPACE;
1071 /* Not all CRB addr/value pair to be written,
1072 * some of them are skipped
1073 */
1074
1075 /* skip if LS bit is set*/
1076 if (off & 0x1) {
1077 DEBUG2(ql4_printk(KERN_WARNING, ha,
1078 "Skip CRB init replay for offset = 0x%lx\n", off));
1079 continue;
1080 }
1081
1082 /* skipping cold reboot MAGIC */
1083 if (off == QLA82XX_CAM_RAM(0x1fc))
1084 continue;
1085
1086 /* do not reset PCI */
1087 if (off == (ROMUSB_GLB + 0xbc))
1088 continue;
1089
1090 /* skip core clock, so that firmware can increase the clock */
1091 if (off == (ROMUSB_GLB + 0xc8))
1092 continue;
1093
1094 /* skip the function enable register */
1095 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1096 continue;
1097
1098 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1099 continue;
1100
1101 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1102 continue;
1103
1104 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1105 continue;
1106
1107 if (off == ADDR_ERROR) {
1108 ql4_printk(KERN_WARNING, ha,
1109 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1110 DRIVER_NAME, buf[i].addr);
1111 continue;
1112 }
1113
1114 qla4_8xxx_wr_32(ha, off, buf[i].data);
1115
1116 /* ISP requires much bigger delay to settle down,
1117 * else crb_window returns 0xffffffff
1118 */
1119 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1120 msleep(1000);
1121
1122 /* ISP requires millisec delay between
1123 * successive CRB register updation
1124 */
1125 msleep(1);
1126 }
1127
1128 kfree(buf);
1129
1130 /* Resetting the data and instruction cache */
1131 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1132 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1133 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1134
1135 /* Clear all protocol processing engines */
1136 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1137 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1138 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1139 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1140 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1141 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1142 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1143 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1144
1145 return 0;
1146 }
1147
1148 static int
1149 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1150 {
1151 int i, rval = 0;
1152 long size = 0;
1153 long flashaddr, memaddr;
1154 u64 data;
1155 u32 high, low;
1156
1157 flashaddr = memaddr = ha->hw.flt_region_bootload;
1158 size = (image_start - flashaddr) / 8;
1159
1160 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1161 ha->host_no, __func__, flashaddr, image_start));
1162
1163 for (i = 0; i < size; i++) {
1164 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1165 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1166 (int *)&high))) {
1167 rval = -1;
1168 goto exit_load_from_flash;
1169 }
1170 data = ((u64)high << 32) | low ;
1171 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1172 if (rval)
1173 goto exit_load_from_flash;
1174
1175 flashaddr += 8;
1176 memaddr += 8;
1177
1178 if (i % 0x1000 == 0)
1179 msleep(1);
1180
1181 }
1182
1183 udelay(100);
1184
1185 read_lock(&ha->hw_lock);
1186 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1187 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1188 read_unlock(&ha->hw_lock);
1189
1190 exit_load_from_flash:
1191 return rval;
1192 }
1193
1194 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1195 {
1196 u32 rst;
1197
1198 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1199 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1200 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1201 __func__);
1202 return QLA_ERROR;
1203 }
1204
1205 udelay(500);
1206
1207 /* at this point, QM is in reset. This could be a problem if there are
1208 * incoming d* transition queue messages. QM/PCIE could wedge.
1209 * To get around this, QM is brought out of reset.
1210 */
1211
1212 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1213 /* unreset qm */
1214 rst &= ~(1 << 28);
1215 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1216
1217 if (qla4_8xxx_load_from_flash(ha, image_start)) {
1218 printk("%s: Error trying to load fw from flash!\n", __func__);
1219 return QLA_ERROR;
1220 }
1221
1222 return QLA_SUCCESS;
1223 }
1224
1225 int
1226 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1227 u64 off, void *data, int size)
1228 {
1229 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1230 int shift_amount;
1231 uint32_t temp;
1232 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1233
1234 /*
1235 * If not MN, go check for MS or invalid.
1236 */
1237
1238 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1239 mem_crb = QLA82XX_CRB_QDR_NET;
1240 else {
1241 mem_crb = QLA82XX_CRB_DDR_NET;
1242 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1243 return qla4_8xxx_pci_mem_read_direct(ha,
1244 off, data, size);
1245 }
1246
1247
1248 off8 = off & 0xfffffff0;
1249 off0[0] = off & 0xf;
1250 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1251 shift_amount = 4;
1252
1253 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1254 off0[1] = 0;
1255 sz[1] = size - sz[0];
1256
1257 for (i = 0; i < loop; i++) {
1258 temp = off8 + (i << shift_amount);
1259 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1260 temp = 0;
1261 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1262 temp = MIU_TA_CTL_ENABLE;
1263 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1264 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1265 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1266
1267 for (j = 0; j < MAX_CTL_CHECK; j++) {
1268 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1269 if ((temp & MIU_TA_CTL_BUSY) == 0)
1270 break;
1271 }
1272
1273 if (j >= MAX_CTL_CHECK) {
1274 if (printk_ratelimit())
1275 ql4_printk(KERN_ERR, ha,
1276 "failed to read through agent\n");
1277 break;
1278 }
1279
1280 start = off0[i] >> 2;
1281 end = (off0[i] + sz[i] - 1) >> 2;
1282 for (k = start; k <= end; k++) {
1283 temp = qla4_8xxx_rd_32(ha,
1284 mem_crb + MIU_TEST_AGT_RDDATA(k));
1285 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1286 }
1287 }
1288
1289 if (j >= MAX_CTL_CHECK)
1290 return -1;
1291
1292 if ((off0[0] & 7) == 0) {
1293 val = word[0];
1294 } else {
1295 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1296 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1297 }
1298
1299 switch (size) {
1300 case 1:
1301 *(uint8_t *)data = val;
1302 break;
1303 case 2:
1304 *(uint16_t *)data = val;
1305 break;
1306 case 4:
1307 *(uint32_t *)data = val;
1308 break;
1309 case 8:
1310 *(uint64_t *)data = val;
1311 break;
1312 }
1313 return 0;
1314 }
1315
1316 int
1317 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1318 u64 off, void *data, int size)
1319 {
1320 int i, j, ret = 0, loop, sz[2], off0;
1321 int scale, shift_amount, startword;
1322 uint32_t temp;
1323 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1324
1325 /*
1326 * If not MN, go check for MS or invalid.
1327 */
1328 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1329 mem_crb = QLA82XX_CRB_QDR_NET;
1330 else {
1331 mem_crb = QLA82XX_CRB_DDR_NET;
1332 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1333 return qla4_8xxx_pci_mem_write_direct(ha,
1334 off, data, size);
1335 }
1336
1337 off0 = off & 0x7;
1338 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1339 sz[1] = size - sz[0];
1340
1341 off8 = off & 0xfffffff0;
1342 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1343 shift_amount = 4;
1344 scale = 2;
1345 startword = (off & 0xf)/8;
1346
1347 for (i = 0; i < loop; i++) {
1348 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1349 (i << shift_amount), &word[i * scale], 8))
1350 return -1;
1351 }
1352
1353 switch (size) {
1354 case 1:
1355 tmpw = *((uint8_t *)data);
1356 break;
1357 case 2:
1358 tmpw = *((uint16_t *)data);
1359 break;
1360 case 4:
1361 tmpw = *((uint32_t *)data);
1362 break;
1363 case 8:
1364 default:
1365 tmpw = *((uint64_t *)data);
1366 break;
1367 }
1368
1369 if (sz[0] == 8)
1370 word[startword] = tmpw;
1371 else {
1372 word[startword] &=
1373 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1374 word[startword] |= tmpw << (off0 * 8);
1375 }
1376
1377 if (sz[1] != 0) {
1378 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1379 word[startword+1] |= tmpw >> (sz[0] * 8);
1380 }
1381
1382 for (i = 0; i < loop; i++) {
1383 temp = off8 + (i << shift_amount);
1384 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1385 temp = 0;
1386 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1387 temp = word[i * scale] & 0xffffffff;
1388 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1389 temp = (word[i * scale] >> 32) & 0xffffffff;
1390 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1391 temp = word[i*scale + 1] & 0xffffffff;
1392 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1393 temp);
1394 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1395 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1396 temp);
1397
1398 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1399 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1400 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1401 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1402
1403 for (j = 0; j < MAX_CTL_CHECK; j++) {
1404 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1405 if ((temp & MIU_TA_CTL_BUSY) == 0)
1406 break;
1407 }
1408
1409 if (j >= MAX_CTL_CHECK) {
1410 if (printk_ratelimit())
1411 ql4_printk(KERN_ERR, ha,
1412 "failed to write through agent\n");
1413 ret = -1;
1414 break;
1415 }
1416 }
1417
1418 return ret;
1419 }
1420
1421 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1422 {
1423 u32 val = 0;
1424 int retries = 60;
1425
1426 if (!pegtune_val) {
1427 do {
1428 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1429 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1430 (val == PHAN_INITIALIZE_ACK))
1431 return 0;
1432 set_current_state(TASK_UNINTERRUPTIBLE);
1433 schedule_timeout(500);
1434
1435 } while (--retries);
1436
1437 if (!retries) {
1438 pegtune_val = qla4_8xxx_rd_32(ha,
1439 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1440 printk(KERN_WARNING "%s: init failed, "
1441 "pegtune_val = %x\n", __func__, pegtune_val);
1442 return -1;
1443 }
1444 }
1445 return 0;
1446 }
1447
1448 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1449 {
1450 uint32_t state = 0;
1451 int loops = 0;
1452
1453 /* Window 1 call */
1454 read_lock(&ha->hw_lock);
1455 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1456 read_unlock(&ha->hw_lock);
1457
1458 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1459 udelay(100);
1460 /* Window 1 call */
1461 read_lock(&ha->hw_lock);
1462 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1463 read_unlock(&ha->hw_lock);
1464
1465 loops++;
1466 }
1467
1468 if (loops >= 30000) {
1469 DEBUG2(ql4_printk(KERN_INFO, ha,
1470 "Receive Peg initialization not complete: 0x%x.\n", state));
1471 return QLA_ERROR;
1472 }
1473
1474 return QLA_SUCCESS;
1475 }
1476
1477 void
1478 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1479 {
1480 uint32_t drv_active;
1481
1482 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1483 drv_active |= (1 << (ha->func_num * 4));
1484 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1485 }
1486
1487 void
1488 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1489 {
1490 uint32_t drv_active;
1491
1492 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1493 drv_active &= ~(1 << (ha->func_num * 4));
1494 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1495 }
1496
1497 static inline int
1498 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1499 {
1500 uint32_t drv_state, drv_active;
1501 int rval;
1502
1503 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1504 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1505 rval = drv_state & (1 << (ha->func_num * 4));
1506 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1507 rval = 1;
1508
1509 return rval;
1510 }
1511
1512 static inline void
1513 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1514 {
1515 uint32_t drv_state;
1516
1517 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1518 drv_state |= (1 << (ha->func_num * 4));
1519 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1520 }
1521
1522 static inline void
1523 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1524 {
1525 uint32_t drv_state;
1526
1527 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1528 drv_state &= ~(1 << (ha->func_num * 4));
1529 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1530 }
1531
1532 static inline void
1533 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1534 {
1535 uint32_t qsnt_state;
1536
1537 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1538 qsnt_state |= (2 << (ha->func_num * 4));
1539 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1540 }
1541
1542
1543 static int
1544 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1545 {
1546 int pcie_cap;
1547 uint16_t lnk;
1548
1549 /* scrub dma mask expansion register */
1550 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1551
1552 /* Overwrite stale initialization register values */
1553 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1554 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1555 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1556 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1557
1558 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1559 printk("%s: Error trying to start fw!\n", __func__);
1560 return QLA_ERROR;
1561 }
1562
1563 /* Handshake with the card before we register the devices. */
1564 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1565 printk("%s: Error during card handshake!\n", __func__);
1566 return QLA_ERROR;
1567 }
1568
1569 /* Negotiated Link width */
1570 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1571 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1572 ha->link_width = (lnk >> 4) & 0x3f;
1573
1574 /* Synchronize with Receive peg */
1575 return qla4_8xxx_rcvpeg_ready(ha);
1576 }
1577
1578 static int
1579 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1580 {
1581 int rval = QLA_ERROR;
1582
1583 /*
1584 * FW Load priority:
1585 * 1) Operational firmware residing in flash.
1586 * 2) Fail
1587 */
1588
1589 ql4_printk(KERN_INFO, ha,
1590 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1591 rval = qla4_8xxx_get_flash_info(ha);
1592 if (rval != QLA_SUCCESS)
1593 return rval;
1594
1595 ql4_printk(KERN_INFO, ha,
1596 "FW: Attempting to load firmware from flash...\n");
1597 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1598
1599 if (rval != QLA_SUCCESS) {
1600 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1601 " FAILED...\n");
1602 return rval;
1603 }
1604
1605 return rval;
1606 }
1607
1608 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1609 {
1610 if (qla4_8xxx_rom_lock(ha)) {
1611 /* Someone else is holding the lock. */
1612 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1613 }
1614
1615 /*
1616 * Either we got the lock, or someone
1617 * else died while holding it.
1618 * In either case, unlock.
1619 */
1620 qla4_8xxx_rom_unlock(ha);
1621 }
1622
1623 /**
1624 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1625 * @ha: pointer to adapter structure
1626 *
1627 * Note: IDC lock must be held upon entry
1628 **/
1629 static int
1630 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
1631 {
1632 int rval = QLA_ERROR;
1633 int i, timeout;
1634 uint32_t old_count, count;
1635 int need_reset = 0, peg_stuck = 1;
1636
1637 need_reset = qla4_8xxx_need_reset(ha);
1638
1639 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1640
1641 for (i = 0; i < 10; i++) {
1642 timeout = msleep_interruptible(200);
1643 if (timeout) {
1644 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1645 QLA82XX_DEV_FAILED);
1646 return rval;
1647 }
1648
1649 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1650 if (count != old_count)
1651 peg_stuck = 0;
1652 }
1653
1654 if (need_reset) {
1655 /* We are trying to perform a recovery here. */
1656 if (peg_stuck)
1657 qla4_8xxx_rom_lock_recovery(ha);
1658 goto dev_initialize;
1659 } else {
1660 /* Start of day for this ha context. */
1661 if (peg_stuck) {
1662 /* Either we are the first or recovery in progress. */
1663 qla4_8xxx_rom_lock_recovery(ha);
1664 goto dev_initialize;
1665 } else {
1666 /* Firmware already running. */
1667 rval = QLA_SUCCESS;
1668 goto dev_ready;
1669 }
1670 }
1671
1672 dev_initialize:
1673 /* set to DEV_INITIALIZING */
1674 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
1675 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
1676
1677 /* Driver that sets device state to initializating sets IDC version */
1678 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
1679
1680 qla4_8xxx_idc_unlock(ha);
1681 rval = qla4_8xxx_try_start_fw(ha);
1682 qla4_8xxx_idc_lock(ha);
1683
1684 if (rval != QLA_SUCCESS) {
1685 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
1686 qla4_8xxx_clear_drv_active(ha);
1687 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
1688 return rval;
1689 }
1690
1691 dev_ready:
1692 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
1693 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
1694
1695 return rval;
1696 }
1697
1698 /**
1699 * qla4_8xxx_need_reset_handler - Code to start reset sequence
1700 * @ha: pointer to adapter structure
1701 *
1702 * Note: IDC lock must be held upon entry
1703 **/
1704 static void
1705 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
1706 {
1707 uint32_t dev_state, drv_state, drv_active;
1708 unsigned long reset_timeout;
1709
1710 ql4_printk(KERN_INFO, ha,
1711 "Performing ISP error recovery\n");
1712
1713 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
1714 qla4_8xxx_idc_unlock(ha);
1715 ha->isp_ops->disable_intrs(ha);
1716 qla4_8xxx_idc_lock(ha);
1717 }
1718
1719 qla4_8xxx_set_rst_ready(ha);
1720
1721 /* wait for 10 seconds for reset ack from all functions */
1722 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
1723
1724 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1725 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1726
1727 ql4_printk(KERN_INFO, ha,
1728 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1729 __func__, ha->host_no, drv_state, drv_active);
1730
1731 while (drv_state != drv_active) {
1732 if (time_after_eq(jiffies, reset_timeout)) {
1733 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME);
1734 break;
1735 }
1736
1737 qla4_8xxx_idc_unlock(ha);
1738 msleep(1000);
1739 qla4_8xxx_idc_lock(ha);
1740
1741 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1742 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1743 }
1744
1745 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1746 ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
1747 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1748
1749 /* Force to DEV_COLD unless someone else is starting a reset */
1750 if (dev_state != QLA82XX_DEV_INITIALIZING) {
1751 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
1752 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
1753 }
1754 }
1755
1756 /**
1757 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1758 * @ha: pointer to adapter structure
1759 **/
1760 void
1761 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
1762 {
1763 qla4_8xxx_idc_lock(ha);
1764 qla4_8xxx_set_qsnt_ready(ha);
1765 qla4_8xxx_idc_unlock(ha);
1766 }
1767
1768 /**
1769 * qla4_8xxx_device_state_handler - Adapter state machine
1770 * @ha: pointer to host adapter structure.
1771 *
1772 * Note: IDC lock must be UNLOCKED upon entry
1773 **/
1774 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
1775 {
1776 uint32_t dev_state;
1777 int rval = QLA_SUCCESS;
1778 unsigned long dev_init_timeout;
1779
1780 if (!test_bit(AF_INIT_DONE, &ha->flags))
1781 qla4_8xxx_set_drv_active(ha);
1782
1783 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1784 ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
1785 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1786
1787 /* wait for 30 seconds for device to go ready */
1788 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
1789
1790 while (1) {
1791 qla4_8xxx_idc_lock(ha);
1792
1793 if (time_after_eq(jiffies, dev_init_timeout)) {
1794 ql4_printk(KERN_WARNING, ha, "Device init failed!\n");
1795 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1796 QLA82XX_DEV_FAILED);
1797 }
1798
1799 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1800 ql4_printk(KERN_INFO, ha,
1801 "2:Device state is 0x%x = %s\n", dev_state,
1802 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1803
1804 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1805 switch (dev_state) {
1806 case QLA82XX_DEV_READY:
1807 qla4_8xxx_idc_unlock(ha);
1808 goto exit;
1809 case QLA82XX_DEV_COLD:
1810 rval = qla4_8xxx_device_bootstrap(ha);
1811 qla4_8xxx_idc_unlock(ha);
1812 goto exit;
1813 case QLA82XX_DEV_INITIALIZING:
1814 qla4_8xxx_idc_unlock(ha);
1815 msleep(1000);
1816 break;
1817 case QLA82XX_DEV_NEED_RESET:
1818 if (!ql4xdontresethba) {
1819 qla4_8xxx_need_reset_handler(ha);
1820 /* Update timeout value after need
1821 * reset handler */
1822 dev_init_timeout = jiffies +
1823 (ha->nx_dev_init_timeout * HZ);
1824 }
1825 qla4_8xxx_idc_unlock(ha);
1826 break;
1827 case QLA82XX_DEV_NEED_QUIESCENT:
1828 qla4_8xxx_idc_unlock(ha);
1829 /* idc locked/unlocked in handler */
1830 qla4_8xxx_need_qsnt_handler(ha);
1831 qla4_8xxx_idc_lock(ha);
1832 /* fall thru needs idc_locked */
1833 case QLA82XX_DEV_QUIESCENT:
1834 qla4_8xxx_idc_unlock(ha);
1835 msleep(1000);
1836 break;
1837 case QLA82XX_DEV_FAILED:
1838 qla4_8xxx_idc_unlock(ha);
1839 qla4xxx_dead_adapter_cleanup(ha);
1840 rval = QLA_ERROR;
1841 goto exit;
1842 default:
1843 qla4_8xxx_idc_unlock(ha);
1844 qla4xxx_dead_adapter_cleanup(ha);
1845 rval = QLA_ERROR;
1846 goto exit;
1847 }
1848 }
1849 exit:
1850 return rval;
1851 }
1852
1853 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
1854 {
1855 int retval;
1856 retval = qla4_8xxx_device_state_handler(ha);
1857
1858 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
1859 retval = qla4xxx_request_irqs(ha);
1860
1861 return retval;
1862 }
1863
1864 /*****************************************************************************/
1865 /* Flash Manipulation Routines */
1866 /*****************************************************************************/
1867
1868 #define OPTROM_BURST_SIZE 0x1000
1869 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
1870
1871 #define FARX_DATA_FLAG BIT_31
1872 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1873 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1874
1875 static inline uint32_t
1876 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1877 {
1878 return hw->flash_conf_off | faddr;
1879 }
1880
1881 static inline uint32_t
1882 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1883 {
1884 return hw->flash_data_off | faddr;
1885 }
1886
1887 static uint32_t *
1888 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
1889 uint32_t faddr, uint32_t length)
1890 {
1891 uint32_t i;
1892 uint32_t val;
1893 int loops = 0;
1894 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
1895 udelay(100);
1896 cond_resched();
1897 loops++;
1898 }
1899 if (loops >= 50000) {
1900 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
1901 return dwptr;
1902 }
1903
1904 /* Dword reads to flash. */
1905 for (i = 0; i < length/4; i++, faddr += 4) {
1906 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
1907 ql4_printk(KERN_WARNING, ha,
1908 "Do ROM fast read failed\n");
1909 goto done_read;
1910 }
1911 dwptr[i] = __constant_cpu_to_le32(val);
1912 }
1913
1914 done_read:
1915 qla4_8xxx_rom_unlock(ha);
1916 return dwptr;
1917 }
1918
1919 /**
1920 * Address and length are byte address
1921 **/
1922 static uint8_t *
1923 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1924 uint32_t offset, uint32_t length)
1925 {
1926 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
1927 return buf;
1928 }
1929
1930 static int
1931 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
1932 {
1933 const char *loc, *locations[] = { "DEF", "PCI" };
1934
1935 /*
1936 * FLT-location structure resides after the last PCI region.
1937 */
1938
1939 /* Begin with sane defaults. */
1940 loc = locations[0];
1941 *start = FA_FLASH_LAYOUT_ADDR_82;
1942
1943 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
1944 return QLA_SUCCESS;
1945 }
1946
1947 static void
1948 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
1949 {
1950 const char *loc, *locations[] = { "DEF", "FLT" };
1951 uint16_t *wptr;
1952 uint16_t cnt, chksum;
1953 uint32_t start;
1954 struct qla_flt_header *flt;
1955 struct qla_flt_region *region;
1956 struct ql82xx_hw_data *hw = &ha->hw;
1957
1958 hw->flt_region_flt = flt_addr;
1959 wptr = (uint16_t *)ha->request_ring;
1960 flt = (struct qla_flt_header *)ha->request_ring;
1961 region = (struct qla_flt_region *)&flt[1];
1962 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1963 flt_addr << 2, OPTROM_BURST_SIZE);
1964 if (*wptr == __constant_cpu_to_le16(0xffff))
1965 goto no_flash_data;
1966 if (flt->version != __constant_cpu_to_le16(1)) {
1967 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
1968 "version=0x%x length=0x%x checksum=0x%x.\n",
1969 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1970 le16_to_cpu(flt->checksum)));
1971 goto no_flash_data;
1972 }
1973
1974 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
1975 for (chksum = 0; cnt; cnt--)
1976 chksum += le16_to_cpu(*wptr++);
1977 if (chksum) {
1978 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
1979 "version=0x%x length=0x%x checksum=0x%x.\n",
1980 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1981 chksum));
1982 goto no_flash_data;
1983 }
1984
1985 loc = locations[1];
1986 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
1987 for ( ; cnt; cnt--, region++) {
1988 /* Store addresses as DWORD offsets. */
1989 start = le32_to_cpu(region->start) >> 2;
1990
1991 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
1992 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
1993 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
1994
1995 switch (le32_to_cpu(region->code) & 0xff) {
1996 case FLT_REG_FDT:
1997 hw->flt_region_fdt = start;
1998 break;
1999 case FLT_REG_BOOT_CODE_82:
2000 hw->flt_region_boot = start;
2001 break;
2002 case FLT_REG_FW_82:
2003 hw->flt_region_fw = start;
2004 break;
2005 case FLT_REG_BOOTLOAD_82:
2006 hw->flt_region_bootload = start;
2007 break;
2008 }
2009 }
2010 goto done;
2011
2012 no_flash_data:
2013 /* Use hardcoded defaults. */
2014 loc = locations[0];
2015
2016 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82;
2017 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82;
2018 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2019 hw->flt_region_fw = FA_RISC_CODE_ADDR_82;
2020 done:
2021 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2022 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2023 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2024 hw->flt_region_fw));
2025 }
2026
2027 static void
2028 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2029 {
2030 #define FLASH_BLK_SIZE_4K 0x1000
2031 #define FLASH_BLK_SIZE_32K 0x8000
2032 #define FLASH_BLK_SIZE_64K 0x10000
2033 const char *loc, *locations[] = { "MID", "FDT" };
2034 uint16_t cnt, chksum;
2035 uint16_t *wptr;
2036 struct qla_fdt_layout *fdt;
2037 uint16_t mid = 0;
2038 uint16_t fid = 0;
2039 struct ql82xx_hw_data *hw = &ha->hw;
2040
2041 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2042 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2043
2044 wptr = (uint16_t *)ha->request_ring;
2045 fdt = (struct qla_fdt_layout *)ha->request_ring;
2046 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2047 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2048
2049 if (*wptr == __constant_cpu_to_le16(0xffff))
2050 goto no_flash_data;
2051
2052 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2053 fdt->sig[3] != 'D')
2054 goto no_flash_data;
2055
2056 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2057 cnt++)
2058 chksum += le16_to_cpu(*wptr++);
2059
2060 if (chksum) {
2061 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2062 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2063 le16_to_cpu(fdt->version)));
2064 goto no_flash_data;
2065 }
2066
2067 loc = locations[1];
2068 mid = le16_to_cpu(fdt->man_id);
2069 fid = le16_to_cpu(fdt->id);
2070 hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2071 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2072 hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2073
2074 if (fdt->unprotect_sec_cmd) {
2075 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2076 fdt->unprotect_sec_cmd);
2077 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2078 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2079 flash_conf_addr(hw, 0x0336);
2080 }
2081 goto done;
2082
2083 no_flash_data:
2084 loc = locations[0];
2085 hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2086 done:
2087 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2088 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2089 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2090 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2091 hw->fdt_block_size));
2092 }
2093
2094 static void
2095 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2096 {
2097 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2098 uint32_t *wptr;
2099
2100 if (!is_qla8022(ha))
2101 return;
2102 wptr = (uint32_t *)ha->request_ring;
2103 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2104 QLA82XX_IDC_PARAM_ADDR , 8);
2105
2106 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2107 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2108 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2109 } else {
2110 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2111 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2112 }
2113
2114 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2115 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2116 DEBUG2(ql4_printk(KERN_DEBUG, ha,
2117 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2118 return;
2119 }
2120
2121 int
2122 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2123 {
2124 int ret;
2125 uint32_t flt_addr;
2126
2127 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2128 if (ret != QLA_SUCCESS)
2129 return ret;
2130
2131 qla4_8xxx_get_flt_info(ha, flt_addr);
2132 qla4_8xxx_get_fdt_info(ha);
2133 qla4_8xxx_get_idc_param(ha);
2134
2135 return QLA_SUCCESS;
2136 }
2137
2138 /**
2139 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2140 * @ha: pointer to host adapter structure.
2141 *
2142 * Remarks:
2143 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2144 * not be available after successful return. Driver must cleanup potential
2145 * outstanding I/O's after calling this funcion.
2146 **/
2147 int
2148 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2149 {
2150 int status;
2151 uint32_t mbox_cmd[MBOX_REG_COUNT];
2152 uint32_t mbox_sts[MBOX_REG_COUNT];
2153
2154 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2155 memset(&mbox_sts, 0, sizeof(mbox_sts));
2156
2157 mbox_cmd[0] = MBOX_CMD_STOP_FW;
2158 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2159 &mbox_cmd[0], &mbox_sts[0]);
2160
2161 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2162 __func__, status));
2163 return status;
2164 }
2165
2166 /**
2167 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2168 * @ha: pointer to host adapter structure.
2169 **/
2170 int
2171 qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2172 {
2173 int rval;
2174 uint32_t dev_state;
2175
2176 qla4_8xxx_idc_lock(ha);
2177 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2178
2179 if (dev_state == QLA82XX_DEV_READY) {
2180 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2181 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2182 QLA82XX_DEV_NEED_RESET);
2183 } else
2184 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2185
2186 qla4_8xxx_idc_unlock(ha);
2187
2188 rval = qla4_8xxx_device_state_handler(ha);
2189
2190 qla4_8xxx_idc_lock(ha);
2191 qla4_8xxx_clear_rst_ready(ha);
2192 qla4_8xxx_idc_unlock(ha);
2193
2194 if (rval == QLA_SUCCESS)
2195 clear_bit(AF_FW_RECOVERY, &ha->flags);
2196
2197 return rval;
2198 }
2199
2200 /**
2201 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2202 * @ha: pointer to host adapter structure.
2203 *
2204 **/
2205 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2206 {
2207 uint32_t mbox_cmd[MBOX_REG_COUNT];
2208 uint32_t mbox_sts[MBOX_REG_COUNT];
2209 struct mbx_sys_info *sys_info;
2210 dma_addr_t sys_info_dma;
2211 int status = QLA_ERROR;
2212
2213 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2214 &sys_info_dma, GFP_KERNEL);
2215 if (sys_info == NULL) {
2216 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2217 ha->host_no, __func__));
2218 return status;
2219 }
2220
2221 memset(sys_info, 0, sizeof(*sys_info));
2222 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2223 memset(&mbox_sts, 0, sizeof(mbox_sts));
2224
2225 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2226 mbox_cmd[1] = LSDW(sys_info_dma);
2227 mbox_cmd[2] = MSDW(sys_info_dma);
2228 mbox_cmd[4] = sizeof(*sys_info);
2229
2230 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2231 &mbox_sts[0]) != QLA_SUCCESS) {
2232 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2233 ha->host_no, __func__));
2234 goto exit_validate_mac82;
2235 }
2236
2237 /* Make sure we receive the minimum required data to cache internally */
2238 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
2239 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2240 " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2241 goto exit_validate_mac82;
2242
2243 }
2244
2245 /* Save M.A.C. address & serial_number */
2246 memcpy(ha->my_mac, &sys_info->mac_addr[0],
2247 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2248 memcpy(ha->serial_number, &sys_info->serial_number,
2249 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2250
2251 DEBUG2(printk("scsi%ld: %s: "
2252 "mac %02x:%02x:%02x:%02x:%02x:%02x "
2253 "serial %s\n", ha->host_no, __func__,
2254 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2255 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2256 ha->serial_number));
2257
2258 status = QLA_SUCCESS;
2259
2260 exit_validate_mac82:
2261 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2262 sys_info_dma);
2263 return status;
2264 }
2265
2266 /* Interrupt handling helpers. */
2267
2268 static int
2269 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2270 {
2271 uint32_t mbox_cmd[MBOX_REG_COUNT];
2272 uint32_t mbox_sts[MBOX_REG_COUNT];
2273
2274 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2275
2276 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2277 memset(&mbox_sts, 0, sizeof(mbox_sts));
2278 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2279 mbox_cmd[1] = INTR_ENABLE;
2280 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2281 &mbox_sts[0]) != QLA_SUCCESS) {
2282 DEBUG2(ql4_printk(KERN_INFO, ha,
2283 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2284 __func__, mbox_sts[0]));
2285 return QLA_ERROR;
2286 }
2287 return QLA_SUCCESS;
2288 }
2289
2290 static int
2291 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
2292 {
2293 uint32_t mbox_cmd[MBOX_REG_COUNT];
2294 uint32_t mbox_sts[MBOX_REG_COUNT];
2295
2296 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2297
2298 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2299 memset(&mbox_sts, 0, sizeof(mbox_sts));
2300 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2301 mbox_cmd[1] = INTR_DISABLE;
2302 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2303 &mbox_sts[0]) != QLA_SUCCESS) {
2304 DEBUG2(ql4_printk(KERN_INFO, ha,
2305 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2306 __func__, mbox_sts[0]));
2307 return QLA_ERROR;
2308 }
2309
2310 return QLA_SUCCESS;
2311 }
2312
2313 void
2314 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
2315 {
2316 qla4_8xxx_mbx_intr_enable(ha);
2317
2318 spin_lock_irq(&ha->hardware_lock);
2319 /* BIT 10 - reset */
2320 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2321 spin_unlock_irq(&ha->hardware_lock);
2322 set_bit(AF_INTERRUPTS_ON, &ha->flags);
2323 }
2324
2325 void
2326 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
2327 {
2328 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
2329 qla4_8xxx_mbx_intr_disable(ha);
2330
2331 spin_lock_irq(&ha->hardware_lock);
2332 /* BIT 10 - set */
2333 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2334 spin_unlock_irq(&ha->hardware_lock);
2335 }
2336
2337 struct ql4_init_msix_entry {
2338 uint16_t entry;
2339 uint16_t index;
2340 const char *name;
2341 irq_handler_t handler;
2342 };
2343
2344 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
2345 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
2346 "qla4xxx (default)",
2347 (irq_handler_t)qla4_8xxx_default_intr_handler },
2348 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
2349 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
2350 };
2351
2352 void
2353 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
2354 {
2355 int i;
2356 struct ql4_msix_entry *qentry;
2357
2358 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2359 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2360 if (qentry->have_irq) {
2361 free_irq(qentry->msix_vector, ha);
2362 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2363 __func__, qla4_8xxx_msix_entries[i].name));
2364 }
2365 }
2366 pci_disable_msix(ha->pdev);
2367 clear_bit(AF_MSIX_ENABLED, &ha->flags);
2368 }
2369
2370 int
2371 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
2372 {
2373 int i, ret;
2374 struct msix_entry entries[QLA_MSIX_ENTRIES];
2375 struct ql4_msix_entry *qentry;
2376
2377 for (i = 0; i < QLA_MSIX_ENTRIES; i++)
2378 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
2379
2380 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
2381 if (ret) {
2382 ql4_printk(KERN_WARNING, ha,
2383 "MSI-X: Failed to enable support -- %d/%d\n",
2384 QLA_MSIX_ENTRIES, ret);
2385 goto msix_out;
2386 }
2387 set_bit(AF_MSIX_ENABLED, &ha->flags);
2388
2389 for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2390 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2391 qentry->msix_vector = entries[i].vector;
2392 qentry->msix_entry = entries[i].entry;
2393 qentry->have_irq = 0;
2394 ret = request_irq(qentry->msix_vector,
2395 qla4_8xxx_msix_entries[i].handler, 0,
2396 qla4_8xxx_msix_entries[i].name, ha);
2397 if (ret) {
2398 ql4_printk(KERN_WARNING, ha,
2399 "MSI-X: Unable to register handler -- %x/%d.\n",
2400 qla4_8xxx_msix_entries[i].index, ret);
2401 qla4_8xxx_disable_msix(ha);
2402 goto msix_out;
2403 }
2404 qentry->have_irq = 1;
2405 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2406 __func__, qla4_8xxx_msix_entries[i].name));
2407 }
2408 msix_out:
2409 return ret;
2410 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree