drivers/staging/msm/mdp4.h

   1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #ifndef MDP4_H
  14 #define MDP4_H
  15
  16 extern struct mdp_dma_data dma2_data;
  17 extern struct mdp_dma_data dma_s_data;
  18 extern struct mdp_dma_data dma_e_data;
  19 extern struct mdp_histogram mdp_hist;
  20 extern struct completion mdp_hist_comp;
  21 extern boolean mdp_is_in_isr;
  22 extern uint32 mdp_intr_mask;
  23 extern spinlock_t mdp_spin_lock;
  24
  25
  26 #define MDP4_NONBLOCKING        /* enable non blocking ioctl */
  27
  28 #define MDP4_OVERLAYPROC0_BASE  0x10000
  29 #define MDP4_OVERLAYPROC1_BASE  0x18000
  30
  31 #define MDP4_VIDEO_BASE 0x20000
  32 #define MDP4_VIDEO_OFF 0x10000
  33
  34 #define MDP4_RGB_BASE 0x40000
  35 #define MDP4_RGB_OFF 0x10000
  36
  37 enum {          /* display */
  38         PRIMARY_INTF_SEL,
  39         SECONDARY_INTF_SEL,
  40         EXTERNAL_INTF_SEL
  41 };
  42
  43 enum {
  44         LCDC_RGB_INTF,
  45         DTV_INTF = LCDC_RGB_INTF,
  46         MDDI_LCDC_INTF,
  47         MDDI_INTF,
  48         EBI2_INTF
  49 };
  50
  51 enum {
  52         MDDI_PRIMARY_SET,
  53         MDDI_SECONDARY_SET,
  54         MDDI_EXTERNAL_SET
  55 };
  56
  57 enum {
  58         EBI2_LCD0,
  59         EBI2_LCD1
  60 };
  61
  62 enum {
  63         OVERLAY_MODE_NONE,
  64         OVERLAY_MODE_BLT
  65 };
  66
  67 enum {
  68         OVERLAY_REFRESH_ON_DEMAND,
  69         OVERLAY_REFRESH_VSYNC,
  70         OVERLAY_REFRESH_VSYNC_HALF,
  71         OVERLAY_REFRESH_VSYNC_QUARTER
  72 };
  73
  74 enum {
  75         OVERLAY_FRAMEBUF,
  76         OVERLAY_DIRECTOUT
  77 };
  78
  79 /* system interrupts */
  80 #define INTR_OVERLAY0_DONE              BIT(0)
  81 #define INTR_OVERLAY1_DONE              BIT(1)
  82 #define INTR_DMA_S_DONE                 BIT(2)
  83 #define INTR_DMA_E_DONE                 BIT(3)
  84 #define INTR_DMA_P_DONE                 BIT(4)
  85 #define INTR_VG1_HISTOGRAM              BIT(5)
  86 #define INTR_VG2_HISTOGRAM              BIT(6)
  87 #define INTR_PRIMARY_VSYNC              BIT(7)
  88 #define INTR_PRIMARY_INTF_UDERRUN       BIT(8)
  89 #define INTR_EXTERNAL_VSYNC             BIT(9)
  90 #define INTR_EXTERNAL_INTF_UDERRUN      BIT(10)
  91 #define INTR_DMA_P_HISTOGRAM            BIT(17)
  92
  93 /* histogram interrupts */
  94 #define INTR_HIST_DONE                  BIT(0)
  95 #define INTR_HIST_RESET_SEQ_DONE        BIT(1)
  96
  97
  98 #ifdef CONFIG_FB_MSM_OVERLAY
  99 #define MDP4_ANY_INTR_MASK      (INTR_OVERLAY0_DONE)
 100 #else
 101 #define MDP4_ANY_INTR_MASK      (INTR_DMA_P_DONE)
 102 #endif
 103
 104 enum {
 105         OVERLAY_PIPE_RGB1,
 106         OVERLAY_PIPE_RGB2,
 107 };
 108
 109 enum {
 110         OVERLAY_PIPE_VG1,       /* video/graphic */
 111         OVERLAY_PIPE_VG2
 112 };
 113
 114 enum {
 115         OVERLAY_TYPE_RGB,
 116         OVERLAY_TYPE_VG         /* video/graphic */
 117 };
 118
 119 enum {
 120         MDP4_MIXER0,
 121         MDP4_MIXER1
 122 };
 123
 124 #define MDP4_MAX_MIXER  2
 125
 126 enum {
 127         OVERLAY_PLANE_INTERLEAVED,
 128         OVERLAY_PLANE_PLANAR,
 129         OVERLAY_PLANE_PSEUDO_PLANAR
 130 };
 131
 132 enum {
 133         MDP4_MIXER_STAGE_UNUNSED,       /* pipe not used */
 134         MDP4_MIXER_STAGE_BASE,
 135         MDP4_MIXER_STAGE0,      /* zorder 0 */
 136         MDP4_MIXER_STAGE1,      /* zorder 1 */
 137         MDP4_MIXER_STAGE2       /* zorder 2 */
 138 };
 139
 140 #define MDP4_MAX_STAGE  4
 141
 142 enum {
 143         MDP4_FRAME_FORMAT_LINEAR,
 144         MDP4_FRAME_FORMAT_ARGB_TILE,
 145         MDP4_FRAME_FORMAT_VIDEO_SUPERTILE
 146 };
 147
 148 enum {
 149         MDP4_CHROMA_RGB,
 150         MDP4_CHROMA_H2V1,
 151         MDP4_CHROMA_H1V2,
 152         MDP4_CHROMA_420
 153 };
 154
 155 #define MDP4_BLEND_BG_TRANSP_EN         BIT(9)
 156 #define MDP4_BLEND_FG_TRANSP_EN         BIT(8)
 157 #define MDP4_BLEND_BG_MOD_ALPHA         BIT(7)
 158 #define MDP4_BLEND_BG_INV_ALPHA         BIT(6)
 159 #define MDP4_BLEND_BG_ALPHA_FG_CONST    (0 << 4)
 160 #define MDP4_BLEND_BG_ALPHA_BG_CONST    (1 << 4)
 161 #define MDP4_BLEND_BG_ALPHA_FG_PIXEL    (2 << 4)
 162 #define MDP4_BLEND_BG_ALPHA_BG_PIXEL    (3 << 4)
 163 #define MDP4_BLEND_FG_MOD_ALPHA         BIT(3)
 164 #define MDP4_BLEND_FG_INV_ALPHA         BIT(2)
 165 #define MDP4_BLEND_FG_ALPHA_FG_CONST    (0 << 0)
 166 #define MDP4_BLEND_FG_ALPHA_BG_CONST    (1 << 0)
 167 #define MDP4_BLEND_FG_ALPHA_FG_PIXEL    (2 << 0)
 168 #define MDP4_BLEND_FG_ALPHA_BG_PIXEL    (3 << 0)
 169
 170 #define MDP4_FORMAT_SOLID_FILL          BIT(22)
 171 #define MDP4_FORMAT_UNPACK_ALIGN_MSB    BIT(18)
 172 #define MDP4_FORMAT_UNPACK_TIGHT        BIT(17)
 173 #define MDP4_FORMAT_90_ROTATED          BIT(12)
 174 #define MDP4_FORMAT_ALPHA_ENABLE        BIT(8)
 175
 176 #define MDP4_OP_DEINT_ODD_REF   BIT(19)
 177 #define MDP4_OP_IGC_LUT_EN      BIT(16)
 178 #define MDP4_OP_DITHER_EN       BIT(15)
 179 #define MDP4_OP_FLIP_UD         BIT(14)
 180 #define MDP4_OP_FLIP_LR         BIT(13)
 181 #define MDP4_OP_CSC_EN          BIT(11)
 182 #define MDP4_OP_SRC_DATA_YCBCR  BIT(9)
 183 #define MDP4_OP_SCALEY_FIR              (0 << 4)
 184 #define MDP4_OP_SCALEY_MN_PHASE         (1 << 4)
 185 #define MDP4_OP_SCALEY_PIXEL_RPT        (2 << 4)
 186 #define MDP4_OP_SCALEX_FIR              (0 << 2)
 187 #define MDP4_OP_SCALEX_MN_PHASE         (1 << 2)
 188 #define MDP4_OP_SCALEX_PIXEL_RPT        (2 << 2)
 189 #define MDP4_OP_SCALEY_EN       BIT(1)
 190 #define MDP4_OP_SCALEX_EN       BIT(0)
 191
 192 #define MDP4_PIPE_PER_MIXER     2
 193
 194 #define MDP4_MAX_PLANE          4
 195
 196 #define MDP4_MAX_VIDEO_PIPE 2
 197 #define MDP4_MAX_RGB_PIPE 2
 198 #define MDP4_MAX_OVERLAY_PIPE   16
 199
 200
 201 struct mdp4_overlay_pipe {
 202         uint32 pipe_type;               /* rgb, video/graphic */
 203         uint32 pipe_num;
 204         uint32 pipe_ndx;
 205         uint32 mixer_num;               /* which mixer used */
 206         uint32 mixer_stage;             /* which stage of mixer used */
 207         uint32 src_format;
 208         uint32 src_width;       /* source img width */
 209         uint32 src_height;      /* source img height */
 210         uint32 src_w;           /* roi */
 211         uint32 src_h;           /* roi */
 212         uint32 src_x;           /* roi */
 213         uint32 src_y;           /* roi */
 214         uint32 dst_w;           /* roi */
 215         uint32 dst_h;           /* roi */
 216         uint32 dst_x;           /* roi */
 217         uint32 dst_y;           /* roi */
 218         uint32 op_mode;
 219         uint32 transp;
 220         uint32 blend_op;
 221         uint32 phasex_step;
 222         uint32 phasey_step;
 223         uint32 alpha;
 224         uint32 is_fg;           /* control alpha & color key */
 225         uint32 srcp0_addr;      /* interleave, luma */
 226         uint32 srcp0_ystride;
 227         uint32 srcp1_addr;      /* pseudoplanar, chroma plane */
 228         uint32 srcp1_ystride;
 229         uint32 srcp2_addr;      /* planar color 2*/
 230         uint32 srcp2_ystride;
 231         uint32 srcp3_addr;      /* alpha/color 3 */
 232         uint32 srcp3_ystride;
 233         uint32 fetch_plane;
 234         uint32 frame_format;            /* video */
 235         uint32 chroma_site;             /* video */
 236         uint32 chroma_sample;           /* video */
 237         uint32 solid_fill;
 238         uint32 vc1_reduce;              /* video */
 239         uint32 fatch_planes;            /* video */
 240         uint32 unpack_align_msb;/* 0 to LSB, 1 to MSB */
 241         uint32 unpack_tight;/* 0 for loose, 1 for tight */
 242         uint32 unpack_count;/* 0 = 1 component, 1 = 2 component ... */
 243         uint32 rotated_90; /* has been rotated 90 degree */
 244         uint32 bpp;     /* byte per pixel */
 245         uint32 alpha_enable;/*  source has alpha */
 246         /*
 247          * number of bits for source component,
 248          * 0 = 1 bit, 1 = 2 bits, 2 = 6 bits, 3 = 8 bits
 249          */
 250         uint32 a_bit;   /* component 3, alpha */
 251         uint32 r_bit;   /* component 2, R_Cr */
 252         uint32 b_bit;   /* component 1, B_Cb */
 253         uint32 g_bit;   /* component 0, G_lumz */
 254         /*
 255          * unpack pattern
 256          * A = C3, R = C2, B = C1, G = C0
 257          */
 258         uint32 element3; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
 259         uint32 element2; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
 260         uint32 element1; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
 261         uint32 element0; /* 0 = C0, 1 = C1, 2 = C2, 3 = C3 */
 262         struct completion comp;
 263         struct mdp_overlay req_data;
 264 };
 265
 266 void mdp4_sw_reset(unsigned long bits);
 267 void mdp4_display_intf_sel(int output, unsigned long intf);
 268 void mdp4_overlay_cfg(int layer, int blt_mode, int refresh, int direct_out);
 269 void mdp4_ebi2_lcd_setup(int lcd, unsigned long base, int ystride);
 270 void mdp4_mddi_setup(int which, unsigned long id);
 271 unsigned long mdp4_display_status(void);
 272 void mdp4_enable_clk_irq(void);
 273 void mdp4_disable_clk_irq(void);
 274 void mdp4_dma_p_update(struct msm_fb_data_type *mfd);
 275 void mdp4_dma_s_update(struct msm_fb_data_type *mfd);
 276 void mdp_pipe_ctrl(MDP_BLOCK_TYPE block, MDP_BLOCK_POWER_STATE state,
 277                    boolean isr);
 278 void mdp4_pipe_kickoff(uint32 pipe, struct msm_fb_data_type *mfd);
 279 int mdp4_lcdc_on(struct platform_device *pdev);
 280 int mdp4_lcdc_off(struct platform_device *pdev);
 281 void mdp4_lcdc_update(struct msm_fb_data_type *mfd);
 282 void mdp4_intr_clear_set(ulong clear, ulong set);
 283 void mdp4_dma_p_cfg(void);
 284 void mdp4_hw_init(void);
 285 void mdp4_isr_read(int);
 286 void mdp4_clear_lcdc(void);
 287 void mdp4_mixer_blend_init(int mixer_num);
 288 void mdp4_vg_qseed_init(int vg_num);
 289 void mdp4_vg_csc_mv_setup(int vp_num);
 290 void mdp4_vg_csc_pre_bv_setup(int vp_num);
 291 void mdp4_vg_csc_post_bv_setup(int vp_num);
 292 void mdp4_vg_csc_pre_lv_setup(int vp_num);
 293 void mdp4_vg_csc_post_lv_setup(int vp_num);
 294 irqreturn_t mdp4_isr(int irq, void *ptr);
 295 void mdp4_overlay_format_to_pipe(uint32 format, struct mdp4_overlay_pipe *pipe);
 296 uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe);
 297 uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe);
 298 uint32 mdp4_overlay_op_mode(struct mdp4_overlay_pipe *pipe);
 299 void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd);
 300 void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe);
 301 void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all);
 302 void mdp4_mixer_blend_setup(struct mdp4_overlay_pipe *pipe);
 303 void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe);
 304 void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe);
 305 int mdp4_mixer_stage_can_run(struct mdp4_overlay_pipe *pipe);
 306 void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe);
 307 void mdp4_mddi_overlay(struct msm_fb_data_type *mfd);
 308 int mdp4_overlay_format2type(uint32 format);
 309 int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe);
 310 int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req);
 311 int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req);
 312 int mdp4_overlay_unset(struct fb_info *info, int ndx);
 313 int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
 314                                 struct file **pp_src_file);
 315 struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(void);
 316 void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe);
 317 void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc);
 318 void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe);
 319 int mdp4_overlay_active(int mixer);
 320 void mdp4_overlay0_done_lcdc(void);
 321 void mdp4_overlay0_done_mddi(void);
 322 void mdp4_mddi_overlay_restore(void);
 323 void mdp4_mddi_overlay_kickoff(struct msm_fb_data_type *mfd,
 324                                 struct mdp4_overlay_pipe *pipe);
 325 void mdp4_rgb_igc_lut_setup(int num);
 326 void mdp4_vg_igc_lut_setup(int num);
 327 void mdp4_mixer_gc_lut_setup(int mixer_num);
 328
 329 #ifdef CONFIG_DEBUG_FS
 330 int mdp4_debugfs_init(void);
 331 #endif
 332
 333 int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req,
 334         struct file **pp_src_file, struct file **pp_dst_file);
 335
 336 #endif /* MDP_H */