1 /****************************************************************************/
4 * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
6 * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
7 * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
8 * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
11 /****************************************************************************/
14 /****************************************************************************/
17 /****************************************************************************/
19 /****************************************************************************/
21 #ifdef CONFIG_COLDFIRE
22 #include <asm/coldfire.h>
23 #include <asm/mcfsim.h>
26 /*---------------------------------------------------------------------------*/
27 #if defined(CONFIG_M5307)
29 * NETtel/5307 based hardware first. DTR/DCD lines are wired to
30 * GPIO lines. Most of the LED's are driver through a latch
33 #define MCFPP_DCD1 0x0001
34 #define MCFPP_DCD0 0x0002
35 #define MCFPP_DTR1 0x0004
36 #define MCFPP_DTR0 0x0008
38 #define NETtel_LEDADDR 0x30400000
42 extern volatile unsigned short ppdata
;
45 * These functions defined to give quasi generic access to the
46 * PPIO bits used for DTR/DCD.
48 static __inline__
unsigned int mcf_getppdata(void)
50 volatile unsigned short *pp
;
51 pp
= (volatile unsigned short *) (MCF_MBAR
+ MCFSIM_PADAT
);
52 return((unsigned int) *pp
);
55 static __inline__
void mcf_setppdata(unsigned int mask
, unsigned int bits
)
57 volatile unsigned short *pp
;
58 pp
= (volatile unsigned short *) (MCF_MBAR
+ MCFSIM_PADAT
);
59 ppdata
= (ppdata
& ~mask
) | bits
;
64 /*---------------------------------------------------------------------------*/
65 #elif defined(CONFIG_M5206e)
67 * NETtel/5206e based hardware has leds on latch on CS3.
68 * No support modem for lines??
70 #define NETtel_LEDADDR 0x50000000
72 /*---------------------------------------------------------------------------*/
73 #elif defined(CONFIG_M5272)
75 * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines.
77 #define MCFPP_DCD0 0x0080
78 #define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */
79 #define MCFPP_DTR0 0x0040
80 #define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */
84 * These functions defined to give quasi generic access to the
85 * PPIO bits used for DTR/DCD.
87 static __inline__
unsigned int mcf_getppdata(void)
89 volatile unsigned short *pp
;
90 pp
= (volatile unsigned short *) (MCF_MBAR
+ MCFSIM_PBDAT
);
91 return((unsigned int) *pp
);
94 static __inline__
void mcf_setppdata(unsigned int mask
, unsigned int bits
)
96 volatile unsigned short *pp
;
97 pp
= (volatile unsigned short *) (MCF_MBAR
+ MCFSIM_PBDAT
);
98 *pp
= (*pp
& ~mask
) | bits
;
103 /*---------------------------------------------------------------------------*/
105 /****************************************************************************/
106 #endif /* CONFIG_NETtel */
107 /****************************************************************************/
108 #endif /* nettel_h */