drivers/media/dvb/ngene/ngene.h

   1 /*
   2  * ngene.h: nGene PCIe bridge driver
   3  *
   4  * Copyright (C) 2005-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #ifndef _NGENE_H_
  25 #define _NGENE_H_
  26
  27 #define ONE_ADAPTER
  28 #define NGENE_COMMAND_API
  29 /*#define NGENE_V4L*/
  30
  31 #include <linux/types.h>
  32 #include <linux/sched.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/i2c.h>
  35 #include <asm/dma.h>
  36 #include <asm/scatterlist.h>
  37 #include <sound/driver.h>
  38 #include <sound/core.h>
  39 #include <sound/initval.h>
  40 #include <sound/control.h>
  41 #include <sound/pcm.h>
  42 #include <sound/pcm_params.h>
  43
  44 #include <linux/dvb/frontend.h>
  45 #include <linux/dvb/ca.h>
  46 #include <linux/dvb/video.h>
  47 #include <linux/dvb/audio.h>
  48
  49 #include "dmxdev.h"
  50 #include "dvbdev.h"
  51 #include "dvb_demux.h"
  52 #include "dvb_frontend.h"
  53 #include "dvb_ringbuffer.h"
  54 #include "drxd.h"
  55 #include "drxh.h"
  56 #include "xc3028.h"
  57 #include "stb0899.h"
  58 #include "stv0900.h"
  59 #include "mt2060.h"
  60
  61 #ifdef NGENE_V4L
  62 #include <media/v4l2-dev.h>
  63 #include <media/videobuf-core.h>
  64 #include <linux/videodev.h>
  65 #endif
  66
  67 #define NGENE_VID       0x18c3
  68 #define NGENE_PID       0x0720
  69
  70 #ifndef VIDEO_CAP_VC1
  71 #define VIDEO_CAP_AVC   128
  72 #define VIDEO_CAP_H264  128
  73 #define VIDEO_CAP_VC1   256
  74 #define VIDEO_CAP_WMV9  256
  75 #define VIDEO_CAP_MPEG4 512
  76 #endif
  77
  78 enum STREAM {
  79         STREAM_VIDEOIN1 = 0,        /* ITU656 or TS Input */
  80         STREAM_VIDEOIN2,
  81         STREAM_AUDIOIN1,            /* I2S or SPI Input */
  82         STREAM_AUDIOIN2,
  83         STREAM_AUDIOOUT,
  84         MAX_STREAM
  85 };
  86
  87 enum SMODE_BITS {
  88         SMODE_AUDIO_SPDIF = 0x20,
  89         SMODE_AVSYNC = 0x10,
  90         SMODE_TRANSPORT_STREAM = 0x08,
  91         SMODE_AUDIO_CAPTURE = 0x04,
  92         SMODE_VBI_CAPTURE = 0x02,
  93         SMODE_VIDEO_CAPTURE = 0x01
  94 };
  95
  96 enum STREAM_FLAG_BITS {
  97         SFLAG_CHROMA_FORMAT_2COMP  = 0x01, /* Chroma Format : 2's complement */
  98         SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
  99         SFLAG_ORDER_LUMA_CHROMA    = 0x02, /* Byte order: Y,Cb,Y,Cr */
 100         SFLAG_ORDER_CHROMA_LUMA    = 0x00, /* Byte order: Cb,Y,Cr,Y */
 101         SFLAG_COLORBAR             = 0x04, /* Select colorbar */
 102 };
 103
 104 #define PROGRAM_ROM     0x0000
 105 #define PROGRAM_SRAM    0x1000
 106 #define PERIPHERALS0    0x8000
 107 #define PERIPHERALS1    0x9000
 108 #define SHARED_BUFFER   0xC000
 109
 110 #define HOST_TO_NGENE    (SHARED_BUFFER+0x0000)
 111 #define NGENE_TO_HOST    (SHARED_BUFFER+0x0100)
 112 #define NGENE_COMMAND    (SHARED_BUFFER+0x0200)
 113 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
 114 #define NGENE_STATUS     (SHARED_BUFFER+0x0208)
 115 #define NGENE_STATUS_HI  (SHARED_BUFFER+0x020C)
 116 #define NGENE_EVENT      (SHARED_BUFFER+0x0210)
 117 #define NGENE_EVENT_HI   (SHARED_BUFFER+0x0214)
 118 #define VARIABLES        (SHARED_BUFFER+0x0210)
 119
 120 #define NGENE_INT_COUNTS       (SHARED_BUFFER+0x0260)
 121 #define NGENE_INT_ENABLE       (SHARED_BUFFER+0x0264)
 122 #define NGENE_VBI_LINE_COUNT   (SHARED_BUFFER+0x0268)
 123
 124 #define BUFFER_GP_XMIT  (SHARED_BUFFER+0x0800)
 125 #define BUFFER_GP_RECV  (SHARED_BUFFER+0x0900)
 126 #define EEPROM_AREA     (SHARED_BUFFER+0x0A00)
 127
 128 #define SG_V_IN_1       (SHARED_BUFFER+0x0A80)
 129 #define SG_VBI_1        (SHARED_BUFFER+0x0B00)
 130 #define SG_A_IN_1       (SHARED_BUFFER+0x0B80)
 131 #define SG_V_IN_2       (SHARED_BUFFER+0x0C00)
 132 #define SG_VBI_2        (SHARED_BUFFER+0x0C80)
 133 #define SG_A_IN_2       (SHARED_BUFFER+0x0D00)
 134 #define SG_V_OUT        (SHARED_BUFFER+0x0D80)
 135 #define SG_A_OUT2       (SHARED_BUFFER+0x0E00)
 136
 137 #define DATA_A_IN_1     (SHARED_BUFFER+0x0E80)
 138 #define DATA_A_IN_2     (SHARED_BUFFER+0x0F00)
 139 #define DATA_A_OUT      (SHARED_BUFFER+0x0F80)
 140 #define DATA_V_IN_1     (SHARED_BUFFER+0x1000)
 141 #define DATA_V_IN_2     (SHARED_BUFFER+0x2000)
 142 #define DATA_V_OUT      (SHARED_BUFFER+0x3000)
 143
 144 #define DATA_FIFO_AREA  (SHARED_BUFFER+0x1000)
 145
 146 #define TIMESTAMPS      0xA000
 147 #define SCRATCHPAD      0xA080
 148 #define FORCE_INT       0xA088
 149 #define FORCE_NMI       0xA090
 150 #define INT_STATUS      0xA0A0
 151
 152 #define DEV_VER         0x9004
 153
 154 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
 155
 156 struct SG_ADDR {
 157         u64 start;
 158         u64 curr;
 159         u16 curr_ptr;
 160         u16 elements;
 161         u32 pad[3];
 162 } __attribute__ ((__packed__));
 163
 164 struct SHARED_MEMORY {
 165         /* C000 */
 166         u32 HostToNgene[64];
 167
 168         /* C100 */
 169         u32 NgeneToHost[64];
 170
 171         /* C200 */
 172         u64 NgeneCommand;
 173         u64 NgeneStatus;
 174         u64 NgeneEvent;
 175
 176         /* C210 */
 177         u8 pad1[0xc260 - 0xc218];
 178
 179         /* C260 */
 180         u32 IntCounts;
 181         u32 IntEnable;
 182
 183         /* C268 */
 184         u8 pad2[0xd000 - 0xc268];
 185
 186 } __attribute__ ((__packed__));
 187
 188 struct BUFFER_STREAM_RESULTS {
 189         u32 Clock;           /* Stream time in 100ns units */
 190         u16 RemainingLines;  /* Remaining lines in this field.
 191                                 0 for complete field */
 192         u8  FieldCount;      /* Video field number */
 193         u8  Flags;           /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
 194                                 Bit 0 = FieldID */
 195         u16 BlockCount;      /* Audio block count (unused) */
 196         u8  Reserved[2];
 197         u32 DTOUpdate;
 198 } __attribute__ ((__packed__));
 199
 200 struct HW_SCATTER_GATHER_ELEMENT {
 201         u64 Address;
 202         u32 Length;
 203         u32 Reserved;
 204 } __attribute__ ((__packed__));
 205
 206 struct BUFFER_HEADER {
 207         u64    Next;
 208         struct BUFFER_STREAM_RESULTS SR;
 209
 210         u32    Number_of_entries_1;
 211         u32    Reserved5;
 212         u64    Address_of_first_entry_1;
 213
 214         u32    Number_of_entries_2;
 215         u32    Reserved7;
 216         u64    Address_of_first_entry_2;
 217 } __attribute__ ((__packed__));
 218
 219 struct EVENT_BUFFER {
 220         u32    TimeStamp;
 221         u8     GPIOStatus;
 222         u8     UARTStatus;
 223         u8     RXCharacter;
 224         u8     EventStatus;
 225         u32    Reserved[2];
 226 } __attribute__ ((__packed__));
 227
 228 typedef struct EVENT_BUFFER *PEVENT_BUFFER;
 229
 230 /* Firmware commands. */
 231
 232 enum OPCODES {
 233         CMD_NOP = 0,
 234         CMD_FWLOAD_PREPARE  = 0x01,
 235         CMD_FWLOAD_FINISH   = 0x02,
 236         CMD_I2C_READ        = 0x03,
 237         CMD_I2C_WRITE       = 0x04,
 238
 239         CMD_I2C_WRITE_NOSTOP = 0x05,
 240         CMD_I2C_CONTINUE_WRITE = 0x06,
 241         CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
 242
 243         CMD_DEBUG_OUTPUT    = 0x09,
 244
 245         CMD_CONTROL         = 0x10,
 246         CMD_CONFIGURE_BUFFER = 0x11,
 247         CMD_CONFIGURE_FREE_BUFFER = 0x12,
 248
 249         CMD_SPI_READ        = 0x13,
 250         CMD_SPI_WRITE       = 0x14,
 251
 252         CMD_MEM_READ        = 0x20,
 253         CMD_MEM_WRITE       = 0x21,
 254         CMD_SFR_READ        = 0x22,
 255         CMD_SFR_WRITE       = 0x23,
 256         CMD_IRAM_READ       = 0x24,
 257         CMD_IRAM_WRITE      = 0x25,
 258         CMD_SET_GPIO_PIN    = 0x26,
 259         CMD_SET_GPIO_INT    = 0x27,
 260         CMD_CONFIGURE_UART  = 0x28,
 261         CMD_WRITE_UART      = 0x29,
 262         MAX_CMD
 263 };
 264
 265 enum RESPONSES {
 266         OK = 0,
 267         ERROR = 1
 268 };
 269
 270 struct FW_HEADER {
 271         u8 Opcode;
 272         u8 Length;
 273 } __attribute__ ((__packed__));
 274
 275 struct FW_I2C_WRITE {
 276         struct FW_HEADER hdr;
 277         u8 Device;
 278         u8 Data[250];
 279 } __attribute__ ((__packed__));
 280
 281 struct FW_I2C_CONTINUE_WRITE {
 282         struct FW_HEADER hdr;
 283         u8 Data[250];
 284 } __attribute__ ((__packed__));
 285
 286 struct FW_I2C_READ {
 287         struct FW_HEADER hdr;
 288         u8 Device;
 289         u8 Data[252];    /* followed by two bytes of read data count */
 290 } __attribute__ ((__packed__));
 291
 292 struct FW_SPI_WRITE {
 293         struct FW_HEADER hdr;
 294         u8 ModeSelect;
 295         u8 Data[250];
 296 } __attribute__ ((__packed__));
 297
 298 struct FW_SPI_READ {
 299         struct FW_HEADER hdr;
 300         u8 ModeSelect;
 301         u8 Data[252];    /* followed by two bytes of read data count */
 302 } __attribute__ ((__packed__));
 303
 304 struct FW_FWLOAD_PREPARE {
 305         struct FW_HEADER hdr;
 306 } __attribute__ ((__packed__));
 307
 308 struct FW_FWLOAD_FINISH {
 309         struct FW_HEADER hdr;
 310         u16 Address;     /* address of final block */
 311         u16 Length;
 312 } __attribute__ ((__packed__));
 313
 314 /*
 315  * Meaning of FW_STREAM_CONTROL::Mode bits:
 316  *  Bit 7: Loopback PEXin to PEXout using TVOut channel
 317  *  Bit 6: AVLOOP
 318  *  Bit 5: Audio select; 0=I2S, 1=SPDIF
 319  *  Bit 4: AVSYNC
 320  *  Bit 3: Enable transport stream
 321  *  Bit 2: Enable audio capture
 322  *  Bit 1: Enable ITU-Video VBI capture
 323  *  Bit 0: Enable ITU-Video capture
 324  *
 325  * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
 326  *  Bit 7: continuous capture
 327  *  Bit 6: capture one field
 328  *  Bit 5: capture one frame
 329  *  Bit 4: unused
 330  *  Bit 3: starting field; 0=odd, 1=even
 331  *  Bit 2: sample size; 0=8-bit, 1=10-bit
 332  *  Bit 1: data format; 0=UYVY, 1=YUY2
 333  *  Bit 0: resets buffer pointers
 334 */
 335
 336 enum FSC_MODE_BITS {
 337         SMODE_LOOPBACK          = 0x80,
 338         SMODE_AVLOOP            = 0x40,
 339         _SMODE_AUDIO_SPDIF      = 0x20,
 340         _SMODE_AVSYNC           = 0x10,
 341         _SMODE_TRANSPORT_STREAM = 0x08,
 342         _SMODE_AUDIO_CAPTURE    = 0x04,
 343         _SMODE_VBI_CAPTURE      = 0x02,
 344         _SMODE_VIDEO_CAPTURE    = 0x01
 345 };
 346
 347
 348 /* Meaning of FW_STREAM_CONTROL::Stream bits:
 349  * Bit 3: Audio sample count:  0 = relative, 1 = absolute
 350  * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
 351  * Bits 1-0: stream select, UVI1, UVI2, TVOUT
 352  */
 353
 354 struct FW_STREAM_CONTROL {
 355         struct FW_HEADER hdr;
 356         u8     Stream;             /* Stream number (UVI1, UVI2, TVOUT) */
 357         u8     Control;            /* Value written to UVI1_CTL */
 358         u8     Mode;               /* Controls clock source */
 359         u8     SetupDataLen;       /* Length of setup data, MSB=1 write
 360                                       backwards */
 361         u16    CaptureBlockCount;  /* Blocks (a 256 Bytes) to capture per buffer
 362                                       for TS and Audio */
 363         u64    Buffer_Address;     /* Address of first buffer header */
 364         u16    BytesPerVideoLine;
 365         u16    MaxLinesPerField;
 366         u16    MinLinesPerField;
 367         u16    Reserved_1;
 368         u16    BytesPerVBILine;
 369         u16    MaxVBILinesPerField;
 370         u16    MinVBILinesPerField;
 371         u16    SetupDataAddr;      /* ngene relative address of setup data */
 372         u8     SetupData[32];      /* setup data */
 373 } __attribute__((__packed__));
 374
 375 #define AUDIO_BLOCK_SIZE    256
 376 #define TS_BLOCK_SIZE       256
 377
 378 struct FW_MEM_READ {
 379         struct FW_HEADER hdr;
 380         u16   address;
 381 } __attribute__ ((__packed__));
 382
 383 struct FW_MEM_WRITE {
 384         struct FW_HEADER hdr;
 385         u16   address;
 386         u8    data;
 387 } __attribute__ ((__packed__));
 388
 389 struct FW_SFR_IRAM_READ {
 390         struct FW_HEADER hdr;
 391         u8    address;
 392 } __attribute__ ((__packed__));
 393
 394 struct FW_SFR_IRAM_WRITE {
 395         struct FW_HEADER hdr;
 396         u8    address;
 397         u8    data;
 398 } __attribute__ ((__packed__));
 399
 400 struct FW_SET_GPIO_PIN {
 401         struct FW_HEADER hdr;
 402         u8    select;
 403 } __attribute__ ((__packed__));
 404
 405 struct FW_SET_GPIO_INT {
 406         struct FW_HEADER hdr;
 407         u8    select;
 408 } __attribute__ ((__packed__));
 409
 410 struct FW_SET_DEBUGMODE {
 411         struct FW_HEADER hdr;
 412         u8   debug_flags;
 413 } __attribute__ ((__packed__));
 414
 415 struct FW_CONFIGURE_BUFFERS {
 416         struct FW_HEADER hdr;
 417         u8   config;
 418 } __attribute__ ((__packed__));
 419
 420 enum _BUFFER_CONFIGS {
 421         /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2  (standard usage) */
 422         BUFFER_CONFIG_4422 = 0,
 423         /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2  (4x TS input usage) */
 424         BUFFER_CONFIG_3333 = 1,
 425         /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut  (HDTV decoder usage) */
 426         BUFFER_CONFIG_8022 = 2,
 427         BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
 428 };
 429
 430 struct FW_CONFIGURE_FREE_BUFFERS {
 431         struct FW_HEADER hdr;
 432         u8   UVI1_BufferLength;
 433         u8   UVI2_BufferLength;
 434         u8   TVO_BufferLength;
 435         u8   AUD1_BufferLength;
 436         u8   AUD2_BufferLength;
 437         u8   TVA_BufferLength;
 438 } __attribute__ ((__packed__));
 439
 440 struct FW_CONFIGURE_UART {
 441         struct FW_HEADER hdr;
 442         u8 UartControl;
 443 } __attribute__ ((__packed__));
 444
 445 enum _UART_CONFIG {
 446         _UART_BAUDRATE_19200 = 0,
 447         _UART_BAUDRATE_9600  = 1,
 448         _UART_BAUDRATE_4800  = 2,
 449         _UART_BAUDRATE_2400  = 3,
 450         _UART_RX_ENABLE      = 0x40,
 451         _UART_TX_ENABLE      = 0x80,
 452 };
 453
 454 struct FW_WRITE_UART {
 455         struct FW_HEADER hdr;
 456         u8 Data[252];
 457 } __attribute__ ((__packed__));
 458
 459
 460 struct ngene_command {
 461         u32 in_len;
 462         u32 out_len;
 463         union {
 464                 u32                              raw[64];
 465                 u8                               raw8[256];
 466                 struct FW_HEADER                 hdr;
 467                 struct FW_I2C_WRITE              I2CWrite;
 468                 struct FW_I2C_CONTINUE_WRITE     I2CContinueWrite;
 469                 struct FW_I2C_READ               I2CRead;
 470                 struct FW_STREAM_CONTROL         StreamControl;
 471                 struct FW_FWLOAD_PREPARE         FWLoadPrepare;
 472                 struct FW_FWLOAD_FINISH          FWLoadFinish;
 473                 struct FW_MEM_READ               MemoryRead;
 474                 struct FW_MEM_WRITE              MemoryWrite;
 475                 struct FW_SFR_IRAM_READ          SfrIramRead;
 476                 struct FW_SFR_IRAM_WRITE         SfrIramWrite;
 477                 struct FW_SPI_WRITE              SPIWrite;
 478                 struct FW_SPI_READ               SPIRead;
 479                 struct FW_SET_GPIO_PIN           SetGpioPin;
 480                 struct FW_SET_GPIO_INT           SetGpioInt;
 481                 struct FW_SET_DEBUGMODE          SetDebugMode;
 482                 struct FW_CONFIGURE_BUFFERS      ConfigureBuffers;
 483                 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
 484                 struct FW_CONFIGURE_UART         ConfigureUart;
 485                 struct FW_WRITE_UART             WriteUart;
 486         } cmd;
 487 } __attribute__ ((__packed__));
 488
 489 #define NGENE_INTERFACE_VERSION 0x103
 490 #define MAX_VIDEO_BUFFER_SIZE   (417792) /* 288*1440 rounded up to next page */
 491 #define MAX_AUDIO_BUFFER_SIZE     (8192) /* Gives room for about 23msec@48KHz */
 492 #define MAX_VBI_BUFFER_SIZE      (28672) /* 1144*18 rounded up to next page */
 493 #define MAX_TS_BUFFER_SIZE       (98304) /* 512*188 rounded up to next page */
 494 #define MAX_HDTV_BUFFER_SIZE   (2080768) /* 541*1920*2 rounded up to next page
 495                                             Max: (1920x1080i60) */
 496
 497 #define OVERFLOW_BUFFER_SIZE    (8192)
 498
 499 #define RING_SIZE_VIDEO     4
 500 #define RING_SIZE_AUDIO     8
 501 #define RING_SIZE_TS        8
 502
 503 #define NUM_SCATTER_GATHER_ENTRIES  8
 504
 505 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
 506                         RING_SIZE_VIDEO * 2) + \
 507                         (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
 508                         (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
 509                         (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
 510                         (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
 511                         (RING_SIZE_TS    * PAGE_SIZE * 4) + \
 512                          8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
 513
 514 #define EVENT_QUEUE_SIZE    16
 515
 516 typedef struct HW_SCATTER_GATHER_ELEMENT *PHW_SCATTER_GATHER_ELEMENT;
 517 typedef struct FWRB *PFWRB;
 518
 519 /* Gathers the current state of a single channel. */
 520
 521 struct SBufferHeader {
 522         struct BUFFER_HEADER   ngeneBuffer; /* Physical descriptor */
 523         struct SBufferHeader  *Next;
 524         void                  *Buffer1;
 525         PHW_SCATTER_GATHER_ELEMENT scList1;
 526         void                  *Buffer2;
 527         PHW_SCATTER_GATHER_ELEMENT scList2;
 528 };
 529
 530 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
 531 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
 532
 533 enum HWSTATE {
 534         HWSTATE_STOP,
 535         HWSTATE_STARTUP,
 536         HWSTATE_RUN,
 537         HWSTATE_PAUSE,
 538 };
 539
 540 enum KSSTATE {
 541         KSSTATE_STOP,
 542         KSSTATE_ACQUIRE,
 543         KSSTATE_PAUSE,
 544         KSSTATE_RUN,
 545 };
 546
 547 struct SRingBufferDescriptor {
 548         struct SBufferHeader *Head; /* Points to first buffer in ring buffer
 549                                        structure*/
 550         u64   PAHead;         /* Physical address of first buffer */
 551         u32   MemSize;        /* Memory size of allocated ring buffers
 552                                  (needed for freeing) */
 553         u32   NumBuffers;     /* Number of buffers in the ring */
 554         u32   Buffer1Length;  /* Allocated length of Buffer 1 */
 555         u32   Buffer2Length;  /* Allocated length of Buffer 2 */
 556         void *SCListMem;      /* Memory to hold scatter gather lists for this
 557                                  ring */
 558         u64   PASCListMem;    /* Physical address  .. */
 559         u32   SCListMemSize;  /* Size of this memory */
 560 };
 561
 562 enum STREAMMODEFLAGS {
 563         StreamMode_NONE   = 0, /* Stream not used */
 564         StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
 565         StreamMode_TSIN   = 2, /* Transport stream input (all) */
 566         StreamMode_HDTV   = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
 567                                   (only stream 0) */
 568         StreamMode_TSOUT  = 8, /* Transport stream output (only stream 3) */
 569 };
 570
 571
 572 enum BufferExchangeFlags {
 573         BEF_EVEN_FIELD   = 0x00000001,
 574         BEF_CONTINUATION = 0x00000002,
 575         BEF_MORE_DATA    = 0x00000004,
 576         BEF_OVERFLOW     = 0x00000008,
 577         DF_SWAP32        = 0x00010000,
 578 };
 579
 580 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
 581
 582 typedef struct {
 583         IBufferExchange    *pExchange;
 584         IBufferExchange    *pExchangeVBI;     /* Secondary (VBI, ancillary) */
 585         u8  Stream;
 586         u8  Flags;
 587         u8  Mode;
 588         u8  Reserved;
 589         u16 nLinesVideo;
 590         u16 nBytesPerLineVideo;
 591         u16 nLinesVBI;
 592         u16 nBytesPerLineVBI;
 593         u32 CaptureLength;    /* Used for audio and transport stream */
 594 } MICI_STREAMINFO, *PMICI_STREAMINFO;
 595
 596 /****************************************************************************/
 597 /* STRUCTS ******************************************************************/
 598 /****************************************************************************/
 599
 600 /* sound hardware definition */
 601 #define MIXER_ADDR_TVTUNER      0
 602 #define MIXER_ADDR_LAST         0
 603
 604 struct ngene_channel;
 605
 606 /*struct sound chip*/
 607
 608 struct mychip {
 609         struct ngene_channel *chan;
 610         struct snd_card *card;
 611         struct pci_dev *pci;
 612         struct snd_pcm_substream *substream;
 613         struct snd_pcm *pcm;
 614         unsigned long port;
 615         int irq;
 616         spinlock_t mixer_lock;
 617         spinlock_t lock;
 618         int mixer_volume[MIXER_ADDR_LAST + 1][2];
 619         int capture_source[MIXER_ADDR_LAST + 1][2];
 620 };
 621
 622 #ifdef NGENE_V4L
 623 struct ngene_overlay {
 624         int                    tvnorm;
 625         struct v4l2_rect       w;
 626         enum v4l2_field        field;
 627         struct v4l2_clip       *clips;
 628         int                    nclips;
 629         int                    setup_ok;
 630 };
 631
 632 struct ngene_tvnorm {
 633         int   v4l2_id;
 634         char  *name;
 635         u16   swidth, sheight; /* scaled standard width, height */
 636         int   tuner_norm;
 637         int   soundstd;
 638 };
 639
 640 struct ngene_vopen {
 641         struct ngene_channel      *ch;
 642         enum v4l2_priority         prio;
 643         int                        width;
 644         int                        height;
 645         int                        depth;
 646         struct videobuf_queue      vbuf_q;
 647         struct videobuf_queue      vbi;
 648         int                        fourcc;
 649         int                        picxcount;
 650         int                        resources;
 651         enum v4l2_buf_type         type;
 652         const struct ngene_format *fmt;
 653
 654         const struct ngene_format *ovfmt;
 655         struct ngene_overlay       ov;
 656 };
 657 #endif
 658
 659 struct ngene_channel {
 660         struct device         device;
 661         struct i2c_adapter    i2c_adapter;
 662
 663         struct ngene         *dev;
 664         int                   number;
 665         int                   type;
 666         int                   mode;
 667
 668         struct dvb_frontend  *fe;
 669         struct dmxdev         dmxdev;
 670         struct dvb_demux      demux;
 671         struct dmx_frontend   hw_frontend;
 672         struct dmx_frontend   mem_frontend;
 673         int                   users;
 674         struct video_device  *v4l_dev;
 675 #ifndef ONE_ADAPTER
 676         struct dvb_adapter    dvb_adapter;
 677 #endif
 678         struct dvb_device    *command_dev;
 679         struct dvb_device    *audio_dev;
 680         struct dvb_device    *video_dev;
 681         struct tasklet_struct demux_tasklet;
 682
 683         struct SBufferHeader *nextBuffer;
 684         enum KSSTATE          State;
 685         enum HWSTATE          HWState;
 686         u8                    Stream;
 687         u8                    Flags;
 688         u8                    Mode;
 689         IBufferExchange      *pBufferExchange;
 690         IBufferExchange      *pBufferExchange2;
 691
 692         spinlock_t            state_lock;
 693         u16                   nLines;
 694         u16                   nBytesPerLine;
 695         u16                   nVBILines;
 696         u16                   nBytesPerVBILine;
 697         u16                   itumode;
 698         u32                   Capture1Length;
 699         u32                   Capture2Length;
 700         struct SRingBufferDescriptor RingBuffer;
 701         struct SRingBufferDescriptor TSRingBuffer;
 702         struct SRingBufferDescriptor TSIdleBuffer;
 703
 704         u32                   DataFormatFlags;
 705
 706         int                   AudioDTOUpdated;
 707         u32                   AudioDTOValue;
 708
 709         int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
 710         u8 lnbh;
 711
 712         /* stuff from analog driver */
 713
 714         int minor;
 715         struct mychip        *mychip;
 716         struct snd_card      *soundcard;
 717         u8                   *evenbuffer;
 718         u8                   *soundbuffer;
 719         u8                    dma_on;
 720         int                   soundstreamon;
 721         int                   audiomute;
 722         int                   soundbuffisallocated;
 723         int                   sndbuffflag;
 724         int                   tun_rdy;
 725         int                   dec_rdy;
 726         int                   tun_dec_rdy;
 727         int                   lastbufferflag;
 728
 729         struct ngene_tvnorm  *tvnorms;
 730         int                   tvnorm_num;
 731         int                   tvnorm;
 732
 733 #ifdef NGENE_V4L
 734         int                   videousers;
 735         struct v4l2_prio_state prio;
 736         struct ngene_vopen    init;
 737         int                   resources;
 738         struct v4l2_framebuffer fbuf;
 739         struct ngene_buffer  *screen;     /* overlay             */
 740         struct list_head      capture;    /* video capture queue */
 741         spinlock_t s_lock;
 742         struct semaphore reslock;
 743 #endif
 744
 745         int running;
 746 };
 747
 748 struct ngene;
 749
 750 typedef void (rx_cb_t)(struct ngene *, u32, u8);
 751 typedef void (tx_cb_t)(struct ngene *, u32);
 752
 753 struct ngene {
 754         int                   nr;
 755         struct pci_dev       *pci_dev;
 756         unsigned char        *iomem;
 757
 758 #ifdef ONE_ADAPTER
 759         struct dvb_adapter    dvb_adapter;
 760 #endif
 761         /*struct i2c_adapter  i2c_adapter;*/
 762
 763         u32                   device_version;
 764         u32                   fw_interface_version;
 765         u32                   icounts;
 766
 767         u8                   *CmdDoneByte;
 768         int                   BootFirmware;
 769         void                 *OverflowBuffer;
 770         dma_addr_t            PAOverflowBuffer;
 771         void                 *FWInterfaceBuffer;
 772         dma_addr_t            PAFWInterfaceBuffer;
 773         u8                   *ngenetohost;
 774         u8                   *hosttongene;
 775
 776         struct EVENT_BUFFER   EventQueue[EVENT_QUEUE_SIZE];
 777         int                   EventQueueOverflowCount;
 778         int                   EventQueueOverflowFlag;
 779         struct tasklet_struct event_tasklet;
 780         struct EVENT_BUFFER  *EventBuffer;
 781         int                   EventQueueWriteIndex;
 782         int                   EventQueueReadIndex;
 783
 784         wait_queue_head_t     cmd_wq;
 785         int                   cmd_done;
 786         struct semaphore      cmd_mutex;
 787         struct semaphore      stream_mutex;
 788         struct semaphore      pll_mutex;
 789         struct semaphore      i2c_switch_mutex;
 790         int                   i2c_current_channel;
 791         int                   i2c_current_bus;
 792         spinlock_t            cmd_lock;
 793
 794         struct ngene_channel  channel[MAX_STREAM];
 795
 796         struct ngene_info    *card_info;
 797
 798         tx_cb_t              *TxEventNotify;
 799         rx_cb_t              *RxEventNotify;
 800         int                   tx_busy;
 801         wait_queue_head_t     tx_wq;
 802         wait_queue_head_t     rx_wq;
 803 #define UART_RBUF_LEN 4096
 804         u8                    uart_rbuf[UART_RBUF_LEN];
 805         int                   uart_rp, uart_wp;
 806
 807         u8                   *tsout_buf;
 808 #define TSOUT_BUF_SIZE (512*188*8)
 809         struct dvb_ringbuffer tsout_rbuf;
 810
 811         u8                   *ain_buf;
 812 #define AIN_BUF_SIZE (128*1024)
 813         struct dvb_ringbuffer ain_rbuf;
 814
 815
 816         u8                   *vin_buf;
 817 #define VIN_BUF_SIZE (4*1920*1080)
 818         struct dvb_ringbuffer vin_rbuf;
 819
 820         unsigned long         exp_val;
 821         int prev_cmd;
 822 };
 823
 824 struct channel_info {
 825         int   io_type;
 826 #define NGENE_IO_NONE    0
 827 #define NGENE_IO_TV      1
 828 #define NGENE_IO_HDTV    2
 829 #define NGENE_IO_TSIN    4
 830 #define NGENE_IO_TSOUT   8
 831 #define NGENE_IO_AIN     16
 832
 833         void *fe_config;
 834         void *tuner_config;
 835
 836         int (*demod_attach)(struct ngene_channel *);
 837         int   demod_type;
 838 #define NGENE_DEMOD_NONE    0
 839 #define NGENE_DEMOD_DRXD    1
 840 #define NGENE_DEMOD_STB0899 2
 841 #define NGENE_DEMOD_DRXH    3
 842
 843         int (*tuner_attach)(struct ngene_channel *);
 844         int   tuner_type;
 845 #define NGENE_TUNER_NONE    0
 846 #define NGENE_TUNER_MT2060  1
 847
 848         u8    demod;
 849         u8    tuner;
 850         u8    lnb;
 851         u8    demoda;
 852         u8    avf;
 853         u8    msp;
 854 };
 855
 856 struct ngene_info {
 857         int   type;
 858 #define NGENE_APP        0
 859 #define NGENE_TERRATEC   1
 860 #define NGENE_SIDEWINDER 2
 861 #define NGENE_RACER      3
 862 #define NGENE_VIPER      4
 863 #define NGENE_PYTHON     5
 864 #define NGENE_VBOX_V1    6
 865 #define NGENE_VBOX_V2    7
 866
 867         int   fw_version;
 868         char *name;
 869
 870         int   io_type[MAX_STREAM];
 871 #define NGENE_IO_NONE    0
 872 #define NGENE_IO_TV      1
 873 #define NGENE_IO_HDTV    2
 874 #define NGENE_IO_TSIN    4
 875 #define NGENE_IO_TSOUT   8
 876 #define NGENE_IO_AIN     16
 877
 878         void *fe_config[4];
 879         void *tuner_config[4];
 880
 881         int (*demod_attach[4])(struct ngene_channel *);
 882         int (*tuner_attach[4])(struct ngene_channel *);
 883
 884         u8    avf[4];
 885         u8    msp[4];
 886         u8    demoda[4];
 887         u8    lnb[4];
 888         int   i2c_access;
 889         u8    ntsc;
 890         u8    exp;
 891         u8    exp_init;
 892         u8    tsf[4];
 893         u8    i2s[4];
 894
 895         int (*gate_ctrl)(struct dvb_frontend *, int);
 896         int (*switch_ctrl)(struct ngene_channel *, int, int);
 897 };
 898
 899 #ifdef NGENE_V4L
 900 struct ngene_format{
 901         char *name;
 902         int   fourcc;          /* video4linux 2      */
 903         int   btformat;        /* BT848_COLOR_FMT_*  */
 904         int   format;
 905         int   btswap;          /* BT848_COLOR_CTL_*  */
 906         int   depth;           /* bit/pixel          */
 907         int   flags;
 908         int   hshift, vshift;  /* for planar modes   */
 909         int   palette;
 910 };
 911
 912 #define RESOURCE_OVERLAY       1
 913 #define RESOURCE_VIDEO         2
 914 #define RESOURCE_VBI           4
 915
 916 struct ngene_buffer {
 917         /* common v4l buffer stuff -- must be first */
 918         struct videobuf_buffer     vb;
 919
 920         /* ngene specific */
 921         const struct ngene_format *fmt;
 922         int                        tvnorm;
 923         int                        btformat;
 924         int                        btswap;
 925 };
 926 #endif
 927
 928 int ngene_command_stream_control(struct ngene *dev,
 929                                  u8 stream, u8 control, u8 mode, u8 flags);
 930 int ngene_command_nop(struct ngene *dev);
 931 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
 932                            u8 *out, u8 outlen, u8 *in, u8 inlen, int flag);
 933 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen);
 934 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type);
 935 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type);
 936 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
 937                          u16 lines, u16 bpl, u16 vblines, u16 vbibpl);
 938 int ngene_v4l2_init(struct ngene_channel *chan);
 939 void ngene_v4l2_remove(struct ngene_channel *chan);
 940 int ngene_snd_exit(struct ngene_channel *chan);
 941 int ngene_snd_init(struct ngene_channel *chan);
 942
 943 struct i2c_client *avf4910a_attach(struct i2c_adapter *adap, int addr);
 944
 945 #endif
 946
 947 /*  LocalWords:  Endif
 948  */