drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h

   1 /*
   2  * cfgdefs.h
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Global CFG constants and types, shared between DSP API and Bridge driver.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #ifndef CFGDEFS_
  20 #define CFGDEFS_
  21
  22 /* Maximum length of module search path. */
  23 #define CFG_MAXSEARCHPATHLEN    255
  24
  25 /* Maximum length of general paths. */
  26 #define CFG_MAXPATH             255
  27
  28 /* Host Resources: */
  29 #define CFG_MAXMEMREGISTERS     9
  30 #define CFG_MAXIOPORTS          20
  31 #define CFG_MAXIRQS             7
  32 #define CFG_MAXDMACHANNELS      7
  33
  34 /* IRQ flag */
  35 #define CFG_IRQSHARED           0x01    /* IRQ can be shared */
  36
  37 /* DSP Resources: */
  38 #define CFG_DSPMAXMEMTYPES      10
  39 #define CFG_DEFAULT_NUM_WINDOWS 1       /* We support only one window. */
  40
  41 /* A platform-related device handle: */
  42 struct cfg_devnode;
  43
  44 /*
  45  *  Host resource structure.
  46  */
  47 struct cfg_hostres {
  48         u32 num_mem_windows;    /* Set to default */
  49         /* This is the base.memory */
  50         u32 dw_mem_base[CFG_MAXMEMREGISTERS];   /* shm virtual address */
  51         u32 dw_mem_length[CFG_MAXMEMREGISTERS]; /* Length of the Base */
  52         u32 dw_mem_phys[CFG_MAXMEMREGISTERS];   /* shm Physical address */
  53         u8 birq_registers;      /* IRQ Number */
  54         u8 birq_attrib;         /* IRQ Attribute */
  55         u32 dw_offset_for_monitor;      /* The Shared memory starts from
  56                                          * dw_mem_base + this offset */
  57         /*
  58          *  Info needed by NODE for allocating channels to communicate with RMS:
  59          *      dw_chnl_offset:       Offset of RMS channels. Lower channels are
  60          *                          reserved.
  61          *      dw_chnl_buf_size:      Size of channel buffer to send to RMS
  62          *      dw_num_chnls:           Total number of channels
  63          *                              (including reserved).
  64          */
  65         u32 dw_chnl_offset;
  66         u32 dw_chnl_buf_size;
  67         u32 dw_num_chnls;
  68         void __iomem *dw_per_base;
  69         u32 dw_per_pm_base;
  70         u32 dw_core_pm_base;
  71         void __iomem *dw_dmmu_base;
  72         void __iomem *dw_sys_ctrl_base;
  73 };
  74
  75 struct cfg_dspmemdesc {
  76         u32 mem_type;           /* Type of memory. */
  77         u32 ul_min;             /* Minimum amount of memory of this type. */
  78         u32 ul_max;             /* Maximum amount of memory of this type. */
  79 };
  80
  81 #endif /* CFGDEFS_ */