drivers/pci/setup-bus.c

   1 /*
   2  *      drivers/pci/setup-bus.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /*
  13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  14  *           PCI-PCI bridges cleanup, sorted resource allocation.
  15  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Converted to allocation in 3 passes, which gives
  17  *           tighter packing. Prefetchable range support.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/pci.h>
  24 #include <linux/errno.h>
  25 #include <linux/ioport.h>
  26 #include <linux/cache.h>
  27 #include <linux/slab.h>
  28 #include "pci.h"
  29
  30 static void pbus_assign_resources_sorted(const struct pci_bus *bus)
  31 {
  32         struct pci_dev *dev;
  33         struct resource *res;
  34         struct resource_list head, *list, *tmp;
  35         int idx;
  36
  37         head.next = NULL;
  38         list_for_each_entry(dev, &bus->devices, bus_list) {
  39                 u16 class = dev->class >> 8;
  40
  41                 /* Don't touch classless devices or host bridges or ioapics.  */
  42                 if (class == PCI_CLASS_NOT_DEFINED ||
  43                     class == PCI_CLASS_BRIDGE_HOST)
  44                         continue;
  45
  46                 /* Don't touch ioapic devices already enabled by firmware */
  47                 if (class == PCI_CLASS_SYSTEM_PIC) {
  48                         u16 command;
  49                         pci_read_config_word(dev, PCI_COMMAND, &command);
  50                         if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
  51                                 continue;
  52                 }
  53
  54                 pdev_sort_resources(dev, &head);
  55         }
  56
  57         for (list = head.next; list;) {
  58                 res = list->res;
  59                 idx = res - &list->dev->resource[0];
  60                 if (pci_assign_resource(list->dev, idx)) {
  61                         res->start = 0;
  62                         res->end = 0;
  63                         res->flags = 0;
  64                 }
  65                 tmp = list;
  66                 list = list->next;
  67                 kfree(tmp);
  68         }
  69 }
  70
  71 void pci_setup_cardbus(struct pci_bus *bus)
  72 {
  73         struct pci_dev *bridge = bus->self;
  74         struct resource *res;
  75         struct pci_bus_region region;
  76
  77         dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
  78                  bus->secondary, bus->subordinate);
  79
  80         res = bus->resource[0];
  81         pcibios_resource_to_bus(bridge, &region, res);
  82         if (res->flags & IORESOURCE_IO) {
  83                 /*
  84                  * The IO resource is allocated a range twice as large as it
  85                  * would normally need.  This allows us to set both IO regs.
  86                  */
  87                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
  88                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
  89                                         region.start);
  90                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
  91                                         region.end);
  92         }
  93
  94         res = bus->resource[1];
  95         pcibios_resource_to_bus(bridge, &region, res);
  96         if (res->flags & IORESOURCE_IO) {
  97                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
  98                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
  99                                         region.start);
 100                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 101                                         region.end);
 102         }
 103
 104         res = bus->resource[2];
 105         pcibios_resource_to_bus(bridge, &region, res);
 106         if (res->flags & IORESOURCE_MEM) {
 107                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
 108                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 109                                         region.start);
 110                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 111                                         region.end);
 112         }
 113
 114         res = bus->resource[3];
 115         pcibios_resource_to_bus(bridge, &region, res);
 116         if (res->flags & IORESOURCE_MEM) {
 117                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
 118                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 119                                         region.start);
 120                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 121                                         region.end);
 122         }
 123 }
 124 EXPORT_SYMBOL(pci_setup_cardbus);
 125
 126 /* Initialize bridges with base/limit values we have collected.
 127    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
 128    requires that if there is no I/O ports or memory behind the
 129    bridge, corresponding range must be turned off by writing base
 130    value greater than limit to the bridge's base/limit registers.
 131
 132    Note: care must be taken when updating I/O base/limit registers
 133    of bridges which support 32-bit I/O. This update requires two
 134    config space writes, so it's quite possible that an I/O window of
 135    the bridge will have some undesirable address (e.g. 0) after the
 136    first write. Ditto 64-bit prefetchable MMIO.  */
 137 static void pci_setup_bridge(struct pci_bus *bus)
 138 {
 139         struct pci_dev *bridge = bus->self;
 140         struct resource *res;
 141         struct pci_bus_region region;
 142         u32 l, bu, lu, io_upper16;
 143
 144         if (pci_is_enabled(bridge))
 145                 return;
 146
 147         dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
 148                  bus->secondary, bus->subordinate);
 149
 150         /* Set up the top and bottom of the PCI I/O segment for this bus. */
 151         res = bus->resource[0];
 152         pcibios_resource_to_bus(bridge, &region, res);
 153         if (res->flags & IORESOURCE_IO) {
 154                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
 155                 l &= 0xffff0000;
 156                 l |= (region.start >> 8) & 0x00f0;
 157                 l |= region.end & 0xf000;
 158                 /* Set up upper 16 bits of I/O base/limit. */
 159                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 160                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
 161         }
 162         else {
 163                 /* Clear upper 16 bits of I/O base/limit. */
 164                 io_upper16 = 0;
 165                 l = 0x00f0;
 166                 dev_info(&bridge->dev, "  bridge window [io  disabled]\n");
 167         }
 168         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 169         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 170         /* Update lower 16 bits of I/O base/limit. */
 171         pci_write_config_dword(bridge, PCI_IO_BASE, l);
 172         /* Update upper 16 bits of I/O base/limit. */
 173         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 174
 175         /* Set up the top and bottom of the PCI Memory segment
 176            for this bus. */
 177         res = bus->resource[1];
 178         pcibios_resource_to_bus(bridge, &region, res);
 179         if (res->flags & IORESOURCE_MEM) {
 180                 l = (region.start >> 16) & 0xfff0;
 181                 l |= region.end & 0xfff00000;
 182                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
 183         }
 184         else {
 185                 l = 0x0000fff0;
 186                 dev_info(&bridge->dev, "  bridge window [mem disabled]\n");
 187         }
 188         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 189
 190         /* Clear out the upper 32 bits of PREF limit.
 191            If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
 192            disables PREF range, which is ok. */
 193         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 194
 195         /* Set up PREF base/limit. */
 196         bu = lu = 0;
 197         res = bus->resource[2];
 198         pcibios_resource_to_bus(bridge, &region, res);
 199         if (res->flags & IORESOURCE_PREFETCH) {
 200                 l = (region.start >> 16) & 0xfff0;
 201                 l |= region.end & 0xfff00000;
 202                 if (res->flags & IORESOURCE_MEM_64) {
 203                         bu = upper_32_bits(region.start);
 204                         lu = upper_32_bits(region.end);
 205                 }
 206                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
 207         }
 208         else {
 209                 l = 0x0000fff0;
 210                 dev_info(&bridge->dev, "  bridge window [mem pref disabled]\n");
 211         }
 212         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 213
 214         /* Set the upper 32 bits of PREF base & limit. */
 215         pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
 216         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
 217
 218         pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 219 }
 220
 221 /* Check whether the bridge supports optional I/O and
 222    prefetchable memory ranges. If not, the respective
 223    base/limit registers must be read-only and read as 0. */
 224 static void pci_bridge_check_ranges(struct pci_bus *bus)
 225 {
 226         u16 io;
 227         u32 pmem;
 228         struct pci_dev *bridge = bus->self;
 229         struct resource *b_res;
 230
 231         b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 232         b_res[1].flags |= IORESOURCE_MEM;
 233
 234         pci_read_config_word(bridge, PCI_IO_BASE, &io);
 235         if (!io) {
 236                 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
 237                 pci_read_config_word(bridge, PCI_IO_BASE, &io);
 238                 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 239         }
 240         if (io)
 241                 b_res[0].flags |= IORESOURCE_IO;
 242         /*  DECchip 21050 pass 2 errata: the bridge may miss an address
 243             disconnect boundary by one PCI data phase.
 244             Workaround: do not use prefetching on this device. */
 245         if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 246                 return;
 247         pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 248         if (!pmem) {
 249                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
 250                                                0xfff0fff0);
 251                 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 252                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 253         }
 254         if (pmem) {
 255                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 256                 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64)
 257                         b_res[2].flags |= IORESOURCE_MEM_64;
 258         }
 259
 260         /* double check if bridge does support 64 bit pref */
 261         if (b_res[2].flags & IORESOURCE_MEM_64) {
 262                 u32 mem_base_hi, tmp;
 263                 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 264                                          &mem_base_hi);
 265                 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 266                                                0xffffffff);
 267                 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
 268                 if (!tmp)
 269                         b_res[2].flags &= ~IORESOURCE_MEM_64;
 270                 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 271                                        mem_base_hi);
 272         }
 273 }
 274
 275 /* Helper function for sizing routines: find first available
 276    bus resource of a given type. Note: we intentionally skip
 277    the bus resources which have already been assigned (that is,
 278    have non-NULL parent resource). */
 279 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
 280 {
 281         int i;
 282         struct resource *r;
 283         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
 284                                   IORESOURCE_PREFETCH;
 285
 286         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
 287                 r = bus->resource[i];
 288                 if (r == &ioport_resource || r == &iomem_resource)
 289                         continue;
 290                 if (r && (r->flags & type_mask) == type && !r->parent)
 291                         return r;
 292         }
 293         return NULL;
 294 }
 295
 296 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
 297    since these windows have 4K granularity and the IO ranges
 298    of non-bridge PCI devices are limited to 256 bytes.
 299    We must be careful with the ISA aliasing though. */
 300 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
 301 {
 302         struct pci_dev *dev;
 303         struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
 304         unsigned long size = 0, size1 = 0;
 305
 306         if (!b_res)
 307                 return;
 308
 309         list_for_each_entry(dev, &bus->devices, bus_list) {
 310                 int i;
 311
 312                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 313                         struct resource *r = &dev->resource[i];
 314                         unsigned long r_size;
 315
 316                         if (r->parent || !(r->flags & IORESOURCE_IO))
 317                                 continue;
 318                         r_size = resource_size(r);
 319
 320                         if (r_size < 0x400)
 321                                 /* Might be re-aligned for ISA */
 322                                 size += r_size;
 323                         else
 324                                 size1 += r_size;
 325                 }
 326         }
 327         if (size < min_size)
 328                 size = min_size;
 329 /* To be fixed in 2.5: we should have sort of HAVE_ISA
 330    flag in the struct pci_bus. */
 331 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 332         size = (size & 0xff) + ((size & ~0xffUL) << 2);
 333 #endif
 334         size = ALIGN(size + size1, 4096);
 335         if (!size) {
 336                 if (b_res->start || b_res->end)
 337                         dev_info(&bus->self->dev, "disabling bridge window "
 338                                  "%pR to [bus %02x-%02x] (unused)\n", b_res,
 339                                  bus->secondary, bus->subordinate);
 340                 b_res->flags = 0;
 341                 return;
 342         }
 343         /* Alignment of the IO window is always 4K */
 344         b_res->start = 4096;
 345         b_res->end = b_res->start + size - 1;
 346         b_res->flags |= IORESOURCE_STARTALIGN;
 347 }
 348
 349 /* Calculate the size of the bus and minimal alignment which
 350    guarantees that all child resources fit in this size. */
 351 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
 352                          unsigned long type, resource_size_t min_size)
 353 {
 354         struct pci_dev *dev;
 355         resource_size_t min_align, align, size;
 356         resource_size_t aligns[12];     /* Alignments from 1Mb to 2Gb */
 357         int order, max_order;
 358         struct resource *b_res = find_free_bus_resource(bus, type);
 359         unsigned int mem64_mask = 0;
 360
 361         if (!b_res)
 362                 return 0;
 363
 364         memset(aligns, 0, sizeof(aligns));
 365         max_order = 0;
 366         size = 0;
 367
 368         mem64_mask = b_res->flags & IORESOURCE_MEM_64;
 369         b_res->flags &= ~IORESOURCE_MEM_64;
 370
 371         list_for_each_entry(dev, &bus->devices, bus_list) {
 372                 int i;
 373
 374                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 375                         struct resource *r = &dev->resource[i];
 376                         resource_size_t r_size;
 377
 378                         if (r->parent || (r->flags & mask) != type)
 379                                 continue;
 380                         r_size = resource_size(r);
 381                         /* For bridges size != alignment */
 382                         align = pci_resource_alignment(dev, r);
 383                         order = __ffs(align) - 20;
 384                         if (order > 11) {
 385                                 dev_warn(&dev->dev, "disabling BAR %d: %pR "
 386                                          "(bad alignment %#llx)\n", i, r,
 387                                          (unsigned long long) align);
 388                                 r->flags = 0;
 389                                 continue;
 390                         }
 391                         size += r_size;
 392                         if (order < 0)
 393                                 order = 0;
 394                         /* Exclude ranges with size > align from
 395                            calculation of the alignment. */
 396                         if (r_size == align)
 397                                 aligns[order] += align;
 398                         if (order > max_order)
 399                                 max_order = order;
 400                         mem64_mask &= r->flags & IORESOURCE_MEM_64;
 401                 }
 402         }
 403         if (size < min_size)
 404                 size = min_size;
 405
 406         align = 0;
 407         min_align = 0;
 408         for (order = 0; order <= max_order; order++) {
 409                 resource_size_t align1 = 1;
 410
 411                 align1 <<= (order + 20);
 412
 413                 if (!align)
 414                         min_align = align1;
 415                 else if (ALIGN(align + min_align, min_align) < align1)
 416                         min_align = align1 >> 1;
 417                 align += aligns[order];
 418         }
 419         size = ALIGN(size, min_align);
 420         if (!size) {
 421                 if (b_res->start || b_res->end)
 422                         dev_info(&bus->self->dev, "disabling bridge window "
 423                                  "%pR to [bus %02x-%02x] (unused)\n", b_res,
 424                                  bus->secondary, bus->subordinate);
 425                 b_res->flags = 0;
 426                 return 1;
 427         }
 428         b_res->start = min_align;
 429         b_res->end = size + min_align - 1;
 430         b_res->flags |= IORESOURCE_STARTALIGN;
 431         b_res->flags |= mem64_mask;
 432         return 1;
 433 }
 434
 435 static void pci_bus_size_cardbus(struct pci_bus *bus)
 436 {
 437         struct pci_dev *bridge = bus->self;
 438         struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 439         u16 ctrl;
 440
 441         /*
 442          * Reserve some resources for CardBus.  We reserve
 443          * a fixed amount of bus space for CardBus bridges.
 444          */
 445         b_res[0].start = 0;
 446         b_res[0].end = pci_cardbus_io_size - 1;
 447         b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
 448
 449         b_res[1].start = 0;
 450         b_res[1].end = pci_cardbus_io_size - 1;
 451         b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
 452
 453         /*
 454          * Check whether prefetchable memory is supported
 455          * by this bridge.
 456          */
 457         pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 458         if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
 459                 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 460                 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
 461                 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
 462         }
 463
 464         /*
 465          * If we have prefetchable memory support, allocate
 466          * two regions.  Otherwise, allocate one region of
 467          * twice the size.
 468          */
 469         if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
 470                 b_res[2].start = 0;
 471                 b_res[2].end = pci_cardbus_mem_size - 1;
 472                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
 473
 474                 b_res[3].start = 0;
 475                 b_res[3].end = pci_cardbus_mem_size - 1;
 476                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
 477         } else {
 478                 b_res[3].start = 0;
 479                 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
 480                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
 481         }
 482 }
 483
 484 void __ref pci_bus_size_bridges(struct pci_bus *bus)
 485 {
 486         struct pci_dev *dev;
 487         unsigned long mask, prefmask;
 488         resource_size_t min_mem_size = 0, min_io_size = 0;
 489
 490         list_for_each_entry(dev, &bus->devices, bus_list) {
 491                 struct pci_bus *b = dev->subordinate;
 492                 if (!b)
 493                         continue;
 494
 495                 switch (dev->class >> 8) {
 496                 case PCI_CLASS_BRIDGE_CARDBUS:
 497                         pci_bus_size_cardbus(b);
 498                         break;
 499
 500                 case PCI_CLASS_BRIDGE_PCI:
 501                 default:
 502                         pci_bus_size_bridges(b);
 503                         break;
 504                 }
 505         }
 506
 507         /* The root bus? */
 508         if (!bus->self)
 509                 return;
 510
 511         switch (bus->self->class >> 8) {
 512         case PCI_CLASS_BRIDGE_CARDBUS:
 513                 /* don't size cardbuses yet. */
 514                 break;
 515
 516         case PCI_CLASS_BRIDGE_PCI:
 517                 pci_bridge_check_ranges(bus);
 518                 if (bus->self->is_hotplug_bridge) {
 519                         min_io_size  = pci_hotplug_io_size;
 520                         min_mem_size = pci_hotplug_mem_size;
 521                 }
 522         default:
 523                 pbus_size_io(bus, min_io_size);
 524                 /* If the bridge supports prefetchable range, size it
 525                    separately. If it doesn't, or its prefetchable window
 526                    has already been allocated by arch code, try
 527                    non-prefetchable range for both types of PCI memory
 528                    resources. */
 529                 mask = IORESOURCE_MEM;
 530                 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
 531                 if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
 532                         mask = prefmask; /* Success, size non-prefetch only. */
 533                 else
 534                         min_mem_size += min_mem_size;
 535                 pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
 536                 break;
 537         }
 538 }
 539 EXPORT_SYMBOL(pci_bus_size_bridges);
 540
 541 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
 542 {
 543         struct pci_bus *b;
 544         struct pci_dev *dev;
 545
 546         pbus_assign_resources_sorted(bus);
 547
 548         list_for_each_entry(dev, &bus->devices, bus_list) {
 549                 b = dev->subordinate;
 550                 if (!b)
 551                         continue;
 552
 553                 pci_bus_assign_resources(b);
 554
 555                 switch (dev->class >> 8) {
 556                 case PCI_CLASS_BRIDGE_PCI:
 557                         pci_setup_bridge(b);
 558                         break;
 559
 560                 case PCI_CLASS_BRIDGE_CARDBUS:
 561                         pci_setup_cardbus(b);
 562                         break;
 563
 564                 default:
 565                         dev_info(&dev->dev, "not setting up bridge for bus "
 566                                  "%04x:%02x\n", pci_domain_nr(b), b->number);
 567                         break;
 568                 }
 569         }
 570 }
 571 EXPORT_SYMBOL(pci_bus_assign_resources);
 572
 573 static void pci_bus_dump_res(struct pci_bus *bus)
 574 {
 575         int i;
 576
 577         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
 578                 struct resource *res = bus->resource[i];
 579                 if (!res || !res->end)
 580                         continue;
 581
 582                 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
 583         }
 584 }
 585
 586 static void pci_bus_dump_resources(struct pci_bus *bus)
 587 {
 588         struct pci_bus *b;
 589         struct pci_dev *dev;
 590
 591
 592         pci_bus_dump_res(bus);
 593
 594         list_for_each_entry(dev, &bus->devices, bus_list) {
 595                 b = dev->subordinate;
 596                 if (!b)
 597                         continue;
 598
 599                 pci_bus_dump_resources(b);
 600         }
 601 }
 602
 603 void __init
 604 pci_assign_unassigned_resources(void)
 605 {
 606         struct pci_bus *bus;
 607
 608         /* Depth first, calculate sizes and alignments of all
 609            subordinate buses. */
 610         list_for_each_entry(bus, &pci_root_buses, node) {
 611                 pci_bus_size_bridges(bus);
 612         }
 613         /* Depth last, allocate resources and update the hardware. */
 614         list_for_each_entry(bus, &pci_root_buses, node) {
 615                 pci_bus_assign_resources(bus);
 616                 pci_enable_bridges(bus);
 617         }
 618
 619         /* dump the resource on buses */
 620         list_for_each_entry(bus, &pci_root_buses, node) {
 621                 pci_bus_dump_resources(bus);
 622         }
 623 }