drivers/dma/shdma.h

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   5  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   6  *
   7  * This is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13 #ifndef __DMA_SHDMA_H
  14 #define __DMA_SHDMA_H
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/list.h>
  19
  20 #define SH_DMA_TCR_MAX 0x00FFFFFF       /* 16MB */
  21
  22 struct sh_dmae_regs {
  23         u32 sar; /* SAR / source address */
  24         u32 dar; /* DAR / destination address */
  25         u32 tcr; /* TCR / transfer count */
  26 };
  27
  28 struct sh_desc {
  29         struct sh_dmae_regs hw;
  30         struct list_head node;
  31         struct dma_async_tx_descriptor async_tx;
  32         dma_cookie_t cookie;
  33         int chunks;
  34         int mark;
  35 };
  36
  37 struct device;
  38
  39 struct sh_dmae_chan {
  40         dma_cookie_t completed_cookie;  /* The maximum cookie completed */
  41         spinlock_t desc_lock;           /* Descriptor operation lock */
  42         struct list_head ld_queue;      /* Link descriptors queue */
  43         struct list_head ld_free;       /* Link descriptors free */
  44         struct dma_chan common;         /* DMA common channel */
  45         struct device *dev;             /* Channel device */
  46         struct tasklet_struct tasklet;  /* Tasklet */
  47         int descs_allocated;            /* desc count */
  48         int id;                         /* Raw id of this channel */
  49         char dev_id[16];                /* unique name per DMAC of channel */
  50
  51         /* Set chcr */
  52         int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs);
  53         /* Set DMA resource */
  54         int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res);
  55 };
  56
  57 struct sh_dmae_device {
  58         struct dma_device common;
  59         struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
  60         struct sh_dmae_pdata pdata;
  61 };
  62
  63 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
  64 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
  65 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
  66
  67 #endif  /* __DMA_SHDMA_H */