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x86/amd-iommu: Add extended feature detection
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / amd_iommu_init.c
blob047905dc3e14e2f995a96e9035aac70a638d4a3d
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 /*
36 * definitions for the ACPI scanning code
37 */
38 #define IVRS_HEADER_LENGTH 48
39
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
44
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
53
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
58
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
61
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70
71 /*
72 * ACPI table definitions
73 *
74 * These data structures are laid over the table to parse the important values
75 * out of it.
76 */
77
78 /*
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
81 */
82 struct ivhd_header {
83 u8 type;
84 u8 flags;
85 u16 length;
86 u16 devid;
87 u16 cap_ptr;
88 u64 mmio_phys;
89 u16 pci_seg;
90 u16 info;
91 u32 reserved;
92 } __attribute__((packed));
93
94 /*
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
97 */
98 struct ivhd_entry {
99 u8 type;
100 u16 devid;
101 u8 flags;
102 u32 ext;
103 } __attribute__((packed));
104
105 /*
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
108 */
109 struct ivmd_header {
110 u8 type;
111 u8 flags;
112 u16 length;
113 u16 devid;
114 u16 aux;
115 u64 resv;
116 u64 range_start;
117 u64 range_length;
118 } __attribute__((packed));
119
120 bool amd_iommu_dump;
121
122 static int __initdata amd_iommu_detected;
123 static bool __initdata amd_iommu_disabled;
124
125 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 to handle */
127 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 we find in ACPI */
129 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130
131 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
132 system */
133
134 /* Array to assign indices to IOMMUs*/
135 struct amd_iommu *amd_iommus[MAX_IOMMUS];
136 int amd_iommus_present;
137
138 /* IOMMUs have a non-present cache? */
139 bool amd_iommu_np_cache __read_mostly;
140
141 /*
142 * The ACPI table parsing functions set this variable on an error
143 */
144 static int __initdata amd_iommu_init_err;
145
146 /*
147 * List of protection domains - used during resume
148 */
149 LIST_HEAD(amd_iommu_pd_list);
150 spinlock_t amd_iommu_pd_lock;
151
152 /*
153 * Pointer to the device table which is shared by all AMD IOMMUs
154 * it is indexed by the PCI device id or the HT unit id and contains
155 * information about the domain the device belongs to as well as the
156 * page table root pointer.
157 */
158 struct dev_table_entry *amd_iommu_dev_table;
159
160 /*
161 * The alias table is a driver specific data structure which contains the
162 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
163 * More than one device can share the same requestor id.
164 */
165 u16 *amd_iommu_alias_table;
166
167 /*
168 * The rlookup table is used to find the IOMMU which is responsible
169 * for a specific device. It is also indexed by the PCI device id.
170 */
171 struct amd_iommu **amd_iommu_rlookup_table;
172
173 /*
174 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
175 * to know which ones are already in use.
176 */
177 unsigned long *amd_iommu_pd_alloc_bitmap;
178
179 static u32 dev_table_size; /* size of the device table */
180 static u32 alias_table_size; /* size of the alias table */
181 static u32 rlookup_table_size; /* size if the rlookup table */
182
183 /*
184 * This function flushes all internal caches of
185 * the IOMMU used by this driver.
186 */
187 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
188
189 static inline void update_last_devid(u16 devid)
190 {
191 if (devid > amd_iommu_last_bdf)
192 amd_iommu_last_bdf = devid;
193 }
194
195 static inline unsigned long tbl_size(int entry_size)
196 {
197 unsigned shift = PAGE_SHIFT +
198 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
199
200 return 1UL << shift;
201 }
202
203 /* Access to l1 and l2 indexed register spaces */
204
205 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
206 {
207 u32 val;
208
209 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
210 pci_read_config_dword(iommu->dev, 0xfc, &val);
211 return val;
212 }
213
214 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
215 {
216 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
217 pci_write_config_dword(iommu->dev, 0xfc, val);
218 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
219 }
220
221 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
222 {
223 u32 val;
224
225 pci_write_config_dword(iommu->dev, 0xf0, address);
226 pci_read_config_dword(iommu->dev, 0xf4, &val);
227 return val;
228 }
229
230 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
231 {
232 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
233 pci_write_config_dword(iommu->dev, 0xf4, val);
234 }
235
236 /****************************************************************************
237 *
238 * AMD IOMMU MMIO register space handling functions
239 *
240 * These functions are used to program the IOMMU device registers in
241 * MMIO space required for that driver.
242 *
243 ****************************************************************************/
244
245 /*
246 * This function set the exclusion range in the IOMMU. DMA accesses to the
247 * exclusion range are passed through untranslated
248 */
249 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
250 {
251 u64 start = iommu->exclusion_start & PAGE_MASK;
252 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
253 u64 entry;
254
255 if (!iommu->exclusion_start)
256 return;
257
258 entry = start | MMIO_EXCL_ENABLE_MASK;
259 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
260 &entry, sizeof(entry));
261
262 entry = limit;
263 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
264 &entry, sizeof(entry));
265 }
266
267 /* Programs the physical address of the device table into the IOMMU hardware */
268 static void __init iommu_set_device_table(struct amd_iommu *iommu)
269 {
270 u64 entry;
271
272 BUG_ON(iommu->mmio_base == NULL);
273
274 entry = virt_to_phys(amd_iommu_dev_table);
275 entry |= (dev_table_size >> 12) - 1;
276 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
277 &entry, sizeof(entry));
278 }
279
280 /* Generic functions to enable/disable certain features of the IOMMU. */
281 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
282 {
283 u32 ctrl;
284
285 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
286 ctrl |= (1 << bit);
287 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
288 }
289
290 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
291 {
292 u32 ctrl;
293
294 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
295 ctrl &= ~(1 << bit);
296 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
297 }
298
299 /* Function to enable the hardware */
300 static void iommu_enable(struct amd_iommu *iommu)
301 {
302 static const char * const feat_str[] = {
303 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
304 "IA", "GA", "HE", "PC", NULL
305 };
306 int i;
307
308 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
309 dev_name(&iommu->dev->dev), iommu->cap_ptr);
310
311 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
312 printk(KERN_CONT " extended features: ");
313 for (i = 0; feat_str[i]; ++i)
314 if (iommu_feature(iommu, (1ULL << i)))
315 printk(KERN_CONT " %s", feat_str[i]);
316 }
317 printk(KERN_CONT "\n");
318
319 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
320 }
321
322 static void iommu_disable(struct amd_iommu *iommu)
323 {
324 /* Disable command buffer */
325 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
326
327 /* Disable event logging and event interrupts */
328 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
329 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
330
331 /* Disable IOMMU hardware itself */
332 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
333 }
334
335 /*
336 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
337 * the system has one.
338 */
339 static u8 * __init iommu_map_mmio_space(u64 address)
340 {
341 u8 *ret;
342
343 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
344 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
345 address);
346 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
347 return NULL;
348 }
349
350 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
351 if (ret != NULL)
352 return ret;
353
354 release_mem_region(address, MMIO_REGION_LENGTH);
355
356 return NULL;
357 }
358
359 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
360 {
361 if (iommu->mmio_base)
362 iounmap(iommu->mmio_base);
363 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
364 }
365
366 /****************************************************************************
367 *
368 * The functions below belong to the first pass of AMD IOMMU ACPI table
369 * parsing. In this pass we try to find out the highest device id this
370 * code has to handle. Upon this information the size of the shared data
371 * structures is determined later.
372 *
373 ****************************************************************************/
374
375 /*
376 * This function calculates the length of a given IVHD entry
377 */
378 static inline int ivhd_entry_length(u8 *ivhd)
379 {
380 return 0x04 << (*ivhd >> 6);
381 }
382
383 /*
384 * This function reads the last device id the IOMMU has to handle from the PCI
385 * capability header for this IOMMU
386 */
387 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
388 {
389 u32 cap;
390
391 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
392 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
393
394 return 0;
395 }
396
397 /*
398 * After reading the highest device id from the IOMMU PCI capability header
399 * this function looks if there is a higher device id defined in the ACPI table
400 */
401 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
402 {
403 u8 *p = (void *)h, *end = (void *)h;
404 struct ivhd_entry *dev;
405
406 p += sizeof(*h);
407 end += h->length;
408
409 find_last_devid_on_pci(PCI_BUS(h->devid),
410 PCI_SLOT(h->devid),
411 PCI_FUNC(h->devid),
412 h->cap_ptr);
413
414 while (p < end) {
415 dev = (struct ivhd_entry *)p;
416 switch (dev->type) {
417 case IVHD_DEV_SELECT:
418 case IVHD_DEV_RANGE_END:
419 case IVHD_DEV_ALIAS:
420 case IVHD_DEV_EXT_SELECT:
421 /* all the above subfield types refer to device ids */
422 update_last_devid(dev->devid);
423 break;
424 default:
425 break;
426 }
427 p += ivhd_entry_length(p);
428 }
429
430 WARN_ON(p != end);
431
432 return 0;
433 }
434
435 /*
436 * Iterate over all IVHD entries in the ACPI table and find the highest device
437 * id which we need to handle. This is the first of three functions which parse
438 * the ACPI table. So we check the checksum here.
439 */
440 static int __init find_last_devid_acpi(struct acpi_table_header *table)
441 {
442 int i;
443 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
444 struct ivhd_header *h;
445
446 /*
447 * Validate checksum here so we don't need to do it when
448 * we actually parse the table
449 */
450 for (i = 0; i < table->length; ++i)
451 checksum += p[i];
452 if (checksum != 0) {
453 /* ACPI table corrupt */
454 amd_iommu_init_err = -ENODEV;
455 return 0;
456 }
457
458 p += IVRS_HEADER_LENGTH;
459
460 end += table->length;
461 while (p < end) {
462 h = (struct ivhd_header *)p;
463 switch (h->type) {
464 case ACPI_IVHD_TYPE:
465 find_last_devid_from_ivhd(h);
466 break;
467 default:
468 break;
469 }
470 p += h->length;
471 }
472 WARN_ON(p != end);
473
474 return 0;
475 }
476
477 /****************************************************************************
478 *
479 * The following functions belong the the code path which parses the ACPI table
480 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
481 * data structures, initialize the device/alias/rlookup table and also
482 * basically initialize the hardware.
483 *
484 ****************************************************************************/
485
486 /*
487 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
488 * write commands to that buffer later and the IOMMU will execute them
489 * asynchronously
490 */
491 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
492 {
493 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
494 get_order(CMD_BUFFER_SIZE));
495
496 if (cmd_buf == NULL)
497 return NULL;
498
499 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
500
501 return cmd_buf;
502 }
503
504 /*
505 * This function resets the command buffer if the IOMMU stopped fetching
506 * commands from it.
507 */
508 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
509 {
510 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
511
512 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
513 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
514
515 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
516 }
517
518 /*
519 * This function writes the command buffer address to the hardware and
520 * enables it.
521 */
522 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
523 {
524 u64 entry;
525
526 BUG_ON(iommu->cmd_buf == NULL);
527
528 entry = (u64)virt_to_phys(iommu->cmd_buf);
529 entry |= MMIO_CMD_SIZE_512;
530
531 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
532 &entry, sizeof(entry));
533
534 amd_iommu_reset_cmd_buffer(iommu);
535 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
536 }
537
538 static void __init free_command_buffer(struct amd_iommu *iommu)
539 {
540 free_pages((unsigned long)iommu->cmd_buf,
541 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
542 }
543
544 /* allocates the memory where the IOMMU will log its events to */
545 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
546 {
547 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
548 get_order(EVT_BUFFER_SIZE));
549
550 if (iommu->evt_buf == NULL)
551 return NULL;
552
553 iommu->evt_buf_size = EVT_BUFFER_SIZE;
554
555 return iommu->evt_buf;
556 }
557
558 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
559 {
560 u64 entry;
561
562 BUG_ON(iommu->evt_buf == NULL);
563
564 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
565
566 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
567 &entry, sizeof(entry));
568
569 /* set head and tail to zero manually */
570 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
571 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
572
573 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
574 }
575
576 static void __init free_event_buffer(struct amd_iommu *iommu)
577 {
578 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
579 }
580
581 /* sets a specific bit in the device table entry. */
582 static void set_dev_entry_bit(u16 devid, u8 bit)
583 {
584 int i = (bit >> 5) & 0x07;
585 int _bit = bit & 0x1f;
586
587 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
588 }
589
590 static int get_dev_entry_bit(u16 devid, u8 bit)
591 {
592 int i = (bit >> 5) & 0x07;
593 int _bit = bit & 0x1f;
594
595 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
596 }
597
598
599 void amd_iommu_apply_erratum_63(u16 devid)
600 {
601 int sysmgt;
602
603 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
604 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
605
606 if (sysmgt == 0x01)
607 set_dev_entry_bit(devid, DEV_ENTRY_IW);
608 }
609
610 /* Writes the specific IOMMU for a device into the rlookup table */
611 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
612 {
613 amd_iommu_rlookup_table[devid] = iommu;
614 }
615
616 /*
617 * This function takes the device specific flags read from the ACPI
618 * table and sets up the device table entry with that information
619 */
620 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
621 u16 devid, u32 flags, u32 ext_flags)
622 {
623 if (flags & ACPI_DEVFLAG_INITPASS)
624 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
625 if (flags & ACPI_DEVFLAG_EXTINT)
626 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
627 if (flags & ACPI_DEVFLAG_NMI)
628 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
629 if (flags & ACPI_DEVFLAG_SYSMGT1)
630 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
631 if (flags & ACPI_DEVFLAG_SYSMGT2)
632 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
633 if (flags & ACPI_DEVFLAG_LINT0)
634 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
635 if (flags & ACPI_DEVFLAG_LINT1)
636 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
637
638 amd_iommu_apply_erratum_63(devid);
639
640 set_iommu_for_device(iommu, devid);
641 }
642
643 /*
644 * Reads the device exclusion range from ACPI and initialize IOMMU with
645 * it
646 */
647 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
648 {
649 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
650
651 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
652 return;
653
654 if (iommu) {
655 /*
656 * We only can configure exclusion ranges per IOMMU, not
657 * per device. But we can enable the exclusion range per
658 * device. This is done here
659 */
660 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
661 iommu->exclusion_start = m->range_start;
662 iommu->exclusion_length = m->range_length;
663 }
664 }
665
666 /*
667 * This function reads some important data from the IOMMU PCI space and
668 * initializes the driver data structure with it. It reads the hardware
669 * capabilities and the first/last device entries
670 */
671 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
672 {
673 int cap_ptr = iommu->cap_ptr;
674 u32 range, misc, low, high;
675 int i, j;
676
677 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
678 &iommu->cap);
679 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
680 &range);
681 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
682 &misc);
683
684 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
685 MMIO_GET_FD(range));
686 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
687 MMIO_GET_LD(range));
688 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
689
690 /* read extended feature bits */
691 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
692 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
693
694 iommu->features = ((u64)high << 32) | low;
695
696 if (!is_rd890_iommu(iommu->dev))
697 return;
698
699 /*
700 * Some rd890 systems may not be fully reconfigured by the BIOS, so
701 * it's necessary for us to store this information so it can be
702 * reprogrammed on resume
703 */
704
705 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
706 &iommu->stored_addr_lo);
707 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
708 &iommu->stored_addr_hi);
709
710 /* Low bit locks writes to configuration space */
711 iommu->stored_addr_lo &= ~1;
712
713 for (i = 0; i < 6; i++)
714 for (j = 0; j < 0x12; j++)
715 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
716
717 for (i = 0; i < 0x83; i++)
718 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
719 }
720
721 /*
722 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
723 * initializes the hardware and our data structures with it.
724 */
725 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
726 struct ivhd_header *h)
727 {
728 u8 *p = (u8 *)h;
729 u8 *end = p, flags = 0;
730 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
731 u32 ext_flags = 0;
732 bool alias = false;
733 struct ivhd_entry *e;
734
735 /*
736 * First save the recommended feature enable bits from ACPI
737 */
738 iommu->acpi_flags = h->flags;
739
740 /*
741 * Done. Now parse the device entries
742 */
743 p += sizeof(struct ivhd_header);
744 end += h->length;
745
746
747 while (p < end) {
748 e = (struct ivhd_entry *)p;
749 switch (e->type) {
750 case IVHD_DEV_ALL:
751
752 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
753 " last device %02x:%02x.%x flags: %02x\n",
754 PCI_BUS(iommu->first_device),
755 PCI_SLOT(iommu->first_device),
756 PCI_FUNC(iommu->first_device),
757 PCI_BUS(iommu->last_device),
758 PCI_SLOT(iommu->last_device),
759 PCI_FUNC(iommu->last_device),
760 e->flags);
761
762 for (dev_i = iommu->first_device;
763 dev_i <= iommu->last_device; ++dev_i)
764 set_dev_entry_from_acpi(iommu, dev_i,
765 e->flags, 0);
766 break;
767 case IVHD_DEV_SELECT:
768
769 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
770 "flags: %02x\n",
771 PCI_BUS(e->devid),
772 PCI_SLOT(e->devid),
773 PCI_FUNC(e->devid),
774 e->flags);
775
776 devid = e->devid;
777 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
778 break;
779 case IVHD_DEV_SELECT_RANGE_START:
780
781 DUMP_printk(" DEV_SELECT_RANGE_START\t "
782 "devid: %02x:%02x.%x flags: %02x\n",
783 PCI_BUS(e->devid),
784 PCI_SLOT(e->devid),
785 PCI_FUNC(e->devid),
786 e->flags);
787
788 devid_start = e->devid;
789 flags = e->flags;
790 ext_flags = 0;
791 alias = false;
792 break;
793 case IVHD_DEV_ALIAS:
794
795 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
796 "flags: %02x devid_to: %02x:%02x.%x\n",
797 PCI_BUS(e->devid),
798 PCI_SLOT(e->devid),
799 PCI_FUNC(e->devid),
800 e->flags,
801 PCI_BUS(e->ext >> 8),
802 PCI_SLOT(e->ext >> 8),
803 PCI_FUNC(e->ext >> 8));
804
805 devid = e->devid;
806 devid_to = e->ext >> 8;
807 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
808 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
809 amd_iommu_alias_table[devid] = devid_to;
810 break;
811 case IVHD_DEV_ALIAS_RANGE:
812
813 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
814 "devid: %02x:%02x.%x flags: %02x "
815 "devid_to: %02x:%02x.%x\n",
816 PCI_BUS(e->devid),
817 PCI_SLOT(e->devid),
818 PCI_FUNC(e->devid),
819 e->flags,
820 PCI_BUS(e->ext >> 8),
821 PCI_SLOT(e->ext >> 8),
822 PCI_FUNC(e->ext >> 8));
823
824 devid_start = e->devid;
825 flags = e->flags;
826 devid_to = e->ext >> 8;
827 ext_flags = 0;
828 alias = true;
829 break;
830 case IVHD_DEV_EXT_SELECT:
831
832 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
833 "flags: %02x ext: %08x\n",
834 PCI_BUS(e->devid),
835 PCI_SLOT(e->devid),
836 PCI_FUNC(e->devid),
837 e->flags, e->ext);
838
839 devid = e->devid;
840 set_dev_entry_from_acpi(iommu, devid, e->flags,
841 e->ext);
842 break;
843 case IVHD_DEV_EXT_SELECT_RANGE:
844
845 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
846 "%02x:%02x.%x flags: %02x ext: %08x\n",
847 PCI_BUS(e->devid),
848 PCI_SLOT(e->devid),
849 PCI_FUNC(e->devid),
850 e->flags, e->ext);
851
852 devid_start = e->devid;
853 flags = e->flags;
854 ext_flags = e->ext;
855 alias = false;
856 break;
857 case IVHD_DEV_RANGE_END:
858
859 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
860 PCI_BUS(e->devid),
861 PCI_SLOT(e->devid),
862 PCI_FUNC(e->devid));
863
864 devid = e->devid;
865 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
866 if (alias) {
867 amd_iommu_alias_table[dev_i] = devid_to;
868 set_dev_entry_from_acpi(iommu,
869 devid_to, flags, ext_flags);
870 }
871 set_dev_entry_from_acpi(iommu, dev_i,
872 flags, ext_flags);
873 }
874 break;
875 default:
876 break;
877 }
878
879 p += ivhd_entry_length(p);
880 }
881 }
882
883 /* Initializes the device->iommu mapping for the driver */
884 static int __init init_iommu_devices(struct amd_iommu *iommu)
885 {
886 u16 i;
887
888 for (i = iommu->first_device; i <= iommu->last_device; ++i)
889 set_iommu_for_device(iommu, i);
890
891 return 0;
892 }
893
894 static void __init free_iommu_one(struct amd_iommu *iommu)
895 {
896 free_command_buffer(iommu);
897 free_event_buffer(iommu);
898 iommu_unmap_mmio_space(iommu);
899 }
900
901 static void __init free_iommu_all(void)
902 {
903 struct amd_iommu *iommu, *next;
904
905 for_each_iommu_safe(iommu, next) {
906 list_del(&iommu->list);
907 free_iommu_one(iommu);
908 kfree(iommu);
909 }
910 }
911
912 /*
913 * This function clues the initialization function for one IOMMU
914 * together and also allocates the command buffer and programs the
915 * hardware. It does NOT enable the IOMMU. This is done afterwards.
916 */
917 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
918 {
919 spin_lock_init(&iommu->lock);
920
921 /* Add IOMMU to internal data structures */
922 list_add_tail(&iommu->list, &amd_iommu_list);
923 iommu->index = amd_iommus_present++;
924
925 if (unlikely(iommu->index >= MAX_IOMMUS)) {
926 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
927 return -ENOSYS;
928 }
929
930 /* Index is fine - add IOMMU to the array */
931 amd_iommus[iommu->index] = iommu;
932
933 /*
934 * Copy data from ACPI table entry to the iommu struct
935 */
936 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
937 if (!iommu->dev)
938 return 1;
939
940 iommu->cap_ptr = h->cap_ptr;
941 iommu->pci_seg = h->pci_seg;
942 iommu->mmio_phys = h->mmio_phys;
943 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
944 if (!iommu->mmio_base)
945 return -ENOMEM;
946
947 iommu->cmd_buf = alloc_command_buffer(iommu);
948 if (!iommu->cmd_buf)
949 return -ENOMEM;
950
951 iommu->evt_buf = alloc_event_buffer(iommu);
952 if (!iommu->evt_buf)
953 return -ENOMEM;
954
955 iommu->int_enabled = false;
956
957 init_iommu_from_pci(iommu);
958 init_iommu_from_acpi(iommu, h);
959 init_iommu_devices(iommu);
960
961 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
962 amd_iommu_np_cache = true;
963
964 return pci_enable_device(iommu->dev);
965 }
966
967 /*
968 * Iterates over all IOMMU entries in the ACPI table, allocates the
969 * IOMMU structure and initializes it with init_iommu_one()
970 */
971 static int __init init_iommu_all(struct acpi_table_header *table)
972 {
973 u8 *p = (u8 *)table, *end = (u8 *)table;
974 struct ivhd_header *h;
975 struct amd_iommu *iommu;
976 int ret;
977
978 end += table->length;
979 p += IVRS_HEADER_LENGTH;
980
981 while (p < end) {
982 h = (struct ivhd_header *)p;
983 switch (*p) {
984 case ACPI_IVHD_TYPE:
985
986 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
987 "seg: %d flags: %01x info %04x\n",
988 PCI_BUS(h->devid), PCI_SLOT(h->devid),
989 PCI_FUNC(h->devid), h->cap_ptr,
990 h->pci_seg, h->flags, h->info);
991 DUMP_printk(" mmio-addr: %016llx\n",
992 h->mmio_phys);
993
994 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
995 if (iommu == NULL) {
996 amd_iommu_init_err = -ENOMEM;
997 return 0;
998 }
999
1000 ret = init_iommu_one(iommu, h);
1001 if (ret) {
1002 amd_iommu_init_err = ret;
1003 return 0;
1004 }
1005 break;
1006 default:
1007 break;
1008 }
1009 p += h->length;
1010
1011 }
1012 WARN_ON(p != end);
1013
1014 return 0;
1015 }
1016
1017 /****************************************************************************
1018 *
1019 * The following functions initialize the MSI interrupts for all IOMMUs
1020 * in the system. Its a bit challenging because there could be multiple
1021 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1022 * pci_dev.
1023 *
1024 ****************************************************************************/
1025
1026 static int iommu_setup_msi(struct amd_iommu *iommu)
1027 {
1028 int r;
1029
1030 if (pci_enable_msi(iommu->dev))
1031 return 1;
1032
1033 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
1034 IRQF_SAMPLE_RANDOM,
1035 "AMD-Vi",
1036 NULL);
1037
1038 if (r) {
1039 pci_disable_msi(iommu->dev);
1040 return 1;
1041 }
1042
1043 iommu->int_enabled = true;
1044 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1045
1046 return 0;
1047 }
1048
1049 static int iommu_init_msi(struct amd_iommu *iommu)
1050 {
1051 if (iommu->int_enabled)
1052 return 0;
1053
1054 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1055 return iommu_setup_msi(iommu);
1056
1057 return 1;
1058 }
1059
1060 /****************************************************************************
1061 *
1062 * The next functions belong to the third pass of parsing the ACPI
1063 * table. In this last pass the memory mapping requirements are
1064 * gathered (like exclusion and unity mapping reanges).
1065 *
1066 ****************************************************************************/
1067
1068 static void __init free_unity_maps(void)
1069 {
1070 struct unity_map_entry *entry, *next;
1071
1072 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1073 list_del(&entry->list);
1074 kfree(entry);
1075 }
1076 }
1077
1078 /* called when we find an exclusion range definition in ACPI */
1079 static int __init init_exclusion_range(struct ivmd_header *m)
1080 {
1081 int i;
1082
1083 switch (m->type) {
1084 case ACPI_IVMD_TYPE:
1085 set_device_exclusion_range(m->devid, m);
1086 break;
1087 case ACPI_IVMD_TYPE_ALL:
1088 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1089 set_device_exclusion_range(i, m);
1090 break;
1091 case ACPI_IVMD_TYPE_RANGE:
1092 for (i = m->devid; i <= m->aux; ++i)
1093 set_device_exclusion_range(i, m);
1094 break;
1095 default:
1096 break;
1097 }
1098
1099 return 0;
1100 }
1101
1102 /* called for unity map ACPI definition */
1103 static int __init init_unity_map_range(struct ivmd_header *m)
1104 {
1105 struct unity_map_entry *e = 0;
1106 char *s;
1107
1108 e = kzalloc(sizeof(*e), GFP_KERNEL);
1109 if (e == NULL)
1110 return -ENOMEM;
1111
1112 switch (m->type) {
1113 default:
1114 kfree(e);
1115 return 0;
1116 case ACPI_IVMD_TYPE:
1117 s = "IVMD_TYPEi\t\t\t";
1118 e->devid_start = e->devid_end = m->devid;
1119 break;
1120 case ACPI_IVMD_TYPE_ALL:
1121 s = "IVMD_TYPE_ALL\t\t";
1122 e->devid_start = 0;
1123 e->devid_end = amd_iommu_last_bdf;
1124 break;
1125 case ACPI_IVMD_TYPE_RANGE:
1126 s = "IVMD_TYPE_RANGE\t\t";
1127 e->devid_start = m->devid;
1128 e->devid_end = m->aux;
1129 break;
1130 }
1131 e->address_start = PAGE_ALIGN(m->range_start);
1132 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1133 e->prot = m->flags >> 1;
1134
1135 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1136 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1137 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1138 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1139 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1140 e->address_start, e->address_end, m->flags);
1141
1142 list_add_tail(&e->list, &amd_iommu_unity_map);
1143
1144 return 0;
1145 }
1146
1147 /* iterates over all memory definitions we find in the ACPI table */
1148 static int __init init_memory_definitions(struct acpi_table_header *table)
1149 {
1150 u8 *p = (u8 *)table, *end = (u8 *)table;
1151 struct ivmd_header *m;
1152
1153 end += table->length;
1154 p += IVRS_HEADER_LENGTH;
1155
1156 while (p < end) {
1157 m = (struct ivmd_header *)p;
1158 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1159 init_exclusion_range(m);
1160 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1161 init_unity_map_range(m);
1162
1163 p += m->length;
1164 }
1165
1166 return 0;
1167 }
1168
1169 /*
1170 * Init the device table to not allow DMA access for devices and
1171 * suppress all page faults
1172 */
1173 static void init_device_table(void)
1174 {
1175 u16 devid;
1176
1177 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1178 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1179 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1180 }
1181 }
1182
1183 static void iommu_init_flags(struct amd_iommu *iommu)
1184 {
1185 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1186 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1187 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1188
1189 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1190 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1191 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1192
1193 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1194 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1195 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1196
1197 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1198 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1199 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1200
1201 /*
1202 * make IOMMU memory accesses cache coherent
1203 */
1204 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1205 }
1206
1207 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1208 {
1209 int i, j;
1210 u32 ioc_feature_control;
1211 struct pci_dev *pdev = NULL;
1212
1213 /* RD890 BIOSes may not have completely reconfigured the iommu */
1214 if (!is_rd890_iommu(iommu->dev))
1215 return;
1216
1217 /*
1218 * First, we need to ensure that the iommu is enabled. This is
1219 * controlled by a register in the northbridge
1220 */
1221 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1222
1223 if (!pdev)
1224 return;
1225
1226 /* Select Northbridge indirect register 0x75 and enable writing */
1227 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1228 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1229
1230 /* Enable the iommu */
1231 if (!(ioc_feature_control & 0x1))
1232 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1233
1234 pci_dev_put(pdev);
1235
1236 /* Restore the iommu BAR */
1237 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1238 iommu->stored_addr_lo);
1239 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1240 iommu->stored_addr_hi);
1241
1242 /* Restore the l1 indirect regs for each of the 6 l1s */
1243 for (i = 0; i < 6; i++)
1244 for (j = 0; j < 0x12; j++)
1245 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1246
1247 /* Restore the l2 indirect regs */
1248 for (i = 0; i < 0x83; i++)
1249 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1250
1251 /* Lock PCI setup registers */
1252 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1253 iommu->stored_addr_lo | 1);
1254 }
1255
1256 /*
1257 * This function finally enables all IOMMUs found in the system after
1258 * they have been initialized
1259 */
1260 static void enable_iommus(void)
1261 {
1262 struct amd_iommu *iommu;
1263
1264 for_each_iommu(iommu) {
1265 iommu_disable(iommu);
1266 iommu_init_flags(iommu);
1267 iommu_set_device_table(iommu);
1268 iommu_enable_command_buffer(iommu);
1269 iommu_enable_event_buffer(iommu);
1270 iommu_set_exclusion_range(iommu);
1271 iommu_init_msi(iommu);
1272 iommu_enable(iommu);
1273 iommu_flush_all_caches(iommu);
1274 }
1275 }
1276
1277 static void disable_iommus(void)
1278 {
1279 struct amd_iommu *iommu;
1280
1281 for_each_iommu(iommu)
1282 iommu_disable(iommu);
1283 }
1284
1285 /*
1286 * Suspend/Resume support
1287 * disable suspend until real resume implemented
1288 */
1289
1290 static void amd_iommu_resume(void)
1291 {
1292 struct amd_iommu *iommu;
1293
1294 for_each_iommu(iommu)
1295 iommu_apply_resume_quirks(iommu);
1296
1297 /* re-load the hardware */
1298 enable_iommus();
1299
1300 /*
1301 * we have to flush after the IOMMUs are enabled because a
1302 * disabled IOMMU will never execute the commands we send
1303 */
1304 for_each_iommu(iommu)
1305 iommu_flush_all_caches(iommu);
1306 }
1307
1308 static int amd_iommu_suspend(void)
1309 {
1310 /* disable IOMMUs to go out of the way for BIOS */
1311 disable_iommus();
1312
1313 return 0;
1314 }
1315
1316 static struct syscore_ops amd_iommu_syscore_ops = {
1317 .suspend = amd_iommu_suspend,
1318 .resume = amd_iommu_resume,
1319 };
1320
1321 /*
1322 * This is the core init function for AMD IOMMU hardware in the system.
1323 * This function is called from the generic x86 DMA layer initialization
1324 * code.
1325 *
1326 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1327 * three times:
1328 *
1329 * 1 pass) Find the highest PCI device id the driver has to handle.
1330 * Upon this information the size of the data structures is
1331 * determined that needs to be allocated.
1332 *
1333 * 2 pass) Initialize the data structures just allocated with the
1334 * information in the ACPI table about available AMD IOMMUs
1335 * in the system. It also maps the PCI devices in the
1336 * system to specific IOMMUs
1337 *
1338 * 3 pass) After the basic data structures are allocated and
1339 * initialized we update them with information about memory
1340 * remapping requirements parsed out of the ACPI table in
1341 * this last pass.
1342 *
1343 * After that the hardware is initialized and ready to go. In the last
1344 * step we do some Linux specific things like registering the driver in
1345 * the dma_ops interface and initializing the suspend/resume support
1346 * functions. Finally it prints some information about AMD IOMMUs and
1347 * the driver state and enables the hardware.
1348 */
1349 static int __init amd_iommu_init(void)
1350 {
1351 int i, ret = 0;
1352
1353 /*
1354 * First parse ACPI tables to find the largest Bus/Dev/Func
1355 * we need to handle. Upon this information the shared data
1356 * structures for the IOMMUs in the system will be allocated
1357 */
1358 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1359 return -ENODEV;
1360
1361 ret = amd_iommu_init_err;
1362 if (ret)
1363 goto out;
1364
1365 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1366 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1367 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1368
1369 ret = -ENOMEM;
1370
1371 /* Device table - directly used by all IOMMUs */
1372 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1373 get_order(dev_table_size));
1374 if (amd_iommu_dev_table == NULL)
1375 goto out;
1376
1377 /*
1378 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1379 * IOMMU see for that device
1380 */
1381 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1382 get_order(alias_table_size));
1383 if (amd_iommu_alias_table == NULL)
1384 goto free;
1385
1386 /* IOMMU rlookup table - find the IOMMU for a specific device */
1387 amd_iommu_rlookup_table = (void *)__get_free_pages(
1388 GFP_KERNEL | __GFP_ZERO,
1389 get_order(rlookup_table_size));
1390 if (amd_iommu_rlookup_table == NULL)
1391 goto free;
1392
1393 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1394 GFP_KERNEL | __GFP_ZERO,
1395 get_order(MAX_DOMAIN_ID/8));
1396 if (amd_iommu_pd_alloc_bitmap == NULL)
1397 goto free;
1398
1399 /* init the device table */
1400 init_device_table();
1401
1402 /*
1403 * let all alias entries point to itself
1404 */
1405 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1406 amd_iommu_alias_table[i] = i;
1407
1408 /*
1409 * never allocate domain 0 because its used as the non-allocated and
1410 * error value placeholder
1411 */
1412 amd_iommu_pd_alloc_bitmap[0] = 1;
1413
1414 spin_lock_init(&amd_iommu_pd_lock);
1415
1416 /*
1417 * now the data structures are allocated and basically initialized
1418 * start the real acpi table scan
1419 */
1420 ret = -ENODEV;
1421 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1422 goto free;
1423
1424 if (amd_iommu_init_err) {
1425 ret = amd_iommu_init_err;
1426 goto free;
1427 }
1428
1429 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1430 goto free;
1431
1432 if (amd_iommu_init_err) {
1433 ret = amd_iommu_init_err;
1434 goto free;
1435 }
1436
1437 ret = amd_iommu_init_devices();
1438 if (ret)
1439 goto free;
1440
1441 enable_iommus();
1442
1443 if (iommu_pass_through)
1444 ret = amd_iommu_init_passthrough();
1445 else
1446 ret = amd_iommu_init_dma_ops();
1447
1448 if (ret)
1449 goto free_disable;
1450
1451 amd_iommu_init_api();
1452
1453 amd_iommu_init_notifier();
1454
1455 register_syscore_ops(&amd_iommu_syscore_ops);
1456
1457 if (iommu_pass_through)
1458 goto out;
1459
1460 if (amd_iommu_unmap_flush)
1461 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1462 else
1463 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1464
1465 x86_platform.iommu_shutdown = disable_iommus;
1466 out:
1467 return ret;
1468
1469 free_disable:
1470 disable_iommus();
1471
1472 free:
1473 amd_iommu_uninit_devices();
1474
1475 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1476 get_order(MAX_DOMAIN_ID/8));
1477
1478 free_pages((unsigned long)amd_iommu_rlookup_table,
1479 get_order(rlookup_table_size));
1480
1481 free_pages((unsigned long)amd_iommu_alias_table,
1482 get_order(alias_table_size));
1483
1484 free_pages((unsigned long)amd_iommu_dev_table,
1485 get_order(dev_table_size));
1486
1487 free_iommu_all();
1488
1489 free_unity_maps();
1490
1491 #ifdef CONFIG_GART_IOMMU
1492 /*
1493 * We failed to initialize the AMD IOMMU - try fallback to GART
1494 * if possible.
1495 */
1496 gart_iommu_init();
1497
1498 #endif
1499
1500 goto out;
1501 }
1502
1503 /****************************************************************************
1504 *
1505 * Early detect code. This code runs at IOMMU detection time in the DMA
1506 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1507 * IOMMUs
1508 *
1509 ****************************************************************************/
1510 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1511 {
1512 return 0;
1513 }
1514
1515 int __init amd_iommu_detect(void)
1516 {
1517 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1518 return -ENODEV;
1519
1520 if (amd_iommu_disabled)
1521 return -ENODEV;
1522
1523 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1524 iommu_detected = 1;
1525 amd_iommu_detected = 1;
1526 x86_init.iommu.iommu_init = amd_iommu_init;
1527
1528 /* Make sure ACS will be enabled */
1529 pci_request_acs();
1530 return 1;
1531 }
1532 return -ENODEV;
1533 }
1534
1535 /****************************************************************************
1536 *
1537 * Parsing functions for the AMD IOMMU specific kernel command line
1538 * options.
1539 *
1540 ****************************************************************************/
1541
1542 static int __init parse_amd_iommu_dump(char *str)
1543 {
1544 amd_iommu_dump = true;
1545
1546 return 1;
1547 }
1548
1549 static int __init parse_amd_iommu_options(char *str)
1550 {
1551 for (; *str; ++str) {
1552 if (strncmp(str, "fullflush", 9) == 0)
1553 amd_iommu_unmap_flush = true;
1554 if (strncmp(str, "off", 3) == 0)
1555 amd_iommu_disabled = true;
1556 }
1557
1558 return 1;
1559 }
1560
1561 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1562 __setup("amd_iommu=", parse_amd_iommu_options);
1563
1564 IOMMU_INIT_FINISH(amd_iommu_detect,
1565 gart_iommu_hole_init,
1566 0,
1567 0);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree