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KVM: x86 emulator: add bsf/bsr instruction emulation
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / emulate.c
blobf6b124fcc3fd1023c0694bbdc59aeefd6a03dce1
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #ifndef __KERNEL__
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <public/xen.h>
27 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
28 #else
29 #include <linux/kvm_host.h>
30 #include "kvm_cache_regs.h"
31 #define DPRINTF(x...) do {} while (0)
32 #endif
33 #include <linux/module.h>
34 #include <asm/kvm_emulate.h>
35
36 #include "x86.h"
37 #include "tss.h"
38
39 /*
40 * Opcode effective-address decode tables.
41 * Note that we only emulate instructions that have at least one memory
42 * operand (excluding implicit stack references). We assume that stack
43 * references and instruction fetches will never occur in special memory
44 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
45 * not be handled.
46 */
47
48 /* Operand sizes: 8-bit operands or specified/overridden size. */
49 #define ByteOp (1<<0) /* 8-bit operands. */
50 /* Destination operand type. */
51 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
52 #define DstReg (2<<1) /* Register operand. */
53 #define DstMem (3<<1) /* Memory operand. */
54 #define DstAcc (4<<1) /* Destination Accumulator */
55 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
56 #define DstMem64 (6<<1) /* 64bit memory operand */
57 #define DstMask (7<<1)
58 /* Source operand type. */
59 #define SrcNone (0<<4) /* No source operand. */
60 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
61 #define SrcReg (1<<4) /* Register operand. */
62 #define SrcMem (2<<4) /* Memory operand. */
63 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
64 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
65 #define SrcImm (5<<4) /* Immediate operand. */
66 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
67 #define SrcOne (7<<4) /* Implied '1' */
68 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
69 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
70 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
71 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
72 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
73 #define SrcAcc (0xd<<4) /* Source Accumulator */
74 #define SrcMask (0xf<<4)
75 /* Generic ModRM decode. */
76 #define ModRM (1<<8)
77 /* Destination is only written; never read. */
78 #define Mov (1<<9)
79 #define BitOp (1<<10)
80 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
81 #define String (1<<12) /* String instruction (rep capable) */
82 #define Stack (1<<13) /* Stack instruction (push/pop) */
83 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
84 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
85 /* Misc flags */
86 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
87 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
88 #define Undefined (1<<25) /* No Such Instruction */
89 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
90 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
91 #define No64 (1<<28)
92 /* Source 2 operand type */
93 #define Src2None (0<<29)
94 #define Src2CL (1<<29)
95 #define Src2ImmByte (2<<29)
96 #define Src2One (3<<29)
97 #define Src2Mask (7<<29)
98
99 #define X2(x...) x, x
100 #define X3(x...) X2(x), x
101 #define X4(x...) X2(x), X2(x)
102 #define X5(x...) X4(x), x
103 #define X6(x...) X4(x), X2(x)
104 #define X7(x...) X4(x), X3(x)
105 #define X8(x...) X4(x), X4(x)
106 #define X16(x...) X8(x), X8(x)
107
108 struct opcode {
109 u32 flags;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 } u;
115 };
116
117 struct group_dual {
118 struct opcode mod012[8];
119 struct opcode mod3[8];
120 };
121
122 /* EFLAGS bit definitions. */
123 #define EFLG_ID (1<<21)
124 #define EFLG_VIP (1<<20)
125 #define EFLG_VIF (1<<19)
126 #define EFLG_AC (1<<18)
127 #define EFLG_VM (1<<17)
128 #define EFLG_RF (1<<16)
129 #define EFLG_IOPL (3<<12)
130 #define EFLG_NT (1<<14)
131 #define EFLG_OF (1<<11)
132 #define EFLG_DF (1<<10)
133 #define EFLG_IF (1<<9)
134 #define EFLG_TF (1<<8)
135 #define EFLG_SF (1<<7)
136 #define EFLG_ZF (1<<6)
137 #define EFLG_AF (1<<4)
138 #define EFLG_PF (1<<2)
139 #define EFLG_CF (1<<0)
140
141 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
142 #define EFLG_RESERVED_ONE_MASK 2
143
144 /*
145 * Instruction emulation:
146 * Most instructions are emulated directly via a fragment of inline assembly
147 * code. This allows us to save/restore EFLAGS and thus very easily pick up
148 * any modified flags.
149 */
150
151 #if defined(CONFIG_X86_64)
152 #define _LO32 "k" /* force 32-bit operand */
153 #define _STK "%%rsp" /* stack pointer */
154 #elif defined(__i386__)
155 #define _LO32 "" /* force 32-bit operand */
156 #define _STK "%%esp" /* stack pointer */
157 #endif
158
159 /*
160 * These EFLAGS bits are restored from saved value during emulation, and
161 * any changes are written back to the saved value after emulation.
162 */
163 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
164
165 /* Before executing instruction: restore necessary bits in EFLAGS. */
166 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
167 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
168 "movl %"_sav",%"_LO32 _tmp"; " \
169 "push %"_tmp"; " \
170 "push %"_tmp"; " \
171 "movl %"_msk",%"_LO32 _tmp"; " \
172 "andl %"_LO32 _tmp",("_STK"); " \
173 "pushf; " \
174 "notl %"_LO32 _tmp"; " \
175 "andl %"_LO32 _tmp",("_STK"); " \
176 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
177 "pop %"_tmp"; " \
178 "orl %"_LO32 _tmp",("_STK"); " \
179 "popf; " \
180 "pop %"_sav"; "
181
182 /* After executing instruction: write-back necessary bits in EFLAGS. */
183 #define _POST_EFLAGS(_sav, _msk, _tmp) \
184 /* _sav |= EFLAGS & _msk; */ \
185 "pushf; " \
186 "pop %"_tmp"; " \
187 "andl %"_msk",%"_LO32 _tmp"; " \
188 "orl %"_LO32 _tmp",%"_sav"; "
189
190 #ifdef CONFIG_X86_64
191 #define ON64(x) x
192 #else
193 #define ON64(x)
194 #endif
195
196 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
197 do { \
198 __asm__ __volatile__ ( \
199 _PRE_EFLAGS("0", "4", "2") \
200 _op _suffix " %"_x"3,%1; " \
201 _POST_EFLAGS("0", "4", "2") \
202 : "=m" (_eflags), "=m" ((_dst).val), \
203 "=&r" (_tmp) \
204 : _y ((_src).val), "i" (EFLAGS_MASK)); \
205 } while (0)
206
207
208 /* Raw emulation: instruction has two explicit operands. */
209 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
210 do { \
211 unsigned long _tmp; \
212 \
213 switch ((_dst).bytes) { \
214 case 2: \
215 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
216 break; \
217 case 4: \
218 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
219 break; \
220 case 8: \
221 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
222 break; \
223 } \
224 } while (0)
225
226 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
227 do { \
228 unsigned long _tmp; \
229 switch ((_dst).bytes) { \
230 case 1: \
231 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
232 break; \
233 default: \
234 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
235 _wx, _wy, _lx, _ly, _qx, _qy); \
236 break; \
237 } \
238 } while (0)
239
240 /* Source operand is byte-sized and may be restricted to just %cl. */
241 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
242 __emulate_2op(_op, _src, _dst, _eflags, \
243 "b", "c", "b", "c", "b", "c", "b", "c")
244
245 /* Source operand is byte, word, long or quad sized. */
246 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
247 __emulate_2op(_op, _src, _dst, _eflags, \
248 "b", "q", "w", "r", _LO32, "r", "", "r")
249
250 /* Source operand is word, long or quad sized. */
251 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
252 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
253 "w", "r", _LO32, "r", "", "r")
254
255 /* Instruction has three operands and one operand is stored in ECX register */
256 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
257 do { \
258 unsigned long _tmp; \
259 _type _clv = (_cl).val; \
260 _type _srcv = (_src).val; \
261 _type _dstv = (_dst).val; \
262 \
263 __asm__ __volatile__ ( \
264 _PRE_EFLAGS("0", "5", "2") \
265 _op _suffix " %4,%1 \n" \
266 _POST_EFLAGS("0", "5", "2") \
267 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
268 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
269 ); \
270 \
271 (_cl).val = (unsigned long) _clv; \
272 (_src).val = (unsigned long) _srcv; \
273 (_dst).val = (unsigned long) _dstv; \
274 } while (0)
275
276 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
277 do { \
278 switch ((_dst).bytes) { \
279 case 2: \
280 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
281 "w", unsigned short); \
282 break; \
283 case 4: \
284 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
285 "l", unsigned int); \
286 break; \
287 case 8: \
288 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
289 "q", unsigned long)); \
290 break; \
291 } \
292 } while (0)
293
294 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
295 do { \
296 unsigned long _tmp; \
297 \
298 __asm__ __volatile__ ( \
299 _PRE_EFLAGS("0", "3", "2") \
300 _op _suffix " %1; " \
301 _POST_EFLAGS("0", "3", "2") \
302 : "=m" (_eflags), "+m" ((_dst).val), \
303 "=&r" (_tmp) \
304 : "i" (EFLAGS_MASK)); \
305 } while (0)
306
307 /* Instruction has only one explicit operand (no source operand). */
308 #define emulate_1op(_op, _dst, _eflags) \
309 do { \
310 switch ((_dst).bytes) { \
311 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
312 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
313 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
314 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
315 } \
316 } while (0)
317
318 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
319 do { \
320 unsigned long _tmp; \
321 \
322 __asm__ __volatile__ ( \
323 _PRE_EFLAGS("0", "4", "1") \
324 _op _suffix " %5; " \
325 _POST_EFLAGS("0", "4", "1") \
326 : "=m" (_eflags), "=&r" (_tmp), \
327 "+a" (_rax), "+d" (_rdx) \
328 : "i" (EFLAGS_MASK), "m" ((_src).val), \
329 "a" (_rax), "d" (_rdx)); \
330 } while (0)
331
332 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
333 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
334 do { \
335 switch((_src).bytes) { \
336 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
337 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
338 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
339 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
340 } \
341 } while (0)
342
343 /* Fetch next part of the instruction being emulated. */
344 #define insn_fetch(_type, _size, _eip) \
345 ({ unsigned long _x; \
346 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
347 if (rc != X86EMUL_CONTINUE) \
348 goto done; \
349 (_eip) += (_size); \
350 (_type)_x; \
351 })
352
353 #define insn_fetch_arr(_arr, _size, _eip) \
354 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
355 if (rc != X86EMUL_CONTINUE) \
356 goto done; \
357 (_eip) += (_size); \
358 })
359
360 static inline unsigned long ad_mask(struct decode_cache *c)
361 {
362 return (1UL << (c->ad_bytes << 3)) - 1;
363 }
364
365 /* Access/update address held in a register, based on addressing mode. */
366 static inline unsigned long
367 address_mask(struct decode_cache *c, unsigned long reg)
368 {
369 if (c->ad_bytes == sizeof(unsigned long))
370 return reg;
371 else
372 return reg & ad_mask(c);
373 }
374
375 static inline unsigned long
376 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
377 {
378 return base + address_mask(c, reg);
379 }
380
381 static inline void
382 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
383 {
384 if (c->ad_bytes == sizeof(unsigned long))
385 *reg += inc;
386 else
387 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
388 }
389
390 static inline void jmp_rel(struct decode_cache *c, int rel)
391 {
392 register_address_increment(c, &c->eip, rel);
393 }
394
395 static void set_seg_override(struct decode_cache *c, int seg)
396 {
397 c->has_seg_override = true;
398 c->seg_override = seg;
399 }
400
401 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
402 struct x86_emulate_ops *ops, int seg)
403 {
404 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
405 return 0;
406
407 return ops->get_cached_segment_base(seg, ctxt->vcpu);
408 }
409
410 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
411 struct x86_emulate_ops *ops,
412 struct decode_cache *c)
413 {
414 if (!c->has_seg_override)
415 return 0;
416
417 return seg_base(ctxt, ops, c->seg_override);
418 }
419
420 static unsigned long es_base(struct x86_emulate_ctxt *ctxt,
421 struct x86_emulate_ops *ops)
422 {
423 return seg_base(ctxt, ops, VCPU_SREG_ES);
424 }
425
426 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt,
427 struct x86_emulate_ops *ops)
428 {
429 return seg_base(ctxt, ops, VCPU_SREG_SS);
430 }
431
432 static void emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
433 u32 error, bool valid)
434 {
435 ctxt->exception = vec;
436 ctxt->error_code = error;
437 ctxt->error_code_valid = valid;
438 ctxt->restart = false;
439 }
440
441 static void emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
442 {
443 emulate_exception(ctxt, GP_VECTOR, err, true);
444 }
445
446 static void emulate_pf(struct x86_emulate_ctxt *ctxt, unsigned long addr,
447 int err)
448 {
449 ctxt->cr2 = addr;
450 emulate_exception(ctxt, PF_VECTOR, err, true);
451 }
452
453 static void emulate_ud(struct x86_emulate_ctxt *ctxt)
454 {
455 emulate_exception(ctxt, UD_VECTOR, 0, false);
456 }
457
458 static void emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
459 {
460 emulate_exception(ctxt, TS_VECTOR, err, true);
461 }
462
463 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
464 struct x86_emulate_ops *ops,
465 unsigned long eip, u8 *dest)
466 {
467 struct fetch_cache *fc = &ctxt->decode.fetch;
468 int rc;
469 int size, cur_size;
470
471 if (eip == fc->end) {
472 cur_size = fc->end - fc->start;
473 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
474 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
475 size, ctxt->vcpu, NULL);
476 if (rc != X86EMUL_CONTINUE)
477 return rc;
478 fc->end += size;
479 }
480 *dest = fc->data[eip - fc->start];
481 return X86EMUL_CONTINUE;
482 }
483
484 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
485 struct x86_emulate_ops *ops,
486 unsigned long eip, void *dest, unsigned size)
487 {
488 int rc;
489
490 /* x86 instructions are limited to 15 bytes. */
491 if (eip + size - ctxt->eip > 15)
492 return X86EMUL_UNHANDLEABLE;
493 while (size--) {
494 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
495 if (rc != X86EMUL_CONTINUE)
496 return rc;
497 }
498 return X86EMUL_CONTINUE;
499 }
500
501 /*
502 * Given the 'reg' portion of a ModRM byte, and a register block, return a
503 * pointer into the block that addresses the relevant register.
504 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
505 */
506 static void *decode_register(u8 modrm_reg, unsigned long *regs,
507 int highbyte_regs)
508 {
509 void *p;
510
511 p = &regs[modrm_reg];
512 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
513 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
514 return p;
515 }
516
517 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
518 struct x86_emulate_ops *ops,
519 ulong addr,
520 u16 *size, unsigned long *address, int op_bytes)
521 {
522 int rc;
523
524 if (op_bytes == 2)
525 op_bytes = 3;
526 *address = 0;
527 rc = ops->read_std(addr, (unsigned long *)size, 2, ctxt->vcpu, NULL);
528 if (rc != X86EMUL_CONTINUE)
529 return rc;
530 rc = ops->read_std(addr + 2, address, op_bytes, ctxt->vcpu, NULL);
531 return rc;
532 }
533
534 static int test_cc(unsigned int condition, unsigned int flags)
535 {
536 int rc = 0;
537
538 switch ((condition & 15) >> 1) {
539 case 0: /* o */
540 rc |= (flags & EFLG_OF);
541 break;
542 case 1: /* b/c/nae */
543 rc |= (flags & EFLG_CF);
544 break;
545 case 2: /* z/e */
546 rc |= (flags & EFLG_ZF);
547 break;
548 case 3: /* be/na */
549 rc |= (flags & (EFLG_CF|EFLG_ZF));
550 break;
551 case 4: /* s */
552 rc |= (flags & EFLG_SF);
553 break;
554 case 5: /* p/pe */
555 rc |= (flags & EFLG_PF);
556 break;
557 case 7: /* le/ng */
558 rc |= (flags & EFLG_ZF);
559 /* fall through */
560 case 6: /* l/nge */
561 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
562 break;
563 }
564
565 /* Odd condition identifiers (lsb == 1) have inverted sense. */
566 return (!!rc ^ (condition & 1));
567 }
568
569 static void fetch_register_operand(struct operand *op)
570 {
571 switch (op->bytes) {
572 case 1:
573 op->val = *(u8 *)op->addr.reg;
574 break;
575 case 2:
576 op->val = *(u16 *)op->addr.reg;
577 break;
578 case 4:
579 op->val = *(u32 *)op->addr.reg;
580 break;
581 case 8:
582 op->val = *(u64 *)op->addr.reg;
583 break;
584 }
585 }
586
587 static void decode_register_operand(struct operand *op,
588 struct decode_cache *c,
589 int inhibit_bytereg)
590 {
591 unsigned reg = c->modrm_reg;
592 int highbyte_regs = c->rex_prefix == 0;
593
594 if (!(c->d & ModRM))
595 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
596 op->type = OP_REG;
597 if ((c->d & ByteOp) && !inhibit_bytereg) {
598 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
599 op->bytes = 1;
600 } else {
601 op->addr.reg = decode_register(reg, c->regs, 0);
602 op->bytes = c->op_bytes;
603 }
604 fetch_register_operand(op);
605 op->orig_val = op->val;
606 }
607
608 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
609 struct x86_emulate_ops *ops,
610 struct operand *op)
611 {
612 struct decode_cache *c = &ctxt->decode;
613 u8 sib;
614 int index_reg = 0, base_reg = 0, scale;
615 int rc = X86EMUL_CONTINUE;
616 ulong modrm_ea = 0;
617
618 if (c->rex_prefix) {
619 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
620 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
621 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
622 }
623
624 c->modrm = insn_fetch(u8, 1, c->eip);
625 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
626 c->modrm_reg |= (c->modrm & 0x38) >> 3;
627 c->modrm_rm |= (c->modrm & 0x07);
628 c->modrm_seg = VCPU_SREG_DS;
629
630 if (c->modrm_mod == 3) {
631 op->type = OP_REG;
632 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
633 op->addr.reg = decode_register(c->modrm_rm,
634 c->regs, c->d & ByteOp);
635 fetch_register_operand(op);
636 return rc;
637 }
638
639 op->type = OP_MEM;
640
641 if (c->ad_bytes == 2) {
642 unsigned bx = c->regs[VCPU_REGS_RBX];
643 unsigned bp = c->regs[VCPU_REGS_RBP];
644 unsigned si = c->regs[VCPU_REGS_RSI];
645 unsigned di = c->regs[VCPU_REGS_RDI];
646
647 /* 16-bit ModR/M decode. */
648 switch (c->modrm_mod) {
649 case 0:
650 if (c->modrm_rm == 6)
651 modrm_ea += insn_fetch(u16, 2, c->eip);
652 break;
653 case 1:
654 modrm_ea += insn_fetch(s8, 1, c->eip);
655 break;
656 case 2:
657 modrm_ea += insn_fetch(u16, 2, c->eip);
658 break;
659 }
660 switch (c->modrm_rm) {
661 case 0:
662 modrm_ea += bx + si;
663 break;
664 case 1:
665 modrm_ea += bx + di;
666 break;
667 case 2:
668 modrm_ea += bp + si;
669 break;
670 case 3:
671 modrm_ea += bp + di;
672 break;
673 case 4:
674 modrm_ea += si;
675 break;
676 case 5:
677 modrm_ea += di;
678 break;
679 case 6:
680 if (c->modrm_mod != 0)
681 modrm_ea += bp;
682 break;
683 case 7:
684 modrm_ea += bx;
685 break;
686 }
687 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
688 (c->modrm_rm == 6 && c->modrm_mod != 0))
689 c->modrm_seg = VCPU_SREG_SS;
690 modrm_ea = (u16)modrm_ea;
691 } else {
692 /* 32/64-bit ModR/M decode. */
693 if ((c->modrm_rm & 7) == 4) {
694 sib = insn_fetch(u8, 1, c->eip);
695 index_reg |= (sib >> 3) & 7;
696 base_reg |= sib & 7;
697 scale = sib >> 6;
698
699 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
700 modrm_ea += insn_fetch(s32, 4, c->eip);
701 else
702 modrm_ea += c->regs[base_reg];
703 if (index_reg != 4)
704 modrm_ea += c->regs[index_reg] << scale;
705 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
706 if (ctxt->mode == X86EMUL_MODE_PROT64)
707 c->rip_relative = 1;
708 } else
709 modrm_ea += c->regs[c->modrm_rm];
710 switch (c->modrm_mod) {
711 case 0:
712 if (c->modrm_rm == 5)
713 modrm_ea += insn_fetch(s32, 4, c->eip);
714 break;
715 case 1:
716 modrm_ea += insn_fetch(s8, 1, c->eip);
717 break;
718 case 2:
719 modrm_ea += insn_fetch(s32, 4, c->eip);
720 break;
721 }
722 }
723 op->addr.mem = modrm_ea;
724 done:
725 return rc;
726 }
727
728 static int decode_abs(struct x86_emulate_ctxt *ctxt,
729 struct x86_emulate_ops *ops,
730 struct operand *op)
731 {
732 struct decode_cache *c = &ctxt->decode;
733 int rc = X86EMUL_CONTINUE;
734
735 op->type = OP_MEM;
736 switch (c->ad_bytes) {
737 case 2:
738 op->addr.mem = insn_fetch(u16, 2, c->eip);
739 break;
740 case 4:
741 op->addr.mem = insn_fetch(u32, 4, c->eip);
742 break;
743 case 8:
744 op->addr.mem = insn_fetch(u64, 8, c->eip);
745 break;
746 }
747 done:
748 return rc;
749 }
750
751 static void fetch_bit_operand(struct decode_cache *c)
752 {
753 long sv, mask;
754
755 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
756 mask = ~(c->dst.bytes * 8 - 1);
757
758 if (c->src.bytes == 2)
759 sv = (s16)c->src.val & (s16)mask;
760 else if (c->src.bytes == 4)
761 sv = (s32)c->src.val & (s32)mask;
762
763 c->dst.addr.mem += (sv >> 3);
764 }
765
766 /* only subword offset */
767 c->src.val &= (c->dst.bytes << 3) - 1;
768 }
769
770 static int read_emulated(struct x86_emulate_ctxt *ctxt,
771 struct x86_emulate_ops *ops,
772 unsigned long addr, void *dest, unsigned size)
773 {
774 int rc;
775 struct read_cache *mc = &ctxt->decode.mem_read;
776 u32 err;
777
778 while (size) {
779 int n = min(size, 8u);
780 size -= n;
781 if (mc->pos < mc->end)
782 goto read_cached;
783
784 rc = ops->read_emulated(addr, mc->data + mc->end, n, &err,
785 ctxt->vcpu);
786 if (rc == X86EMUL_PROPAGATE_FAULT)
787 emulate_pf(ctxt, addr, err);
788 if (rc != X86EMUL_CONTINUE)
789 return rc;
790 mc->end += n;
791
792 read_cached:
793 memcpy(dest, mc->data + mc->pos, n);
794 mc->pos += n;
795 dest += n;
796 addr += n;
797 }
798 return X86EMUL_CONTINUE;
799 }
800
801 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
802 struct x86_emulate_ops *ops,
803 unsigned int size, unsigned short port,
804 void *dest)
805 {
806 struct read_cache *rc = &ctxt->decode.io_read;
807
808 if (rc->pos == rc->end) { /* refill pio read ahead */
809 struct decode_cache *c = &ctxt->decode;
810 unsigned int in_page, n;
811 unsigned int count = c->rep_prefix ?
812 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
813 in_page = (ctxt->eflags & EFLG_DF) ?
814 offset_in_page(c->regs[VCPU_REGS_RDI]) :
815 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
816 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
817 count);
818 if (n == 0)
819 n = 1;
820 rc->pos = rc->end = 0;
821 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
822 return 0;
823 rc->end = n * size;
824 }
825
826 memcpy(dest, rc->data + rc->pos, size);
827 rc->pos += size;
828 return 1;
829 }
830
831 static u32 desc_limit_scaled(struct desc_struct *desc)
832 {
833 u32 limit = get_desc_limit(desc);
834
835 return desc->g ? (limit << 12) | 0xfff : limit;
836 }
837
838 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
839 struct x86_emulate_ops *ops,
840 u16 selector, struct desc_ptr *dt)
841 {
842 if (selector & 1 << 2) {
843 struct desc_struct desc;
844 memset (dt, 0, sizeof *dt);
845 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu))
846 return;
847
848 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
849 dt->address = get_desc_base(&desc);
850 } else
851 ops->get_gdt(dt, ctxt->vcpu);
852 }
853
854 /* allowed just for 8 bytes segments */
855 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
856 struct x86_emulate_ops *ops,
857 u16 selector, struct desc_struct *desc)
858 {
859 struct desc_ptr dt;
860 u16 index = selector >> 3;
861 int ret;
862 u32 err;
863 ulong addr;
864
865 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
866
867 if (dt.size < index * 8 + 7) {
868 emulate_gp(ctxt, selector & 0xfffc);
869 return X86EMUL_PROPAGATE_FAULT;
870 }
871 addr = dt.address + index * 8;
872 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
873 if (ret == X86EMUL_PROPAGATE_FAULT)
874 emulate_pf(ctxt, addr, err);
875
876 return ret;
877 }
878
879 /* allowed just for 8 bytes segments */
880 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
881 struct x86_emulate_ops *ops,
882 u16 selector, struct desc_struct *desc)
883 {
884 struct desc_ptr dt;
885 u16 index = selector >> 3;
886 u32 err;
887 ulong addr;
888 int ret;
889
890 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
891
892 if (dt.size < index * 8 + 7) {
893 emulate_gp(ctxt, selector & 0xfffc);
894 return X86EMUL_PROPAGATE_FAULT;
895 }
896
897 addr = dt.address + index * 8;
898 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err);
899 if (ret == X86EMUL_PROPAGATE_FAULT)
900 emulate_pf(ctxt, addr, err);
901
902 return ret;
903 }
904
905 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
906 struct x86_emulate_ops *ops,
907 u16 selector, int seg)
908 {
909 struct desc_struct seg_desc;
910 u8 dpl, rpl, cpl;
911 unsigned err_vec = GP_VECTOR;
912 u32 err_code = 0;
913 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
914 int ret;
915
916 memset(&seg_desc, 0, sizeof seg_desc);
917
918 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
919 || ctxt->mode == X86EMUL_MODE_REAL) {
920 /* set real mode segment descriptor */
921 set_desc_base(&seg_desc, selector << 4);
922 set_desc_limit(&seg_desc, 0xffff);
923 seg_desc.type = 3;
924 seg_desc.p = 1;
925 seg_desc.s = 1;
926 goto load;
927 }
928
929 /* NULL selector is not valid for TR, CS and SS */
930 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
931 && null_selector)
932 goto exception;
933
934 /* TR should be in GDT only */
935 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
936 goto exception;
937
938 if (null_selector) /* for NULL selector skip all following checks */
939 goto load;
940
941 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
942 if (ret != X86EMUL_CONTINUE)
943 return ret;
944
945 err_code = selector & 0xfffc;
946 err_vec = GP_VECTOR;
947
948 /* can't load system descriptor into segment selecor */
949 if (seg <= VCPU_SREG_GS && !seg_desc.s)
950 goto exception;
951
952 if (!seg_desc.p) {
953 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
954 goto exception;
955 }
956
957 rpl = selector & 3;
958 dpl = seg_desc.dpl;
959 cpl = ops->cpl(ctxt->vcpu);
960
961 switch (seg) {
962 case VCPU_SREG_SS:
963 /*
964 * segment is not a writable data segment or segment
965 * selector's RPL != CPL or segment selector's RPL != CPL
966 */
967 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
968 goto exception;
969 break;
970 case VCPU_SREG_CS:
971 if (!(seg_desc.type & 8))
972 goto exception;
973
974 if (seg_desc.type & 4) {
975 /* conforming */
976 if (dpl > cpl)
977 goto exception;
978 } else {
979 /* nonconforming */
980 if (rpl > cpl || dpl != cpl)
981 goto exception;
982 }
983 /* CS(RPL) <- CPL */
984 selector = (selector & 0xfffc) | cpl;
985 break;
986 case VCPU_SREG_TR:
987 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
988 goto exception;
989 break;
990 case VCPU_SREG_LDTR:
991 if (seg_desc.s || seg_desc.type != 2)
992 goto exception;
993 break;
994 default: /* DS, ES, FS, or GS */
995 /*
996 * segment is not a data or readable code segment or
997 * ((segment is a data or nonconforming code segment)
998 * and (both RPL and CPL > DPL))
999 */
1000 if ((seg_desc.type & 0xa) == 0x8 ||
1001 (((seg_desc.type & 0xc) != 0xc) &&
1002 (rpl > dpl && cpl > dpl)))
1003 goto exception;
1004 break;
1005 }
1006
1007 if (seg_desc.s) {
1008 /* mark segment as accessed */
1009 seg_desc.type |= 1;
1010 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1011 if (ret != X86EMUL_CONTINUE)
1012 return ret;
1013 }
1014 load:
1015 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1016 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu);
1017 return X86EMUL_CONTINUE;
1018 exception:
1019 emulate_exception(ctxt, err_vec, err_code, true);
1020 return X86EMUL_PROPAGATE_FAULT;
1021 }
1022
1023 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1024 struct x86_emulate_ops *ops)
1025 {
1026 int rc;
1027 struct decode_cache *c = &ctxt->decode;
1028 u32 err;
1029
1030 switch (c->dst.type) {
1031 case OP_REG:
1032 /* The 4-byte case *is* correct:
1033 * in 64-bit mode we zero-extend.
1034 */
1035 switch (c->dst.bytes) {
1036 case 1:
1037 *(u8 *)c->dst.addr.reg = (u8)c->dst.val;
1038 break;
1039 case 2:
1040 *(u16 *)c->dst.addr.reg = (u16)c->dst.val;
1041 break;
1042 case 4:
1043 *c->dst.addr.reg = (u32)c->dst.val;
1044 break; /* 64b: zero-ext */
1045 case 8:
1046 *c->dst.addr.reg = c->dst.val;
1047 break;
1048 }
1049 break;
1050 case OP_MEM:
1051 if (c->lock_prefix)
1052 rc = ops->cmpxchg_emulated(
1053 c->dst.addr.mem,
1054 &c->dst.orig_val,
1055 &c->dst.val,
1056 c->dst.bytes,
1057 &err,
1058 ctxt->vcpu);
1059 else
1060 rc = ops->write_emulated(
1061 c->dst.addr.mem,
1062 &c->dst.val,
1063 c->dst.bytes,
1064 &err,
1065 ctxt->vcpu);
1066 if (rc == X86EMUL_PROPAGATE_FAULT)
1067 emulate_pf(ctxt, c->dst.addr.mem, err);
1068 if (rc != X86EMUL_CONTINUE)
1069 return rc;
1070 break;
1071 case OP_NONE:
1072 /* no writeback */
1073 break;
1074 default:
1075 break;
1076 }
1077 return X86EMUL_CONTINUE;
1078 }
1079
1080 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1081 struct x86_emulate_ops *ops)
1082 {
1083 struct decode_cache *c = &ctxt->decode;
1084
1085 c->dst.type = OP_MEM;
1086 c->dst.bytes = c->op_bytes;
1087 c->dst.val = c->src.val;
1088 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1089 c->dst.addr.mem = register_address(c, ss_base(ctxt, ops),
1090 c->regs[VCPU_REGS_RSP]);
1091 }
1092
1093 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1094 struct x86_emulate_ops *ops,
1095 void *dest, int len)
1096 {
1097 struct decode_cache *c = &ctxt->decode;
1098 int rc;
1099
1100 rc = read_emulated(ctxt, ops, register_address(c, ss_base(ctxt, ops),
1101 c->regs[VCPU_REGS_RSP]),
1102 dest, len);
1103 if (rc != X86EMUL_CONTINUE)
1104 return rc;
1105
1106 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1107 return rc;
1108 }
1109
1110 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1111 struct x86_emulate_ops *ops,
1112 void *dest, int len)
1113 {
1114 int rc;
1115 unsigned long val, change_mask;
1116 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1117 int cpl = ops->cpl(ctxt->vcpu);
1118
1119 rc = emulate_pop(ctxt, ops, &val, len);
1120 if (rc != X86EMUL_CONTINUE)
1121 return rc;
1122
1123 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1124 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1125
1126 switch(ctxt->mode) {
1127 case X86EMUL_MODE_PROT64:
1128 case X86EMUL_MODE_PROT32:
1129 case X86EMUL_MODE_PROT16:
1130 if (cpl == 0)
1131 change_mask |= EFLG_IOPL;
1132 if (cpl <= iopl)
1133 change_mask |= EFLG_IF;
1134 break;
1135 case X86EMUL_MODE_VM86:
1136 if (iopl < 3) {
1137 emulate_gp(ctxt, 0);
1138 return X86EMUL_PROPAGATE_FAULT;
1139 }
1140 change_mask |= EFLG_IF;
1141 break;
1142 default: /* real mode */
1143 change_mask |= (EFLG_IOPL | EFLG_IF);
1144 break;
1145 }
1146
1147 *(unsigned long *)dest =
1148 (ctxt->eflags & ~change_mask) | (val & change_mask);
1149
1150 return rc;
1151 }
1152
1153 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1154 struct x86_emulate_ops *ops, int seg)
1155 {
1156 struct decode_cache *c = &ctxt->decode;
1157
1158 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1159
1160 emulate_push(ctxt, ops);
1161 }
1162
1163 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1164 struct x86_emulate_ops *ops, int seg)
1165 {
1166 struct decode_cache *c = &ctxt->decode;
1167 unsigned long selector;
1168 int rc;
1169
1170 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1171 if (rc != X86EMUL_CONTINUE)
1172 return rc;
1173
1174 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1175 return rc;
1176 }
1177
1178 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1179 struct x86_emulate_ops *ops)
1180 {
1181 struct decode_cache *c = &ctxt->decode;
1182 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1183 int rc = X86EMUL_CONTINUE;
1184 int reg = VCPU_REGS_RAX;
1185
1186 while (reg <= VCPU_REGS_RDI) {
1187 (reg == VCPU_REGS_RSP) ?
1188 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1189
1190 emulate_push(ctxt, ops);
1191
1192 rc = writeback(ctxt, ops);
1193 if (rc != X86EMUL_CONTINUE)
1194 return rc;
1195
1196 ++reg;
1197 }
1198
1199 /* Disable writeback. */
1200 c->dst.type = OP_NONE;
1201
1202 return rc;
1203 }
1204
1205 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1206 struct x86_emulate_ops *ops)
1207 {
1208 struct decode_cache *c = &ctxt->decode;
1209 int rc = X86EMUL_CONTINUE;
1210 int reg = VCPU_REGS_RDI;
1211
1212 while (reg >= VCPU_REGS_RAX) {
1213 if (reg == VCPU_REGS_RSP) {
1214 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1215 c->op_bytes);
1216 --reg;
1217 }
1218
1219 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1220 if (rc != X86EMUL_CONTINUE)
1221 break;
1222 --reg;
1223 }
1224 return rc;
1225 }
1226
1227 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1228 struct x86_emulate_ops *ops, int irq)
1229 {
1230 struct decode_cache *c = &ctxt->decode;
1231 int rc = X86EMUL_CONTINUE;
1232 struct desc_ptr dt;
1233 gva_t cs_addr;
1234 gva_t eip_addr;
1235 u16 cs, eip;
1236 u32 err;
1237
1238 /* TODO: Add limit checks */
1239 c->src.val = ctxt->eflags;
1240 emulate_push(ctxt, ops);
1241
1242 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1243
1244 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1245 emulate_push(ctxt, ops);
1246
1247 c->src.val = c->eip;
1248 emulate_push(ctxt, ops);
1249
1250 ops->get_idt(&dt, ctxt->vcpu);
1251
1252 eip_addr = dt.address + (irq << 2);
1253 cs_addr = dt.address + (irq << 2) + 2;
1254
1255 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &err);
1256 if (rc != X86EMUL_CONTINUE)
1257 return rc;
1258
1259 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &err);
1260 if (rc != X86EMUL_CONTINUE)
1261 return rc;
1262
1263 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1264 if (rc != X86EMUL_CONTINUE)
1265 return rc;
1266
1267 c->eip = eip;
1268
1269 return rc;
1270 }
1271
1272 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1273 struct x86_emulate_ops *ops, int irq)
1274 {
1275 switch(ctxt->mode) {
1276 case X86EMUL_MODE_REAL:
1277 return emulate_int_real(ctxt, ops, irq);
1278 case X86EMUL_MODE_VM86:
1279 case X86EMUL_MODE_PROT16:
1280 case X86EMUL_MODE_PROT32:
1281 case X86EMUL_MODE_PROT64:
1282 default:
1283 /* Protected mode interrupts unimplemented yet */
1284 return X86EMUL_UNHANDLEABLE;
1285 }
1286 }
1287
1288 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1289 struct x86_emulate_ops *ops)
1290 {
1291 struct decode_cache *c = &ctxt->decode;
1292 int rc = X86EMUL_CONTINUE;
1293 unsigned long temp_eip = 0;
1294 unsigned long temp_eflags = 0;
1295 unsigned long cs = 0;
1296 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1297 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1298 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1299 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1300
1301 /* TODO: Add stack limit check */
1302
1303 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1304
1305 if (rc != X86EMUL_CONTINUE)
1306 return rc;
1307
1308 if (temp_eip & ~0xffff) {
1309 emulate_gp(ctxt, 0);
1310 return X86EMUL_PROPAGATE_FAULT;
1311 }
1312
1313 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1314
1315 if (rc != X86EMUL_CONTINUE)
1316 return rc;
1317
1318 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1319
1320 if (rc != X86EMUL_CONTINUE)
1321 return rc;
1322
1323 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1324
1325 if (rc != X86EMUL_CONTINUE)
1326 return rc;
1327
1328 c->eip = temp_eip;
1329
1330
1331 if (c->op_bytes == 4)
1332 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1333 else if (c->op_bytes == 2) {
1334 ctxt->eflags &= ~0xffff;
1335 ctxt->eflags |= temp_eflags;
1336 }
1337
1338 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1339 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1340
1341 return rc;
1342 }
1343
1344 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1345 struct x86_emulate_ops* ops)
1346 {
1347 switch(ctxt->mode) {
1348 case X86EMUL_MODE_REAL:
1349 return emulate_iret_real(ctxt, ops);
1350 case X86EMUL_MODE_VM86:
1351 case X86EMUL_MODE_PROT16:
1352 case X86EMUL_MODE_PROT32:
1353 case X86EMUL_MODE_PROT64:
1354 default:
1355 /* iret from protected mode unimplemented yet */
1356 return X86EMUL_UNHANDLEABLE;
1357 }
1358 }
1359
1360 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1361 struct x86_emulate_ops *ops)
1362 {
1363 struct decode_cache *c = &ctxt->decode;
1364
1365 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1366 }
1367
1368 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1369 {
1370 struct decode_cache *c = &ctxt->decode;
1371 switch (c->modrm_reg) {
1372 case 0: /* rol */
1373 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1374 break;
1375 case 1: /* ror */
1376 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1377 break;
1378 case 2: /* rcl */
1379 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1380 break;
1381 case 3: /* rcr */
1382 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1383 break;
1384 case 4: /* sal/shl */
1385 case 6: /* sal/shl */
1386 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1387 break;
1388 case 5: /* shr */
1389 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1390 break;
1391 case 7: /* sar */
1392 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1393 break;
1394 }
1395 }
1396
1397 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1398 struct x86_emulate_ops *ops)
1399 {
1400 struct decode_cache *c = &ctxt->decode;
1401 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1402 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1403
1404 switch (c->modrm_reg) {
1405 case 0 ... 1: /* test */
1406 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1407 break;
1408 case 2: /* not */
1409 c->dst.val = ~c->dst.val;
1410 break;
1411 case 3: /* neg */
1412 emulate_1op("neg", c->dst, ctxt->eflags);
1413 break;
1414 case 4: /* mul */
1415 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1416 break;
1417 case 5: /* imul */
1418 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1419 break;
1420 case 6: /* div */
1421 emulate_1op_rax_rdx("div", c->src, *rax, *rdx, ctxt->eflags);
1422 break;
1423 case 7: /* idiv */
1424 emulate_1op_rax_rdx("idiv", c->src, *rax, *rdx, ctxt->eflags);
1425 break;
1426 default:
1427 return X86EMUL_UNHANDLEABLE;
1428 }
1429 return X86EMUL_CONTINUE;
1430 }
1431
1432 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1433 struct x86_emulate_ops *ops)
1434 {
1435 struct decode_cache *c = &ctxt->decode;
1436
1437 switch (c->modrm_reg) {
1438 case 0: /* inc */
1439 emulate_1op("inc", c->dst, ctxt->eflags);
1440 break;
1441 case 1: /* dec */
1442 emulate_1op("dec", c->dst, ctxt->eflags);
1443 break;
1444 case 2: /* call near abs */ {
1445 long int old_eip;
1446 old_eip = c->eip;
1447 c->eip = c->src.val;
1448 c->src.val = old_eip;
1449 emulate_push(ctxt, ops);
1450 break;
1451 }
1452 case 4: /* jmp abs */
1453 c->eip = c->src.val;
1454 break;
1455 case 6: /* push */
1456 emulate_push(ctxt, ops);
1457 break;
1458 }
1459 return X86EMUL_CONTINUE;
1460 }
1461
1462 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1463 struct x86_emulate_ops *ops)
1464 {
1465 struct decode_cache *c = &ctxt->decode;
1466 u64 old = c->dst.orig_val64;
1467
1468 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1469 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1470 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1471 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1472 ctxt->eflags &= ~EFLG_ZF;
1473 } else {
1474 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1475 (u32) c->regs[VCPU_REGS_RBX];
1476
1477 ctxt->eflags |= EFLG_ZF;
1478 }
1479 return X86EMUL_CONTINUE;
1480 }
1481
1482 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1483 struct x86_emulate_ops *ops)
1484 {
1485 struct decode_cache *c = &ctxt->decode;
1486 int rc;
1487 unsigned long cs;
1488
1489 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1490 if (rc != X86EMUL_CONTINUE)
1491 return rc;
1492 if (c->op_bytes == 4)
1493 c->eip = (u32)c->eip;
1494 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1495 if (rc != X86EMUL_CONTINUE)
1496 return rc;
1497 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1498 return rc;
1499 }
1500
1501 static inline void
1502 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1503 struct x86_emulate_ops *ops, struct desc_struct *cs,
1504 struct desc_struct *ss)
1505 {
1506 memset(cs, 0, sizeof(struct desc_struct));
1507 ops->get_cached_descriptor(cs, VCPU_SREG_CS, ctxt->vcpu);
1508 memset(ss, 0, sizeof(struct desc_struct));
1509
1510 cs->l = 0; /* will be adjusted later */
1511 set_desc_base(cs, 0); /* flat segment */
1512 cs->g = 1; /* 4kb granularity */
1513 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1514 cs->type = 0x0b; /* Read, Execute, Accessed */
1515 cs->s = 1;
1516 cs->dpl = 0; /* will be adjusted later */
1517 cs->p = 1;
1518 cs->d = 1;
1519
1520 set_desc_base(ss, 0); /* flat segment */
1521 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1522 ss->g = 1; /* 4kb granularity */
1523 ss->s = 1;
1524 ss->type = 0x03; /* Read/Write, Accessed */
1525 ss->d = 1; /* 32bit stack segment */
1526 ss->dpl = 0;
1527 ss->p = 1;
1528 }
1529
1530 static int
1531 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1532 {
1533 struct decode_cache *c = &ctxt->decode;
1534 struct desc_struct cs, ss;
1535 u64 msr_data;
1536 u16 cs_sel, ss_sel;
1537
1538 /* syscall is not available in real mode */
1539 if (ctxt->mode == X86EMUL_MODE_REAL ||
1540 ctxt->mode == X86EMUL_MODE_VM86) {
1541 emulate_ud(ctxt);
1542 return X86EMUL_PROPAGATE_FAULT;
1543 }
1544
1545 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1546
1547 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1548 msr_data >>= 32;
1549 cs_sel = (u16)(msr_data & 0xfffc);
1550 ss_sel = (u16)(msr_data + 8);
1551
1552 if (is_long_mode(ctxt->vcpu)) {
1553 cs.d = 0;
1554 cs.l = 1;
1555 }
1556 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1557 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1558 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1559 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1560
1561 c->regs[VCPU_REGS_RCX] = c->eip;
1562 if (is_long_mode(ctxt->vcpu)) {
1563 #ifdef CONFIG_X86_64
1564 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1565
1566 ops->get_msr(ctxt->vcpu,
1567 ctxt->mode == X86EMUL_MODE_PROT64 ?
1568 MSR_LSTAR : MSR_CSTAR, &msr_data);
1569 c->eip = msr_data;
1570
1571 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1572 ctxt->eflags &= ~(msr_data | EFLG_RF);
1573 #endif
1574 } else {
1575 /* legacy mode */
1576 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1577 c->eip = (u32)msr_data;
1578
1579 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1580 }
1581
1582 return X86EMUL_CONTINUE;
1583 }
1584
1585 static int
1586 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1587 {
1588 struct decode_cache *c = &ctxt->decode;
1589 struct desc_struct cs, ss;
1590 u64 msr_data;
1591 u16 cs_sel, ss_sel;
1592
1593 /* inject #GP if in real mode */
1594 if (ctxt->mode == X86EMUL_MODE_REAL) {
1595 emulate_gp(ctxt, 0);
1596 return X86EMUL_PROPAGATE_FAULT;
1597 }
1598
1599 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1600 * Therefore, we inject an #UD.
1601 */
1602 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1603 emulate_ud(ctxt);
1604 return X86EMUL_PROPAGATE_FAULT;
1605 }
1606
1607 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1608
1609 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1610 switch (ctxt->mode) {
1611 case X86EMUL_MODE_PROT32:
1612 if ((msr_data & 0xfffc) == 0x0) {
1613 emulate_gp(ctxt, 0);
1614 return X86EMUL_PROPAGATE_FAULT;
1615 }
1616 break;
1617 case X86EMUL_MODE_PROT64:
1618 if (msr_data == 0x0) {
1619 emulate_gp(ctxt, 0);
1620 return X86EMUL_PROPAGATE_FAULT;
1621 }
1622 break;
1623 }
1624
1625 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1626 cs_sel = (u16)msr_data;
1627 cs_sel &= ~SELECTOR_RPL_MASK;
1628 ss_sel = cs_sel + 8;
1629 ss_sel &= ~SELECTOR_RPL_MASK;
1630 if (ctxt->mode == X86EMUL_MODE_PROT64
1631 || is_long_mode(ctxt->vcpu)) {
1632 cs.d = 0;
1633 cs.l = 1;
1634 }
1635
1636 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1637 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1638 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1639 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1640
1641 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1642 c->eip = msr_data;
1643
1644 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1645 c->regs[VCPU_REGS_RSP] = msr_data;
1646
1647 return X86EMUL_CONTINUE;
1648 }
1649
1650 static int
1651 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1652 {
1653 struct decode_cache *c = &ctxt->decode;
1654 struct desc_struct cs, ss;
1655 u64 msr_data;
1656 int usermode;
1657 u16 cs_sel, ss_sel;
1658
1659 /* inject #GP if in real mode or Virtual 8086 mode */
1660 if (ctxt->mode == X86EMUL_MODE_REAL ||
1661 ctxt->mode == X86EMUL_MODE_VM86) {
1662 emulate_gp(ctxt, 0);
1663 return X86EMUL_PROPAGATE_FAULT;
1664 }
1665
1666 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1667
1668 if ((c->rex_prefix & 0x8) != 0x0)
1669 usermode = X86EMUL_MODE_PROT64;
1670 else
1671 usermode = X86EMUL_MODE_PROT32;
1672
1673 cs.dpl = 3;
1674 ss.dpl = 3;
1675 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1676 switch (usermode) {
1677 case X86EMUL_MODE_PROT32:
1678 cs_sel = (u16)(msr_data + 16);
1679 if ((msr_data & 0xfffc) == 0x0) {
1680 emulate_gp(ctxt, 0);
1681 return X86EMUL_PROPAGATE_FAULT;
1682 }
1683 ss_sel = (u16)(msr_data + 24);
1684 break;
1685 case X86EMUL_MODE_PROT64:
1686 cs_sel = (u16)(msr_data + 32);
1687 if (msr_data == 0x0) {
1688 emulate_gp(ctxt, 0);
1689 return X86EMUL_PROPAGATE_FAULT;
1690 }
1691 ss_sel = cs_sel + 8;
1692 cs.d = 0;
1693 cs.l = 1;
1694 break;
1695 }
1696 cs_sel |= SELECTOR_RPL_MASK;
1697 ss_sel |= SELECTOR_RPL_MASK;
1698
1699 ops->set_cached_descriptor(&cs, VCPU_SREG_CS, ctxt->vcpu);
1700 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1701 ops->set_cached_descriptor(&ss, VCPU_SREG_SS, ctxt->vcpu);
1702 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1703
1704 c->eip = c->regs[VCPU_REGS_RDX];
1705 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1706
1707 return X86EMUL_CONTINUE;
1708 }
1709
1710 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1711 struct x86_emulate_ops *ops)
1712 {
1713 int iopl;
1714 if (ctxt->mode == X86EMUL_MODE_REAL)
1715 return false;
1716 if (ctxt->mode == X86EMUL_MODE_VM86)
1717 return true;
1718 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1719 return ops->cpl(ctxt->vcpu) > iopl;
1720 }
1721
1722 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1723 struct x86_emulate_ops *ops,
1724 u16 port, u16 len)
1725 {
1726 struct desc_struct tr_seg;
1727 int r;
1728 u16 io_bitmap_ptr;
1729 u8 perm, bit_idx = port & 0x7;
1730 unsigned mask = (1 << len) - 1;
1731
1732 ops->get_cached_descriptor(&tr_seg, VCPU_SREG_TR, ctxt->vcpu);
1733 if (!tr_seg.p)
1734 return false;
1735 if (desc_limit_scaled(&tr_seg) < 103)
1736 return false;
1737 r = ops->read_std(get_desc_base(&tr_seg) + 102, &io_bitmap_ptr, 2,
1738 ctxt->vcpu, NULL);
1739 if (r != X86EMUL_CONTINUE)
1740 return false;
1741 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1742 return false;
1743 r = ops->read_std(get_desc_base(&tr_seg) + io_bitmap_ptr + port/8,
1744 &perm, 1, ctxt->vcpu, NULL);
1745 if (r != X86EMUL_CONTINUE)
1746 return false;
1747 if ((perm >> bit_idx) & mask)
1748 return false;
1749 return true;
1750 }
1751
1752 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1753 struct x86_emulate_ops *ops,
1754 u16 port, u16 len)
1755 {
1756 if (ctxt->perm_ok)
1757 return true;
1758
1759 if (emulator_bad_iopl(ctxt, ops))
1760 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1761 return false;
1762
1763 ctxt->perm_ok = true;
1764
1765 return true;
1766 }
1767
1768 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1769 struct x86_emulate_ops *ops,
1770 struct tss_segment_16 *tss)
1771 {
1772 struct decode_cache *c = &ctxt->decode;
1773
1774 tss->ip = c->eip;
1775 tss->flag = ctxt->eflags;
1776 tss->ax = c->regs[VCPU_REGS_RAX];
1777 tss->cx = c->regs[VCPU_REGS_RCX];
1778 tss->dx = c->regs[VCPU_REGS_RDX];
1779 tss->bx = c->regs[VCPU_REGS_RBX];
1780 tss->sp = c->regs[VCPU_REGS_RSP];
1781 tss->bp = c->regs[VCPU_REGS_RBP];
1782 tss->si = c->regs[VCPU_REGS_RSI];
1783 tss->di = c->regs[VCPU_REGS_RDI];
1784
1785 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1786 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1787 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1788 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1789 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1790 }
1791
1792 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1793 struct x86_emulate_ops *ops,
1794 struct tss_segment_16 *tss)
1795 {
1796 struct decode_cache *c = &ctxt->decode;
1797 int ret;
1798
1799 c->eip = tss->ip;
1800 ctxt->eflags = tss->flag | 2;
1801 c->regs[VCPU_REGS_RAX] = tss->ax;
1802 c->regs[VCPU_REGS_RCX] = tss->cx;
1803 c->regs[VCPU_REGS_RDX] = tss->dx;
1804 c->regs[VCPU_REGS_RBX] = tss->bx;
1805 c->regs[VCPU_REGS_RSP] = tss->sp;
1806 c->regs[VCPU_REGS_RBP] = tss->bp;
1807 c->regs[VCPU_REGS_RSI] = tss->si;
1808 c->regs[VCPU_REGS_RDI] = tss->di;
1809
1810 /*
1811 * SDM says that segment selectors are loaded before segment
1812 * descriptors
1813 */
1814 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
1815 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1816 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1817 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1818 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1819
1820 /*
1821 * Now load segment descriptors. If fault happenes at this stage
1822 * it is handled in a context of new task
1823 */
1824 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
1825 if (ret != X86EMUL_CONTINUE)
1826 return ret;
1827 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1828 if (ret != X86EMUL_CONTINUE)
1829 return ret;
1830 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1831 if (ret != X86EMUL_CONTINUE)
1832 return ret;
1833 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1834 if (ret != X86EMUL_CONTINUE)
1835 return ret;
1836 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1837 if (ret != X86EMUL_CONTINUE)
1838 return ret;
1839
1840 return X86EMUL_CONTINUE;
1841 }
1842
1843 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
1844 struct x86_emulate_ops *ops,
1845 u16 tss_selector, u16 old_tss_sel,
1846 ulong old_tss_base, struct desc_struct *new_desc)
1847 {
1848 struct tss_segment_16 tss_seg;
1849 int ret;
1850 u32 err, new_tss_base = get_desc_base(new_desc);
1851
1852 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1853 &err);
1854 if (ret == X86EMUL_PROPAGATE_FAULT) {
1855 /* FIXME: need to provide precise fault address */
1856 emulate_pf(ctxt, old_tss_base, err);
1857 return ret;
1858 }
1859
1860 save_state_to_tss16(ctxt, ops, &tss_seg);
1861
1862 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1863 &err);
1864 if (ret == X86EMUL_PROPAGATE_FAULT) {
1865 /* FIXME: need to provide precise fault address */
1866 emulate_pf(ctxt, old_tss_base, err);
1867 return ret;
1868 }
1869
1870 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1871 &err);
1872 if (ret == X86EMUL_PROPAGATE_FAULT) {
1873 /* FIXME: need to provide precise fault address */
1874 emulate_pf(ctxt, new_tss_base, err);
1875 return ret;
1876 }
1877
1878 if (old_tss_sel != 0xffff) {
1879 tss_seg.prev_task_link = old_tss_sel;
1880
1881 ret = ops->write_std(new_tss_base,
1882 &tss_seg.prev_task_link,
1883 sizeof tss_seg.prev_task_link,
1884 ctxt->vcpu, &err);
1885 if (ret == X86EMUL_PROPAGATE_FAULT) {
1886 /* FIXME: need to provide precise fault address */
1887 emulate_pf(ctxt, new_tss_base, err);
1888 return ret;
1889 }
1890 }
1891
1892 return load_state_from_tss16(ctxt, ops, &tss_seg);
1893 }
1894
1895 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
1896 struct x86_emulate_ops *ops,
1897 struct tss_segment_32 *tss)
1898 {
1899 struct decode_cache *c = &ctxt->decode;
1900
1901 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
1902 tss->eip = c->eip;
1903 tss->eflags = ctxt->eflags;
1904 tss->eax = c->regs[VCPU_REGS_RAX];
1905 tss->ecx = c->regs[VCPU_REGS_RCX];
1906 tss->edx = c->regs[VCPU_REGS_RDX];
1907 tss->ebx = c->regs[VCPU_REGS_RBX];
1908 tss->esp = c->regs[VCPU_REGS_RSP];
1909 tss->ebp = c->regs[VCPU_REGS_RBP];
1910 tss->esi = c->regs[VCPU_REGS_RSI];
1911 tss->edi = c->regs[VCPU_REGS_RDI];
1912
1913 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1914 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1915 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1916 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1917 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
1918 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
1919 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1920 }
1921
1922 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
1923 struct x86_emulate_ops *ops,
1924 struct tss_segment_32 *tss)
1925 {
1926 struct decode_cache *c = &ctxt->decode;
1927 int ret;
1928
1929 if (ops->set_cr(3, tss->cr3, ctxt->vcpu)) {
1930 emulate_gp(ctxt, 0);
1931 return X86EMUL_PROPAGATE_FAULT;
1932 }
1933 c->eip = tss->eip;
1934 ctxt->eflags = tss->eflags | 2;
1935 c->regs[VCPU_REGS_RAX] = tss->eax;
1936 c->regs[VCPU_REGS_RCX] = tss->ecx;
1937 c->regs[VCPU_REGS_RDX] = tss->edx;
1938 c->regs[VCPU_REGS_RBX] = tss->ebx;
1939 c->regs[VCPU_REGS_RSP] = tss->esp;
1940 c->regs[VCPU_REGS_RBP] = tss->ebp;
1941 c->regs[VCPU_REGS_RSI] = tss->esi;
1942 c->regs[VCPU_REGS_RDI] = tss->edi;
1943
1944 /*
1945 * SDM says that segment selectors are loaded before segment
1946 * descriptors
1947 */
1948 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
1949 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
1950 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
1951 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
1952 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
1953 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
1954 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
1955
1956 /*
1957 * Now load segment descriptors. If fault happenes at this stage
1958 * it is handled in a context of new task
1959 */
1960 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
1961 if (ret != X86EMUL_CONTINUE)
1962 return ret;
1963 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
1964 if (ret != X86EMUL_CONTINUE)
1965 return ret;
1966 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
1967 if (ret != X86EMUL_CONTINUE)
1968 return ret;
1969 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
1970 if (ret != X86EMUL_CONTINUE)
1971 return ret;
1972 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
1973 if (ret != X86EMUL_CONTINUE)
1974 return ret;
1975 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
1976 if (ret != X86EMUL_CONTINUE)
1977 return ret;
1978 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
1979 if (ret != X86EMUL_CONTINUE)
1980 return ret;
1981
1982 return X86EMUL_CONTINUE;
1983 }
1984
1985 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
1986 struct x86_emulate_ops *ops,
1987 u16 tss_selector, u16 old_tss_sel,
1988 ulong old_tss_base, struct desc_struct *new_desc)
1989 {
1990 struct tss_segment_32 tss_seg;
1991 int ret;
1992 u32 err, new_tss_base = get_desc_base(new_desc);
1993
1994 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
1995 &err);
1996 if (ret == X86EMUL_PROPAGATE_FAULT) {
1997 /* FIXME: need to provide precise fault address */
1998 emulate_pf(ctxt, old_tss_base, err);
1999 return ret;
2000 }
2001
2002 save_state_to_tss32(ctxt, ops, &tss_seg);
2003
2004 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2005 &err);
2006 if (ret == X86EMUL_PROPAGATE_FAULT) {
2007 /* FIXME: need to provide precise fault address */
2008 emulate_pf(ctxt, old_tss_base, err);
2009 return ret;
2010 }
2011
2012 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2013 &err);
2014 if (ret == X86EMUL_PROPAGATE_FAULT) {
2015 /* FIXME: need to provide precise fault address */
2016 emulate_pf(ctxt, new_tss_base, err);
2017 return ret;
2018 }
2019
2020 if (old_tss_sel != 0xffff) {
2021 tss_seg.prev_task_link = old_tss_sel;
2022
2023 ret = ops->write_std(new_tss_base,
2024 &tss_seg.prev_task_link,
2025 sizeof tss_seg.prev_task_link,
2026 ctxt->vcpu, &err);
2027 if (ret == X86EMUL_PROPAGATE_FAULT) {
2028 /* FIXME: need to provide precise fault address */
2029 emulate_pf(ctxt, new_tss_base, err);
2030 return ret;
2031 }
2032 }
2033
2034 return load_state_from_tss32(ctxt, ops, &tss_seg);
2035 }
2036
2037 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2038 struct x86_emulate_ops *ops,
2039 u16 tss_selector, int reason,
2040 bool has_error_code, u32 error_code)
2041 {
2042 struct desc_struct curr_tss_desc, next_tss_desc;
2043 int ret;
2044 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2045 ulong old_tss_base =
2046 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2047 u32 desc_limit;
2048
2049 /* FIXME: old_tss_base == ~0 ? */
2050
2051 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2052 if (ret != X86EMUL_CONTINUE)
2053 return ret;
2054 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2055 if (ret != X86EMUL_CONTINUE)
2056 return ret;
2057
2058 /* FIXME: check that next_tss_desc is tss */
2059
2060 if (reason != TASK_SWITCH_IRET) {
2061 if ((tss_selector & 3) > next_tss_desc.dpl ||
2062 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) {
2063 emulate_gp(ctxt, 0);
2064 return X86EMUL_PROPAGATE_FAULT;
2065 }
2066 }
2067
2068 desc_limit = desc_limit_scaled(&next_tss_desc);
2069 if (!next_tss_desc.p ||
2070 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2071 desc_limit < 0x2b)) {
2072 emulate_ts(ctxt, tss_selector & 0xfffc);
2073 return X86EMUL_PROPAGATE_FAULT;
2074 }
2075
2076 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2077 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2078 write_segment_descriptor(ctxt, ops, old_tss_sel,
2079 &curr_tss_desc);
2080 }
2081
2082 if (reason == TASK_SWITCH_IRET)
2083 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2084
2085 /* set back link to prev task only if NT bit is set in eflags
2086 note that old_tss_sel is not used afetr this point */
2087 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2088 old_tss_sel = 0xffff;
2089
2090 if (next_tss_desc.type & 8)
2091 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2092 old_tss_base, &next_tss_desc);
2093 else
2094 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2095 old_tss_base, &next_tss_desc);
2096 if (ret != X86EMUL_CONTINUE)
2097 return ret;
2098
2099 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2100 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2101
2102 if (reason != TASK_SWITCH_IRET) {
2103 next_tss_desc.type |= (1 << 1); /* set busy flag */
2104 write_segment_descriptor(ctxt, ops, tss_selector,
2105 &next_tss_desc);
2106 }
2107
2108 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2109 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu);
2110 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2111
2112 if (has_error_code) {
2113 struct decode_cache *c = &ctxt->decode;
2114
2115 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2116 c->lock_prefix = 0;
2117 c->src.val = (unsigned long) error_code;
2118 emulate_push(ctxt, ops);
2119 }
2120
2121 return ret;
2122 }
2123
2124 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2125 u16 tss_selector, int reason,
2126 bool has_error_code, u32 error_code)
2127 {
2128 struct x86_emulate_ops *ops = ctxt->ops;
2129 struct decode_cache *c = &ctxt->decode;
2130 int rc;
2131
2132 c->eip = ctxt->eip;
2133 c->dst.type = OP_NONE;
2134
2135 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2136 has_error_code, error_code);
2137
2138 if (rc == X86EMUL_CONTINUE) {
2139 rc = writeback(ctxt, ops);
2140 if (rc == X86EMUL_CONTINUE)
2141 ctxt->eip = c->eip;
2142 }
2143
2144 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2145 }
2146
2147 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base,
2148 int reg, struct operand *op)
2149 {
2150 struct decode_cache *c = &ctxt->decode;
2151 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2152
2153 register_address_increment(c, &c->regs[reg], df * op->bytes);
2154 op->addr.mem = register_address(c, base, c->regs[reg]);
2155 }
2156
2157 static int em_push(struct x86_emulate_ctxt *ctxt)
2158 {
2159 emulate_push(ctxt, ctxt->ops);
2160 return X86EMUL_CONTINUE;
2161 }
2162
2163 #define D(_y) { .flags = (_y) }
2164 #define N D(0)
2165 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2166 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2167 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2168
2169 static struct opcode group1[] = {
2170 X7(D(Lock)), N
2171 };
2172
2173 static struct opcode group1A[] = {
2174 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2175 };
2176
2177 static struct opcode group3[] = {
2178 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2179 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2180 X4(D(SrcMem | ModRM)),
2181 };
2182
2183 static struct opcode group4[] = {
2184 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2185 N, N, N, N, N, N,
2186 };
2187
2188 static struct opcode group5[] = {
2189 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2190 D(SrcMem | ModRM | Stack), N,
2191 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2192 D(SrcMem | ModRM | Stack), N,
2193 };
2194
2195 static struct group_dual group7 = { {
2196 N, N, D(ModRM | SrcMem | Priv), D(ModRM | SrcMem | Priv),
2197 D(SrcNone | ModRM | DstMem | Mov), N,
2198 D(SrcMem16 | ModRM | Mov | Priv),
2199 D(SrcMem | ModRM | ByteOp | Priv | NoAccess),
2200 }, {
2201 D(SrcNone | ModRM | Priv), N, N, D(SrcNone | ModRM | Priv),
2202 D(SrcNone | ModRM | DstMem | Mov), N,
2203 D(SrcMem16 | ModRM | Mov | Priv), N,
2204 } };
2205
2206 static struct opcode group8[] = {
2207 N, N, N, N,
2208 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2209 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2210 };
2211
2212 static struct group_dual group9 = { {
2213 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2214 }, {
2215 N, N, N, N, N, N, N, N,
2216 } };
2217
2218 static struct opcode opcode_table[256] = {
2219 /* 0x00 - 0x07 */
2220 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2221 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2222 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2223 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2224 /* 0x08 - 0x0F */
2225 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2226 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2227 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2228 D(ImplicitOps | Stack | No64), N,
2229 /* 0x10 - 0x17 */
2230 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2231 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2232 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2233 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2234 /* 0x18 - 0x1F */
2235 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2236 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2237 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2238 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2239 /* 0x20 - 0x27 */
2240 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2241 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2242 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2243 /* 0x28 - 0x2F */
2244 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2245 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2246 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2247 /* 0x30 - 0x37 */
2248 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2249 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2250 D(ByteOp | DstAcc | SrcImmByte), D(DstAcc | SrcImm), N, N,
2251 /* 0x38 - 0x3F */
2252 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2253 D(ByteOp | DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2254 D(ByteOp | DstAcc | SrcImm), D(DstAcc | SrcImm),
2255 N, N,
2256 /* 0x40 - 0x4F */
2257 X16(D(DstReg)),
2258 /* 0x50 - 0x57 */
2259 X8(I(SrcReg | Stack, em_push)),
2260 /* 0x58 - 0x5F */
2261 X8(D(DstReg | Stack)),
2262 /* 0x60 - 0x67 */
2263 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2264 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2265 N, N, N, N,
2266 /* 0x68 - 0x6F */
2267 I(SrcImm | Mov | Stack, em_push), N,
2268 I(SrcImmByte | Mov | Stack, em_push), N,
2269 D(DstDI | ByteOp | Mov | String), D(DstDI | Mov | String), /* insb, insw/insd */
2270 D(SrcSI | ByteOp | ImplicitOps | String), D(SrcSI | ImplicitOps | String), /* outsb, outsw/outsd */
2271 /* 0x70 - 0x7F */
2272 X16(D(SrcImmByte)),
2273 /* 0x80 - 0x87 */
2274 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2275 G(DstMem | SrcImm | ModRM | Group, group1),
2276 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2277 G(DstMem | SrcImmByte | ModRM | Group, group1),
2278 D(ByteOp | DstMem | SrcReg | ModRM), D(DstMem | SrcReg | ModRM),
2279 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2280 /* 0x88 - 0x8F */
2281 D(ByteOp | DstMem | SrcReg | ModRM | Mov), D(DstMem | SrcReg | ModRM | Mov),
2282 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem | ModRM | Mov),
2283 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2284 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2285 /* 0x90 - 0x97 */
2286 X8(D(SrcAcc | DstReg)),
2287 /* 0x98 - 0x9F */
2288 N, N, D(SrcImmFAddr | No64), N,
2289 D(ImplicitOps | Stack), D(ImplicitOps | Stack), N, N,
2290 /* 0xA0 - 0xA7 */
2291 D(ByteOp | DstAcc | SrcMem | Mov | MemAbs), D(DstAcc | SrcMem | Mov | MemAbs),
2292 D(ByteOp | DstMem | SrcAcc | Mov | MemAbs), D(DstMem | SrcAcc | Mov | MemAbs),
2293 D(ByteOp | SrcSI | DstDI | Mov | String), D(SrcSI | DstDI | Mov | String),
2294 D(ByteOp | SrcSI | DstDI | String), D(SrcSI | DstDI | String),
2295 /* 0xA8 - 0xAF */
2296 D(DstAcc | SrcImmByte | ByteOp), D(DstAcc | SrcImm),
2297 D(ByteOp | SrcAcc | DstDI | Mov | String), D(SrcAcc | DstDI | Mov | String),
2298 D(ByteOp | SrcSI | DstAcc | Mov | String), D(SrcSI | DstAcc | Mov | String),
2299 D(ByteOp | DstDI | String), D(DstDI | String),
2300 /* 0xB0 - 0xB7 */
2301 X8(D(ByteOp | DstReg | SrcImm | Mov)),
2302 /* 0xB8 - 0xBF */
2303 X8(D(DstReg | SrcImm | Mov)),
2304 /* 0xC0 - 0xC7 */
2305 D(ByteOp | DstMem | SrcImm | ModRM), D(DstMem | SrcImmByte | ModRM),
2306 N, D(ImplicitOps | Stack), N, N,
2307 D(ByteOp | DstMem | SrcImm | ModRM | Mov), D(DstMem | SrcImm | ModRM | Mov),
2308 /* 0xC8 - 0xCF */
2309 N, N, N, D(ImplicitOps | Stack),
2310 D(ImplicitOps), D(SrcImmByte), D(ImplicitOps | No64), D(ImplicitOps),
2311 /* 0xD0 - 0xD7 */
2312 D(ByteOp | DstMem | SrcOne | ModRM), D(DstMem | SrcOne | ModRM),
2313 D(ByteOp | DstMem | SrcImplicit | ModRM), D(DstMem | SrcImplicit | ModRM),
2314 N, N, N, N,
2315 /* 0xD8 - 0xDF */
2316 N, N, N, N, N, N, N, N,
2317 /* 0xE0 - 0xE7 */
2318 N, N, N, N,
2319 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2320 D(ByteOp | SrcImmUByte | DstAcc), D(SrcImmUByte | DstAcc),
2321 /* 0xE8 - 0xEF */
2322 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2323 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2324 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2325 D(SrcNone | ByteOp | DstAcc), D(SrcNone | DstAcc),
2326 /* 0xF0 - 0xF7 */
2327 N, N, N, N,
2328 D(ImplicitOps | Priv), D(ImplicitOps), G(ByteOp, group3), G(0, group3),
2329 /* 0xF8 - 0xFF */
2330 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2331 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2332 };
2333
2334 static struct opcode twobyte_table[256] = {
2335 /* 0x00 - 0x0F */
2336 N, GD(0, &group7), N, N,
2337 N, D(ImplicitOps), D(ImplicitOps | Priv), N,
2338 D(ImplicitOps | Priv), D(ImplicitOps | Priv), N, N,
2339 N, D(ImplicitOps | ModRM), N, N,
2340 /* 0x10 - 0x1F */
2341 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2342 /* 0x20 - 0x2F */
2343 D(ModRM | DstMem | Priv | Op3264), D(ModRM | DstMem | Priv | Op3264),
2344 D(ModRM | SrcMem | Priv | Op3264), D(ModRM | SrcMem | Priv | Op3264),
2345 N, N, N, N,
2346 N, N, N, N, N, N, N, N,
2347 /* 0x30 - 0x3F */
2348 D(ImplicitOps | Priv), N, D(ImplicitOps | Priv), N,
2349 D(ImplicitOps), D(ImplicitOps | Priv), N, N,
2350 N, N, N, N, N, N, N, N,
2351 /* 0x40 - 0x4F */
2352 X16(D(DstReg | SrcMem | ModRM | Mov)),
2353 /* 0x50 - 0x5F */
2354 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2355 /* 0x60 - 0x6F */
2356 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2357 /* 0x70 - 0x7F */
2358 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2359 /* 0x80 - 0x8F */
2360 X16(D(SrcImm)),
2361 /* 0x90 - 0x9F */
2362 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2363 /* 0xA0 - 0xA7 */
2364 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2365 N, D(DstMem | SrcReg | ModRM | BitOp),
2366 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2367 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2368 /* 0xA8 - 0xAF */
2369 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2370 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2371 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2372 D(DstMem | SrcReg | Src2CL | ModRM),
2373 D(ModRM), N,
2374 /* 0xB0 - 0xB7 */
2375 D(ByteOp | DstMem | SrcReg | ModRM | Lock), D(DstMem | SrcReg | ModRM | Lock),
2376 N, D(DstMem | SrcReg | ModRM | BitOp | Lock),
2377 N, N, D(ByteOp | DstReg | SrcMem | ModRM | Mov),
2378 D(DstReg | SrcMem16 | ModRM | Mov),
2379 /* 0xB8 - 0xBF */
2380 N, N,
2381 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2382 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2383 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2384 /* 0xC0 - 0xCF */
2385 N, N, N, D(DstMem | SrcReg | ModRM | Mov),
2386 N, N, N, GD(0, &group9),
2387 N, N, N, N, N, N, N, N,
2388 /* 0xD0 - 0xDF */
2389 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2390 /* 0xE0 - 0xEF */
2391 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2392 /* 0xF0 - 0xFF */
2393 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2394 };
2395
2396 #undef D
2397 #undef N
2398 #undef G
2399 #undef GD
2400 #undef I
2401
2402 int
2403 x86_decode_insn(struct x86_emulate_ctxt *ctxt)
2404 {
2405 struct x86_emulate_ops *ops = ctxt->ops;
2406 struct decode_cache *c = &ctxt->decode;
2407 int rc = X86EMUL_CONTINUE;
2408 int mode = ctxt->mode;
2409 int def_op_bytes, def_ad_bytes, dual, goffset;
2410 struct opcode opcode, *g_mod012, *g_mod3;
2411 struct operand memop = { .type = OP_NONE };
2412
2413 /* we cannot decode insn before we complete previous rep insn */
2414 WARN_ON(ctxt->restart);
2415
2416 c->eip = ctxt->eip;
2417 c->fetch.start = c->fetch.end = c->eip;
2418 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
2419
2420 switch (mode) {
2421 case X86EMUL_MODE_REAL:
2422 case X86EMUL_MODE_VM86:
2423 case X86EMUL_MODE_PROT16:
2424 def_op_bytes = def_ad_bytes = 2;
2425 break;
2426 case X86EMUL_MODE_PROT32:
2427 def_op_bytes = def_ad_bytes = 4;
2428 break;
2429 #ifdef CONFIG_X86_64
2430 case X86EMUL_MODE_PROT64:
2431 def_op_bytes = 4;
2432 def_ad_bytes = 8;
2433 break;
2434 #endif
2435 default:
2436 return -1;
2437 }
2438
2439 c->op_bytes = def_op_bytes;
2440 c->ad_bytes = def_ad_bytes;
2441
2442 /* Legacy prefixes. */
2443 for (;;) {
2444 switch (c->b = insn_fetch(u8, 1, c->eip)) {
2445 case 0x66: /* operand-size override */
2446 /* switch between 2/4 bytes */
2447 c->op_bytes = def_op_bytes ^ 6;
2448 break;
2449 case 0x67: /* address-size override */
2450 if (mode == X86EMUL_MODE_PROT64)
2451 /* switch between 4/8 bytes */
2452 c->ad_bytes = def_ad_bytes ^ 12;
2453 else
2454 /* switch between 2/4 bytes */
2455 c->ad_bytes = def_ad_bytes ^ 6;
2456 break;
2457 case 0x26: /* ES override */
2458 case 0x2e: /* CS override */
2459 case 0x36: /* SS override */
2460 case 0x3e: /* DS override */
2461 set_seg_override(c, (c->b >> 3) & 3);
2462 break;
2463 case 0x64: /* FS override */
2464 case 0x65: /* GS override */
2465 set_seg_override(c, c->b & 7);
2466 break;
2467 case 0x40 ... 0x4f: /* REX */
2468 if (mode != X86EMUL_MODE_PROT64)
2469 goto done_prefixes;
2470 c->rex_prefix = c->b;
2471 continue;
2472 case 0xf0: /* LOCK */
2473 c->lock_prefix = 1;
2474 break;
2475 case 0xf2: /* REPNE/REPNZ */
2476 c->rep_prefix = REPNE_PREFIX;
2477 break;
2478 case 0xf3: /* REP/REPE/REPZ */
2479 c->rep_prefix = REPE_PREFIX;
2480 break;
2481 default:
2482 goto done_prefixes;
2483 }
2484
2485 /* Any legacy prefix after a REX prefix nullifies its effect. */
2486
2487 c->rex_prefix = 0;
2488 }
2489
2490 done_prefixes:
2491
2492 /* REX prefix. */
2493 if (c->rex_prefix & 8)
2494 c->op_bytes = 8; /* REX.W */
2495
2496 /* Opcode byte(s). */
2497 opcode = opcode_table[c->b];
2498 /* Two-byte opcode? */
2499 if (c->b == 0x0f) {
2500 c->twobyte = 1;
2501 c->b = insn_fetch(u8, 1, c->eip);
2502 opcode = twobyte_table[c->b];
2503 }
2504 c->d = opcode.flags;
2505
2506 if (c->d & Group) {
2507 dual = c->d & GroupDual;
2508 c->modrm = insn_fetch(u8, 1, c->eip);
2509 --c->eip;
2510
2511 if (c->d & GroupDual) {
2512 g_mod012 = opcode.u.gdual->mod012;
2513 g_mod3 = opcode.u.gdual->mod3;
2514 } else
2515 g_mod012 = g_mod3 = opcode.u.group;
2516
2517 c->d &= ~(Group | GroupDual);
2518
2519 goffset = (c->modrm >> 3) & 7;
2520
2521 if ((c->modrm >> 6) == 3)
2522 opcode = g_mod3[goffset];
2523 else
2524 opcode = g_mod012[goffset];
2525 c->d |= opcode.flags;
2526 }
2527
2528 c->execute = opcode.u.execute;
2529
2530 /* Unrecognised? */
2531 if (c->d == 0 || (c->d & Undefined)) {
2532 DPRINTF("Cannot emulate %02x\n", c->b);
2533 return -1;
2534 }
2535
2536 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
2537 c->op_bytes = 8;
2538
2539 if (c->d & Op3264) {
2540 if (mode == X86EMUL_MODE_PROT64)
2541 c->op_bytes = 8;
2542 else
2543 c->op_bytes = 4;
2544 }
2545
2546 /* ModRM and SIB bytes. */
2547 if (c->d & ModRM) {
2548 rc = decode_modrm(ctxt, ops, &memop);
2549 if (!c->has_seg_override)
2550 set_seg_override(c, c->modrm_seg);
2551 } else if (c->d & MemAbs)
2552 rc = decode_abs(ctxt, ops, &memop);
2553 if (rc != X86EMUL_CONTINUE)
2554 goto done;
2555
2556 if (!c->has_seg_override)
2557 set_seg_override(c, VCPU_SREG_DS);
2558
2559 if (memop.type == OP_MEM && !(!c->twobyte && c->b == 0x8d))
2560 memop.addr.mem += seg_override_base(ctxt, ops, c);
2561
2562 if (memop.type == OP_MEM && c->ad_bytes != 8)
2563 memop.addr.mem = (u32)memop.addr.mem;
2564
2565 if (memop.type == OP_MEM && c->rip_relative)
2566 memop.addr.mem += c->eip;
2567
2568 /*
2569 * Decode and fetch the source operand: register, memory
2570 * or immediate.
2571 */
2572 switch (c->d & SrcMask) {
2573 case SrcNone:
2574 break;
2575 case SrcReg:
2576 decode_register_operand(&c->src, c, 0);
2577 break;
2578 case SrcMem16:
2579 memop.bytes = 2;
2580 goto srcmem_common;
2581 case SrcMem32:
2582 memop.bytes = 4;
2583 goto srcmem_common;
2584 case SrcMem:
2585 memop.bytes = (c->d & ByteOp) ? 1 :
2586 c->op_bytes;
2587 srcmem_common:
2588 c->src = memop;
2589 break;
2590 case SrcImm:
2591 case SrcImmU:
2592 c->src.type = OP_IMM;
2593 c->src.addr.mem = c->eip;
2594 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2595 if (c->src.bytes == 8)
2596 c->src.bytes = 4;
2597 /* NB. Immediates are sign-extended as necessary. */
2598 switch (c->src.bytes) {
2599 case 1:
2600 c->src.val = insn_fetch(s8, 1, c->eip);
2601 break;
2602 case 2:
2603 c->src.val = insn_fetch(s16, 2, c->eip);
2604 break;
2605 case 4:
2606 c->src.val = insn_fetch(s32, 4, c->eip);
2607 break;
2608 }
2609 if ((c->d & SrcMask) == SrcImmU) {
2610 switch (c->src.bytes) {
2611 case 1:
2612 c->src.val &= 0xff;
2613 break;
2614 case 2:
2615 c->src.val &= 0xffff;
2616 break;
2617 case 4:
2618 c->src.val &= 0xffffffff;
2619 break;
2620 }
2621 }
2622 break;
2623 case SrcImmByte:
2624 case SrcImmUByte:
2625 c->src.type = OP_IMM;
2626 c->src.addr.mem = c->eip;
2627 c->src.bytes = 1;
2628 if ((c->d & SrcMask) == SrcImmByte)
2629 c->src.val = insn_fetch(s8, 1, c->eip);
2630 else
2631 c->src.val = insn_fetch(u8, 1, c->eip);
2632 break;
2633 case SrcAcc:
2634 c->src.type = OP_REG;
2635 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2636 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
2637 fetch_register_operand(&c->src);
2638 break;
2639 case SrcOne:
2640 c->src.bytes = 1;
2641 c->src.val = 1;
2642 break;
2643 case SrcSI:
2644 c->src.type = OP_MEM;
2645 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2646 c->src.addr.mem =
2647 register_address(c, seg_override_base(ctxt, ops, c),
2648 c->regs[VCPU_REGS_RSI]);
2649 c->src.val = 0;
2650 break;
2651 case SrcImmFAddr:
2652 c->src.type = OP_IMM;
2653 c->src.addr.mem = c->eip;
2654 c->src.bytes = c->op_bytes + 2;
2655 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
2656 break;
2657 case SrcMemFAddr:
2658 memop.bytes = c->op_bytes + 2;
2659 goto srcmem_common;
2660 break;
2661 }
2662
2663 /*
2664 * Decode and fetch the second source operand: register, memory
2665 * or immediate.
2666 */
2667 switch (c->d & Src2Mask) {
2668 case Src2None:
2669 break;
2670 case Src2CL:
2671 c->src2.bytes = 1;
2672 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
2673 break;
2674 case Src2ImmByte:
2675 c->src2.type = OP_IMM;
2676 c->src2.addr.mem = c->eip;
2677 c->src2.bytes = 1;
2678 c->src2.val = insn_fetch(u8, 1, c->eip);
2679 break;
2680 case Src2One:
2681 c->src2.bytes = 1;
2682 c->src2.val = 1;
2683 break;
2684 }
2685
2686 /* Decode and fetch the destination operand: register or memory. */
2687 switch (c->d & DstMask) {
2688 case DstReg:
2689 decode_register_operand(&c->dst, c,
2690 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
2691 break;
2692 case DstMem:
2693 case DstMem64:
2694 c->dst = memop;
2695 if ((c->d & DstMask) == DstMem64)
2696 c->dst.bytes = 8;
2697 else
2698 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2699 if (c->d & BitOp)
2700 fetch_bit_operand(c);
2701 c->dst.orig_val = c->dst.val;
2702 break;
2703 case DstAcc:
2704 c->dst.type = OP_REG;
2705 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2706 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
2707 fetch_register_operand(&c->dst);
2708 c->dst.orig_val = c->dst.val;
2709 break;
2710 case DstDI:
2711 c->dst.type = OP_MEM;
2712 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
2713 c->dst.addr.mem =
2714 register_address(c, es_base(ctxt, ops),
2715 c->regs[VCPU_REGS_RDI]);
2716 c->dst.val = 0;
2717 break;
2718 case ImplicitOps:
2719 /* Special instructions do their own operand decoding. */
2720 default:
2721 c->dst.type = OP_NONE; /* Disable writeback. */
2722 return 0;
2723 }
2724
2725 done:
2726 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
2727 }
2728
2729 int
2730 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
2731 {
2732 struct x86_emulate_ops *ops = ctxt->ops;
2733 u64 msr_data;
2734 struct decode_cache *c = &ctxt->decode;
2735 int rc = X86EMUL_CONTINUE;
2736 int saved_dst_type = c->dst.type;
2737 int irq; /* Used for int 3, int, and into */
2738
2739 ctxt->decode.mem_read.pos = 0;
2740
2741 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
2742 emulate_ud(ctxt);
2743 goto done;
2744 }
2745
2746 /* LOCK prefix is allowed only with some instructions */
2747 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
2748 emulate_ud(ctxt);
2749 goto done;
2750 }
2751
2752 /* Privileged instruction can be executed only in CPL=0 */
2753 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
2754 emulate_gp(ctxt, 0);
2755 goto done;
2756 }
2757
2758 if (c->rep_prefix && (c->d & String)) {
2759 ctxt->restart = true;
2760 /* All REP prefixes have the same first termination condition */
2761 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
2762 string_done:
2763 ctxt->restart = false;
2764 ctxt->eip = c->eip;
2765 goto done;
2766 }
2767 /* The second termination condition only applies for REPE
2768 * and REPNE. Test if the repeat string operation prefix is
2769 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
2770 * corresponding termination condition according to:
2771 * - if REPE/REPZ and ZF = 0 then done
2772 * - if REPNE/REPNZ and ZF = 1 then done
2773 */
2774 if ((c->b == 0xa6) || (c->b == 0xa7) ||
2775 (c->b == 0xae) || (c->b == 0xaf)) {
2776 if ((c->rep_prefix == REPE_PREFIX) &&
2777 ((ctxt->eflags & EFLG_ZF) == 0))
2778 goto string_done;
2779 if ((c->rep_prefix == REPNE_PREFIX) &&
2780 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))
2781 goto string_done;
2782 }
2783 c->eip = ctxt->eip;
2784 }
2785
2786 if (c->src.type == OP_MEM) {
2787 if (c->d & NoAccess)
2788 goto no_fetch;
2789 rc = read_emulated(ctxt, ops, c->src.addr.mem,
2790 c->src.valptr, c->src.bytes);
2791 if (rc != X86EMUL_CONTINUE)
2792 goto done;
2793 c->src.orig_val64 = c->src.val64;
2794 no_fetch:
2795 ;
2796 }
2797
2798 if (c->src2.type == OP_MEM) {
2799 rc = read_emulated(ctxt, ops, c->src2.addr.mem,
2800 &c->src2.val, c->src2.bytes);
2801 if (rc != X86EMUL_CONTINUE)
2802 goto done;
2803 }
2804
2805 if ((c->d & DstMask) == ImplicitOps)
2806 goto special_insn;
2807
2808
2809 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
2810 /* optimisation - avoid slow emulated read if Mov */
2811 rc = read_emulated(ctxt, ops, c->dst.addr.mem,
2812 &c->dst.val, c->dst.bytes);
2813 if (rc != X86EMUL_CONTINUE)
2814 goto done;
2815 }
2816 c->dst.orig_val = c->dst.val;
2817
2818 special_insn:
2819
2820 if (c->execute) {
2821 rc = c->execute(ctxt);
2822 if (rc != X86EMUL_CONTINUE)
2823 goto done;
2824 goto writeback;
2825 }
2826
2827 if (c->twobyte)
2828 goto twobyte_insn;
2829
2830 switch (c->b) {
2831 case 0x00 ... 0x05:
2832 add: /* add */
2833 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
2834 break;
2835 case 0x06: /* push es */
2836 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
2837 break;
2838 case 0x07: /* pop es */
2839 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
2840 if (rc != X86EMUL_CONTINUE)
2841 goto done;
2842 break;
2843 case 0x08 ... 0x0d:
2844 or: /* or */
2845 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2846 break;
2847 case 0x0e: /* push cs */
2848 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
2849 break;
2850 case 0x10 ... 0x15:
2851 adc: /* adc */
2852 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
2853 break;
2854 case 0x16: /* push ss */
2855 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
2856 break;
2857 case 0x17: /* pop ss */
2858 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
2859 if (rc != X86EMUL_CONTINUE)
2860 goto done;
2861 break;
2862 case 0x18 ... 0x1d:
2863 sbb: /* sbb */
2864 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
2865 break;
2866 case 0x1e: /* push ds */
2867 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
2868 break;
2869 case 0x1f: /* pop ds */
2870 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
2871 if (rc != X86EMUL_CONTINUE)
2872 goto done;
2873 break;
2874 case 0x20 ... 0x25:
2875 and: /* and */
2876 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
2877 break;
2878 case 0x28 ... 0x2d:
2879 sub: /* sub */
2880 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
2881 break;
2882 case 0x30 ... 0x35:
2883 xor: /* xor */
2884 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
2885 break;
2886 case 0x38 ... 0x3d:
2887 cmp: /* cmp */
2888 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2889 break;
2890 case 0x40 ... 0x47: /* inc r16/r32 */
2891 emulate_1op("inc", c->dst, ctxt->eflags);
2892 break;
2893 case 0x48 ... 0x4f: /* dec r16/r32 */
2894 emulate_1op("dec", c->dst, ctxt->eflags);
2895 break;
2896 case 0x58 ... 0x5f: /* pop reg */
2897 pop_instruction:
2898 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
2899 if (rc != X86EMUL_CONTINUE)
2900 goto done;
2901 break;
2902 case 0x60: /* pusha */
2903 rc = emulate_pusha(ctxt, ops);
2904 if (rc != X86EMUL_CONTINUE)
2905 goto done;
2906 break;
2907 case 0x61: /* popa */
2908 rc = emulate_popa(ctxt, ops);
2909 if (rc != X86EMUL_CONTINUE)
2910 goto done;
2911 break;
2912 case 0x63: /* movsxd */
2913 if (ctxt->mode != X86EMUL_MODE_PROT64)
2914 goto cannot_emulate;
2915 c->dst.val = (s32) c->src.val;
2916 break;
2917 case 0x6c: /* insb */
2918 case 0x6d: /* insw/insd */
2919 c->dst.bytes = min(c->dst.bytes, 4u);
2920 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2921 c->dst.bytes)) {
2922 emulate_gp(ctxt, 0);
2923 goto done;
2924 }
2925 if (!pio_in_emulated(ctxt, ops, c->dst.bytes,
2926 c->regs[VCPU_REGS_RDX], &c->dst.val))
2927 goto done; /* IO is needed, skip writeback */
2928 break;
2929 case 0x6e: /* outsb */
2930 case 0x6f: /* outsw/outsd */
2931 c->src.bytes = min(c->src.bytes, 4u);
2932 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX],
2933 c->src.bytes)) {
2934 emulate_gp(ctxt, 0);
2935 goto done;
2936 }
2937 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX],
2938 &c->src.val, 1, ctxt->vcpu);
2939
2940 c->dst.type = OP_NONE; /* nothing to writeback */
2941 break;
2942 case 0x70 ... 0x7f: /* jcc (short) */
2943 if (test_cc(c->b, ctxt->eflags))
2944 jmp_rel(c, c->src.val);
2945 break;
2946 case 0x80 ... 0x83: /* Grp1 */
2947 switch (c->modrm_reg) {
2948 case 0:
2949 goto add;
2950 case 1:
2951 goto or;
2952 case 2:
2953 goto adc;
2954 case 3:
2955 goto sbb;
2956 case 4:
2957 goto and;
2958 case 5:
2959 goto sub;
2960 case 6:
2961 goto xor;
2962 case 7:
2963 goto cmp;
2964 }
2965 break;
2966 case 0x84 ... 0x85:
2967 test:
2968 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
2969 break;
2970 case 0x86 ... 0x87: /* xchg */
2971 xchg:
2972 /* Write back the register source. */
2973 switch (c->dst.bytes) {
2974 case 1:
2975 *(u8 *) c->src.addr.reg = (u8) c->dst.val;
2976 break;
2977 case 2:
2978 *(u16 *) c->src.addr.reg = (u16) c->dst.val;
2979 break;
2980 case 4:
2981 *c->src.addr.reg = (u32) c->dst.val;
2982 break; /* 64b reg: zero-extend */
2983 case 8:
2984 *c->src.addr.reg = c->dst.val;
2985 break;
2986 }
2987 /*
2988 * Write back the memory destination with implicit LOCK
2989 * prefix.
2990 */
2991 c->dst.val = c->src.val;
2992 c->lock_prefix = 1;
2993 break;
2994 case 0x88 ... 0x8b: /* mov */
2995 goto mov;
2996 case 0x8c: /* mov r/m, sreg */
2997 if (c->modrm_reg > VCPU_SREG_GS) {
2998 emulate_ud(ctxt);
2999 goto done;
3000 }
3001 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3002 break;
3003 case 0x8d: /* lea r16/r32, m */
3004 c->dst.val = c->src.addr.mem;
3005 break;
3006 case 0x8e: { /* mov seg, r/m16 */
3007 uint16_t sel;
3008
3009 sel = c->src.val;
3010
3011 if (c->modrm_reg == VCPU_SREG_CS ||
3012 c->modrm_reg > VCPU_SREG_GS) {
3013 emulate_ud(ctxt);
3014 goto done;
3015 }
3016
3017 if (c->modrm_reg == VCPU_SREG_SS)
3018 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3019
3020 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3021
3022 c->dst.type = OP_NONE; /* Disable writeback. */
3023 break;
3024 }
3025 case 0x8f: /* pop (sole member of Grp1a) */
3026 rc = emulate_grp1a(ctxt, ops);
3027 if (rc != X86EMUL_CONTINUE)
3028 goto done;
3029 break;
3030 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3031 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3032 break;
3033 goto xchg;
3034 case 0x9c: /* pushf */
3035 c->src.val = (unsigned long) ctxt->eflags;
3036 emulate_push(ctxt, ops);
3037 break;
3038 case 0x9d: /* popf */
3039 c->dst.type = OP_REG;
3040 c->dst.addr.reg = &ctxt->eflags;
3041 c->dst.bytes = c->op_bytes;
3042 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3043 if (rc != X86EMUL_CONTINUE)
3044 goto done;
3045 break;
3046 case 0xa0 ... 0xa3: /* mov */
3047 case 0xa4 ... 0xa5: /* movs */
3048 goto mov;
3049 case 0xa6 ... 0xa7: /* cmps */
3050 c->dst.type = OP_NONE; /* Disable writeback. */
3051 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.addr.mem, c->dst.addr.mem);
3052 goto cmp;
3053 case 0xa8 ... 0xa9: /* test ax, imm */
3054 goto test;
3055 case 0xaa ... 0xab: /* stos */
3056 case 0xac ... 0xad: /* lods */
3057 goto mov;
3058 case 0xae ... 0xaf: /* scas */
3059 DPRINTF("Urk! I don't handle SCAS.\n");
3060 goto cannot_emulate;
3061 case 0xb0 ... 0xbf: /* mov r, imm */
3062 goto mov;
3063 case 0xc0 ... 0xc1:
3064 emulate_grp2(ctxt);
3065 break;
3066 case 0xc3: /* ret */
3067 c->dst.type = OP_REG;
3068 c->dst.addr.reg = &c->eip;
3069 c->dst.bytes = c->op_bytes;
3070 goto pop_instruction;
3071 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
3072 mov:
3073 c->dst.val = c->src.val;
3074 break;
3075 case 0xcb: /* ret far */
3076 rc = emulate_ret_far(ctxt, ops);
3077 if (rc != X86EMUL_CONTINUE)
3078 goto done;
3079 break;
3080 case 0xcc: /* int3 */
3081 irq = 3;
3082 goto do_interrupt;
3083 case 0xcd: /* int n */
3084 irq = c->src.val;
3085 do_interrupt:
3086 rc = emulate_int(ctxt, ops, irq);
3087 if (rc != X86EMUL_CONTINUE)
3088 goto done;
3089 break;
3090 case 0xce: /* into */
3091 if (ctxt->eflags & EFLG_OF) {
3092 irq = 4;
3093 goto do_interrupt;
3094 }
3095 break;
3096 case 0xcf: /* iret */
3097 rc = emulate_iret(ctxt, ops);
3098
3099 if (rc != X86EMUL_CONTINUE)
3100 goto done;
3101 break;
3102 case 0xd0 ... 0xd1: /* Grp2 */
3103 emulate_grp2(ctxt);
3104 break;
3105 case 0xd2 ... 0xd3: /* Grp2 */
3106 c->src.val = c->regs[VCPU_REGS_RCX];
3107 emulate_grp2(ctxt);
3108 break;
3109 case 0xe4: /* inb */
3110 case 0xe5: /* in */
3111 goto do_io_in;
3112 case 0xe6: /* outb */
3113 case 0xe7: /* out */
3114 goto do_io_out;
3115 case 0xe8: /* call (near) */ {
3116 long int rel = c->src.val;
3117 c->src.val = (unsigned long) c->eip;
3118 jmp_rel(c, rel);
3119 emulate_push(ctxt, ops);
3120 break;
3121 }
3122 case 0xe9: /* jmp rel */
3123 goto jmp;
3124 case 0xea: { /* jmp far */
3125 unsigned short sel;
3126 jump_far:
3127 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3128
3129 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3130 goto done;
3131
3132 c->eip = 0;
3133 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3134 break;
3135 }
3136 case 0xeb:
3137 jmp: /* jmp rel short */
3138 jmp_rel(c, c->src.val);
3139 c->dst.type = OP_NONE; /* Disable writeback. */
3140 break;
3141 case 0xec: /* in al,dx */
3142 case 0xed: /* in (e/r)ax,dx */
3143 c->src.val = c->regs[VCPU_REGS_RDX];
3144 do_io_in:
3145 c->dst.bytes = min(c->dst.bytes, 4u);
3146 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3147 emulate_gp(ctxt, 0);
3148 goto done;
3149 }
3150 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3151 &c->dst.val))
3152 goto done; /* IO is needed */
3153 break;
3154 case 0xee: /* out dx,al */
3155 case 0xef: /* out dx,(e/r)ax */
3156 c->src.val = c->regs[VCPU_REGS_RDX];
3157 do_io_out:
3158 c->dst.bytes = min(c->dst.bytes, 4u);
3159 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) {
3160 emulate_gp(ctxt, 0);
3161 goto done;
3162 }
3163 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1,
3164 ctxt->vcpu);
3165 c->dst.type = OP_NONE; /* Disable writeback. */
3166 break;
3167 case 0xf4: /* hlt */
3168 ctxt->vcpu->arch.halt_request = 1;
3169 break;
3170 case 0xf5: /* cmc */
3171 /* complement carry flag from eflags reg */
3172 ctxt->eflags ^= EFLG_CF;
3173 break;
3174 case 0xf6 ... 0xf7: /* Grp3 */
3175 if (emulate_grp3(ctxt, ops) != X86EMUL_CONTINUE)
3176 goto cannot_emulate;
3177 break;
3178 case 0xf8: /* clc */
3179 ctxt->eflags &= ~EFLG_CF;
3180 break;
3181 case 0xf9: /* stc */
3182 ctxt->eflags |= EFLG_CF;
3183 break;
3184 case 0xfa: /* cli */
3185 if (emulator_bad_iopl(ctxt, ops)) {
3186 emulate_gp(ctxt, 0);
3187 goto done;
3188 } else
3189 ctxt->eflags &= ~X86_EFLAGS_IF;
3190 break;
3191 case 0xfb: /* sti */
3192 if (emulator_bad_iopl(ctxt, ops)) {
3193 emulate_gp(ctxt, 0);
3194 goto done;
3195 } else {
3196 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3197 ctxt->eflags |= X86_EFLAGS_IF;
3198 }
3199 break;
3200 case 0xfc: /* cld */
3201 ctxt->eflags &= ~EFLG_DF;
3202 break;
3203 case 0xfd: /* std */
3204 ctxt->eflags |= EFLG_DF;
3205 break;
3206 case 0xfe: /* Grp4 */
3207 grp45:
3208 rc = emulate_grp45(ctxt, ops);
3209 if (rc != X86EMUL_CONTINUE)
3210 goto done;
3211 break;
3212 case 0xff: /* Grp5 */
3213 if (c->modrm_reg == 5)
3214 goto jump_far;
3215 goto grp45;
3216 default:
3217 goto cannot_emulate;
3218 }
3219
3220 writeback:
3221 rc = writeback(ctxt, ops);
3222 if (rc != X86EMUL_CONTINUE)
3223 goto done;
3224
3225 /*
3226 * restore dst type in case the decoding will be reused
3227 * (happens for string instruction )
3228 */
3229 c->dst.type = saved_dst_type;
3230
3231 if ((c->d & SrcMask) == SrcSI)
3232 string_addr_inc(ctxt, seg_override_base(ctxt, ops, c),
3233 VCPU_REGS_RSI, &c->src);
3234
3235 if ((c->d & DstMask) == DstDI)
3236 string_addr_inc(ctxt, es_base(ctxt, ops), VCPU_REGS_RDI,
3237 &c->dst);
3238
3239 if (c->rep_prefix && (c->d & String)) {
3240 struct read_cache *rc = &ctxt->decode.io_read;
3241 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3242 /*
3243 * Re-enter guest when pio read ahead buffer is empty or,
3244 * if it is not used, after each 1024 iteration.
3245 */
3246 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) ||
3247 (rc->end != 0 && rc->end == rc->pos))
3248 ctxt->restart = false;
3249 }
3250 /*
3251 * reset read cache here in case string instruction is restared
3252 * without decoding
3253 */
3254 ctxt->decode.mem_read.end = 0;
3255 ctxt->eip = c->eip;
3256
3257 done:
3258 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
3259
3260 twobyte_insn:
3261 switch (c->b) {
3262 case 0x01: /* lgdt, lidt, lmsw */
3263 switch (c->modrm_reg) {
3264 u16 size;
3265 unsigned long address;
3266
3267 case 0: /* vmcall */
3268 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3269 goto cannot_emulate;
3270
3271 rc = kvm_fix_hypercall(ctxt->vcpu);
3272 if (rc != X86EMUL_CONTINUE)
3273 goto done;
3274
3275 /* Let the processor re-execute the fixed hypercall */
3276 c->eip = ctxt->eip;
3277 /* Disable writeback. */
3278 c->dst.type = OP_NONE;
3279 break;
3280 case 2: /* lgdt */
3281 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3282 &size, &address, c->op_bytes);
3283 if (rc != X86EMUL_CONTINUE)
3284 goto done;
3285 realmode_lgdt(ctxt->vcpu, size, address);
3286 /* Disable writeback. */
3287 c->dst.type = OP_NONE;
3288 break;
3289 case 3: /* lidt/vmmcall */
3290 if (c->modrm_mod == 3) {
3291 switch (c->modrm_rm) {
3292 case 1:
3293 rc = kvm_fix_hypercall(ctxt->vcpu);
3294 if (rc != X86EMUL_CONTINUE)
3295 goto done;
3296 break;
3297 default:
3298 goto cannot_emulate;
3299 }
3300 } else {
3301 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3302 &size, &address,
3303 c->op_bytes);
3304 if (rc != X86EMUL_CONTINUE)
3305 goto done;
3306 realmode_lidt(ctxt->vcpu, size, address);
3307 }
3308 /* Disable writeback. */
3309 c->dst.type = OP_NONE;
3310 break;
3311 case 4: /* smsw */
3312 c->dst.bytes = 2;
3313 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3314 break;
3315 case 6: /* lmsw */
3316 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3317 (c->src.val & 0x0f), ctxt->vcpu);
3318 c->dst.type = OP_NONE;
3319 break;
3320 case 5: /* not defined */
3321 emulate_ud(ctxt);
3322 goto done;
3323 case 7: /* invlpg*/
3324 emulate_invlpg(ctxt->vcpu, c->src.addr.mem);
3325 /* Disable writeback. */
3326 c->dst.type = OP_NONE;
3327 break;
3328 default:
3329 goto cannot_emulate;
3330 }
3331 break;
3332 case 0x05: /* syscall */
3333 rc = emulate_syscall(ctxt, ops);
3334 if (rc != X86EMUL_CONTINUE)
3335 goto done;
3336 else
3337 goto writeback;
3338 break;
3339 case 0x06:
3340 emulate_clts(ctxt->vcpu);
3341 break;
3342 case 0x09: /* wbinvd */
3343 kvm_emulate_wbinvd(ctxt->vcpu);
3344 break;
3345 case 0x08: /* invd */
3346 case 0x0d: /* GrpP (prefetch) */
3347 case 0x18: /* Grp16 (prefetch/nop) */
3348 break;
3349 case 0x20: /* mov cr, reg */
3350 switch (c->modrm_reg) {
3351 case 1:
3352 case 5 ... 7:
3353 case 9 ... 15:
3354 emulate_ud(ctxt);
3355 goto done;
3356 }
3357 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3358 break;
3359 case 0x21: /* mov from dr to reg */
3360 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3361 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3362 emulate_ud(ctxt);
3363 goto done;
3364 }
3365 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
3366 break;
3367 case 0x22: /* mov reg, cr */
3368 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
3369 emulate_gp(ctxt, 0);
3370 goto done;
3371 }
3372 c->dst.type = OP_NONE;
3373 break;
3374 case 0x23: /* mov from reg to dr */
3375 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) &&
3376 (c->modrm_reg == 4 || c->modrm_reg == 5)) {
3377 emulate_ud(ctxt);
3378 goto done;
3379 }
3380
3381 if (ops->set_dr(c->modrm_reg, c->src.val &
3382 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
3383 ~0ULL : ~0U), ctxt->vcpu) < 0) {
3384 /* #UD condition is already handled by the code above */
3385 emulate_gp(ctxt, 0);
3386 goto done;
3387 }
3388
3389 c->dst.type = OP_NONE; /* no writeback */
3390 break;
3391 case 0x30:
3392 /* wrmsr */
3393 msr_data = (u32)c->regs[VCPU_REGS_RAX]
3394 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
3395 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
3396 emulate_gp(ctxt, 0);
3397 goto done;
3398 }
3399 rc = X86EMUL_CONTINUE;
3400 break;
3401 case 0x32:
3402 /* rdmsr */
3403 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
3404 emulate_gp(ctxt, 0);
3405 goto done;
3406 } else {
3407 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
3408 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
3409 }
3410 rc = X86EMUL_CONTINUE;
3411 break;
3412 case 0x34: /* sysenter */
3413 rc = emulate_sysenter(ctxt, ops);
3414 if (rc != X86EMUL_CONTINUE)
3415 goto done;
3416 else
3417 goto writeback;
3418 break;
3419 case 0x35: /* sysexit */
3420 rc = emulate_sysexit(ctxt, ops);
3421 if (rc != X86EMUL_CONTINUE)
3422 goto done;
3423 else
3424 goto writeback;
3425 break;
3426 case 0x40 ... 0x4f: /* cmov */
3427 c->dst.val = c->dst.orig_val = c->src.val;
3428 if (!test_cc(c->b, ctxt->eflags))
3429 c->dst.type = OP_NONE; /* no writeback */
3430 break;
3431 case 0x80 ... 0x8f: /* jnz rel, etc*/
3432 if (test_cc(c->b, ctxt->eflags))
3433 jmp_rel(c, c->src.val);
3434 break;
3435 case 0xa0: /* push fs */
3436 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
3437 break;
3438 case 0xa1: /* pop fs */
3439 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
3440 if (rc != X86EMUL_CONTINUE)
3441 goto done;
3442 break;
3443 case 0xa3:
3444 bt: /* bt */
3445 c->dst.type = OP_NONE;
3446 /* only subword offset */
3447 c->src.val &= (c->dst.bytes << 3) - 1;
3448 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
3449 break;
3450 case 0xa4: /* shld imm8, r, r/m */
3451 case 0xa5: /* shld cl, r, r/m */
3452 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
3453 break;
3454 case 0xa8: /* push gs */
3455 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
3456 break;
3457 case 0xa9: /* pop gs */
3458 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
3459 if (rc != X86EMUL_CONTINUE)
3460 goto done;
3461 break;
3462 case 0xab:
3463 bts: /* bts */
3464 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
3465 break;
3466 case 0xac: /* shrd imm8, r, r/m */
3467 case 0xad: /* shrd cl, r, r/m */
3468 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
3469 break;
3470 case 0xae: /* clflush */
3471 break;
3472 case 0xb0 ... 0xb1: /* cmpxchg */
3473 /*
3474 * Save real source value, then compare EAX against
3475 * destination.
3476 */
3477 c->src.orig_val = c->src.val;
3478 c->src.val = c->regs[VCPU_REGS_RAX];
3479 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3480 if (ctxt->eflags & EFLG_ZF) {
3481 /* Success: write back to memory. */
3482 c->dst.val = c->src.orig_val;
3483 } else {
3484 /* Failure: write the value we saw to EAX. */
3485 c->dst.type = OP_REG;
3486 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
3487 }
3488 break;
3489 case 0xb3:
3490 btr: /* btr */
3491 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
3492 break;
3493 case 0xb6 ... 0xb7: /* movzx */
3494 c->dst.bytes = c->op_bytes;
3495 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
3496 : (u16) c->src.val;
3497 break;
3498 case 0xba: /* Grp8 */
3499 switch (c->modrm_reg & 3) {
3500 case 0:
3501 goto bt;
3502 case 1:
3503 goto bts;
3504 case 2:
3505 goto btr;
3506 case 3:
3507 goto btc;
3508 }
3509 break;
3510 case 0xbb:
3511 btc: /* btc */
3512 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
3513 break;
3514 case 0xbc: { /* bsf */
3515 u8 zf;
3516 __asm__ ("bsf %2, %0; setz %1"
3517 : "=r"(c->dst.val), "=q"(zf)
3518 : "r"(c->src.val));
3519 ctxt->eflags &= ~X86_EFLAGS_ZF;
3520 if (zf) {
3521 ctxt->eflags |= X86_EFLAGS_ZF;
3522 c->dst.type = OP_NONE; /* Disable writeback. */
3523 }
3524 break;
3525 }
3526 case 0xbd: { /* bsr */
3527 u8 zf;
3528 __asm__ ("bsr %2, %0; setz %1"
3529 : "=r"(c->dst.val), "=q"(zf)
3530 : "r"(c->src.val));
3531 ctxt->eflags &= ~X86_EFLAGS_ZF;
3532 if (zf) {
3533 ctxt->eflags |= X86_EFLAGS_ZF;
3534 c->dst.type = OP_NONE; /* Disable writeback. */
3535 }
3536 break;
3537 }
3538 case 0xbe ... 0xbf: /* movsx */
3539 c->dst.bytes = c->op_bytes;
3540 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
3541 (s16) c->src.val;
3542 break;
3543 case 0xc3: /* movnti */
3544 c->dst.bytes = c->op_bytes;
3545 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
3546 (u64) c->src.val;
3547 break;
3548 case 0xc7: /* Grp9 (cmpxchg8b) */
3549 rc = emulate_grp9(ctxt, ops);
3550 if (rc != X86EMUL_CONTINUE)
3551 goto done;
3552 break;
3553 default:
3554 goto cannot_emulate;
3555 }
3556 goto writeback;
3557
3558 cannot_emulate:
3559 DPRINTF("Cannot emulate %02x\n", c->b);
3560 return -1;
3561 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree