2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 /* this file is part of ehci-hcd.c */
22 /*-------------------------------------------------------------------------*/
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
37 static int ehci_get_frame (struct usb_hcd
*hcd
);
39 /*-------------------------------------------------------------------------*/
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
46 static union ehci_shadow
*
47 periodic_next_shadow(struct ehci_hcd
*ehci
, union ehci_shadow
*periodic
,
50 switch (hc32_to_cpu(ehci
, tag
)) {
52 return &periodic
->qh
->qh_next
;
54 return &periodic
->fstn
->fstn_next
;
56 return &periodic
->itd
->itd_next
;
59 return &periodic
->sitd
->sitd_next
;
64 shadow_next_periodic(struct ehci_hcd
*ehci
, union ehci_shadow
*periodic
,
67 switch (hc32_to_cpu(ehci
, tag
)) {
68 /* our ehci_shadow.qh is actually software part */
70 return &periodic
->qh
->hw
->hw_next
;
71 /* others are hw parts */
73 return periodic
->hw_next
;
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd
*ehci
, unsigned frame
, void *ptr
)
80 union ehci_shadow
*prev_p
= &ehci
->pshadow
[frame
];
81 __hc32
*hw_p
= &ehci
->periodic
[frame
];
82 union ehci_shadow here
= *prev_p
;
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here
.ptr
&& here
.ptr
!= ptr
) {
86 prev_p
= periodic_next_shadow(ehci
, prev_p
,
87 Q_NEXT_TYPE(ehci
, *hw_p
));
88 hw_p
= shadow_next_periodic(ehci
, &here
,
89 Q_NEXT_TYPE(ehci
, *hw_p
));
92 /* an interrupt entry (at list end) could have been shared */
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
99 *prev_p
= *periodic_next_shadow(ehci
, &here
,
100 Q_NEXT_TYPE(ehci
, *hw_p
));
102 if (!ehci
->use_dummy_qh
||
103 *shadow_next_periodic(ehci
, &here
, Q_NEXT_TYPE(ehci
, *hw_p
))
104 != EHCI_LIST_END(ehci
))
105 *hw_p
= *shadow_next_periodic(ehci
, &here
,
106 Q_NEXT_TYPE(ehci
, *hw_p
));
108 *hw_p
= ehci
->dummy
->qh_dma
;
111 /* how many of the uframe's 125 usecs are allocated? */
112 static unsigned short
113 periodic_usecs (struct ehci_hcd
*ehci
, unsigned frame
, unsigned uframe
)
115 __hc32
*hw_p
= &ehci
->periodic
[frame
];
116 union ehci_shadow
*q
= &ehci
->pshadow
[frame
];
118 struct ehci_qh_hw
*hw
;
121 switch (hc32_to_cpu(ehci
, Q_NEXT_TYPE(ehci
, *hw_p
))) {
124 /* is it in the S-mask? */
125 if (hw
->hw_info2
& cpu_to_hc32(ehci
, 1 << uframe
))
126 usecs
+= q
->qh
->usecs
;
128 if (hw
->hw_info2
& cpu_to_hc32(ehci
,
130 usecs
+= q
->qh
->c_usecs
;
136 /* for "save place" FSTNs, count the relevant INTR
137 * bandwidth from the previous frame
139 if (q
->fstn
->hw_prev
!= EHCI_LIST_END(ehci
)) {
140 ehci_dbg (ehci
, "ignoring FSTN cost ...\n");
142 hw_p
= &q
->fstn
->hw_next
;
143 q
= &q
->fstn
->fstn_next
;
146 if (q
->itd
->hw_transaction
[uframe
])
147 usecs
+= q
->itd
->stream
->usecs
;
148 hw_p
= &q
->itd
->hw_next
;
149 q
= &q
->itd
->itd_next
;
152 /* is it in the S-mask? (count SPLIT, DATA) */
153 if (q
->sitd
->hw_uframe
& cpu_to_hc32(ehci
,
155 if (q
->sitd
->hw_fullspeed_ep
&
156 cpu_to_hc32(ehci
, 1<<31))
157 usecs
+= q
->sitd
->stream
->usecs
;
158 else /* worst case for OUT start-split */
159 usecs
+= HS_USECS_ISO (188);
162 /* ... C-mask? (count CSPLIT, DATA) */
163 if (q
->sitd
->hw_uframe
&
164 cpu_to_hc32(ehci
, 1 << (8 + uframe
))) {
165 /* worst case for IN complete-split */
166 usecs
+= q
->sitd
->stream
->c_usecs
;
169 hw_p
= &q
->sitd
->hw_next
;
170 q
= &q
->sitd
->sitd_next
;
176 ehci_err (ehci
, "uframe %d sched overrun: %d usecs\n",
177 frame
* 8 + uframe
, usecs
);
182 /*-------------------------------------------------------------------------*/
184 static int same_tt (struct usb_device
*dev1
, struct usb_device
*dev2
)
186 if (!dev1
->tt
|| !dev2
->tt
)
188 if (dev1
->tt
!= dev2
->tt
)
191 return dev1
->ttport
== dev2
->ttport
;
196 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
198 /* Which uframe does the low/fullspeed transfer start in?
200 * The parameter is the mask of ssplits in "H-frame" terms
201 * and this returns the transfer start uframe in "B-frame" terms,
202 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
203 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
204 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
206 static inline unsigned char tt_start_uframe(struct ehci_hcd
*ehci
, __hc32 mask
)
208 unsigned char smask
= QH_SMASK
& hc32_to_cpu(ehci
, mask
);
210 ehci_err(ehci
, "invalid empty smask!\n");
211 /* uframe 7 can't have bw so this will indicate failure */
214 return ffs(smask
) - 1;
217 static const unsigned char
218 max_tt_usecs
[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
220 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
221 static inline void carryover_tt_bandwidth(unsigned short tt_usecs
[8])
224 for (i
=0; i
<7; i
++) {
225 if (max_tt_usecs
[i
] < tt_usecs
[i
]) {
226 tt_usecs
[i
+1] += tt_usecs
[i
] - max_tt_usecs
[i
];
227 tt_usecs
[i
] = max_tt_usecs
[i
];
232 /* How many of the tt's periodic downstream 1000 usecs are allocated?
234 * While this measures the bandwidth in terms of usecs/uframe,
235 * the low/fullspeed bus has no notion of uframes, so any particular
236 * low/fullspeed transfer can "carry over" from one uframe to the next,
237 * since the TT just performs downstream transfers in sequence.
239 * For example two separate 100 usec transfers can start in the same uframe,
240 * and the second one would "carry over" 75 usecs into the next uframe.
244 struct ehci_hcd
*ehci
,
245 struct usb_device
*dev
,
247 unsigned short tt_usecs
[8]
250 __hc32
*hw_p
= &ehci
->periodic
[frame
];
251 union ehci_shadow
*q
= &ehci
->pshadow
[frame
];
254 memset(tt_usecs
, 0, 16);
257 switch (hc32_to_cpu(ehci
, Q_NEXT_TYPE(ehci
, *hw_p
))) {
259 hw_p
= &q
->itd
->hw_next
;
260 q
= &q
->itd
->itd_next
;
263 if (same_tt(dev
, q
->qh
->dev
)) {
264 uf
= tt_start_uframe(ehci
, q
->qh
->hw
->hw_info2
);
265 tt_usecs
[uf
] += q
->qh
->tt_usecs
;
267 hw_p
= &q
->qh
->hw
->hw_next
;
271 if (same_tt(dev
, q
->sitd
->urb
->dev
)) {
272 uf
= tt_start_uframe(ehci
, q
->sitd
->hw_uframe
);
273 tt_usecs
[uf
] += q
->sitd
->stream
->tt_usecs
;
275 hw_p
= &q
->sitd
->hw_next
;
276 q
= &q
->sitd
->sitd_next
;
280 ehci_dbg(ehci
, "ignoring periodic frame %d FSTN\n",
282 hw_p
= &q
->fstn
->hw_next
;
283 q
= &q
->fstn
->fstn_next
;
287 carryover_tt_bandwidth(tt_usecs
);
289 if (max_tt_usecs
[7] < tt_usecs
[7])
290 ehci_err(ehci
, "frame %d tt sched overrun: %d usecs\n",
291 frame
, tt_usecs
[7] - max_tt_usecs
[7]);
295 * Return true if the device's tt's downstream bus is available for a
296 * periodic transfer of the specified length (usecs), starting at the
297 * specified frame/uframe. Note that (as summarized in section 11.19
298 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
301 * The uframe parameter is when the fullspeed/lowspeed transfer
302 * should be executed in "B-frame" terms, which is the same as the
303 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
304 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
305 * See the EHCI spec sec 4.5 and fig 4.7.
307 * This checks if the full/lowspeed bus, at the specified starting uframe,
308 * has the specified bandwidth available, according to rules listed
309 * in USB 2.0 spec section 11.18.1 fig 11-60.
311 * This does not check if the transfer would exceed the max ssplit
312 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
313 * since proper scheduling limits ssplits to less than 16 per uframe.
315 static int tt_available (
316 struct ehci_hcd
*ehci
,
318 struct usb_device
*dev
,
324 if ((period
== 0) || (uframe
>= 7)) /* error */
327 for (; frame
< ehci
->periodic_size
; frame
+= period
) {
328 unsigned short tt_usecs
[8];
330 periodic_tt_usecs (ehci
, dev
, frame
, tt_usecs
);
332 ehci_vdbg(ehci
, "tt frame %d check %d usecs start uframe %d in"
333 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
334 frame
, usecs
, uframe
,
335 tt_usecs
[0], tt_usecs
[1], tt_usecs
[2], tt_usecs
[3],
336 tt_usecs
[4], tt_usecs
[5], tt_usecs
[6], tt_usecs
[7]);
338 if (max_tt_usecs
[uframe
] <= tt_usecs
[uframe
]) {
339 ehci_vdbg(ehci
, "frame %d uframe %d fully scheduled\n",
344 /* special case for isoc transfers larger than 125us:
345 * the first and each subsequent fully used uframe
346 * must be empty, so as to not illegally delay
347 * already scheduled transactions
350 int ufs
= (usecs
/ 125);
352 for (i
= uframe
; i
< (uframe
+ ufs
) && i
< 8; i
++)
353 if (0 < tt_usecs
[i
]) {
355 "multi-uframe xfer can't fit "
356 "in frame %d uframe %d\n",
362 tt_usecs
[uframe
] += usecs
;
364 carryover_tt_bandwidth(tt_usecs
);
366 /* fail if the carryover pushed bw past the last uframe's limit */
367 if (max_tt_usecs
[7] < tt_usecs
[7]) {
369 "tt unavailable usecs %d frame %d uframe %d\n",
370 usecs
, frame
, uframe
);
380 /* return true iff the device's transaction translator is available
381 * for a periodic transfer starting at the specified frame, using
382 * all the uframes in the mask.
384 static int tt_no_collision (
385 struct ehci_hcd
*ehci
,
387 struct usb_device
*dev
,
392 if (period
== 0) /* error */
395 /* note bandwidth wastage: split never follows csplit
396 * (different dev or endpoint) until the next uframe.
397 * calling convention doesn't make that distinction.
399 for (; frame
< ehci
->periodic_size
; frame
+= period
) {
400 union ehci_shadow here
;
402 struct ehci_qh_hw
*hw
;
404 here
= ehci
->pshadow
[frame
];
405 type
= Q_NEXT_TYPE(ehci
, ehci
->periodic
[frame
]);
407 switch (hc32_to_cpu(ehci
, type
)) {
409 type
= Q_NEXT_TYPE(ehci
, here
.itd
->hw_next
);
410 here
= here
.itd
->itd_next
;
414 if (same_tt (dev
, here
.qh
->dev
)) {
417 mask
= hc32_to_cpu(ehci
,
419 /* "knows" no gap is needed */
424 type
= Q_NEXT_TYPE(ehci
, hw
->hw_next
);
425 here
= here
.qh
->qh_next
;
428 if (same_tt (dev
, here
.sitd
->urb
->dev
)) {
431 mask
= hc32_to_cpu(ehci
, here
.sitd
433 /* FIXME assumes no gap for IN! */
438 type
= Q_NEXT_TYPE(ehci
, here
.sitd
->hw_next
);
439 here
= here
.sitd
->sitd_next
;
444 "periodic frame %d bogus type %d\n",
448 /* collision or error */
457 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
459 /*-------------------------------------------------------------------------*/
461 static int enable_periodic (struct ehci_hcd
*ehci
)
466 if (ehci
->periodic_sched
++)
469 /* did clearing PSE did take effect yet?
470 * takes effect only at frame boundaries...
472 status
= handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
473 STS_PSS
, 0, 9 * 125);
475 usb_hc_died(ehci_to_hcd(ehci
));
479 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
) | CMD_PSE
;
480 ehci_writel(ehci
, cmd
, &ehci
->regs
->command
);
481 /* posted write ... PSS happens later */
482 ehci_to_hcd(ehci
)->state
= HC_STATE_RUNNING
;
484 /* make sure ehci_work scans these */
485 ehci
->next_uframe
= ehci_readl(ehci
, &ehci
->regs
->frame_index
)
486 % (ehci
->periodic_size
<< 3);
487 if (unlikely(ehci
->broken_periodic
))
488 ehci
->last_periodic_enable
= ktime_get_real();
492 static int disable_periodic (struct ehci_hcd
*ehci
)
497 if (--ehci
->periodic_sched
)
500 if (unlikely(ehci
->broken_periodic
)) {
501 /* delay experimentally determined */
502 ktime_t safe
= ktime_add_us(ehci
->last_periodic_enable
, 1000);
503 ktime_t now
= ktime_get_real();
504 s64 delay
= ktime_us_delta(safe
, now
);
506 if (unlikely(delay
> 0))
510 /* did setting PSE not take effect yet?
511 * takes effect only at frame boundaries...
513 status
= handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
514 STS_PSS
, STS_PSS
, 9 * 125);
516 usb_hc_died(ehci_to_hcd(ehci
));
520 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
) & ~CMD_PSE
;
521 ehci_writel(ehci
, cmd
, &ehci
->regs
->command
);
522 /* posted write ... */
524 free_cached_lists(ehci
);
526 ehci
->next_uframe
= -1;
530 /*-------------------------------------------------------------------------*/
532 /* periodic schedule slots have iso tds (normal or split) first, then a
533 * sparse tree for active interrupt transfers.
535 * this just links in a qh; caller guarantees uframe masks are set right.
536 * no FSTN support (yet; ehci 0.96+)
538 static int qh_link_periodic (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
541 unsigned period
= qh
->period
;
543 dev_dbg (&qh
->dev
->dev
,
544 "link qh%d-%04x/%p start %d [%d/%d us]\n",
545 period
, hc32_to_cpup(ehci
, &qh
->hw
->hw_info2
)
546 & (QH_CMASK
| QH_SMASK
),
547 qh
, qh
->start
, qh
->usecs
, qh
->c_usecs
);
549 /* high bandwidth, or otherwise every microframe */
553 for (i
= qh
->start
; i
< ehci
->periodic_size
; i
+= period
) {
554 union ehci_shadow
*prev
= &ehci
->pshadow
[i
];
555 __hc32
*hw_p
= &ehci
->periodic
[i
];
556 union ehci_shadow here
= *prev
;
559 /* skip the iso nodes at list head */
561 type
= Q_NEXT_TYPE(ehci
, *hw_p
);
562 if (type
== cpu_to_hc32(ehci
, Q_TYPE_QH
))
564 prev
= periodic_next_shadow(ehci
, prev
, type
);
565 hw_p
= shadow_next_periodic(ehci
, &here
, type
);
569 /* sorting each branch by period (slow-->fast)
570 * enables sharing interior tree nodes
572 while (here
.ptr
&& qh
!= here
.qh
) {
573 if (qh
->period
> here
.qh
->period
)
575 prev
= &here
.qh
->qh_next
;
576 hw_p
= &here
.qh
->hw
->hw_next
;
579 /* link in this qh, unless some earlier pass did that */
583 qh
->hw
->hw_next
= *hw_p
;
586 *hw_p
= QH_NEXT (ehci
, qh
->qh_dma
);
589 qh
->qh_state
= QH_STATE_LINKED
;
593 /* update per-qh bandwidth for usbfs */
594 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
+= qh
->period
595 ? ((qh
->usecs
+ qh
->c_usecs
) / qh
->period
)
598 /* maybe enable periodic schedule processing */
599 return enable_periodic(ehci
);
602 static int qh_unlink_periodic(struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
608 // IF this isn't high speed
609 // and this qh is active in the current uframe
610 // (and overlay token SplitXstate is false?)
612 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
614 /* high bandwidth, or otherwise part of every microframe */
615 if ((period
= qh
->period
) == 0)
618 for (i
= qh
->start
; i
< ehci
->periodic_size
; i
+= period
)
619 periodic_unlink (ehci
, i
, qh
);
621 /* update per-qh bandwidth for usbfs */
622 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
-= qh
->period
623 ? ((qh
->usecs
+ qh
->c_usecs
) / qh
->period
)
626 dev_dbg (&qh
->dev
->dev
,
627 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
629 hc32_to_cpup(ehci
, &qh
->hw
->hw_info2
) & (QH_CMASK
| QH_SMASK
),
630 qh
, qh
->start
, qh
->usecs
, qh
->c_usecs
);
632 /* qh->qh_next still "live" to HC */
633 qh
->qh_state
= QH_STATE_UNLINK
;
634 qh
->qh_next
.ptr
= NULL
;
637 /* maybe turn off periodic schedule */
638 return disable_periodic(ehci
);
641 static void intr_deschedule (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
644 struct ehci_qh_hw
*hw
= qh
->hw
;
647 /* If the QH isn't linked then there's nothing we can do
648 * unless we were called during a giveback, in which case
649 * qh_completions() has to deal with it.
651 if (qh
->qh_state
!= QH_STATE_LINKED
) {
652 if (qh
->qh_state
== QH_STATE_COMPLETING
)
653 qh
->needs_rescan
= 1;
657 qh_unlink_periodic (ehci
, qh
);
659 /* simple/paranoid: always delay, expecting the HC needs to read
660 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
661 * expect khubd to clean up after any CSPLITs we won't issue.
662 * active high speed queues may need bigger delays...
664 if (list_empty (&qh
->qtd_list
)
665 || (cpu_to_hc32(ehci
, QH_CMASK
)
666 & hw
->hw_info2
) != 0)
669 wait
= 55; /* worst case: 3 * 1024 */
672 qh
->qh_state
= QH_STATE_IDLE
;
673 hw
->hw_next
= EHCI_LIST_END(ehci
);
676 qh_completions(ehci
, qh
);
678 /* reschedule QH iff another request is queued */
679 if (!list_empty(&qh
->qtd_list
) &&
680 HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
)) {
681 rc
= qh_schedule(ehci
, qh
);
683 /* An error here likely indicates handshake failure
684 * or no space left in the schedule. Neither fault
685 * should happen often ...
687 * FIXME kill the now-dysfunctional queued urbs
690 ehci_err(ehci
, "can't reschedule qh %p, err %d\n",
695 /*-------------------------------------------------------------------------*/
697 static int check_period (
698 struct ehci_hcd
*ehci
,
706 /* complete split running into next frame?
707 * given FSTN support, we could sometimes check...
713 * 80% periodic == 100 usec/uframe available
714 * convert "usecs we need" to "max already claimed"
718 /* we "know" 2 and 4 uframe intervals were rejected; so
719 * for period 0, check _every_ microframe in the schedule.
721 if (unlikely (period
== 0)) {
723 for (uframe
= 0; uframe
< 7; uframe
++) {
724 claimed
= periodic_usecs (ehci
, frame
, uframe
);
728 } while ((frame
+= 1) < ehci
->periodic_size
);
730 /* just check the specified uframe, at that period */
733 claimed
= periodic_usecs (ehci
, frame
, uframe
);
736 } while ((frame
+= period
) < ehci
->periodic_size
);
743 static int check_intr_schedule (
744 struct ehci_hcd
*ehci
,
747 const struct ehci_qh
*qh
,
751 int retval
= -ENOSPC
;
754 if (qh
->c_usecs
&& uframe
>= 6) /* FSTN territory? */
757 if (!check_period (ehci
, frame
, uframe
, qh
->period
, qh
->usecs
))
765 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
766 if (tt_available (ehci
, qh
->period
, qh
->dev
, frame
, uframe
,
770 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
771 for (i
=uframe
+1; i
<8 && i
<uframe
+4; i
++)
772 if (!check_period (ehci
, frame
, i
,
773 qh
->period
, qh
->c_usecs
))
780 *c_maskp
= cpu_to_hc32(ehci
, mask
<< 8);
783 /* Make sure this tt's buffer is also available for CSPLITs.
784 * We pessimize a bit; probably the typical full speed case
785 * doesn't need the second CSPLIT.
787 * NOTE: both SPLIT and CSPLIT could be checked in just
790 mask
= 0x03 << (uframe
+ qh
->gap_uf
);
791 *c_maskp
= cpu_to_hc32(ehci
, mask
<< 8);
794 if (tt_no_collision (ehci
, qh
->period
, qh
->dev
, frame
, mask
)) {
795 if (!check_period (ehci
, frame
, uframe
+ qh
->gap_uf
+ 1,
796 qh
->period
, qh
->c_usecs
))
798 if (!check_period (ehci
, frame
, uframe
+ qh
->gap_uf
,
799 qh
->period
, qh
->c_usecs
))
808 /* "first fit" scheduling policy used the first time through,
809 * or when the previous schedule slot can't be re-used.
811 static int qh_schedule(struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
816 unsigned frame
; /* 0..(qh->period - 1), or NO_FRAME */
817 struct ehci_qh_hw
*hw
= qh
->hw
;
819 qh_refresh(ehci
, qh
);
820 hw
->hw_next
= EHCI_LIST_END(ehci
);
823 /* reuse the previous schedule slots, if we can */
824 if (frame
< qh
->period
) {
825 uframe
= ffs(hc32_to_cpup(ehci
, &hw
->hw_info2
) & QH_SMASK
);
826 status
= check_intr_schedule (ehci
, frame
, --uframe
,
834 /* else scan the schedule to find a group of slots such that all
835 * uframes have enough periodic bandwidth available.
838 /* "normal" case, uframing flexible except with splits */
842 for (i
= qh
->period
; status
&& i
> 0; --i
) {
843 frame
= ++ehci
->random_frame
% qh
->period
;
844 for (uframe
= 0; uframe
< 8; uframe
++) {
845 status
= check_intr_schedule (ehci
,
853 /* qh->period == 0 means every uframe */
856 status
= check_intr_schedule (ehci
, 0, 0, qh
, &c_mask
);
862 /* reset S-frame and (maybe) C-frame masks */
863 hw
->hw_info2
&= cpu_to_hc32(ehci
, ~(QH_CMASK
| QH_SMASK
));
864 hw
->hw_info2
|= qh
->period
865 ? cpu_to_hc32(ehci
, 1 << uframe
)
866 : cpu_to_hc32(ehci
, QH_SMASK
);
867 hw
->hw_info2
|= c_mask
;
869 ehci_dbg (ehci
, "reused qh %p schedule\n", qh
);
871 /* stuff into the periodic schedule */
872 status
= qh_link_periodic (ehci
, qh
);
877 static int intr_submit (
878 struct ehci_hcd
*ehci
,
880 struct list_head
*qtd_list
,
887 struct list_head empty
;
889 /* get endpoint and transfer/schedule data */
890 epnum
= urb
->ep
->desc
.bEndpointAddress
;
892 spin_lock_irqsave (&ehci
->lock
, flags
);
894 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci
)))) {
896 goto done_not_linked
;
898 status
= usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci
), urb
);
899 if (unlikely(status
))
900 goto done_not_linked
;
902 /* get qh and force any scheduling errors */
903 INIT_LIST_HEAD (&empty
);
904 qh
= qh_append_tds(ehci
, urb
, &empty
, epnum
, &urb
->ep
->hcpriv
);
909 if (qh
->qh_state
== QH_STATE_IDLE
) {
910 if ((status
= qh_schedule (ehci
, qh
)) != 0)
914 /* then queue the urb's tds to the qh */
915 qh
= qh_append_tds(ehci
, urb
, qtd_list
, epnum
, &urb
->ep
->hcpriv
);
918 /* ... update usbfs periodic stats */
919 ehci_to_hcd(ehci
)->self
.bandwidth_int_reqs
++;
922 if (unlikely(status
))
923 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci
), urb
);
925 spin_unlock_irqrestore (&ehci
->lock
, flags
);
927 qtd_list_free (ehci
, urb
, qtd_list
);
932 /*-------------------------------------------------------------------------*/
934 /* ehci_iso_stream ops work with both ITD and SITD */
936 static struct ehci_iso_stream
*
937 iso_stream_alloc (gfp_t mem_flags
)
939 struct ehci_iso_stream
*stream
;
941 stream
= kzalloc(sizeof *stream
, mem_flags
);
942 if (likely (stream
!= NULL
)) {
943 INIT_LIST_HEAD(&stream
->td_list
);
944 INIT_LIST_HEAD(&stream
->free_list
);
945 stream
->next_uframe
= -1;
946 stream
->refcount
= 1;
953 struct ehci_hcd
*ehci
,
954 struct ehci_iso_stream
*stream
,
955 struct usb_device
*dev
,
960 static const u8 smask_out
[] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
963 unsigned epnum
, maxp
;
968 * this might be a "high bandwidth" highspeed endpoint,
969 * as encoded in the ep descriptor's wMaxPacket field
971 epnum
= usb_pipeendpoint (pipe
);
972 is_input
= usb_pipein (pipe
) ? USB_DIR_IN
: 0;
973 maxp
= usb_maxpacket(dev
, pipe
, !is_input
);
980 /* knows about ITD vs SITD */
981 if (dev
->speed
== USB_SPEED_HIGH
) {
982 unsigned multi
= hb_mult(maxp
);
984 stream
->highspeed
= 1;
986 maxp
= max_packet(maxp
);
990 stream
->buf0
= cpu_to_hc32(ehci
, (epnum
<< 8) | dev
->devnum
);
991 stream
->buf1
= cpu_to_hc32(ehci
, buf1
);
992 stream
->buf2
= cpu_to_hc32(ehci
, multi
);
994 /* usbfs wants to report the average usecs per frame tied up
995 * when transfers on this endpoint are scheduled ...
997 stream
->usecs
= HS_USECS_ISO (maxp
);
998 bandwidth
= stream
->usecs
* 8;
999 bandwidth
/= interval
;
1006 addr
= dev
->ttport
<< 24;
1007 if (!ehci_is_TDI(ehci
)
1009 ehci_to_hcd(ehci
)->self
.root_hub
))
1010 addr
|= dev
->tt
->hub
->devnum
<< 16;
1012 addr
|= dev
->devnum
;
1013 stream
->usecs
= HS_USECS_ISO (maxp
);
1014 think_time
= dev
->tt
? dev
->tt
->think_time
: 0;
1015 stream
->tt_usecs
= NS_TO_US (think_time
+ usb_calc_bus_time (
1016 dev
->speed
, is_input
, 1, maxp
));
1017 hs_transfers
= max (1u, (maxp
+ 187) / 188);
1022 stream
->c_usecs
= stream
->usecs
;
1023 stream
->usecs
= HS_USECS_ISO (1);
1024 stream
->raw_mask
= 1;
1026 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1027 tmp
= (1 << (hs_transfers
+ 2)) - 1;
1028 stream
->raw_mask
|= tmp
<< (8 + 2);
1030 stream
->raw_mask
= smask_out
[hs_transfers
- 1];
1031 bandwidth
= stream
->usecs
+ stream
->c_usecs
;
1032 bandwidth
/= interval
<< 3;
1034 /* stream->splits gets created from raw_mask later */
1035 stream
->address
= cpu_to_hc32(ehci
, addr
);
1037 stream
->bandwidth
= bandwidth
;
1041 stream
->bEndpointAddress
= is_input
| epnum
;
1042 stream
->interval
= interval
;
1043 stream
->maxp
= maxp
;
1047 iso_stream_put(struct ehci_hcd
*ehci
, struct ehci_iso_stream
*stream
)
1051 /* free whenever just a dev->ep reference remains.
1052 * not like a QH -- no persistent state (toggle, halt)
1054 if (stream
->refcount
== 1) {
1057 // BUG_ON (!list_empty(&stream->td_list));
1059 while (!list_empty (&stream
->free_list
)) {
1060 struct list_head
*entry
;
1062 entry
= stream
->free_list
.next
;
1065 /* knows about ITD vs SITD */
1066 if (stream
->highspeed
) {
1067 struct ehci_itd
*itd
;
1069 itd
= list_entry (entry
, struct ehci_itd
,
1071 dma_pool_free (ehci
->itd_pool
, itd
,
1074 struct ehci_sitd
*sitd
;
1076 sitd
= list_entry (entry
, struct ehci_sitd
,
1078 dma_pool_free (ehci
->sitd_pool
, sitd
,
1083 is_in
= (stream
->bEndpointAddress
& USB_DIR_IN
) ? 0x10 : 0;
1084 stream
->bEndpointAddress
&= 0x0f;
1086 stream
->ep
->hcpriv
= NULL
;
1092 static inline struct ehci_iso_stream
*
1093 iso_stream_get (struct ehci_iso_stream
*stream
)
1095 if (likely (stream
!= NULL
))
1100 static struct ehci_iso_stream
*
1101 iso_stream_find (struct ehci_hcd
*ehci
, struct urb
*urb
)
1104 struct ehci_iso_stream
*stream
;
1105 struct usb_host_endpoint
*ep
;
1106 unsigned long flags
;
1108 epnum
= usb_pipeendpoint (urb
->pipe
);
1109 if (usb_pipein(urb
->pipe
))
1110 ep
= urb
->dev
->ep_in
[epnum
];
1112 ep
= urb
->dev
->ep_out
[epnum
];
1114 spin_lock_irqsave (&ehci
->lock
, flags
);
1115 stream
= ep
->hcpriv
;
1117 if (unlikely (stream
== NULL
)) {
1118 stream
= iso_stream_alloc(GFP_ATOMIC
);
1119 if (likely (stream
!= NULL
)) {
1120 /* dev->ep owns the initial refcount */
1121 ep
->hcpriv
= stream
;
1123 iso_stream_init(ehci
, stream
, urb
->dev
, urb
->pipe
,
1127 /* if dev->ep [epnum] is a QH, hw is set */
1128 } else if (unlikely (stream
->hw
!= NULL
)) {
1129 ehci_dbg (ehci
, "dev %s ep%d%s, not iso??\n",
1130 urb
->dev
->devpath
, epnum
,
1131 usb_pipein(urb
->pipe
) ? "in" : "out");
1135 /* caller guarantees an eventual matching iso_stream_put */
1136 stream
= iso_stream_get (stream
);
1138 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1142 /*-------------------------------------------------------------------------*/
1144 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1146 static struct ehci_iso_sched
*
1147 iso_sched_alloc (unsigned packets
, gfp_t mem_flags
)
1149 struct ehci_iso_sched
*iso_sched
;
1150 int size
= sizeof *iso_sched
;
1152 size
+= packets
* sizeof (struct ehci_iso_packet
);
1153 iso_sched
= kzalloc(size
, mem_flags
);
1154 if (likely (iso_sched
!= NULL
)) {
1155 INIT_LIST_HEAD (&iso_sched
->td_list
);
1162 struct ehci_hcd
*ehci
,
1163 struct ehci_iso_sched
*iso_sched
,
1164 struct ehci_iso_stream
*stream
,
1169 dma_addr_t dma
= urb
->transfer_dma
;
1171 /* how many uframes are needed for these transfers */
1172 iso_sched
->span
= urb
->number_of_packets
* stream
->interval
;
1174 /* figure out per-uframe itd fields that we'll need later
1175 * when we fit new itds into the schedule.
1177 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1178 struct ehci_iso_packet
*uframe
= &iso_sched
->packet
[i
];
1183 length
= urb
->iso_frame_desc
[i
].length
;
1184 buf
= dma
+ urb
->iso_frame_desc
[i
].offset
;
1186 trans
= EHCI_ISOC_ACTIVE
;
1187 trans
|= buf
& 0x0fff;
1188 if (unlikely (((i
+ 1) == urb
->number_of_packets
))
1189 && !(urb
->transfer_flags
& URB_NO_INTERRUPT
))
1190 trans
|= EHCI_ITD_IOC
;
1191 trans
|= length
<< 16;
1192 uframe
->transaction
= cpu_to_hc32(ehci
, trans
);
1194 /* might need to cross a buffer page within a uframe */
1195 uframe
->bufp
= (buf
& ~(u64
)0x0fff);
1197 if (unlikely ((uframe
->bufp
!= (buf
& ~(u64
)0x0fff))))
1204 struct ehci_iso_stream
*stream
,
1205 struct ehci_iso_sched
*iso_sched
1210 // caller must hold ehci->lock!
1211 list_splice (&iso_sched
->td_list
, &stream
->free_list
);
1216 itd_urb_transaction (
1217 struct ehci_iso_stream
*stream
,
1218 struct ehci_hcd
*ehci
,
1223 struct ehci_itd
*itd
;
1227 struct ehci_iso_sched
*sched
;
1228 unsigned long flags
;
1230 sched
= iso_sched_alloc (urb
->number_of_packets
, mem_flags
);
1231 if (unlikely (sched
== NULL
))
1234 itd_sched_init(ehci
, sched
, stream
, urb
);
1236 if (urb
->interval
< 8)
1237 num_itds
= 1 + (sched
->span
+ 7) / 8;
1239 num_itds
= urb
->number_of_packets
;
1241 /* allocate/init ITDs */
1242 spin_lock_irqsave (&ehci
->lock
, flags
);
1243 for (i
= 0; i
< num_itds
; i
++) {
1245 /* free_list.next might be cache-hot ... but maybe
1246 * the HC caches it too. avoid that issue for now.
1249 /* prefer previously-allocated itds */
1250 if (likely (!list_empty(&stream
->free_list
))) {
1251 itd
= list_entry (stream
->free_list
.prev
,
1252 struct ehci_itd
, itd_list
);
1253 list_del (&itd
->itd_list
);
1254 itd_dma
= itd
->itd_dma
;
1256 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1257 itd
= dma_pool_alloc (ehci
->itd_pool
, mem_flags
,
1259 spin_lock_irqsave (&ehci
->lock
, flags
);
1261 iso_sched_free(stream
, sched
);
1262 spin_unlock_irqrestore(&ehci
->lock
, flags
);
1267 memset (itd
, 0, sizeof *itd
);
1268 itd
->itd_dma
= itd_dma
;
1269 list_add (&itd
->itd_list
, &sched
->td_list
);
1271 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1273 /* temporarily store schedule info in hcpriv */
1274 urb
->hcpriv
= sched
;
1275 urb
->error_count
= 0;
1279 /*-------------------------------------------------------------------------*/
1283 struct ehci_hcd
*ehci
,
1292 /* can't commit more than 80% periodic == 100 usec */
1293 if (periodic_usecs (ehci
, uframe
>> 3, uframe
& 0x7)
1297 /* we know urb->interval is 2^N uframes */
1299 } while (uframe
< mod
);
1305 struct ehci_hcd
*ehci
,
1307 struct ehci_iso_stream
*stream
,
1309 struct ehci_iso_sched
*sched
,
1316 mask
= stream
->raw_mask
<< (uframe
& 7);
1318 /* for IN, don't wrap CSPLIT into the next frame */
1322 /* this multi-pass logic is simple, but performance may
1323 * suffer when the schedule data isn't cached.
1326 /* check bandwidth */
1327 uframe
%= period_uframes
;
1331 frame
= uframe
>> 3;
1334 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1335 /* The tt's fullspeed bus bandwidth must be available.
1336 * tt_available scheduling guarantees 10+% for control/bulk.
1338 if (!tt_available (ehci
, period_uframes
<< 3,
1339 stream
->udev
, frame
, uf
, stream
->tt_usecs
))
1342 /* tt must be idle for start(s), any gap, and csplit.
1343 * assume scheduling slop leaves 10+% for control/bulk.
1345 if (!tt_no_collision (ehci
, period_uframes
<< 3,
1346 stream
->udev
, frame
, mask
))
1350 /* check starts (OUT uses more than one) */
1351 max_used
= 100 - stream
->usecs
;
1352 for (tmp
= stream
->raw_mask
& 0xff; tmp
; tmp
>>= 1, uf
++) {
1353 if (periodic_usecs (ehci
, frame
, uf
) > max_used
)
1357 /* for IN, check CSPLIT */
1358 if (stream
->c_usecs
) {
1360 max_used
= 100 - stream
->c_usecs
;
1364 if ((stream
->raw_mask
& tmp
) == 0)
1366 if (periodic_usecs (ehci
, frame
, uf
)
1372 /* we know urb->interval is 2^N uframes */
1373 uframe
+= period_uframes
;
1374 } while (uframe
< mod
);
1376 stream
->splits
= cpu_to_hc32(ehci
, stream
->raw_mask
<< (uframe
& 7));
1381 * This scheduler plans almost as far into the future as it has actual
1382 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1383 * "as small as possible" to be cache-friendlier.) That limits the size
1384 * transfers you can stream reliably; avoid more than 64 msec per urb.
1385 * Also avoid queue depths of less than ehci's worst irq latency (affected
1386 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1387 * and other factors); or more than about 230 msec total (for portability,
1388 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1391 #define SCHEDULE_SLOP 80 /* microframes */
1394 iso_stream_schedule (
1395 struct ehci_hcd
*ehci
,
1397 struct ehci_iso_stream
*stream
1400 u32 now
, next
, start
, period
, span
;
1402 unsigned mod
= ehci
->periodic_size
<< 3;
1403 struct ehci_iso_sched
*sched
= urb
->hcpriv
;
1405 period
= urb
->interval
;
1407 if (!stream
->highspeed
) {
1412 if (span
> mod
- SCHEDULE_SLOP
) {
1413 ehci_dbg (ehci
, "iso request %p too long\n", urb
);
1418 now
= ehci_readl(ehci
, &ehci
->regs
->frame_index
) & (mod
- 1);
1420 /* Typical case: reuse current schedule, stream is still active.
1421 * Hopefully there are no gaps from the host falling behind
1422 * (irq delays etc), but if there are we'll take the next
1423 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1425 if (likely (!list_empty (&stream
->td_list
))) {
1428 /* For high speed devices, allow scheduling within the
1429 * isochronous scheduling threshold. For full speed devices
1430 * and Intel PCI-based controllers, don't (work around for
1433 if (!stream
->highspeed
&& ehci
->fs_i_thresh
)
1434 next
= now
+ ehci
->i_thresh
;
1438 /* Fell behind (by up to twice the slop amount)?
1439 * We decide based on the time of the last currently-scheduled
1440 * slot, not the time of the next available slot.
1442 excess
= (stream
->next_uframe
- period
- next
) & (mod
- 1);
1443 if (excess
>= mod
- 2 * SCHEDULE_SLOP
)
1444 start
= next
+ excess
- mod
+ period
*
1445 DIV_ROUND_UP(mod
- excess
, period
);
1447 start
= next
+ excess
+ period
;
1448 if (start
- now
>= mod
) {
1449 ehci_dbg(ehci
, "request %p would overflow (%d+%d >= %d)\n",
1450 urb
, start
- now
- period
, period
,
1457 /* need to schedule; when's the next (u)frame we could start?
1458 * this is bigger than ehci->i_thresh allows; scheduling itself
1459 * isn't free, the slop should handle reasonably slow cpus. it
1460 * can also help high bandwidth if the dma and irq loads don't
1461 * jump until after the queue is primed.
1464 start
= SCHEDULE_SLOP
+ (now
& ~0x07);
1466 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1468 /* find a uframe slot with enough bandwidth */
1469 next
= start
+ period
;
1470 for (; start
< next
; start
++) {
1472 /* check schedule: enough space? */
1473 if (stream
->highspeed
) {
1474 if (itd_slot_ok(ehci
, mod
, start
,
1475 stream
->usecs
, period
))
1478 if ((start
% 8) >= 6)
1480 if (sitd_slot_ok(ehci
, mod
, stream
,
1481 start
, sched
, period
))
1486 /* no room in the schedule */
1487 if (start
== next
) {
1488 ehci_dbg(ehci
, "iso resched full %p (now %d max %d)\n",
1489 urb
, now
, now
+ mod
);
1495 /* Tried to schedule too far into the future? */
1496 if (unlikely(start
- now
+ span
- period
1497 >= mod
- 2 * SCHEDULE_SLOP
)) {
1498 ehci_dbg(ehci
, "request %p would overflow (%d+%d >= %d)\n",
1499 urb
, start
- now
, span
- period
,
1500 mod
- 2 * SCHEDULE_SLOP
);
1505 stream
->next_uframe
= start
& (mod
- 1);
1507 /* report high speed start in uframes; full speed, in frames */
1508 urb
->start_frame
= stream
->next_uframe
;
1509 if (!stream
->highspeed
)
1510 urb
->start_frame
>>= 3;
1514 iso_sched_free(stream
, sched
);
1519 /*-------------------------------------------------------------------------*/
1522 itd_init(struct ehci_hcd
*ehci
, struct ehci_iso_stream
*stream
,
1523 struct ehci_itd
*itd
)
1527 /* it's been recently zeroed */
1528 itd
->hw_next
= EHCI_LIST_END(ehci
);
1529 itd
->hw_bufp
[0] = stream
->buf0
;
1530 itd
->hw_bufp
[1] = stream
->buf1
;
1531 itd
->hw_bufp
[2] = stream
->buf2
;
1533 for (i
= 0; i
< 8; i
++)
1536 /* All other fields are filled when scheduling */
1541 struct ehci_hcd
*ehci
,
1542 struct ehci_itd
*itd
,
1543 struct ehci_iso_sched
*iso_sched
,
1548 struct ehci_iso_packet
*uf
= &iso_sched
->packet
[index
];
1549 unsigned pg
= itd
->pg
;
1551 // BUG_ON (pg == 6 && uf->cross);
1554 itd
->index
[uframe
] = index
;
1556 itd
->hw_transaction
[uframe
] = uf
->transaction
;
1557 itd
->hw_transaction
[uframe
] |= cpu_to_hc32(ehci
, pg
<< 12);
1558 itd
->hw_bufp
[pg
] |= cpu_to_hc32(ehci
, uf
->bufp
& ~(u32
)0);
1559 itd
->hw_bufp_hi
[pg
] |= cpu_to_hc32(ehci
, (u32
)(uf
->bufp
>> 32));
1561 /* iso_frame_desc[].offset must be strictly increasing */
1562 if (unlikely (uf
->cross
)) {
1563 u64 bufp
= uf
->bufp
+ 4096;
1566 itd
->hw_bufp
[pg
] |= cpu_to_hc32(ehci
, bufp
& ~(u32
)0);
1567 itd
->hw_bufp_hi
[pg
] |= cpu_to_hc32(ehci
, (u32
)(bufp
>> 32));
1572 itd_link (struct ehci_hcd
*ehci
, unsigned frame
, struct ehci_itd
*itd
)
1574 union ehci_shadow
*prev
= &ehci
->pshadow
[frame
];
1575 __hc32
*hw_p
= &ehci
->periodic
[frame
];
1576 union ehci_shadow here
= *prev
;
1579 /* skip any iso nodes which might belong to previous microframes */
1581 type
= Q_NEXT_TYPE(ehci
, *hw_p
);
1582 if (type
== cpu_to_hc32(ehci
, Q_TYPE_QH
))
1584 prev
= periodic_next_shadow(ehci
, prev
, type
);
1585 hw_p
= shadow_next_periodic(ehci
, &here
, type
);
1589 itd
->itd_next
= here
;
1590 itd
->hw_next
= *hw_p
;
1594 *hw_p
= cpu_to_hc32(ehci
, itd
->itd_dma
| Q_TYPE_ITD
);
1597 #define AB_REG_BAR_LOW 0xe0
1598 #define AB_REG_BAR_HIGH 0xe1
1599 #define AB_INDX(addr) ((addr) + 0x00)
1600 #define AB_DATA(addr) ((addr) + 0x04)
1601 #define NB_PCIE_INDX_ADDR 0xe0
1602 #define NB_PCIE_INDX_DATA 0xe4
1603 #define NB_PIF0_PWRDOWN_0 0x01100012
1604 #define NB_PIF0_PWRDOWN_1 0x01100013
1606 static void ehci_quirk_amd_L1(struct ehci_hcd
*ehci
, int disable
)
1608 u32 addr
, addr_low
, addr_high
, val
;
1610 outb_p(AB_REG_BAR_LOW
, 0xcd6);
1611 addr_low
= inb_p(0xcd7);
1612 outb_p(AB_REG_BAR_HIGH
, 0xcd6);
1613 addr_high
= inb_p(0xcd7);
1614 addr
= addr_high
<< 8 | addr_low
;
1615 outl_p(0x30, AB_INDX(addr
));
1616 outl_p(0x40, AB_DATA(addr
));
1617 outl_p(0x34, AB_INDX(addr
));
1618 val
= inl_p(AB_DATA(addr
));
1622 val
|= (1 << 4) | (1 << 9);
1625 val
&= ~((1 << 4) | (1 << 9));
1627 outl_p(val
, AB_DATA(addr
));
1630 addr
= NB_PIF0_PWRDOWN_0
;
1631 pci_write_config_dword(amd_nb_dev
, NB_PCIE_INDX_ADDR
, addr
);
1632 pci_read_config_dword(amd_nb_dev
, NB_PCIE_INDX_DATA
, &val
);
1634 val
&= ~(0x3f << 7);
1638 pci_write_config_dword(amd_nb_dev
, NB_PCIE_INDX_DATA
, val
);
1640 addr
= NB_PIF0_PWRDOWN_1
;
1641 pci_write_config_dword(amd_nb_dev
, NB_PCIE_INDX_ADDR
, addr
);
1642 pci_read_config_dword(amd_nb_dev
, NB_PCIE_INDX_DATA
, &val
);
1644 val
&= ~(0x3f << 7);
1648 pci_write_config_dword(amd_nb_dev
, NB_PCIE_INDX_DATA
, val
);
1654 /* fit urb's itds into the selected schedule slot; activate as needed */
1657 struct ehci_hcd
*ehci
,
1660 struct ehci_iso_stream
*stream
1664 unsigned next_uframe
, uframe
, frame
;
1665 struct ehci_iso_sched
*iso_sched
= urb
->hcpriv
;
1666 struct ehci_itd
*itd
;
1668 next_uframe
= stream
->next_uframe
& (mod
- 1);
1670 if (unlikely (list_empty(&stream
->td_list
))) {
1671 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
1672 += stream
->bandwidth
;
1674 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1675 urb
->dev
->devpath
, stream
->bEndpointAddress
& 0x0f,
1676 (stream
->bEndpointAddress
& USB_DIR_IN
) ? "in" : "out",
1678 next_uframe
>> 3, next_uframe
& 0x7);
1681 if (ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
== 0) {
1682 if (ehci
->amd_l1_fix
== 1)
1683 ehci_quirk_amd_L1(ehci
, 1);
1686 ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
++;
1688 /* fill iTDs uframe by uframe */
1689 for (packet
= 0, itd
= NULL
; packet
< urb
->number_of_packets
; ) {
1691 /* ASSERT: we have all necessary itds */
1692 // BUG_ON (list_empty (&iso_sched->td_list));
1694 /* ASSERT: no itds for this endpoint in this uframe */
1696 itd
= list_entry (iso_sched
->td_list
.next
,
1697 struct ehci_itd
, itd_list
);
1698 list_move_tail (&itd
->itd_list
, &stream
->td_list
);
1699 itd
->stream
= iso_stream_get (stream
);
1701 itd_init (ehci
, stream
, itd
);
1704 uframe
= next_uframe
& 0x07;
1705 frame
= next_uframe
>> 3;
1707 itd_patch(ehci
, itd
, iso_sched
, packet
, uframe
);
1709 next_uframe
+= stream
->interval
;
1710 next_uframe
&= mod
- 1;
1713 /* link completed itds into the schedule */
1714 if (((next_uframe
>> 3) != frame
)
1715 || packet
== urb
->number_of_packets
) {
1716 itd_link(ehci
, frame
& (ehci
->periodic_size
- 1), itd
);
1720 stream
->next_uframe
= next_uframe
;
1722 /* don't need that schedule data any more */
1723 iso_sched_free (stream
, iso_sched
);
1726 timer_action (ehci
, TIMER_IO_WATCHDOG
);
1727 return enable_periodic(ehci
);
1730 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1732 /* Process and recycle a completed ITD. Return true iff its urb completed,
1733 * and hence its completion callback probably added things to the hardware
1736 * Note that we carefully avoid recycling this descriptor until after any
1737 * completion callback runs, so that it won't be reused quickly. That is,
1738 * assuming (a) no more than two urbs per frame on this endpoint, and also
1739 * (b) only this endpoint's completions submit URBs. It seems some silicon
1740 * corrupts things if you reuse completed descriptors very quickly...
1744 struct ehci_hcd
*ehci
,
1745 struct ehci_itd
*itd
1747 struct urb
*urb
= itd
->urb
;
1748 struct usb_iso_packet_descriptor
*desc
;
1752 struct ehci_iso_stream
*stream
= itd
->stream
;
1753 struct usb_device
*dev
;
1754 unsigned retval
= false;
1756 /* for each uframe with a packet */
1757 for (uframe
= 0; uframe
< 8; uframe
++) {
1758 if (likely (itd
->index
[uframe
] == -1))
1760 urb_index
= itd
->index
[uframe
];
1761 desc
= &urb
->iso_frame_desc
[urb_index
];
1763 t
= hc32_to_cpup(ehci
, &itd
->hw_transaction
[uframe
]);
1764 itd
->hw_transaction
[uframe
] = 0;
1766 /* report transfer status */
1767 if (unlikely (t
& ISO_ERRS
)) {
1769 if (t
& EHCI_ISOC_BUF_ERR
)
1770 desc
->status
= usb_pipein (urb
->pipe
)
1771 ? -ENOSR
/* hc couldn't read */
1772 : -ECOMM
; /* hc couldn't write */
1773 else if (t
& EHCI_ISOC_BABBLE
)
1774 desc
->status
= -EOVERFLOW
;
1775 else /* (t & EHCI_ISOC_XACTERR) */
1776 desc
->status
= -EPROTO
;
1778 /* HC need not update length with this error */
1779 if (!(t
& EHCI_ISOC_BABBLE
)) {
1780 desc
->actual_length
= EHCI_ITD_LENGTH(t
);
1781 urb
->actual_length
+= desc
->actual_length
;
1783 } else if (likely ((t
& EHCI_ISOC_ACTIVE
) == 0)) {
1785 desc
->actual_length
= EHCI_ITD_LENGTH(t
);
1786 urb
->actual_length
+= desc
->actual_length
;
1788 /* URB was too late */
1789 desc
->status
= -EXDEV
;
1793 /* handle completion now? */
1794 if (likely ((urb_index
+ 1) != urb
->number_of_packets
))
1797 /* ASSERT: it's really the last itd for this urb
1798 list_for_each_entry (itd, &stream->td_list, itd_list)
1799 BUG_ON (itd->urb == urb);
1802 /* give urb back to the driver; completion often (re)submits */
1804 ehci_urb_done(ehci
, urb
, 0);
1807 (void) disable_periodic(ehci
);
1808 ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
--;
1810 if (ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
== 0) {
1811 if (ehci
->amd_l1_fix
== 1)
1812 ehci_quirk_amd_L1(ehci
, 0);
1815 if (unlikely(list_is_singular(&stream
->td_list
))) {
1816 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
1817 -= stream
->bandwidth
;
1819 "deschedule devp %s ep%d%s-iso\n",
1820 dev
->devpath
, stream
->bEndpointAddress
& 0x0f,
1821 (stream
->bEndpointAddress
& USB_DIR_IN
) ? "in" : "out");
1823 iso_stream_put (ehci
, stream
);
1827 if (ehci
->clock_frame
!= itd
->frame
|| itd
->index
[7] != -1) {
1828 /* OK to recycle this ITD now. */
1830 list_move(&itd
->itd_list
, &stream
->free_list
);
1831 iso_stream_put(ehci
, stream
);
1833 /* HW might remember this ITD, so we can't recycle it yet.
1834 * Move it to a safe place until a new frame starts.
1836 list_move(&itd
->itd_list
, &ehci
->cached_itd_list
);
1837 if (stream
->refcount
== 2) {
1838 /* If iso_stream_put() were called here, stream
1839 * would be freed. Instead, just prevent reuse.
1841 stream
->ep
->hcpriv
= NULL
;
1848 /*-------------------------------------------------------------------------*/
1850 static int itd_submit (struct ehci_hcd
*ehci
, struct urb
*urb
,
1853 int status
= -EINVAL
;
1854 unsigned long flags
;
1855 struct ehci_iso_stream
*stream
;
1857 /* Get iso_stream head */
1858 stream
= iso_stream_find (ehci
, urb
);
1859 if (unlikely (stream
== NULL
)) {
1860 ehci_dbg (ehci
, "can't get iso stream\n");
1863 if (unlikely (urb
->interval
!= stream
->interval
)) {
1864 ehci_dbg (ehci
, "can't change iso interval %d --> %d\n",
1865 stream
->interval
, urb
->interval
);
1869 #ifdef EHCI_URB_TRACE
1871 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1872 __func__
, urb
->dev
->devpath
, urb
,
1873 usb_pipeendpoint (urb
->pipe
),
1874 usb_pipein (urb
->pipe
) ? "in" : "out",
1875 urb
->transfer_buffer_length
,
1876 urb
->number_of_packets
, urb
->interval
,
1880 /* allocate ITDs w/o locking anything */
1881 status
= itd_urb_transaction (stream
, ehci
, urb
, mem_flags
);
1882 if (unlikely (status
< 0)) {
1883 ehci_dbg (ehci
, "can't init itds\n");
1887 /* schedule ... need to lock */
1888 spin_lock_irqsave (&ehci
->lock
, flags
);
1889 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci
)))) {
1890 status
= -ESHUTDOWN
;
1891 goto done_not_linked
;
1893 status
= usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci
), urb
);
1894 if (unlikely(status
))
1895 goto done_not_linked
;
1896 status
= iso_stream_schedule(ehci
, urb
, stream
);
1897 if (likely (status
== 0))
1898 itd_link_urb (ehci
, urb
, ehci
->periodic_size
<< 3, stream
);
1900 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci
), urb
);
1902 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1905 if (unlikely (status
< 0))
1906 iso_stream_put (ehci
, stream
);
1910 /*-------------------------------------------------------------------------*/
1913 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1914 * TTs in USB 2.0 hubs. These need microframe scheduling.
1919 struct ehci_hcd
*ehci
,
1920 struct ehci_iso_sched
*iso_sched
,
1921 struct ehci_iso_stream
*stream
,
1926 dma_addr_t dma
= urb
->transfer_dma
;
1928 /* how many frames are needed for these transfers */
1929 iso_sched
->span
= urb
->number_of_packets
* stream
->interval
;
1931 /* figure out per-frame sitd fields that we'll need later
1932 * when we fit new sitds into the schedule.
1934 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1935 struct ehci_iso_packet
*packet
= &iso_sched
->packet
[i
];
1940 length
= urb
->iso_frame_desc
[i
].length
& 0x03ff;
1941 buf
= dma
+ urb
->iso_frame_desc
[i
].offset
;
1943 trans
= SITD_STS_ACTIVE
;
1944 if (((i
+ 1) == urb
->number_of_packets
)
1945 && !(urb
->transfer_flags
& URB_NO_INTERRUPT
))
1947 trans
|= length
<< 16;
1948 packet
->transaction
= cpu_to_hc32(ehci
, trans
);
1950 /* might need to cross a buffer page within a td */
1952 packet
->buf1
= (buf
+ length
) & ~0x0fff;
1953 if (packet
->buf1
!= (buf
& ~(u64
)0x0fff))
1956 /* OUT uses multiple start-splits */
1957 if (stream
->bEndpointAddress
& USB_DIR_IN
)
1959 length
= (length
+ 187) / 188;
1960 if (length
> 1) /* BEGIN vs ALL */
1962 packet
->buf1
|= length
;
1967 sitd_urb_transaction (
1968 struct ehci_iso_stream
*stream
,
1969 struct ehci_hcd
*ehci
,
1974 struct ehci_sitd
*sitd
;
1975 dma_addr_t sitd_dma
;
1977 struct ehci_iso_sched
*iso_sched
;
1978 unsigned long flags
;
1980 iso_sched
= iso_sched_alloc (urb
->number_of_packets
, mem_flags
);
1981 if (iso_sched
== NULL
)
1984 sitd_sched_init(ehci
, iso_sched
, stream
, urb
);
1986 /* allocate/init sITDs */
1987 spin_lock_irqsave (&ehci
->lock
, flags
);
1988 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
1990 /* NOTE: for now, we don't try to handle wraparound cases
1991 * for IN (using sitd->hw_backpointer, like a FSTN), which
1992 * means we never need two sitds for full speed packets.
1995 /* free_list.next might be cache-hot ... but maybe
1996 * the HC caches it too. avoid that issue for now.
1999 /* prefer previously-allocated sitds */
2000 if (!list_empty(&stream
->free_list
)) {
2001 sitd
= list_entry (stream
->free_list
.prev
,
2002 struct ehci_sitd
, sitd_list
);
2003 list_del (&sitd
->sitd_list
);
2004 sitd_dma
= sitd
->sitd_dma
;
2006 spin_unlock_irqrestore (&ehci
->lock
, flags
);
2007 sitd
= dma_pool_alloc (ehci
->sitd_pool
, mem_flags
,
2009 spin_lock_irqsave (&ehci
->lock
, flags
);
2011 iso_sched_free(stream
, iso_sched
);
2012 spin_unlock_irqrestore(&ehci
->lock
, flags
);
2017 memset (sitd
, 0, sizeof *sitd
);
2018 sitd
->sitd_dma
= sitd_dma
;
2019 list_add (&sitd
->sitd_list
, &iso_sched
->td_list
);
2022 /* temporarily store schedule info in hcpriv */
2023 urb
->hcpriv
= iso_sched
;
2024 urb
->error_count
= 0;
2026 spin_unlock_irqrestore (&ehci
->lock
, flags
);
2030 /*-------------------------------------------------------------------------*/
2034 struct ehci_hcd
*ehci
,
2035 struct ehci_iso_stream
*stream
,
2036 struct ehci_sitd
*sitd
,
2037 struct ehci_iso_sched
*iso_sched
,
2041 struct ehci_iso_packet
*uf
= &iso_sched
->packet
[index
];
2042 u64 bufp
= uf
->bufp
;
2044 sitd
->hw_next
= EHCI_LIST_END(ehci
);
2045 sitd
->hw_fullspeed_ep
= stream
->address
;
2046 sitd
->hw_uframe
= stream
->splits
;
2047 sitd
->hw_results
= uf
->transaction
;
2048 sitd
->hw_backpointer
= EHCI_LIST_END(ehci
);
2051 sitd
->hw_buf
[0] = cpu_to_hc32(ehci
, bufp
);
2052 sitd
->hw_buf_hi
[0] = cpu_to_hc32(ehci
, bufp
>> 32);
2054 sitd
->hw_buf
[1] = cpu_to_hc32(ehci
, uf
->buf1
);
2057 sitd
->hw_buf_hi
[1] = cpu_to_hc32(ehci
, bufp
>> 32);
2058 sitd
->index
= index
;
2062 sitd_link (struct ehci_hcd
*ehci
, unsigned frame
, struct ehci_sitd
*sitd
)
2064 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
2065 sitd
->sitd_next
= ehci
->pshadow
[frame
];
2066 sitd
->hw_next
= ehci
->periodic
[frame
];
2067 ehci
->pshadow
[frame
].sitd
= sitd
;
2068 sitd
->frame
= frame
;
2070 ehci
->periodic
[frame
] = cpu_to_hc32(ehci
, sitd
->sitd_dma
| Q_TYPE_SITD
);
2073 /* fit urb's sitds into the selected schedule slot; activate as needed */
2076 struct ehci_hcd
*ehci
,
2079 struct ehci_iso_stream
*stream
2083 unsigned next_uframe
;
2084 struct ehci_iso_sched
*sched
= urb
->hcpriv
;
2085 struct ehci_sitd
*sitd
;
2087 next_uframe
= stream
->next_uframe
;
2089 if (list_empty(&stream
->td_list
)) {
2090 /* usbfs ignores TT bandwidth */
2091 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
2092 += stream
->bandwidth
;
2094 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2095 urb
->dev
->devpath
, stream
->bEndpointAddress
& 0x0f,
2096 (stream
->bEndpointAddress
& USB_DIR_IN
) ? "in" : "out",
2097 (next_uframe
>> 3) & (ehci
->periodic_size
- 1),
2098 stream
->interval
, hc32_to_cpu(ehci
, stream
->splits
));
2101 if (ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
== 0) {
2102 if (ehci
->amd_l1_fix
== 1)
2103 ehci_quirk_amd_L1(ehci
, 1);
2106 ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
++;
2108 /* fill sITDs frame by frame */
2109 for (packet
= 0, sitd
= NULL
;
2110 packet
< urb
->number_of_packets
;
2113 /* ASSERT: we have all necessary sitds */
2114 BUG_ON (list_empty (&sched
->td_list
));
2116 /* ASSERT: no itds for this endpoint in this frame */
2118 sitd
= list_entry (sched
->td_list
.next
,
2119 struct ehci_sitd
, sitd_list
);
2120 list_move_tail (&sitd
->sitd_list
, &stream
->td_list
);
2121 sitd
->stream
= iso_stream_get (stream
);
2124 sitd_patch(ehci
, stream
, sitd
, sched
, packet
);
2125 sitd_link(ehci
, (next_uframe
>> 3) & (ehci
->periodic_size
- 1),
2128 next_uframe
+= stream
->interval
<< 3;
2130 stream
->next_uframe
= next_uframe
& (mod
- 1);
2132 /* don't need that schedule data any more */
2133 iso_sched_free (stream
, sched
);
2136 timer_action (ehci
, TIMER_IO_WATCHDOG
);
2137 return enable_periodic(ehci
);
2140 /*-------------------------------------------------------------------------*/
2142 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2143 | SITD_STS_XACT | SITD_STS_MMF)
2145 /* Process and recycle a completed SITD. Return true iff its urb completed,
2146 * and hence its completion callback probably added things to the hardware
2149 * Note that we carefully avoid recycling this descriptor until after any
2150 * completion callback runs, so that it won't be reused quickly. That is,
2151 * assuming (a) no more than two urbs per frame on this endpoint, and also
2152 * (b) only this endpoint's completions submit URBs. It seems some silicon
2153 * corrupts things if you reuse completed descriptors very quickly...
2157 struct ehci_hcd
*ehci
,
2158 struct ehci_sitd
*sitd
2160 struct urb
*urb
= sitd
->urb
;
2161 struct usb_iso_packet_descriptor
*desc
;
2164 struct ehci_iso_stream
*stream
= sitd
->stream
;
2165 struct usb_device
*dev
;
2166 unsigned retval
= false;
2168 urb_index
= sitd
->index
;
2169 desc
= &urb
->iso_frame_desc
[urb_index
];
2170 t
= hc32_to_cpup(ehci
, &sitd
->hw_results
);
2172 /* report transfer status */
2173 if (t
& SITD_ERRS
) {
2175 if (t
& SITD_STS_DBE
)
2176 desc
->status
= usb_pipein (urb
->pipe
)
2177 ? -ENOSR
/* hc couldn't read */
2178 : -ECOMM
; /* hc couldn't write */
2179 else if (t
& SITD_STS_BABBLE
)
2180 desc
->status
= -EOVERFLOW
;
2181 else /* XACT, MMF, etc */
2182 desc
->status
= -EPROTO
;
2185 desc
->actual_length
= desc
->length
- SITD_LENGTH(t
);
2186 urb
->actual_length
+= desc
->actual_length
;
2189 /* handle completion now? */
2190 if ((urb_index
+ 1) != urb
->number_of_packets
)
2193 /* ASSERT: it's really the last sitd for this urb
2194 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2195 BUG_ON (sitd->urb == urb);
2198 /* give urb back to the driver; completion often (re)submits */
2200 ehci_urb_done(ehci
, urb
, 0);
2203 (void) disable_periodic(ehci
);
2204 ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
--;
2206 if (ehci_to_hcd(ehci
)->self
.bandwidth_isoc_reqs
== 0) {
2207 if (ehci
->amd_l1_fix
== 1)
2208 ehci_quirk_amd_L1(ehci
, 0);
2211 if (list_is_singular(&stream
->td_list
)) {
2212 ehci_to_hcd(ehci
)->self
.bandwidth_allocated
2213 -= stream
->bandwidth
;
2215 "deschedule devp %s ep%d%s-iso\n",
2216 dev
->devpath
, stream
->bEndpointAddress
& 0x0f,
2217 (stream
->bEndpointAddress
& USB_DIR_IN
) ? "in" : "out");
2219 iso_stream_put (ehci
, stream
);
2223 if (ehci
->clock_frame
!= sitd
->frame
) {
2224 /* OK to recycle this SITD now. */
2225 sitd
->stream
= NULL
;
2226 list_move(&sitd
->sitd_list
, &stream
->free_list
);
2227 iso_stream_put(ehci
, stream
);
2229 /* HW might remember this SITD, so we can't recycle it yet.
2230 * Move it to a safe place until a new frame starts.
2232 list_move(&sitd
->sitd_list
, &ehci
->cached_sitd_list
);
2233 if (stream
->refcount
== 2) {
2234 /* If iso_stream_put() were called here, stream
2235 * would be freed. Instead, just prevent reuse.
2237 stream
->ep
->hcpriv
= NULL
;
2245 static int sitd_submit (struct ehci_hcd
*ehci
, struct urb
*urb
,
2248 int status
= -EINVAL
;
2249 unsigned long flags
;
2250 struct ehci_iso_stream
*stream
;
2252 /* Get iso_stream head */
2253 stream
= iso_stream_find (ehci
, urb
);
2254 if (stream
== NULL
) {
2255 ehci_dbg (ehci
, "can't get iso stream\n");
2258 if (urb
->interval
!= stream
->interval
) {
2259 ehci_dbg (ehci
, "can't change iso interval %d --> %d\n",
2260 stream
->interval
, urb
->interval
);
2264 #ifdef EHCI_URB_TRACE
2266 "submit %p dev%s ep%d%s-iso len %d\n",
2267 urb
, urb
->dev
->devpath
,
2268 usb_pipeendpoint (urb
->pipe
),
2269 usb_pipein (urb
->pipe
) ? "in" : "out",
2270 urb
->transfer_buffer_length
);
2273 /* allocate SITDs */
2274 status
= sitd_urb_transaction (stream
, ehci
, urb
, mem_flags
);
2276 ehci_dbg (ehci
, "can't init sitds\n");
2280 /* schedule ... need to lock */
2281 spin_lock_irqsave (&ehci
->lock
, flags
);
2282 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci
)))) {
2283 status
= -ESHUTDOWN
;
2284 goto done_not_linked
;
2286 status
= usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci
), urb
);
2287 if (unlikely(status
))
2288 goto done_not_linked
;
2289 status
= iso_stream_schedule(ehci
, urb
, stream
);
2291 sitd_link_urb (ehci
, urb
, ehci
->periodic_size
<< 3, stream
);
2293 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci
), urb
);
2295 spin_unlock_irqrestore (&ehci
->lock
, flags
);
2299 iso_stream_put (ehci
, stream
);
2303 /*-------------------------------------------------------------------------*/
2305 static void free_cached_lists(struct ehci_hcd
*ehci
)
2307 struct ehci_itd
*itd
, *n
;
2308 struct ehci_sitd
*sitd
, *sn
;
2310 list_for_each_entry_safe(itd
, n
, &ehci
->cached_itd_list
, itd_list
) {
2311 struct ehci_iso_stream
*stream
= itd
->stream
;
2313 list_move(&itd
->itd_list
, &stream
->free_list
);
2314 iso_stream_put(ehci
, stream
);
2317 list_for_each_entry_safe(sitd
, sn
, &ehci
->cached_sitd_list
, sitd_list
) {
2318 struct ehci_iso_stream
*stream
= sitd
->stream
;
2319 sitd
->stream
= NULL
;
2320 list_move(&sitd
->sitd_list
, &stream
->free_list
);
2321 iso_stream_put(ehci
, stream
);
2325 /*-------------------------------------------------------------------------*/
2328 scan_periodic (struct ehci_hcd
*ehci
)
2330 unsigned now_uframe
, frame
, clock
, clock_frame
, mod
;
2333 mod
= ehci
->periodic_size
<< 3;
2336 * When running, scan from last scan point up to "now"
2337 * else clean up by scanning everything that's left.
2338 * Touches as few pages as possible: cache-friendly.
2340 now_uframe
= ehci
->next_uframe
;
2341 if (HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
)) {
2342 clock
= ehci_readl(ehci
, &ehci
->regs
->frame_index
);
2343 clock_frame
= (clock
>> 3) & (ehci
->periodic_size
- 1);
2345 clock
= now_uframe
+ mod
- 1;
2348 if (ehci
->clock_frame
!= clock_frame
) {
2349 free_cached_lists(ehci
);
2350 ehci
->clock_frame
= clock_frame
;
2353 clock_frame
= clock
>> 3;
2356 union ehci_shadow q
, *q_p
;
2358 unsigned incomplete
= false;
2360 frame
= now_uframe
>> 3;
2363 /* scan each element in frame's queue for completions */
2364 q_p
= &ehci
->pshadow
[frame
];
2365 hw_p
= &ehci
->periodic
[frame
];
2367 type
= Q_NEXT_TYPE(ehci
, *hw_p
);
2370 while (q
.ptr
!= NULL
) {
2372 union ehci_shadow temp
;
2375 live
= HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
);
2376 switch (hc32_to_cpu(ehci
, type
)) {
2378 /* handle any completions */
2379 temp
.qh
= qh_get (q
.qh
);
2380 type
= Q_NEXT_TYPE(ehci
, q
.qh
->hw
->hw_next
);
2382 modified
= qh_completions (ehci
, temp
.qh
);
2383 if (unlikely(list_empty(&temp
.qh
->qtd_list
) ||
2384 temp
.qh
->needs_rescan
))
2385 intr_deschedule (ehci
, temp
.qh
);
2389 /* for "save place" FSTNs, look at QH entries
2390 * in the previous frame for completions.
2392 if (q
.fstn
->hw_prev
!= EHCI_LIST_END(ehci
)) {
2393 dbg ("ignoring completions from FSTNs");
2395 type
= Q_NEXT_TYPE(ehci
, q
.fstn
->hw_next
);
2396 q
= q
.fstn
->fstn_next
;
2399 /* If this ITD is still active, leave it for
2400 * later processing ... check the next entry.
2401 * No need to check for activity unless the
2404 if (frame
== clock_frame
&& live
) {
2406 for (uf
= 0; uf
< 8; uf
++) {
2407 if (q
.itd
->hw_transaction
[uf
] &
2413 q_p
= &q
.itd
->itd_next
;
2414 hw_p
= &q
.itd
->hw_next
;
2415 type
= Q_NEXT_TYPE(ehci
,
2422 /* Take finished ITDs out of the schedule
2423 * and process them: recycle, maybe report
2424 * URB completion. HC won't cache the
2425 * pointer for much longer, if at all.
2427 *q_p
= q
.itd
->itd_next
;
2428 if (!ehci
->use_dummy_qh
||
2429 q
.itd
->hw_next
!= EHCI_LIST_END(ehci
))
2430 *hw_p
= q
.itd
->hw_next
;
2432 *hw_p
= ehci
->dummy
->qh_dma
;
2433 type
= Q_NEXT_TYPE(ehci
, q
.itd
->hw_next
);
2435 modified
= itd_complete (ehci
, q
.itd
);
2439 /* If this SITD is still active, leave it for
2440 * later processing ... check the next entry.
2441 * No need to check for activity unless the
2444 if (((frame
== clock_frame
) ||
2445 (((frame
+ 1) & (ehci
->periodic_size
- 1))
2448 && (q
.sitd
->hw_results
&
2449 SITD_ACTIVE(ehci
))) {
2452 q_p
= &q
.sitd
->sitd_next
;
2453 hw_p
= &q
.sitd
->hw_next
;
2454 type
= Q_NEXT_TYPE(ehci
,
2460 /* Take finished SITDs out of the schedule
2461 * and process them: recycle, maybe report
2464 *q_p
= q
.sitd
->sitd_next
;
2465 if (!ehci
->use_dummy_qh
||
2466 q
.sitd
->hw_next
!= EHCI_LIST_END(ehci
))
2467 *hw_p
= q
.sitd
->hw_next
;
2469 *hw_p
= ehci
->dummy
->qh_dma
;
2470 type
= Q_NEXT_TYPE(ehci
, q
.sitd
->hw_next
);
2472 modified
= sitd_complete (ehci
, q
.sitd
);
2476 dbg ("corrupt type %d frame %d shadow %p",
2477 type
, frame
, q
.ptr
);
2482 /* assume completion callbacks modify the queue */
2483 if (unlikely (modified
)) {
2484 if (likely(ehci
->periodic_sched
> 0))
2486 /* short-circuit this scan */
2492 /* If we can tell we caught up to the hardware, stop now.
2493 * We can't advance our scan without collecting the ISO
2494 * transfers that are still pending in this frame.
2496 if (incomplete
&& HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
)) {
2497 ehci
->next_uframe
= now_uframe
;
2501 // FIXME: this assumes we won't get lapped when
2502 // latencies climb; that should be rare, but...
2503 // detect it, and just go all the way around.
2504 // FLR might help detect this case, so long as latencies
2505 // don't exceed periodic_size msec (default 1.024 sec).
2507 // FIXME: likewise assumes HC doesn't halt mid-scan
2509 if (now_uframe
== clock
) {
2512 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)
2513 || ehci
->periodic_sched
== 0)
2515 ehci
->next_uframe
= now_uframe
;
2516 now
= ehci_readl(ehci
, &ehci
->regs
->frame_index
) &
2518 if (now_uframe
== now
)
2521 /* rescan the rest of this frame, then ... */
2523 clock_frame
= clock
>> 3;
2524 if (ehci
->clock_frame
!= clock_frame
) {
2525 free_cached_lists(ehci
);
2526 ehci
->clock_frame
= clock_frame
;
2530 now_uframe
&= mod
- 1;