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[media] ir-core: make struct rc_dev the primary interface
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / rc / nuvoton-cir.c
blob0ce328f9dacf64fb0244a1febc33640a4f9d3e41
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pnp.h>
31 #include <linux/io.h>
32 #include <linux/interrupt.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <media/ir-core.h>
36 #include <linux/pci_ids.h>
37
38 #include "nuvoton-cir.h"
39
40 static char *chip_id = "w836x7hg";
41
42 /* write val to config reg */
43 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
44 {
45 outb(reg, nvt->cr_efir);
46 outb(val, nvt->cr_efdr);
47 }
48
49 /* read val from config reg */
50 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
51 {
52 outb(reg, nvt->cr_efir);
53 return inb(nvt->cr_efdr);
54 }
55
56 /* update config register bit without changing other bits */
57 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
58 {
59 u8 tmp = nvt_cr_read(nvt, reg) | val;
60 nvt_cr_write(nvt, tmp, reg);
61 }
62
63 /* clear config register bit without changing other bits */
64 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
65 {
66 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
67 nvt_cr_write(nvt, tmp, reg);
68 }
69
70 /* enter extended function mode */
71 static inline void nvt_efm_enable(struct nvt_dev *nvt)
72 {
73 /* Enabling Extended Function Mode explicitly requires writing 2x */
74 outb(EFER_EFM_ENABLE, nvt->cr_efir);
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76 }
77
78 /* exit extended function mode */
79 static inline void nvt_efm_disable(struct nvt_dev *nvt)
80 {
81 outb(EFER_EFM_DISABLE, nvt->cr_efir);
82 }
83
84 /*
85 * When you want to address a specific logical device, write its logical
86 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
87 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
88 */
89 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
90 {
91 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
92 outb(ldev, nvt->cr_efdr);
93 }
94
95 /* write val to cir config register */
96 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
97 {
98 outb(val, nvt->cir_addr + offset);
99 }
100
101 /* read val from cir config register */
102 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
103 {
104 u8 val;
105
106 val = inb(nvt->cir_addr + offset);
107
108 return val;
109 }
110
111 /* write val to cir wake register */
112 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
113 u8 val, u8 offset)
114 {
115 outb(val, nvt->cir_wake_addr + offset);
116 }
117
118 /* read val from cir wake config register */
119 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
120 {
121 u8 val;
122
123 val = inb(nvt->cir_wake_addr + offset);
124
125 return val;
126 }
127
128 #define pr_reg(text, ...) \
129 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
130
131 /* dump current cir register contents */
132 static void cir_dump_regs(struct nvt_dev *nvt)
133 {
134 nvt_efm_enable(nvt);
135 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
136
137 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
138 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
139 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
140 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
141 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
142 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
143 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
144 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
145
146 nvt_efm_disable(nvt);
147
148 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
149 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
150 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
151 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
152 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
153 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
154 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
155 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
156 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
157 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
158 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
159 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
160 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
161 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
162 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
163 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
164 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
165 }
166
167 /* dump current cir wake register contents */
168 static void cir_wake_dump_regs(struct nvt_dev *nvt)
169 {
170 u8 i, fifo_len;
171
172 nvt_efm_enable(nvt);
173 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
174
175 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
176 NVT_DRIVER_NAME);
177 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
178 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
179 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
180 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
181 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
182 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
183 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
184
185 nvt_efm_disable(nvt);
186
187 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
188 pr_reg(" * IRCON: 0x%x\n",
189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
190 pr_reg(" * IRSTS: 0x%x\n",
191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
192 pr_reg(" * IREN: 0x%x\n",
193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
194 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
196 pr_reg(" * FIFO CMP TOL: 0x%x\n",
197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
198 pr_reg(" * FIFO COUNT: 0x%x\n",
199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
200 pr_reg(" * SLCH: 0x%x\n",
201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
202 pr_reg(" * SLCL: 0x%x\n",
203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
204 pr_reg(" * FIFOCON: 0x%x\n",
205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
206 pr_reg(" * SRXFSTS: 0x%x\n",
207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
208 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
210 pr_reg(" * WR FIFO DATA: 0x%x\n",
211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
212 pr_reg(" * RD FIFO ONLY: 0x%x\n",
213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
214 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
216 pr_reg(" * FIFO IGNORE: 0x%x\n",
217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
218 pr_reg(" * IRFSM: 0x%x\n",
219 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
220
221 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
222 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
223 pr_reg("* Contents = ");
224 for (i = 0; i < fifo_len; i++)
225 printk(KERN_CONT "%02x ",
226 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
227 printk(KERN_CONT "\n");
228 }
229
230 /* detect hardware features */
231 static int nvt_hw_detect(struct nvt_dev *nvt)
232 {
233 unsigned long flags;
234 u8 chip_major, chip_minor;
235 int ret = 0;
236
237 nvt_efm_enable(nvt);
238
239 /* Check if we're wired for the alternate EFER setup */
240 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
241 if (chip_major == 0xff) {
242 nvt->cr_efir = CR_EFIR2;
243 nvt->cr_efdr = CR_EFDR2;
244 nvt_efm_enable(nvt);
245 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
246 }
247
248 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
249 nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
250
251 if (chip_major != CHIP_ID_HIGH &&
252 (chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
253 ret = -ENODEV;
254
255 nvt_efm_disable(nvt);
256
257 spin_lock_irqsave(&nvt->nvt_lock, flags);
258 nvt->chip_major = chip_major;
259 nvt->chip_minor = chip_minor;
260 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
261
262 return ret;
263 }
264
265 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
266 {
267 u8 val;
268
269 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
270 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
271 val &= OUTPUT_PIN_SEL_MASK;
272 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
273 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
274
275 /* Select CIR logical device and enable */
276 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
277 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
278
279 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
280 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
281
282 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
283
284 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
285 nvt->cir_addr, nvt->cir_irq);
286 }
287
288 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
289 {
290 /* Select ACPI logical device, enable it and CIR Wake */
291 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
292 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
293
294 /* Enable CIR Wake via PSOUT# (Pin60) */
295 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
296
297 /* enable cir interrupt of mouse/keyboard IRQ event */
298 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
299
300 /* enable pme interrupt of cir wakeup event */
301 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
302
303 /* Select CIR Wake logical device and enable */
304 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
305 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
306
307 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
308 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
309
310 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
311
312 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
313 nvt->cir_wake_addr, nvt->cir_wake_irq);
314 }
315
316 /* clear out the hardware's cir rx fifo */
317 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
318 {
319 u8 val;
320
321 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
322 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
323 }
324
325 /* clear out the hardware's cir wake rx fifo */
326 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
327 {
328 u8 val;
329
330 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
331 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
332 CIR_WAKE_FIFOCON);
333 }
334
335 /* clear out the hardware's cir tx fifo */
336 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
337 {
338 u8 val;
339
340 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
341 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
342 }
343
344 /* enable RX Trigger Level Reach and Packet End interrupts */
345 static void nvt_set_cir_iren(struct nvt_dev *nvt)
346 {
347 u8 iren;
348
349 iren = CIR_IREN_RTR | CIR_IREN_PE;
350 nvt_cir_reg_write(nvt, iren, CIR_IREN);
351 }
352
353 static void nvt_cir_regs_init(struct nvt_dev *nvt)
354 {
355 /* set sample limit count (PE interrupt raised when reached) */
356 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
357 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
358
359 /* set fifo irq trigger levels */
360 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
361 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
362
363 /*
364 * Enable TX and RX, specify carrier on = low, off = high, and set
365 * sample period (currently 50us)
366 */
367 nvt_cir_reg_write(nvt,
368 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
369 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
370 CIR_IRCON);
371
372 /* clear hardware rx and tx fifos */
373 nvt_clear_cir_fifo(nvt);
374 nvt_clear_tx_fifo(nvt);
375
376 /* clear any and all stray interrupts */
377 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
378
379 /* and finally, enable interrupts */
380 nvt_set_cir_iren(nvt);
381 }
382
383 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
384 {
385 /* set number of bytes needed for wake key comparison (default 67) */
386 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
387
388 /* set tolerance/variance allowed per byte during wake compare */
389 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
390 CIR_WAKE_FIFO_CMP_TOL);
391
392 /* set sample limit count (PE interrupt raised when reached) */
393 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
394 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
395
396 /* set cir wake fifo rx trigger level (currently 67) */
397 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
398 CIR_WAKE_FIFOCON);
399
400 /*
401 * Enable TX and RX, specific carrier on = low, off = high, and set
402 * sample period (currently 50us)
403 */
404 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
405 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
406 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
407 CIR_WAKE_IRCON);
408
409 /* clear cir wake rx fifo */
410 nvt_clear_cir_wake_fifo(nvt);
411
412 /* clear any and all stray interrupts */
413 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
414 }
415
416 static void nvt_enable_wake(struct nvt_dev *nvt)
417 {
418 nvt_efm_enable(nvt);
419
420 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
421 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
422 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
423 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
424
425 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
426 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
427
428 nvt_efm_disable(nvt);
429
430 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
431 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
432 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
433 CIR_WAKE_IRCON);
434 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
435 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
436 }
437
438 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
439 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
440 {
441 u32 count, carrier, duration = 0;
442 int i;
443
444 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
445 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
446
447 for (i = 0; i < nvt->pkts; i++) {
448 if (nvt->buf[i] & BUF_PULSE_BIT)
449 duration += nvt->buf[i] & BUF_LEN_MASK;
450 }
451
452 duration *= SAMPLE_PERIOD;
453
454 if (!count || !duration) {
455 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
456 count, duration);
457 return 0;
458 }
459
460 carrier = (count * 1000000) / duration;
461
462 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
463 nvt_dbg("WTF? Carrier frequency out of range!");
464
465 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
466 carrier, count, duration);
467
468 return carrier;
469 }
470
471 /*
472 * set carrier frequency
473 *
474 * set carrier on 2 registers: CP & CC
475 * always set CP as 0x81
476 * set CC by SPEC, CC = 3MHz/carrier - 1
477 */
478 static int nvt_set_tx_carrier(struct rc_dev *dev, u32 carrier)
479 {
480 struct nvt_dev *nvt = dev->priv;
481 u16 val;
482
483 nvt_cir_reg_write(nvt, 1, CIR_CP);
484 val = 3000000 / (carrier) - 1;
485 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
486
487 nvt_dbg("cp: 0x%x cc: 0x%x\n",
488 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
489
490 return 0;
491 }
492
493 /*
494 * nvt_tx_ir
495 *
496 * 1) clean TX fifo first (handled by AP)
497 * 2) copy data from user space
498 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
499 * 4) send 9 packets to TX FIFO to open TTR
500 * in interrupt_handler:
501 * 5) send all data out
502 * go back to write():
503 * 6) disable TX interrupts, re-enable RX interupts
504 *
505 * The key problem of this function is user space data may larger than
506 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
507 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
508 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
509 * set TXFCONT as 0xff, until buf_count less than 0xff.
510 */
511 static int nvt_tx_ir(struct rc_dev *dev, int *txbuf, u32 n)
512 {
513 struct nvt_dev *nvt = dev->priv;
514 unsigned long flags;
515 size_t cur_count;
516 unsigned int i;
517 u8 iren;
518 int ret;
519
520 spin_lock_irqsave(&nvt->tx.lock, flags);
521
522 if (n >= TX_BUF_LEN) {
523 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
524 ret = TX_BUF_LEN;
525 } else {
526 nvt->tx.buf_count = cur_count = n;
527 ret = n;
528 }
529
530 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
531
532 nvt->tx.cur_buf_num = 0;
533
534 /* save currently enabled interrupts */
535 iren = nvt_cir_reg_read(nvt, CIR_IREN);
536
537 /* now disable all interrupts, save TFU & TTR */
538 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
539
540 nvt->tx.tx_state = ST_TX_REPLY;
541
542 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
543 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
544
545 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
546 for (i = 0; i < 9; i++)
547 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
548
549 spin_unlock_irqrestore(&nvt->tx.lock, flags);
550
551 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
552
553 spin_lock_irqsave(&nvt->tx.lock, flags);
554 nvt->tx.tx_state = ST_TX_NONE;
555 spin_unlock_irqrestore(&nvt->tx.lock, flags);
556
557 /* restore enabled interrupts to prior state */
558 nvt_cir_reg_write(nvt, iren, CIR_IREN);
559
560 return ret;
561 }
562
563 /* dump contents of the last rx buffer we got from the hw rx fifo */
564 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
565 {
566 int i;
567
568 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
569 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
570 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
571 printk(KERN_CONT "\n");
572 }
573
574 /*
575 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
576 * trigger decode when appropriate.
577 *
578 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
579 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
580 * (default 50us) intervals for that pulse/space. A discrete signal is
581 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
582 * to signal more IR coming (repeats) or end of IR, respectively. We store
583 * sample data in the raw event kfifo until we see 0x7<something> (except f)
584 * or 0x80, at which time, we trigger a decode operation.
585 */
586 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
587 {
588 DEFINE_IR_RAW_EVENT(rawir);
589 unsigned int count;
590 u32 carrier;
591 u8 sample;
592 int i;
593
594 nvt_dbg_verbose("%s firing", __func__);
595
596 if (debug)
597 nvt_dump_rx_buf(nvt);
598
599 if (nvt->carrier_detect_enabled)
600 carrier = nvt_rx_carrier_detect(nvt);
601
602 count = nvt->pkts;
603 nvt_dbg_verbose("Processing buffer of len %d", count);
604
605 init_ir_raw_event(&rawir);
606
607 for (i = 0; i < count; i++) {
608 nvt->pkts--;
609 sample = nvt->buf[i];
610
611 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
612 rawir.duration = (sample & BUF_LEN_MASK)
613 * SAMPLE_PERIOD * 1000;
614
615 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
616 if (nvt->rawir.pulse == rawir.pulse)
617 nvt->rawir.duration += rawir.duration;
618 else {
619 nvt->rawir.duration = rawir.duration;
620 nvt->rawir.pulse = rawir.pulse;
621 }
622 continue;
623 }
624
625 rawir.duration += nvt->rawir.duration;
626
627 init_ir_raw_event(&nvt->rawir);
628 nvt->rawir.duration = 0;
629 nvt->rawir.pulse = rawir.pulse;
630
631 if (sample == BUF_PULSE_BIT)
632 rawir.pulse = false;
633
634 if (rawir.duration) {
635 nvt_dbg("Storing %s with duration %d",
636 rawir.pulse ? "pulse" : "space",
637 rawir.duration);
638
639 ir_raw_event_store(nvt->rdev, &rawir);
640 }
641
642 /*
643 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
644 * indicates end of IR signal, but new data incoming. In both
645 * cases, it means we're ready to call ir_raw_event_handle
646 */
647 if ((sample == BUF_PULSE_BIT) && nvt->pkts) {
648 nvt_dbg("Calling ir_raw_event_handle (signal end)\n");
649 ir_raw_event_handle(nvt->rdev);
650 }
651 }
652
653 nvt_dbg("Calling ir_raw_event_handle (buffer empty)\n");
654 ir_raw_event_handle(nvt->rdev);
655
656 if (nvt->pkts) {
657 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
658 nvt->pkts = 0;
659 }
660
661 nvt_dbg_verbose("%s done", __func__);
662 }
663
664 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
665 {
666 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
667
668 nvt->pkts = 0;
669 nvt_clear_cir_fifo(nvt);
670 ir_raw_event_reset(nvt->rdev);
671 }
672
673 /* copy data from hardware rx fifo into driver buffer */
674 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
675 {
676 unsigned long flags;
677 u8 fifocount, val;
678 unsigned int b_idx;
679 bool overrun = false;
680 int i;
681
682 /* Get count of how many bytes to read from RX FIFO */
683 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
684 /* if we get 0xff, probably means the logical dev is disabled */
685 if (fifocount == 0xff)
686 return;
687 /* watch out for a fifo overrun condition */
688 else if (fifocount > RX_BUF_LEN) {
689 overrun = true;
690 fifocount = RX_BUF_LEN;
691 }
692
693 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
694
695 spin_lock_irqsave(&nvt->nvt_lock, flags);
696
697 b_idx = nvt->pkts;
698
699 /* This should never happen, but lets check anyway... */
700 if (b_idx + fifocount > RX_BUF_LEN) {
701 nvt_process_rx_ir_data(nvt);
702 b_idx = 0;
703 }
704
705 /* Read fifocount bytes from CIR Sample RX FIFO register */
706 for (i = 0; i < fifocount; i++) {
707 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
708 nvt->buf[b_idx + i] = val;
709 }
710
711 nvt->pkts += fifocount;
712 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
713
714 nvt_process_rx_ir_data(nvt);
715
716 if (overrun)
717 nvt_handle_rx_fifo_overrun(nvt);
718
719 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
720 }
721
722 static void nvt_cir_log_irqs(u8 status, u8 iren)
723 {
724 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
725 status, iren,
726 status & CIR_IRSTS_RDR ? " RDR" : "",
727 status & CIR_IRSTS_RTR ? " RTR" : "",
728 status & CIR_IRSTS_PE ? " PE" : "",
729 status & CIR_IRSTS_RFO ? " RFO" : "",
730 status & CIR_IRSTS_TE ? " TE" : "",
731 status & CIR_IRSTS_TTR ? " TTR" : "",
732 status & CIR_IRSTS_TFU ? " TFU" : "",
733 status & CIR_IRSTS_GH ? " GH" : "",
734 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
735 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
736 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
737 }
738
739 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
740 {
741 unsigned long flags;
742 bool tx_inactive;
743 u8 tx_state;
744
745 spin_lock_irqsave(&nvt->tx.lock, flags);
746 tx_state = nvt->tx.tx_state;
747 spin_unlock_irqrestore(&nvt->tx.lock, flags);
748
749 tx_inactive = (tx_state == ST_TX_NONE);
750
751 return tx_inactive;
752 }
753
754 /* interrupt service routine for incoming and outgoing CIR data */
755 static irqreturn_t nvt_cir_isr(int irq, void *data)
756 {
757 struct nvt_dev *nvt = data;
758 u8 status, iren, cur_state;
759 unsigned long flags;
760
761 nvt_dbg_verbose("%s firing", __func__);
762
763 nvt_efm_enable(nvt);
764 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
765 nvt_efm_disable(nvt);
766
767 /*
768 * Get IR Status register contents. Write 1 to ack/clear
769 *
770 * bit: reg name - description
771 * 7: CIR_IRSTS_RDR - RX Data Ready
772 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
773 * 5: CIR_IRSTS_PE - Packet End
774 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
775 * 3: CIR_IRSTS_TE - TX FIFO Empty
776 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
777 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
778 * 0: CIR_IRSTS_GH - Min Length Detected
779 */
780 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
781 if (!status) {
782 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
783 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
784 return IRQ_RETVAL(IRQ_NONE);
785 }
786
787 /* ack/clear all irq flags we've got */
788 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
789 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
790
791 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
792 iren = nvt_cir_reg_read(nvt, CIR_IREN);
793 if (!iren) {
794 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
795 return IRQ_RETVAL(IRQ_NONE);
796 }
797
798 if (debug)
799 nvt_cir_log_irqs(status, iren);
800
801 if (status & CIR_IRSTS_RTR) {
802 /* FIXME: add code for study/learn mode */
803 /* We only do rx if not tx'ing */
804 if (nvt_cir_tx_inactive(nvt))
805 nvt_get_rx_ir_data(nvt);
806 }
807
808 if (status & CIR_IRSTS_PE) {
809 if (nvt_cir_tx_inactive(nvt))
810 nvt_get_rx_ir_data(nvt);
811
812 spin_lock_irqsave(&nvt->nvt_lock, flags);
813
814 cur_state = nvt->study_state;
815
816 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
817
818 if (cur_state == ST_STUDY_NONE)
819 nvt_clear_cir_fifo(nvt);
820 }
821
822 if (status & CIR_IRSTS_TE)
823 nvt_clear_tx_fifo(nvt);
824
825 if (status & CIR_IRSTS_TTR) {
826 unsigned int pos, count;
827 u8 tmp;
828
829 spin_lock_irqsave(&nvt->tx.lock, flags);
830
831 pos = nvt->tx.cur_buf_num;
832 count = nvt->tx.buf_count;
833
834 /* Write data into the hardware tx fifo while pos < count */
835 if (pos < count) {
836 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
837 nvt->tx.cur_buf_num++;
838 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
839 } else {
840 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
841 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
842 }
843
844 spin_unlock_irqrestore(&nvt->tx.lock, flags);
845
846 }
847
848 if (status & CIR_IRSTS_TFU) {
849 spin_lock_irqsave(&nvt->tx.lock, flags);
850 if (nvt->tx.tx_state == ST_TX_REPLY) {
851 nvt->tx.tx_state = ST_TX_REQUEST;
852 wake_up(&nvt->tx.queue);
853 }
854 spin_unlock_irqrestore(&nvt->tx.lock, flags);
855 }
856
857 nvt_dbg_verbose("%s done", __func__);
858 return IRQ_RETVAL(IRQ_HANDLED);
859 }
860
861 /* Interrupt service routine for CIR Wake */
862 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
863 {
864 u8 status, iren, val;
865 struct nvt_dev *nvt = data;
866 unsigned long flags;
867
868 nvt_dbg_wake("%s firing", __func__);
869
870 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
871 if (!status)
872 return IRQ_RETVAL(IRQ_NONE);
873
874 if (status & CIR_WAKE_IRSTS_IR_PENDING)
875 nvt_clear_cir_wake_fifo(nvt);
876
877 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
878 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
879
880 /* Interrupt may be shared with CIR, bail if Wake not enabled */
881 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
882 if (!iren) {
883 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
884 return IRQ_RETVAL(IRQ_HANDLED);
885 }
886
887 if ((status & CIR_WAKE_IRSTS_PE) &&
888 (nvt->wake_state == ST_WAKE_START)) {
889 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
890 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
891 nvt_dbg("setting wake up key: 0x%x", val);
892 }
893
894 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
895 spin_lock_irqsave(&nvt->nvt_lock, flags);
896 nvt->wake_state = ST_WAKE_FINISH;
897 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
898 }
899
900 nvt_dbg_wake("%s done", __func__);
901 return IRQ_RETVAL(IRQ_HANDLED);
902 }
903
904 static void nvt_enable_cir(struct nvt_dev *nvt)
905 {
906 /* set function enable flags */
907 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
908 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
909 CIR_IRCON);
910
911 nvt_efm_enable(nvt);
912
913 /* enable the CIR logical device */
914 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
915 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
916
917 nvt_efm_disable(nvt);
918
919 /* clear all pending interrupts */
920 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
921
922 /* enable interrupts */
923 nvt_set_cir_iren(nvt);
924 }
925
926 static void nvt_disable_cir(struct nvt_dev *nvt)
927 {
928 /* disable CIR interrupts */
929 nvt_cir_reg_write(nvt, 0, CIR_IREN);
930
931 /* clear any and all pending interrupts */
932 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
933
934 /* clear all function enable flags */
935 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
936
937 /* clear hardware rx and tx fifos */
938 nvt_clear_cir_fifo(nvt);
939 nvt_clear_tx_fifo(nvt);
940
941 nvt_efm_enable(nvt);
942
943 /* disable the CIR logical device */
944 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
945 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
946
947 nvt_efm_disable(nvt);
948 }
949
950 static int nvt_open(struct rc_dev *dev)
951 {
952 struct nvt_dev *nvt = dev->priv;
953 unsigned long flags;
954
955 spin_lock_irqsave(&nvt->nvt_lock, flags);
956 nvt->in_use = true;
957 nvt_enable_cir(nvt);
958 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
959
960 return 0;
961 }
962
963 static void nvt_close(struct rc_dev *dev)
964 {
965 struct nvt_dev *nvt = dev->priv;
966 unsigned long flags;
967
968 spin_lock_irqsave(&nvt->nvt_lock, flags);
969 nvt->in_use = false;
970 nvt_disable_cir(nvt);
971 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
972 }
973
974 /* Allocate memory, probe hardware, and initialize everything */
975 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
976 {
977 struct nvt_dev *nvt;
978 struct rc_dev *rdev;
979 int ret = -ENOMEM;
980
981 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
982 if (!nvt)
983 return ret;
984
985 /* input device for IR remote (and tx) */
986 rdev = rc_allocate_device();
987 if (!rdev)
988 goto failure;
989
990 ret = -ENODEV;
991 /* validate pnp resources */
992 if (!pnp_port_valid(pdev, 0) ||
993 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
994 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
995 goto failure;
996 }
997
998 if (!pnp_irq_valid(pdev, 0)) {
999 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1000 goto failure;
1001 }
1002
1003 if (!pnp_port_valid(pdev, 1) ||
1004 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1005 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1006 goto failure;
1007 }
1008
1009 nvt->cir_addr = pnp_port_start(pdev, 0);
1010 nvt->cir_irq = pnp_irq(pdev, 0);
1011
1012 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1013 /* irq is always shared between cir and cir wake */
1014 nvt->cir_wake_irq = nvt->cir_irq;
1015
1016 nvt->cr_efir = CR_EFIR;
1017 nvt->cr_efdr = CR_EFDR;
1018
1019 spin_lock_init(&nvt->nvt_lock);
1020 spin_lock_init(&nvt->tx.lock);
1021 init_ir_raw_event(&nvt->rawir);
1022
1023 ret = -EBUSY;
1024 /* now claim resources */
1025 if (!request_region(nvt->cir_addr,
1026 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1027 goto failure;
1028
1029 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1030 NVT_DRIVER_NAME, (void *)nvt))
1031 goto failure;
1032
1033 if (!request_region(nvt->cir_wake_addr,
1034 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1035 goto failure;
1036
1037 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1038 NVT_DRIVER_NAME, (void *)nvt))
1039 goto failure;
1040
1041 pnp_set_drvdata(pdev, nvt);
1042 nvt->pdev = pdev;
1043
1044 init_waitqueue_head(&nvt->tx.queue);
1045
1046 ret = nvt_hw_detect(nvt);
1047 if (ret)
1048 goto failure;
1049
1050 /* Initialize CIR & CIR Wake Logical Devices */
1051 nvt_efm_enable(nvt);
1052 nvt_cir_ldev_init(nvt);
1053 nvt_cir_wake_ldev_init(nvt);
1054 nvt_efm_disable(nvt);
1055
1056 /* Initialize CIR & CIR Wake Config Registers */
1057 nvt_cir_regs_init(nvt);
1058 nvt_cir_wake_regs_init(nvt);
1059
1060 /* Set up the rc device */
1061 rdev->priv = nvt;
1062 rdev->driver_type = RC_DRIVER_IR_RAW;
1063 rdev->allowed_protos = IR_TYPE_ALL;
1064 rdev->open = nvt_open;
1065 rdev->close = nvt_close;
1066 rdev->tx_ir = nvt_tx_ir;
1067 rdev->s_tx_carrier = nvt_set_tx_carrier;
1068 rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1069 rdev->input_id.bustype = BUS_HOST;
1070 rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
1071 rdev->input_id.product = nvt->chip_major;
1072 rdev->input_id.version = nvt->chip_minor;
1073 rdev->driver_name = NVT_DRIVER_NAME;
1074 rdev->map_name = RC_MAP_RC6_MCE;
1075 #if 0
1076 rdev->min_timeout = XYZ;
1077 rdev->max_timeout = XYZ;
1078 rdev->timeout = XYZ;
1079 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1080 rdev->rx_resolution = XYZ;
1081 /* tx bits */
1082 rdev->tx_resolution = XYZ;
1083 #endif
1084
1085 ret = rc_register_device(rdev);
1086 if (ret)
1087 goto failure;
1088
1089 device_set_wakeup_capable(&pdev->dev, 1);
1090 device_set_wakeup_enable(&pdev->dev, 1);
1091 nvt->rdev = rdev;
1092 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1093 if (debug) {
1094 cir_dump_regs(nvt);
1095 cir_wake_dump_regs(nvt);
1096 }
1097
1098 return 0;
1099
1100 failure:
1101 if (nvt->cir_irq)
1102 free_irq(nvt->cir_irq, nvt);
1103 if (nvt->cir_addr)
1104 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1105
1106 if (nvt->cir_wake_irq)
1107 free_irq(nvt->cir_wake_irq, nvt);
1108 if (nvt->cir_wake_addr)
1109 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1110
1111 rc_free_device(rdev);
1112 kfree(nvt);
1113
1114 return ret;
1115 }
1116
1117 static void __devexit nvt_remove(struct pnp_dev *pdev)
1118 {
1119 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&nvt->nvt_lock, flags);
1123 /* disable CIR */
1124 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1125 nvt_disable_cir(nvt);
1126 /* enable CIR Wake (for IR power-on) */
1127 nvt_enable_wake(nvt);
1128 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1129
1130 /* free resources */
1131 free_irq(nvt->cir_irq, nvt);
1132 free_irq(nvt->cir_wake_irq, nvt);
1133 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1134 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1135
1136 rc_unregister_device(nvt->rdev);
1137
1138 kfree(nvt);
1139 }
1140
1141 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1142 {
1143 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1144 unsigned long flags;
1145
1146 nvt_dbg("%s called", __func__);
1147
1148 /* zero out misc state tracking */
1149 spin_lock_irqsave(&nvt->nvt_lock, flags);
1150 nvt->study_state = ST_STUDY_NONE;
1151 nvt->wake_state = ST_WAKE_NONE;
1152 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1153
1154 spin_lock_irqsave(&nvt->tx.lock, flags);
1155 nvt->tx.tx_state = ST_TX_NONE;
1156 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1157
1158 /* disable all CIR interrupts */
1159 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1160
1161 nvt_efm_enable(nvt);
1162
1163 /* disable cir logical dev */
1164 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1165 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1166
1167 nvt_efm_disable(nvt);
1168
1169 /* make sure wake is enabled */
1170 nvt_enable_wake(nvt);
1171
1172 return 0;
1173 }
1174
1175 static int nvt_resume(struct pnp_dev *pdev)
1176 {
1177 int ret = 0;
1178 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1179
1180 nvt_dbg("%s called", __func__);
1181
1182 /* open interrupt */
1183 nvt_set_cir_iren(nvt);
1184
1185 /* Enable CIR logical device */
1186 nvt_efm_enable(nvt);
1187 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1188 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1189
1190 nvt_efm_disable(nvt);
1191
1192 nvt_cir_regs_init(nvt);
1193 nvt_cir_wake_regs_init(nvt);
1194
1195 return ret;
1196 }
1197
1198 static void nvt_shutdown(struct pnp_dev *pdev)
1199 {
1200 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1201 nvt_enable_wake(nvt);
1202 }
1203
1204 static const struct pnp_device_id nvt_ids[] = {
1205 { "WEC0530", 0 }, /* CIR */
1206 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1207 { "", 0 },
1208 };
1209
1210 static struct pnp_driver nvt_driver = {
1211 .name = NVT_DRIVER_NAME,
1212 .id_table = nvt_ids,
1213 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1214 .probe = nvt_probe,
1215 .remove = __devexit_p(nvt_remove),
1216 .suspend = nvt_suspend,
1217 .resume = nvt_resume,
1218 .shutdown = nvt_shutdown,
1219 };
1220
1221 int nvt_init(void)
1222 {
1223 return pnp_register_driver(&nvt_driver);
1224 }
1225
1226 void nvt_exit(void)
1227 {
1228 pnp_unregister_driver(&nvt_driver);
1229 }
1230
1231 module_param(debug, int, S_IRUGO | S_IWUSR);
1232 MODULE_PARM_DESC(debug, "Enable debugging output");
1233
1234 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1235 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1236
1237 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1238 MODULE_LICENSE("GPL");
1239
1240 module_init(nvt_init);
1241 module_exit(nvt_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree