2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
55 #include <linux/etherdevice.h>
57 #include <net/ieee80211_radiotap.h>
59 #include <asm/unaligned.h>
67 static int modparam_nohwcrypt
;
68 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
69 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
71 static int modparam_all_channels
;
72 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
73 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
76 MODULE_AUTHOR("Jiri Slaby");
77 MODULE_AUTHOR("Nick Kossifidis");
78 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80 MODULE_LICENSE("Dual BSD/GPL");
81 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
84 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
85 struct ieee80211_vif
*vif
);
86 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
89 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table
) = {
90 { PCI_VDEVICE(ATHEROS
, 0x0207) }, /* 5210 early */
91 { PCI_VDEVICE(ATHEROS
, 0x0007) }, /* 5210 */
92 { PCI_VDEVICE(ATHEROS
, 0x0011) }, /* 5311 - this is on AHB bus !*/
93 { PCI_VDEVICE(ATHEROS
, 0x0012) }, /* 5211 */
94 { PCI_VDEVICE(ATHEROS
, 0x0013) }, /* 5212 */
95 { PCI_VDEVICE(3COM_2
, 0x0013) }, /* 3com 5212 */
96 { PCI_VDEVICE(3COM
, 0x0013) }, /* 3com 3CRDAG675 5212 */
97 { PCI_VDEVICE(ATHEROS
, 0x1014) }, /* IBM minipci 5212 */
98 { PCI_VDEVICE(ATHEROS
, 0x0014) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0015) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0016) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x0017) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS
, 0x0018) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS
, 0x0019) }, /* 5212 combatible */
104 { PCI_VDEVICE(ATHEROS
, 0x001a) }, /* 2413 Griffin-lite */
105 { PCI_VDEVICE(ATHEROS
, 0x001b) }, /* 5413 Eagle */
106 { PCI_VDEVICE(ATHEROS
, 0x001c) }, /* PCI-E cards */
107 { PCI_VDEVICE(ATHEROS
, 0x001d) }, /* 2417 Nala */
110 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
113 static const struct ath5k_srev_name srev_names
[] = {
114 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
115 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
116 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
117 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
118 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
119 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
120 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
121 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
122 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
123 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
124 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
125 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
126 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
127 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
128 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
129 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
130 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
131 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
132 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
133 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
134 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
135 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
136 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
137 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
138 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
139 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
140 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
141 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
142 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
143 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
144 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
145 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
146 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
147 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
148 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
149 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
152 static const struct ieee80211_rate ath5k_rates
[] = {
154 .hw_value
= ATH5K_RATE_CODE_1M
, },
156 .hw_value
= ATH5K_RATE_CODE_2M
,
157 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
158 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
160 .hw_value
= ATH5K_RATE_CODE_5_5M
,
161 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
162 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
164 .hw_value
= ATH5K_RATE_CODE_11M
,
165 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
166 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
168 .hw_value
= ATH5K_RATE_CODE_6M
,
171 .hw_value
= ATH5K_RATE_CODE_9M
,
174 .hw_value
= ATH5K_RATE_CODE_12M
,
177 .hw_value
= ATH5K_RATE_CODE_18M
,
180 .hw_value
= ATH5K_RATE_CODE_24M
,
183 .hw_value
= ATH5K_RATE_CODE_36M
,
186 .hw_value
= ATH5K_RATE_CODE_48M
,
189 .hw_value
= ATH5K_RATE_CODE_54M
,
194 static inline void ath5k_txbuf_free_skb(struct ath5k_softc
*sc
,
195 struct ath5k_buf
*bf
)
200 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
202 dev_kfree_skb_any(bf
->skb
);
205 bf
->desc
->ds_data
= 0;
208 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc
*sc
,
209 struct ath5k_buf
*bf
)
211 struct ath5k_hw
*ah
= sc
->ah
;
212 struct ath_common
*common
= ath5k_hw_common(ah
);
217 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, common
->rx_bufsize
,
219 dev_kfree_skb_any(bf
->skb
);
222 bf
->desc
->ds_data
= 0;
226 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
228 u64 tsf
= ath5k_hw_get_tsf64(ah
);
230 if ((tsf
& 0x7fff) < rstamp
)
233 return (tsf
& ~0x7fff) | rstamp
;
237 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
239 const char *name
= "xxxxx";
242 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
243 if (srev_names
[i
].sr_type
!= type
)
246 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
247 name
= srev_names
[i
].sr_name
;
249 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
250 name
= srev_names
[i
].sr_name
;
257 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
259 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
260 return ath5k_hw_reg_read(ah
, reg_offset
);
263 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
265 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
266 ath5k_hw_reg_write(ah
, val
, reg_offset
);
269 static const struct ath_ops ath5k_common_ops
= {
270 .read
= ath5k_ioread32
,
271 .write
= ath5k_iowrite32
,
274 /***********************\
275 * Driver Initialization *
276 \***********************/
278 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
280 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
281 struct ath5k_softc
*sc
= hw
->priv
;
282 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(sc
->ah
);
284 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
287 /********************\
288 * Channel/mode setup *
289 \********************/
292 * Convert IEEE channel number to MHz frequency.
295 ath5k_ieee2mhz(short chan
)
297 if (chan
<= 14 || chan
>= 27)
298 return ieee80211chan2mhz(chan
);
300 return 2212 + chan
* 20;
304 * Returns true for the channel numbers used without all_channels modparam.
306 static bool ath5k_is_standard_channel(short chan
)
308 return ((chan
<= 14) ||
310 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
312 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
314 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
318 ath5k_copy_channels(struct ath5k_hw
*ah
,
319 struct ieee80211_channel
*channels
,
323 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
325 if (!test_bit(mode
, ah
->ah_modes
))
330 case AR5K_MODE_11A_TURBO
:
331 /* 1..220, but 2GHz frequencies are filtered by check_channel */
333 chfreq
= CHANNEL_5GHZ
;
337 case AR5K_MODE_11G_TURBO
:
339 chfreq
= CHANNEL_2GHZ
;
342 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
346 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
348 freq
= ath5k_ieee2mhz(ch
);
350 /* Check if channel is supported by the chipset */
351 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
354 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
357 /* Write channel info and increment counter */
358 channels
[count
].center_freq
= freq
;
359 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
360 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
364 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
366 case AR5K_MODE_11A_TURBO
:
367 case AR5K_MODE_11G_TURBO
:
368 channels
[count
].hw_value
= chfreq
|
369 CHANNEL_OFDM
| CHANNEL_TURBO
;
372 channels
[count
].hw_value
= CHANNEL_B
;
383 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
387 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
388 sc
->rate_idx
[b
->band
][i
] = -1;
390 for (i
= 0; i
< b
->n_bitrates
; i
++) {
391 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
392 if (b
->bitrates
[i
].hw_value_short
)
393 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
398 ath5k_setup_bands(struct ieee80211_hw
*hw
)
400 struct ath5k_softc
*sc
= hw
->priv
;
401 struct ath5k_hw
*ah
= sc
->ah
;
402 struct ieee80211_supported_band
*sband
;
403 int max_c
, count_c
= 0;
406 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
407 max_c
= ARRAY_SIZE(sc
->channels
);
410 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
411 sband
->band
= IEEE80211_BAND_2GHZ
;
412 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
414 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
416 memcpy(sband
->bitrates
, &ath5k_rates
[0],
417 sizeof(struct ieee80211_rate
) * 12);
418 sband
->n_bitrates
= 12;
420 sband
->channels
= sc
->channels
;
421 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
422 AR5K_MODE_11G
, max_c
);
424 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
425 count_c
= sband
->n_channels
;
427 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
429 memcpy(sband
->bitrates
, &ath5k_rates
[0],
430 sizeof(struct ieee80211_rate
) * 4);
431 sband
->n_bitrates
= 4;
433 /* 5211 only supports B rates and uses 4bit rate codes
434 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
437 if (ah
->ah_version
== AR5K_AR5211
) {
438 for (i
= 0; i
< 4; i
++) {
439 sband
->bitrates
[i
].hw_value
=
440 sband
->bitrates
[i
].hw_value
& 0xF;
441 sband
->bitrates
[i
].hw_value_short
=
442 sband
->bitrates
[i
].hw_value_short
& 0xF;
446 sband
->channels
= sc
->channels
;
447 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
448 AR5K_MODE_11B
, max_c
);
450 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
451 count_c
= sband
->n_channels
;
454 ath5k_setup_rate_idx(sc
, sband
);
456 /* 5GHz band, A mode */
457 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
458 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
459 sband
->band
= IEEE80211_BAND_5GHZ
;
460 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
462 memcpy(sband
->bitrates
, &ath5k_rates
[4],
463 sizeof(struct ieee80211_rate
) * 8);
464 sband
->n_bitrates
= 8;
466 sband
->channels
= &sc
->channels
[count_c
];
467 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
468 AR5K_MODE_11A
, max_c
);
470 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
472 ath5k_setup_rate_idx(sc
, sband
);
474 ath5k_debug_dump_bands(sc
);
480 * Set/change channels. We always reset the chip.
481 * To accomplish this we must first cleanup any pending DMA,
482 * then restart stuff after a la ath5k_init.
484 * Called with sc->lock.
487 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
489 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
490 "channel set, resetting (%u -> %u MHz)\n",
491 sc
->curchan
->center_freq
, chan
->center_freq
);
494 * To switch channels clear any pending DMA operations;
495 * wait long enough for the RX fifo to drain, reset the
496 * hardware at the new frequency, and then re-enable
497 * the relevant bits of the h/w.
499 return ath5k_reset(sc
, chan
);
503 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
507 if (mode
== AR5K_MODE_11A
) {
508 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
510 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
514 struct ath_vif_iter_data
{
515 const u8
*hw_macaddr
;
517 u8 active_mac
[ETH_ALEN
]; /* first active MAC */
518 bool need_set_hw_addr
;
521 enum nl80211_iftype opmode
;
524 static void ath_vif_iter(void *data
, u8
*mac
, struct ieee80211_vif
*vif
)
526 struct ath_vif_iter_data
*iter_data
= data
;
528 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
530 if (iter_data
->hw_macaddr
)
531 for (i
= 0; i
< ETH_ALEN
; i
++)
532 iter_data
->mask
[i
] &=
533 ~(iter_data
->hw_macaddr
[i
] ^ mac
[i
]);
535 if (!iter_data
->found_active
) {
536 iter_data
->found_active
= true;
537 memcpy(iter_data
->active_mac
, mac
, ETH_ALEN
);
540 if (iter_data
->need_set_hw_addr
&& iter_data
->hw_macaddr
)
541 if (compare_ether_addr(iter_data
->hw_macaddr
, mac
) == 0)
542 iter_data
->need_set_hw_addr
= false;
544 if (!iter_data
->any_assoc
) {
546 iter_data
->any_assoc
= true;
549 /* Calculate combined mode - when APs are active, operate in AP mode.
550 * Otherwise use the mode of the new interface. This can currently
551 * only deal with combinations of APs and STAs. Only one ad-hoc
552 * interfaces is allowed above.
554 if (avf
->opmode
== NL80211_IFTYPE_AP
)
555 iter_data
->opmode
= NL80211_IFTYPE_AP
;
557 if (iter_data
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
558 iter_data
->opmode
= avf
->opmode
;
561 static void ath_do_set_opmode(struct ath5k_softc
*sc
)
563 struct ath5k_hw
*ah
= sc
->ah
;
564 ath5k_hw_set_opmode(ah
, sc
->opmode
);
565 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "mode setup opmode %d (%s)\n",
566 sc
->opmode
, ath_opmode_to_string(sc
->opmode
));
569 void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc
*sc
,
570 struct ieee80211_vif
*vif
)
572 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
573 struct ath_vif_iter_data iter_data
;
576 * Use the hardware MAC address as reference, the hardware uses it
577 * together with the BSSID mask when matching addresses.
579 iter_data
.hw_macaddr
= common
->macaddr
;
580 memset(&iter_data
.mask
, 0xff, ETH_ALEN
);
581 iter_data
.found_active
= false;
582 iter_data
.need_set_hw_addr
= true;
583 iter_data
.opmode
= NL80211_IFTYPE_UNSPECIFIED
;
586 ath_vif_iter(&iter_data
, vif
->addr
, vif
);
588 /* Get list of all active MAC addresses */
589 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
591 memcpy(sc
->bssidmask
, iter_data
.mask
, ETH_ALEN
);
593 sc
->opmode
= iter_data
.opmode
;
594 if (sc
->opmode
== NL80211_IFTYPE_UNSPECIFIED
)
595 /* Nothing active, default to station mode */
596 sc
->opmode
= NL80211_IFTYPE_STATION
;
598 ath_do_set_opmode(sc
);
600 if (iter_data
.need_set_hw_addr
&& iter_data
.found_active
)
601 ath5k_hw_set_lladdr(sc
->ah
, iter_data
.active_mac
);
603 if (ath5k_hw_hasbssidmask(sc
->ah
))
604 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
608 ath5k_mode_setup(struct ath5k_softc
*sc
, struct ieee80211_vif
*vif
)
610 struct ath5k_hw
*ah
= sc
->ah
;
613 /* configure rx filter */
614 rfilt
= sc
->filter_flags
;
615 ath5k_hw_set_rx_filter(ah
, rfilt
);
616 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
618 ath5k_update_bssid_mask_and_opmode(sc
, vif
);
622 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
626 /* return base rate on errors */
627 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
628 "hw_rix out of bounds: %x\n", hw_rix
))
631 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
632 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
643 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
645 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
649 * Allocate buffer with headroom_needed space for the
650 * fake physical layer header at the start.
652 skb
= ath_rxbuf_alloc(common
,
657 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
662 *skb_addr
= pci_map_single(sc
->pdev
,
663 skb
->data
, common
->rx_bufsize
,
665 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
666 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
674 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
676 struct ath5k_hw
*ah
= sc
->ah
;
677 struct sk_buff
*skb
= bf
->skb
;
678 struct ath5k_desc
*ds
;
682 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
689 * Setup descriptors. For receive we always terminate
690 * the descriptor list with a self-linked entry so we'll
691 * not get overrun under high load (as can happen with a
692 * 5212 when ANI processing enables PHY error frames).
694 * To ensure the last descriptor is self-linked we create
695 * each descriptor as self-linked and add it to the end. As
696 * each additional descriptor is added the previous self-linked
697 * entry is "fixed" naturally. This should be safe even
698 * if DMA is happening. When processing RX interrupts we
699 * never remove/process the last, self-linked, entry on the
700 * descriptor list. This ensures the hardware always has
701 * someplace to write a new frame.
704 ds
->ds_link
= bf
->daddr
; /* link to self */
705 ds
->ds_data
= bf
->skbaddr
;
706 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
708 ATH5K_ERR(sc
, "%s: could not setup RX desc\n", __func__
);
712 if (sc
->rxlink
!= NULL
)
713 *sc
->rxlink
= bf
->daddr
;
714 sc
->rxlink
= &ds
->ds_link
;
718 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
720 struct ieee80211_hdr
*hdr
;
721 enum ath5k_pkt_type htype
;
724 hdr
= (struct ieee80211_hdr
*)skb
->data
;
725 fc
= hdr
->frame_control
;
727 if (ieee80211_is_beacon(fc
))
728 htype
= AR5K_PKT_TYPE_BEACON
;
729 else if (ieee80211_is_probe_resp(fc
))
730 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
731 else if (ieee80211_is_atim(fc
))
732 htype
= AR5K_PKT_TYPE_ATIM
;
733 else if (ieee80211_is_pspoll(fc
))
734 htype
= AR5K_PKT_TYPE_PSPOLL
;
736 htype
= AR5K_PKT_TYPE_NORMAL
;
742 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
743 struct ath5k_txq
*txq
, int padsize
)
745 struct ath5k_hw
*ah
= sc
->ah
;
746 struct ath5k_desc
*ds
= bf
->desc
;
747 struct sk_buff
*skb
= bf
->skb
;
748 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
749 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
750 struct ieee80211_rate
*rate
;
751 unsigned int mrr_rate
[3], mrr_tries
[3];
758 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
761 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
764 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
770 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
771 flags
|= AR5K_TXDESC_NOACK
;
773 rc_flags
= info
->control
.rates
[0].flags
;
774 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
775 rate
->hw_value_short
: rate
->hw_value
;
779 /* FIXME: If we are in g mode and rate is a CCK rate
780 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
781 * from tx power (value is in dB units already) */
782 if (info
->control
.hw_key
) {
783 keyidx
= info
->control
.hw_key
->hw_key_idx
;
784 pktlen
+= info
->control
.hw_key
->icv_len
;
786 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
787 flags
|= AR5K_TXDESC_RTSENA
;
788 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
789 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
790 info
->control
.vif
, pktlen
, info
));
792 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
793 flags
|= AR5K_TXDESC_CTSENA
;
794 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
795 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
796 info
->control
.vif
, pktlen
, info
));
798 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
799 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
800 get_hw_packet_type(skb
),
801 (sc
->power_level
* 2),
803 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
808 memset(mrr_rate
, 0, sizeof(mrr_rate
));
809 memset(mrr_tries
, 0, sizeof(mrr_tries
));
810 for (i
= 0; i
< 3; i
++) {
811 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
815 mrr_rate
[i
] = rate
->hw_value
;
816 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
819 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
820 mrr_rate
[0], mrr_tries
[0],
821 mrr_rate
[1], mrr_tries
[1],
822 mrr_rate
[2], mrr_tries
[2]);
825 ds
->ds_data
= bf
->skbaddr
;
827 spin_lock_bh(&txq
->lock
);
828 list_add_tail(&bf
->list
, &txq
->q
);
830 if (txq
->link
== NULL
) /* is this first packet? */
831 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
832 else /* no, so only link it */
833 *txq
->link
= bf
->daddr
;
835 txq
->link
= &ds
->ds_link
;
836 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
838 spin_unlock_bh(&txq
->lock
);
842 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
846 /*******************\
847 * Descriptors setup *
848 \*******************/
851 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
853 struct ath5k_desc
*ds
;
854 struct ath5k_buf
*bf
;
859 /* allocate descriptors */
860 sc
->desc_len
= sizeof(struct ath5k_desc
) *
861 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
862 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
863 if (sc
->desc
== NULL
) {
864 ATH5K_ERR(sc
, "can't allocate descriptors\n");
870 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
871 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
873 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
874 sizeof(struct ath5k_buf
), GFP_KERNEL
);
876 ATH5K_ERR(sc
, "can't allocate bufptr\n");
882 INIT_LIST_HEAD(&sc
->rxbuf
);
883 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
886 list_add_tail(&bf
->list
, &sc
->rxbuf
);
889 INIT_LIST_HEAD(&sc
->txbuf
);
890 sc
->txbuf_len
= ATH_TXBUF
;
891 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
895 list_add_tail(&bf
->list
, &sc
->txbuf
);
899 INIT_LIST_HEAD(&sc
->bcbuf
);
900 for (i
= 0; i
< ATH_BCBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
903 list_add_tail(&bf
->list
, &sc
->bcbuf
);
908 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
915 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
917 struct ath5k_buf
*bf
;
919 list_for_each_entry(bf
, &sc
->txbuf
, list
)
920 ath5k_txbuf_free_skb(sc
, bf
);
921 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
922 ath5k_rxbuf_free_skb(sc
, bf
);
923 list_for_each_entry(bf
, &sc
->bcbuf
, list
)
924 ath5k_txbuf_free_skb(sc
, bf
);
926 /* Free memory associated with all descriptors */
927 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
940 static struct ath5k_txq
*
941 ath5k_txq_setup(struct ath5k_softc
*sc
,
942 int qtype
, int subtype
)
944 struct ath5k_hw
*ah
= sc
->ah
;
945 struct ath5k_txq
*txq
;
946 struct ath5k_txq_info qi
= {
947 .tqi_subtype
= subtype
,
948 /* XXX: default values not correct for B and XR channels,
950 .tqi_aifs
= AR5K_TUNE_AIFS
,
951 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
952 .tqi_cw_max
= AR5K_TUNE_CWMAX
957 * Enable interrupts only for EOL and DESC conditions.
958 * We mark tx descriptors to receive a DESC interrupt
959 * when a tx queue gets deep; otherwise we wait for the
960 * EOL to reap descriptors. Note that this is done to
961 * reduce interrupt load and this only defers reaping
962 * descriptors, never transmitting frames. Aside from
963 * reducing interrupts this also permits more concurrency.
964 * The only potential downside is if the tx queue backs
965 * up in which case the top half of the kernel may backup
966 * due to a lack of tx descriptors.
968 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
969 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
970 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
973 * NB: don't print a message, this happens
974 * normally on parts with too few tx queues
976 return ERR_PTR(qnum
);
978 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
979 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
980 qnum
, ARRAY_SIZE(sc
->txqs
));
981 ath5k_hw_release_tx_queue(ah
, qnum
);
982 return ERR_PTR(-EINVAL
);
984 txq
= &sc
->txqs
[qnum
];
988 INIT_LIST_HEAD(&txq
->q
);
989 spin_lock_init(&txq
->lock
);
992 txq
->txq_poll_mark
= false;
995 return &sc
->txqs
[qnum
];
999 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1001 struct ath5k_txq_info qi
= {
1002 /* XXX: default values not correct for B and XR channels,
1004 .tqi_aifs
= AR5K_TUNE_AIFS
,
1005 .tqi_cw_min
= AR5K_TUNE_CWMIN
,
1006 .tqi_cw_max
= AR5K_TUNE_CWMAX
,
1007 /* NB: for dynamic turbo, don't enable any other interrupts */
1008 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1011 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1015 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1017 struct ath5k_hw
*ah
= sc
->ah
;
1018 struct ath5k_txq_info qi
;
1021 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1025 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1026 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1028 * Always burst out beacon and CAB traffic
1029 * (aifs = cwmin = cwmax = 0)
1034 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1036 * Adhoc mode; backoff between 0 and (2 * cw_min).
1040 qi
.tqi_cw_max
= 2 * AR5K_TUNE_CWMIN
;
1043 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1044 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1045 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1047 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1049 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1050 "hardware queue!\n", __func__
);
1053 ret
= ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */
1057 /* reconfigure cabq with ready time to 80% of beacon_interval */
1058 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1062 qi
.tqi_ready_time
= (sc
->bintval
* 80) / 100;
1063 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1067 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1073 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1075 struct ath5k_buf
*bf
, *bf0
;
1078 * NB: this assumes output has been stopped and
1079 * we do not need to block ath5k_tx_tasklet
1081 spin_lock_bh(&txq
->lock
);
1082 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1083 ath5k_debug_printtxbuf(sc
, bf
);
1085 ath5k_txbuf_free_skb(sc
, bf
);
1087 spin_lock_bh(&sc
->txbuflock
);
1088 list_move_tail(&bf
->list
, &sc
->txbuf
);
1091 spin_unlock_bh(&sc
->txbuflock
);
1094 txq
->txq_poll_mark
= false;
1095 spin_unlock_bh(&txq
->lock
);
1099 * Drain the transmit queues and reclaim resources.
1102 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1104 struct ath5k_hw
*ah
= sc
->ah
;
1107 /* XXX return value */
1108 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1109 /* don't touch the hardware if marked invalid */
1110 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1111 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1112 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1113 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1114 if (sc
->txqs
[i
].setup
) {
1115 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1116 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1119 ath5k_hw_get_txdp(ah
,
1125 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1126 if (sc
->txqs
[i
].setup
)
1127 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1131 ath5k_txq_release(struct ath5k_softc
*sc
)
1133 struct ath5k_txq
*txq
= sc
->txqs
;
1136 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1138 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1149 * Enable the receive h/w following a reset.
1152 ath5k_rx_start(struct ath5k_softc
*sc
)
1154 struct ath5k_hw
*ah
= sc
->ah
;
1155 struct ath_common
*common
= ath5k_hw_common(ah
);
1156 struct ath5k_buf
*bf
;
1159 common
->rx_bufsize
= roundup(IEEE80211_MAX_FRAME_LEN
, common
->cachelsz
);
1161 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1162 common
->cachelsz
, common
->rx_bufsize
);
1164 spin_lock_bh(&sc
->rxbuflock
);
1166 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1167 ret
= ath5k_rxbuf_setup(sc
, bf
);
1169 spin_unlock_bh(&sc
->rxbuflock
);
1173 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1174 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1175 spin_unlock_bh(&sc
->rxbuflock
);
1177 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1178 ath5k_mode_setup(sc
, NULL
); /* set filters, etc. */
1179 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1187 * Disable the receive h/w in preparation for a reset.
1190 ath5k_rx_stop(struct ath5k_softc
*sc
)
1192 struct ath5k_hw
*ah
= sc
->ah
;
1194 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1195 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1196 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1198 ath5k_debug_printrxbuffs(sc
, ah
);
1202 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1203 struct ath5k_rx_status
*rs
)
1205 struct ath5k_hw
*ah
= sc
->ah
;
1206 struct ath_common
*common
= ath5k_hw_common(ah
);
1207 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1208 unsigned int keyix
, hlen
;
1210 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1211 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1212 return RX_FLAG_DECRYPTED
;
1214 /* Apparently when a default key is used to decrypt the packet
1215 the hw does not set the index used to decrypt. In such cases
1216 get the index from the packet. */
1217 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1218 if (ieee80211_has_protected(hdr
->frame_control
) &&
1219 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1220 skb
->len
>= hlen
+ 4) {
1221 keyix
= skb
->data
[hlen
+ 3] >> 6;
1223 if (test_bit(keyix
, common
->keymap
))
1224 return RX_FLAG_DECRYPTED
;
1232 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1233 struct ieee80211_rx_status
*rxs
)
1235 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1238 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1240 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1241 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1242 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1244 * Received an IBSS beacon with the same BSSID. Hardware *must*
1245 * have updated the local TSF. We have to work around various
1246 * hardware bugs, though...
1248 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1249 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1250 hw_tu
= TSF_TO_TU(tsf
);
1252 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1253 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1254 (unsigned long long)bc_tstamp
,
1255 (unsigned long long)rxs
->mactime
,
1256 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1257 (unsigned long long)tsf
);
1260 * Sometimes the HW will give us a wrong tstamp in the rx
1261 * status, causing the timestamp extension to go wrong.
1262 * (This seems to happen especially with beacon frames bigger
1263 * than 78 byte (incl. FCS))
1264 * But we know that the receive timestamp must be later than the
1265 * timestamp of the beacon since HW must have synced to that.
1267 * NOTE: here we assume mactime to be after the frame was
1268 * received, not like mac80211 which defines it at the start.
1270 if (bc_tstamp
> rxs
->mactime
) {
1271 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1272 "fixing mactime from %llx to %llx\n",
1273 (unsigned long long)rxs
->mactime
,
1274 (unsigned long long)tsf
);
1279 * Local TSF might have moved higher than our beacon timers,
1280 * in that case we have to update them to continue sending
1281 * beacons. This also takes care of synchronizing beacon sending
1282 * times with other stations.
1284 if (hw_tu
>= sc
->nexttbtt
)
1285 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1287 /* Check if the beacon timers are still correct, because a TSF
1288 * update might have created a window between them - for a
1289 * longer description see the comment of this function: */
1290 if (!ath5k_hw_check_beacon_timers(sc
->ah
, sc
->bintval
)) {
1291 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1292 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1293 "fixed beacon timers after beacon receive\n");
1299 ath5k_update_beacon_rssi(struct ath5k_softc
*sc
, struct sk_buff
*skb
, int rssi
)
1301 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1302 struct ath5k_hw
*ah
= sc
->ah
;
1303 struct ath_common
*common
= ath5k_hw_common(ah
);
1305 /* only beacons from our BSSID */
1306 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1307 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) != 0)
1310 ah
->ah_beacon_rssi_avg
= ath5k_moving_average(ah
->ah_beacon_rssi_avg
,
1313 /* in IBSS mode we should keep RSSI statistics per neighbour */
1314 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1318 * Compute padding position. skb must contain an IEEE 802.11 frame
1320 static int ath5k_common_padpos(struct sk_buff
*skb
)
1322 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1323 __le16 frame_control
= hdr
->frame_control
;
1326 if (ieee80211_has_a4(frame_control
)) {
1329 if (ieee80211_is_data_qos(frame_control
)) {
1330 padpos
+= IEEE80211_QOS_CTL_LEN
;
1337 * This function expects an 802.11 frame and returns the number of
1338 * bytes added, or -1 if we don't have enough header room.
1340 static int ath5k_add_padding(struct sk_buff
*skb
)
1342 int padpos
= ath5k_common_padpos(skb
);
1343 int padsize
= padpos
& 3;
1345 if (padsize
&& skb
->len
>padpos
) {
1347 if (skb_headroom(skb
) < padsize
)
1350 skb_push(skb
, padsize
);
1351 memmove(skb
->data
, skb
->data
+padsize
, padpos
);
1359 * The MAC header is padded to have 32-bit boundary if the
1360 * packet payload is non-zero. The general calculation for
1361 * padsize would take into account odd header lengths:
1362 * padsize = 4 - (hdrlen & 3); however, since only
1363 * even-length headers are used, padding can only be 0 or 2
1364 * bytes and we can optimize this a bit. We must not try to
1365 * remove padding from short control frames that do not have a
1368 * This function expects an 802.11 frame and returns the number of
1371 static int ath5k_remove_padding(struct sk_buff
*skb
)
1373 int padpos
= ath5k_common_padpos(skb
);
1374 int padsize
= padpos
& 3;
1376 if (padsize
&& skb
->len
>=padpos
+padsize
) {
1377 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1378 skb_pull(skb
, padsize
);
1386 ath5k_receive_frame(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1387 struct ath5k_rx_status
*rs
)
1389 struct ieee80211_rx_status
*rxs
;
1391 ath5k_remove_padding(skb
);
1393 rxs
= IEEE80211_SKB_RXCB(skb
);
1396 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1397 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1400 * always extend the mac timestamp, since this information is
1401 * also needed for proper IBSS merging.
1403 * XXX: it might be too late to do it here, since rs_tstamp is
1404 * 15bit only. that means TSF extension has to be done within
1405 * 32768usec (about 32ms). it might be necessary to move this to
1406 * the interrupt handler, like it is done in madwifi.
1408 * Unfortunately we don't know when the hardware takes the rx
1409 * timestamp (beginning of phy frame, data frame, end of rx?).
1410 * The only thing we know is that it is hardware specific...
1411 * On AR5213 it seems the rx timestamp is at the end of the
1412 * frame, but i'm not sure.
1414 * NOTE: mac80211 defines mactime at the beginning of the first
1415 * data symbol. Since we don't have any time references it's
1416 * impossible to comply to that. This affects IBSS merge only
1417 * right now, so it's not too bad...
1419 rxs
->mactime
= ath5k_extend_tsf(sc
->ah
, rs
->rs_tstamp
);
1420 rxs
->flag
|= RX_FLAG_TSFT
;
1422 rxs
->freq
= sc
->curchan
->center_freq
;
1423 rxs
->band
= sc
->curband
->band
;
1425 rxs
->signal
= sc
->ah
->ah_noise_floor
+ rs
->rs_rssi
;
1427 rxs
->antenna
= rs
->rs_antenna
;
1429 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1430 sc
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1432 sc
->stats
.antenna_rx
[0]++; /* invalid */
1434 rxs
->rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
->rs_rate
);
1435 rxs
->flag
|= ath5k_rx_decrypted(sc
, skb
, rs
);
1437 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1438 sc
->curband
->bitrates
[rxs
->rate_idx
].hw_value_short
)
1439 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1441 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1443 ath5k_update_beacon_rssi(sc
, skb
, rs
->rs_rssi
);
1445 /* check beacons in IBSS mode */
1446 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1447 ath5k_check_ibss_tsf(sc
, skb
, rxs
);
1449 ieee80211_rx(sc
->hw
, skb
);
1452 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1454 * Check if we want to further process this frame or not. Also update
1455 * statistics. Return true if we want this frame, false if not.
1458 ath5k_receive_frame_ok(struct ath5k_softc
*sc
, struct ath5k_rx_status
*rs
)
1460 sc
->stats
.rx_all_count
++;
1461 sc
->stats
.rx_bytes_count
+= rs
->rs_datalen
;
1463 if (unlikely(rs
->rs_status
)) {
1464 if (rs
->rs_status
& AR5K_RXERR_CRC
)
1465 sc
->stats
.rxerr_crc
++;
1466 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
1467 sc
->stats
.rxerr_fifo
++;
1468 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
1469 sc
->stats
.rxerr_phy
++;
1470 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
1471 sc
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
1474 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
1476 * Decrypt error. If the error occurred
1477 * because there was no hardware key, then
1478 * let the frame through so the upper layers
1479 * can process it. This is necessary for 5210
1480 * parts which have no way to setup a ``clear''
1483 * XXX do key cache faulting
1485 sc
->stats
.rxerr_decrypt
++;
1486 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1487 !(rs
->rs_status
& AR5K_RXERR_CRC
))
1490 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
1491 sc
->stats
.rxerr_mic
++;
1495 /* reject any frames with non-crypto errors */
1496 if (rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
))
1500 if (unlikely(rs
->rs_more
)) {
1501 sc
->stats
.rxerr_jumbo
++;
1508 ath5k_tasklet_rx(unsigned long data
)
1510 struct ath5k_rx_status rs
= {};
1511 struct sk_buff
*skb
, *next_skb
;
1512 dma_addr_t next_skb_addr
;
1513 struct ath5k_softc
*sc
= (void *)data
;
1514 struct ath5k_hw
*ah
= sc
->ah
;
1515 struct ath_common
*common
= ath5k_hw_common(ah
);
1516 struct ath5k_buf
*bf
;
1517 struct ath5k_desc
*ds
;
1520 spin_lock(&sc
->rxbuflock
);
1521 if (list_empty(&sc
->rxbuf
)) {
1522 ATH5K_WARN(sc
, "empty rx buf pool\n");
1526 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1527 BUG_ON(bf
->skb
== NULL
);
1531 /* bail if HW is still using self-linked descriptor */
1532 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
1535 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1536 if (unlikely(ret
== -EINPROGRESS
))
1538 else if (unlikely(ret
)) {
1539 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1540 sc
->stats
.rxerr_proc
++;
1544 if (ath5k_receive_frame_ok(sc
, &rs
)) {
1545 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
1548 * If we can't replace bf->skb with a new skb under
1549 * memory pressure, just skip this packet
1554 pci_unmap_single(sc
->pdev
, bf
->skbaddr
,
1556 PCI_DMA_FROMDEVICE
);
1558 skb_put(skb
, rs
.rs_datalen
);
1560 ath5k_receive_frame(sc
, skb
, &rs
);
1563 bf
->skbaddr
= next_skb_addr
;
1566 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1567 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1569 spin_unlock(&sc
->rxbuflock
);
1577 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1578 struct ath5k_txq
*txq
)
1580 struct ath5k_softc
*sc
= hw
->priv
;
1581 struct ath5k_buf
*bf
;
1582 unsigned long flags
;
1585 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
1588 * The hardware expects the header padded to 4 byte boundaries.
1589 * If this is not the case, we add the padding after the header.
1591 padsize
= ath5k_add_padding(skb
);
1593 ATH5K_ERR(sc
, "tx hdrlen not %%4: not enough"
1594 " headroom to pad");
1598 if (txq
->txq_len
>= ATH5K_TXQ_LEN_MAX
)
1599 ieee80211_stop_queue(hw
, txq
->qnum
);
1601 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1602 if (list_empty(&sc
->txbuf
)) {
1603 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
1604 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1605 ieee80211_stop_queues(hw
);
1608 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
1609 list_del(&bf
->list
);
1611 if (list_empty(&sc
->txbuf
))
1612 ieee80211_stop_queues(hw
);
1613 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1617 if (ath5k_txbuf_setup(sc
, bf
, txq
, padsize
)) {
1619 spin_lock_irqsave(&sc
->txbuflock
, flags
);
1620 list_add_tail(&bf
->list
, &sc
->txbuf
);
1622 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
1625 return NETDEV_TX_OK
;
1628 dev_kfree_skb_any(skb
);
1629 return NETDEV_TX_OK
;
1633 ath5k_tx_frame_completed(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1634 struct ath5k_tx_status
*ts
)
1636 struct ieee80211_tx_info
*info
;
1639 sc
->stats
.tx_all_count
++;
1640 sc
->stats
.tx_bytes_count
+= skb
->len
;
1641 info
= IEEE80211_SKB_CB(skb
);
1643 ieee80211_tx_info_clear_status(info
);
1644 for (i
= 0; i
< 4; i
++) {
1645 struct ieee80211_tx_rate
*r
=
1646 &info
->status
.rates
[i
];
1648 if (ts
->ts_rate
[i
]) {
1649 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
->ts_rate
[i
]);
1650 r
->count
= ts
->ts_retry
[i
];
1657 /* count the successful attempt as well */
1658 info
->status
.rates
[ts
->ts_final_idx
].count
++;
1660 if (unlikely(ts
->ts_status
)) {
1661 sc
->stats
.ack_fail
++;
1662 if (ts
->ts_status
& AR5K_TXERR_FILT
) {
1663 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1664 sc
->stats
.txerr_filt
++;
1666 if (ts
->ts_status
& AR5K_TXERR_XRETRY
)
1667 sc
->stats
.txerr_retry
++;
1668 if (ts
->ts_status
& AR5K_TXERR_FIFO
)
1669 sc
->stats
.txerr_fifo
++;
1671 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1672 info
->status
.ack_signal
= ts
->ts_rssi
;
1676 * Remove MAC header padding before giving the frame
1679 ath5k_remove_padding(skb
);
1681 if (ts
->ts_antenna
> 0 && ts
->ts_antenna
< 5)
1682 sc
->stats
.antenna_tx
[ts
->ts_antenna
]++;
1684 sc
->stats
.antenna_tx
[0]++; /* invalid */
1686 ieee80211_tx_status(sc
->hw
, skb
);
1690 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1692 struct ath5k_tx_status ts
= {};
1693 struct ath5k_buf
*bf
, *bf0
;
1694 struct ath5k_desc
*ds
;
1695 struct sk_buff
*skb
;
1698 spin_lock(&txq
->lock
);
1699 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1701 txq
->txq_poll_mark
= false;
1703 /* skb might already have been processed last time. */
1704 if (bf
->skb
!= NULL
) {
1707 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1708 if (unlikely(ret
== -EINPROGRESS
))
1710 else if (unlikely(ret
)) {
1712 "error %d while processing "
1713 "queue %u\n", ret
, txq
->qnum
);
1719 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1721 ath5k_tx_frame_completed(sc
, skb
, &ts
);
1725 * It's possible that the hardware can say the buffer is
1726 * completed when it hasn't yet loaded the ds_link from
1727 * host memory and moved on.
1728 * Always keep the last descriptor to avoid HW races...
1730 if (ath5k_hw_get_txdp(sc
->ah
, txq
->qnum
) != bf
->daddr
) {
1731 spin_lock(&sc
->txbuflock
);
1732 list_move_tail(&bf
->list
, &sc
->txbuf
);
1735 spin_unlock(&sc
->txbuflock
);
1738 spin_unlock(&txq
->lock
);
1739 if (txq
->txq_len
< ATH5K_TXQ_LEN_LOW
&& txq
->qnum
< 4)
1740 ieee80211_wake_queue(sc
->hw
, txq
->qnum
);
1744 ath5k_tasklet_tx(unsigned long data
)
1747 struct ath5k_softc
*sc
= (void *)data
;
1749 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
1750 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
1751 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
1760 * Setup the beacon frame for transmit.
1763 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1765 struct sk_buff
*skb
= bf
->skb
;
1766 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1767 struct ath5k_hw
*ah
= sc
->ah
;
1768 struct ath5k_desc
*ds
;
1772 const int padsize
= 0;
1774 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1776 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1777 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1778 (unsigned long long)bf
->skbaddr
);
1779 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1780 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1785 antenna
= ah
->ah_tx_ant
;
1787 flags
= AR5K_TXDESC_NOACK
;
1788 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1789 ds
->ds_link
= bf
->daddr
; /* self-linked */
1790 flags
|= AR5K_TXDESC_VEOL
;
1795 * If we use multiple antennas on AP and use
1796 * the Sectored AP scenario, switch antenna every
1797 * 4 beacons to make sure everybody hears our AP.
1798 * When a client tries to associate, hw will keep
1799 * track of the tx antenna to be used for this client
1800 * automaticaly, based on ACKed packets.
1802 * Note: AP still listens and transmits RTS on the
1803 * default antenna which is supposed to be an omni.
1805 * Note2: On sectored scenarios it's possible to have
1806 * multiple antennas (1 omni -- the default -- and 14
1807 * sectors), so if we choose to actually support this
1808 * mode, we need to allow the user to set how many antennas
1809 * we have and tweak the code below to send beacons
1812 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
1813 antenna
= sc
->bsent
& 4 ? 2 : 1;
1816 /* FIXME: If we are in g mode and rate is a CCK rate
1817 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1818 * from tx power (value is in dB units already) */
1819 ds
->ds_data
= bf
->skbaddr
;
1820 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1821 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1822 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1823 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1824 1, AR5K_TXKEYIX_INVALID
,
1825 antenna
, flags
, 0, 0);
1831 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1836 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1837 * this is called only once at config_bss time, for AP we do it every
1838 * SWBA interrupt so that the TIM will reflect buffered frames.
1840 * Called with the beacon lock.
1843 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
1846 struct ath5k_softc
*sc
= hw
->priv
;
1847 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
1848 struct sk_buff
*skb
;
1850 if (WARN_ON(!vif
)) {
1855 skb
= ieee80211_beacon_get(hw
, vif
);
1862 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
1864 ath5k_txbuf_free_skb(sc
, avf
->bbuf
);
1865 avf
->bbuf
->skb
= skb
;
1866 ret
= ath5k_beacon_setup(sc
, avf
->bbuf
);
1868 avf
->bbuf
->skb
= NULL
;
1874 * Transmit a beacon frame at SWBA. Dynamic updates to the
1875 * frame contents are done as needed and the slot time is
1876 * also adjusted based on current state.
1878 * This is called from software irq context (beacontq tasklets)
1879 * or user context from ath5k_beacon_config.
1882 ath5k_beacon_send(struct ath5k_softc
*sc
)
1884 struct ath5k_hw
*ah
= sc
->ah
;
1885 struct ieee80211_vif
*vif
;
1886 struct ath5k_vif
*avf
;
1887 struct ath5k_buf
*bf
;
1888 struct sk_buff
*skb
;
1890 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1893 * Check if the previous beacon has gone out. If
1894 * not, don't don't try to post another: skip this
1895 * period and wait for the next. Missed beacons
1896 * indicate a problem and should not occur. If we
1897 * miss too many consecutive beacons reset the device.
1899 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1901 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1902 "missed %u consecutive beacons\n", sc
->bmisscount
);
1903 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
1904 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1905 "stuck beacon time (%u missed)\n",
1907 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
1908 "stuck beacon, resetting\n");
1909 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
1913 if (unlikely(sc
->bmisscount
!= 0)) {
1914 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1915 "resume beacon xmit after %u misses\n",
1920 if (sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) {
1921 u64 tsf
= ath5k_hw_get_tsf64(ah
);
1922 u32 tsftu
= TSF_TO_TU(tsf
);
1923 int slot
= ((tsftu
% sc
->bintval
) * ATH_BCBUF
) / sc
->bintval
;
1924 vif
= sc
->bslot
[(slot
+ 1) % ATH_BCBUF
];
1925 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1926 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1927 (unsigned long long)tsf
, tsftu
, sc
->bintval
, slot
, vif
);
1928 } else /* only one interface */
1934 avf
= (void *)vif
->drv_priv
;
1936 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1937 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1938 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1943 * Stop any current dma and put the new frame on the queue.
1944 * This should never fail since we check above that no frames
1945 * are still pending on the queue.
1947 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
1948 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
1949 /* NB: hw still stops DMA, so proceed */
1952 /* refresh the beacon for AP mode */
1953 if (sc
->opmode
== NL80211_IFTYPE_AP
)
1954 ath5k_beacon_update(sc
->hw
, vif
);
1956 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
1957 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
1958 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
1959 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
1961 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1963 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
1964 skb
= ieee80211_get_buffered_bc(sc
->hw
, vif
);
1971 * ath5k_beacon_update_timers - update beacon timers
1973 * @sc: struct ath5k_softc pointer we are operating on
1974 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1975 * beacon timer update based on the current HW TSF.
1977 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1978 * of a received beacon or the current local hardware TSF and write it to the
1979 * beacon timer registers.
1981 * This is called in a variety of situations, e.g. when a beacon is received,
1982 * when a TSF update has been detected, but also when an new IBSS is created or
1983 * when we otherwise know we have to update the timers, but we keep it in this
1984 * function to have it all together in one place.
1987 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
1989 struct ath5k_hw
*ah
= sc
->ah
;
1990 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
1993 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
1994 if (sc
->opmode
== NL80211_IFTYPE_AP
&& sc
->num_ap_vifs
> 1) {
1995 intval
/= ATH_BCBUF
; /* staggered multi-bss beacons */
1997 ATH5K_WARN(sc
, "intval %u is too low, min 15\n",
2000 if (WARN_ON(!intval
))
2003 /* beacon TSF converted to TU */
2004 bc_tu
= TSF_TO_TU(bc_tsf
);
2006 /* current TSF converted to TU */
2007 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2008 hw_tu
= TSF_TO_TU(hw_tsf
);
2010 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
2011 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
2012 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
2013 * configuration we need to make sure it is bigger than that. */
2017 * no beacons received, called internally.
2018 * just need to refresh timers based on HW TSF.
2020 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2021 } else if (bc_tsf
== 0) {
2023 * no beacon received, probably called by ath5k_reset_tsf().
2024 * reset TSF to start with 0.
2027 intval
|= AR5K_BEACON_RESET_TSF
;
2028 } else if (bc_tsf
> hw_tsf
) {
2030 * beacon received, SW merge happend but HW TSF not yet updated.
2031 * not possible to reconfigure timers yet, but next time we
2032 * receive a beacon with the same BSSID, the hardware will
2033 * automatically update the TSF and then we need to reconfigure
2036 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2037 "need to wait for HW TSF sync\n");
2041 * most important case for beacon synchronization between STA.
2043 * beacon received and HW TSF has been already updated by HW.
2044 * update next TBTT based on the TSF of the beacon, but make
2045 * sure it is ahead of our local TSF timer.
2047 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2051 sc
->nexttbtt
= nexttbtt
;
2053 intval
|= AR5K_BEACON_ENA
;
2054 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2057 * debugging output last in order to preserve the time critical aspect
2061 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2062 "reconfigured timers based on HW TSF\n");
2063 else if (bc_tsf
== 0)
2064 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2065 "reset HW TSF and timers\n");
2067 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2068 "updated timers based on beacon TSF\n");
2070 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2071 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2072 (unsigned long long) bc_tsf
,
2073 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2074 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2075 intval
& AR5K_BEACON_PERIOD
,
2076 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2077 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2081 * ath5k_beacon_config - Configure the beacon queues and interrupts
2083 * @sc: struct ath5k_softc pointer we are operating on
2085 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2086 * interrupts to detect TSF updates only.
2089 ath5k_beacon_config(struct ath5k_softc
*sc
)
2091 struct ath5k_hw
*ah
= sc
->ah
;
2092 unsigned long flags
;
2094 spin_lock_irqsave(&sc
->block
, flags
);
2096 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2098 if (sc
->enable_beacon
) {
2100 * In IBSS mode we use a self-linked tx descriptor and let the
2101 * hardware send the beacons automatically. We have to load it
2103 * We use the SWBA interrupt only to keep track of the beacon
2104 * timers in order to detect automatic TSF updates.
2106 ath5k_beaconq_config(sc
);
2108 sc
->imask
|= AR5K_INT_SWBA
;
2110 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2111 if (ath5k_hw_hasveol(ah
))
2112 ath5k_beacon_send(sc
);
2114 ath5k_beacon_update_timers(sc
, -1);
2116 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2119 ath5k_hw_set_imr(ah
, sc
->imask
);
2121 spin_unlock_irqrestore(&sc
->block
, flags
);
2124 static void ath5k_tasklet_beacon(unsigned long data
)
2126 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2129 * Software beacon alert--time to send a beacon.
2131 * In IBSS mode we use this interrupt just to
2132 * keep track of the next TBTT (target beacon
2133 * transmission time) in order to detect wether
2134 * automatic TSF updates happened.
2136 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2137 /* XXX: only if VEOL suppported */
2138 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2139 sc
->nexttbtt
+= sc
->bintval
;
2140 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2141 "SWBA nexttbtt: %x hw_tu: %x "
2145 (unsigned long long) tsf
);
2147 spin_lock(&sc
->block
);
2148 ath5k_beacon_send(sc
);
2149 spin_unlock(&sc
->block
);
2154 /********************\
2155 * Interrupt handling *
2156 \********************/
2159 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2161 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2162 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)) {
2163 /* run ANI only when full calibration is not active */
2164 ah
->ah_cal_next_ani
= jiffies
+
2165 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2166 tasklet_schedule(&ah
->ah_sc
->ani_tasklet
);
2168 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2169 ah
->ah_cal_next_full
= jiffies
+
2170 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2171 tasklet_schedule(&ah
->ah_sc
->calib
);
2173 /* we could use SWI to generate enough interrupts to meet our
2174 * calibration interval requirements, if necessary:
2175 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2179 ath5k_intr(int irq
, void *dev_id
)
2181 struct ath5k_softc
*sc
= dev_id
;
2182 struct ath5k_hw
*ah
= sc
->ah
;
2183 enum ath5k_int status
;
2184 unsigned int counter
= 1000;
2186 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2187 !ath5k_hw_is_intr_pending(ah
)))
2191 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2192 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2194 if (unlikely(status
& AR5K_INT_FATAL
)) {
2196 * Fatal errors are unrecoverable.
2197 * Typically these are caused by DMA errors.
2199 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2200 "fatal int, resetting\n");
2201 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2202 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2204 * Receive buffers are full. Either the bus is busy or
2205 * the CPU is not fast enough to process all received
2207 * Older chipsets need a reset to come out of this
2208 * condition, but we treat it as RX for newer chips.
2209 * We don't know exactly which versions need a reset -
2210 * this guess is copied from the HAL.
2212 sc
->stats
.rxorn_intr
++;
2213 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2214 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2215 "rx overrun, resetting\n");
2216 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2219 tasklet_schedule(&sc
->rxtq
);
2221 if (status
& AR5K_INT_SWBA
) {
2222 tasklet_hi_schedule(&sc
->beacontq
);
2224 if (status
& AR5K_INT_RXEOL
) {
2226 * NB: the hardware should re-read the link when
2227 * RXE bit is written, but it doesn't work at
2228 * least on older hardware revs.
2230 sc
->stats
.rxeol_intr
++;
2232 if (status
& AR5K_INT_TXURN
) {
2233 /* bump tx trigger level */
2234 ath5k_hw_update_tx_triglevel(ah
, true);
2236 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2237 tasklet_schedule(&sc
->rxtq
);
2238 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2239 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2240 tasklet_schedule(&sc
->txtq
);
2241 if (status
& AR5K_INT_BMISS
) {
2244 if (status
& AR5K_INT_MIB
) {
2245 sc
->stats
.mib_intr
++;
2246 ath5k_hw_update_mib_counters(ah
);
2247 ath5k_ani_mib_intr(ah
);
2249 if (status
& AR5K_INT_GPIO
)
2250 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2253 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2255 if (unlikely(!counter
))
2256 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2258 ath5k_intr_calibration_poll(ah
);
2264 * Periodically recalibrate the PHY to account
2265 * for temperature/environment changes.
2268 ath5k_tasklet_calibrate(unsigned long data
)
2270 struct ath5k_softc
*sc
= (void *)data
;
2271 struct ath5k_hw
*ah
= sc
->ah
;
2273 /* Only full calibration for now */
2274 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2276 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2277 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2278 sc
->curchan
->hw_value
);
2280 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2282 * Rfgain is out of bounds, reset the chip
2283 * to load new gain values.
2285 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2286 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2288 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2289 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2290 ieee80211_frequency_to_channel(
2291 sc
->curchan
->center_freq
));
2293 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2295 * TODO: We should stop TX here, so that it doesn't interfere.
2296 * Note that stopping the queues is not enough to stop TX! */
2297 if (time_is_before_eq_jiffies(ah
->ah_cal_next_nf
)) {
2298 ah
->ah_cal_next_nf
= jiffies
+
2299 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF
);
2300 ath5k_hw_update_noise_floor(ah
);
2303 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2308 ath5k_tasklet_ani(unsigned long data
)
2310 struct ath5k_softc
*sc
= (void *)data
;
2311 struct ath5k_hw
*ah
= sc
->ah
;
2313 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2314 ath5k_ani_calibration(ah
);
2315 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2320 ath5k_tx_complete_poll_work(struct work_struct
*work
)
2322 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2323 tx_complete_work
.work
);
2324 struct ath5k_txq
*txq
;
2326 bool needreset
= false;
2328 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++) {
2329 if (sc
->txqs
[i
].setup
) {
2331 spin_lock_bh(&txq
->lock
);
2332 if (txq
->txq_len
> 1) {
2333 if (txq
->txq_poll_mark
) {
2334 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
,
2335 "TX queue stuck %d\n",
2339 spin_unlock_bh(&txq
->lock
);
2342 txq
->txq_poll_mark
= true;
2345 spin_unlock_bh(&txq
->lock
);
2350 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2351 "TX queues stuck, resetting\n");
2352 ath5k_reset(sc
, sc
->curchan
);
2355 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2356 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2360 /*************************\
2361 * Initialization routines *
2362 \*************************/
2365 ath5k_stop_locked(struct ath5k_softc
*sc
)
2367 struct ath5k_hw
*ah
= sc
->ah
;
2369 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2370 test_bit(ATH_STAT_INVALID
, sc
->status
));
2373 * Shutdown the hardware and driver:
2374 * stop output from above
2375 * disable interrupts
2377 * turn off the radio
2378 * clear transmit machinery
2379 * clear receive machinery
2380 * drain and release tx queues
2381 * reclaim beacon resources
2382 * power down hardware
2384 * Note that some of this work is not possible if the
2385 * hardware is gone (invalid).
2387 ieee80211_stop_queues(sc
->hw
);
2389 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2391 ath5k_hw_set_imr(ah
, 0);
2392 synchronize_irq(sc
->pdev
->irq
);
2394 ath5k_txq_cleanup(sc
);
2395 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2397 ath5k_hw_phy_disable(ah
);
2404 ath5k_init(struct ath5k_softc
*sc
)
2406 struct ath5k_hw
*ah
= sc
->ah
;
2407 struct ath_common
*common
= ath5k_hw_common(ah
);
2410 mutex_lock(&sc
->lock
);
2412 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2415 * Stop anything previously setup. This is safe
2416 * no matter this is the first time through or not.
2418 ath5k_stop_locked(sc
);
2421 * The basic interface to setting the hardware in a good
2422 * state is ``reset''. On return the hardware is known to
2423 * be powered up and with interrupts disabled. This must
2424 * be followed by initialization of the appropriate bits
2425 * and then setup of the interrupt mask.
2427 sc
->curchan
= sc
->hw
->conf
.channel
;
2428 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2429 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2430 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2431 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2433 ret
= ath5k_reset(sc
, NULL
);
2437 ath5k_rfkill_hw_start(ah
);
2440 * Reset the key cache since some parts do not reset the
2441 * contents on initial power up or resume from suspend.
2443 for (i
= 0; i
< common
->keymax
; i
++)
2444 ath_hw_keyreset(common
, (u16
) i
);
2446 ath5k_hw_set_ack_bitrate_high(ah
, true);
2448 for (i
= 0; i
< ARRAY_SIZE(sc
->bslot
); i
++)
2449 sc
->bslot
[i
] = NULL
;
2454 mutex_unlock(&sc
->lock
);
2456 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2457 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT
));
2462 static void stop_tasklets(struct ath5k_softc
*sc
)
2464 tasklet_kill(&sc
->rxtq
);
2465 tasklet_kill(&sc
->txtq
);
2466 tasklet_kill(&sc
->calib
);
2467 tasklet_kill(&sc
->beacontq
);
2468 tasklet_kill(&sc
->ani_tasklet
);
2472 * Stop the device, grabbing the top-level lock to protect
2473 * against concurrent entry through ath5k_init (which can happen
2474 * if another thread does a system call and the thread doing the
2475 * stop is preempted).
2478 ath5k_stop_hw(struct ath5k_softc
*sc
)
2482 mutex_lock(&sc
->lock
);
2483 ret
= ath5k_stop_locked(sc
);
2484 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2486 * Don't set the card in full sleep mode!
2488 * a) When the device is in this state it must be carefully
2489 * woken up or references to registers in the PCI clock
2490 * domain may freeze the bus (and system). This varies
2491 * by chip and is mostly an issue with newer parts
2492 * (madwifi sources mentioned srev >= 0x78) that go to
2493 * sleep more quickly.
2495 * b) On older chips full sleep results a weird behaviour
2496 * during wakeup. I tested various cards with srev < 0x78
2497 * and they don't wake up after module reload, a second
2498 * module reload is needed to bring the card up again.
2500 * Until we figure out what's going on don't enable
2501 * full chip reset on any chip (this is what Legacy HAL
2502 * and Sam's HAL do anyway). Instead Perform a full reset
2503 * on the device (same as initial state after attach) and
2504 * leave it idle (keep MAC/BB on warm reset) */
2505 ret
= ath5k_hw_on_hold(sc
->ah
);
2507 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2508 "putting device to sleep\n");
2512 mutex_unlock(&sc
->lock
);
2516 cancel_delayed_work_sync(&sc
->tx_complete_work
);
2518 ath5k_rfkill_hw_stop(sc
->ah
);
2524 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2525 * and change to the given channel.
2527 * This should be called with sc->lock.
2530 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2532 struct ath5k_hw
*ah
= sc
->ah
;
2535 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2537 ath5k_hw_set_imr(ah
, 0);
2538 synchronize_irq(sc
->pdev
->irq
);
2542 ath5k_txq_cleanup(sc
);
2546 sc
->curband
= &sc
->sbands
[chan
->band
];
2548 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
);
2550 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2554 ret
= ath5k_rx_start(sc
);
2556 ATH5K_ERR(sc
, "can't start recv logic\n");
2560 ath5k_ani_init(ah
, ah
->ah_sc
->ani_state
.ani_mode
);
2562 ah
->ah_cal_next_full
= jiffies
;
2563 ah
->ah_cal_next_ani
= jiffies
;
2564 ah
->ah_cal_next_nf
= jiffies
;
2567 * Change channels and update the h/w rate map if we're switching;
2568 * e.g. 11a to 11b/g.
2570 * We may be doing a reset in response to an ioctl that changes the
2571 * channel so update any state that might change as a result.
2575 /* ath5k_chan_change(sc, c); */
2577 ath5k_beacon_config(sc
);
2578 /* intrs are enabled by ath5k_beacon_config */
2580 ieee80211_wake_queues(sc
->hw
);
2587 static void ath5k_reset_work(struct work_struct
*work
)
2589 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
2592 mutex_lock(&sc
->lock
);
2593 ath5k_reset(sc
, sc
->curchan
);
2594 mutex_unlock(&sc
->lock
);
2598 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
2600 struct ath5k_softc
*sc
= hw
->priv
;
2601 struct ath5k_hw
*ah
= sc
->ah
;
2602 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
2603 struct ath5k_txq
*txq
;
2604 u8 mac
[ETH_ALEN
] = {};
2607 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
2610 * Check if the MAC has multi-rate retry support.
2611 * We do this by trying to setup a fake extended
2612 * descriptor. MACs that don't have support will
2613 * return false w/o doing anything. MACs that do
2614 * support it will return true w/o doing anything.
2616 ret
= ath5k_hw_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
2621 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
2624 * Collect the channel list. The 802.11 layer
2625 * is resposible for filtering this list based
2626 * on settings like the phy mode and regulatory
2627 * domain restrictions.
2629 ret
= ath5k_setup_bands(hw
);
2631 ATH5K_ERR(sc
, "can't get channels\n");
2635 /* NB: setup here so ath5k_rate_update is happy */
2636 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
2637 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
2639 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
2642 * Allocate tx+rx descriptors and populate the lists.
2644 ret
= ath5k_desc_alloc(sc
, pdev
);
2646 ATH5K_ERR(sc
, "can't allocate descriptors\n");
2651 * Allocate hardware transmit queues: one queue for
2652 * beacon frames and one data queue for each QoS
2653 * priority. Note that hw functions handle resetting
2654 * these queues at the needed time.
2656 ret
= ath5k_beaconq_setup(ah
);
2658 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
2662 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
2663 if (IS_ERR(sc
->cabq
)) {
2664 ATH5K_ERR(sc
, "can't setup cab queue\n");
2665 ret
= PTR_ERR(sc
->cabq
);
2669 /* This order matches mac80211's queue priority, so we can
2670 * directly use the mac80211 queue number without any mapping */
2671 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VO
);
2673 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2677 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_VI
);
2679 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2683 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BE
);
2685 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2689 txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
2691 ATH5K_ERR(sc
, "can't setup xmit queue\n");
2697 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
2698 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
2699 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
2700 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
2701 tasklet_init(&sc
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)sc
);
2703 INIT_WORK(&sc
->reset_work
, ath5k_reset_work
);
2704 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath5k_tx_complete_poll_work
);
2706 ret
= ath5k_eeprom_read_mac(ah
, mac
);
2708 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
2713 SET_IEEE80211_PERM_ADDR(hw
, mac
);
2714 memcpy(&sc
->lladdr
, mac
, ETH_ALEN
);
2715 /* All MAC address bits matter for ACKs */
2716 ath5k_update_bssid_mask_and_opmode(sc
, NULL
);
2718 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
2719 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
2721 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
2725 ret
= ieee80211_register_hw(hw
);
2727 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
2731 if (!ath_is_world_regd(regulatory
))
2732 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
2734 ath5k_init_leds(sc
);
2736 ath5k_sysfs_register(sc
);
2740 ath5k_txq_release(sc
);
2742 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
2744 ath5k_desc_free(sc
, pdev
);
2750 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
2752 struct ath5k_softc
*sc
= hw
->priv
;
2755 * NB: the order of these is important:
2756 * o call the 802.11 layer before detaching ath5k_hw to
2757 * ensure callbacks into the driver to delete global
2758 * key cache entries can be handled
2759 * o reclaim the tx queue data structures after calling
2760 * the 802.11 layer as we'll get called back to reclaim
2761 * node state and potentially want to use them
2762 * o to cleanup the tx queues the hal is called, so detach
2764 * XXX: ??? detach ath5k_hw ???
2765 * Other than that, it's straightforward...
2767 ieee80211_unregister_hw(hw
);
2768 ath5k_desc_free(sc
, pdev
);
2769 ath5k_txq_release(sc
);
2770 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
2771 ath5k_unregister_leds(sc
);
2773 ath5k_sysfs_unregister(sc
);
2775 * NB: can't reclaim these until after ieee80211_ifdetach
2776 * returns because we'll get called back to reclaim node
2777 * state and potentially want to use them.
2781 /********************\
2782 * Mac80211 functions *
2783 \********************/
2786 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2788 struct ath5k_softc
*sc
= hw
->priv
;
2789 u16 qnum
= skb_get_queue_mapping(skb
);
2791 if (WARN_ON(qnum
>= sc
->ah
->ah_capabilities
.cap_queues
.q_tx_num
)) {
2792 dev_kfree_skb_any(skb
);
2796 return ath5k_tx_queue(hw
, skb
, &sc
->txqs
[qnum
]);
2799 static int ath5k_start(struct ieee80211_hw
*hw
)
2801 return ath5k_init(hw
->priv
);
2804 static void ath5k_stop(struct ieee80211_hw
*hw
)
2806 ath5k_stop_hw(hw
->priv
);
2809 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2810 struct ieee80211_vif
*vif
)
2812 struct ath5k_softc
*sc
= hw
->priv
;
2814 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
2816 mutex_lock(&sc
->lock
);
2818 if ((vif
->type
== NL80211_IFTYPE_AP
||
2819 vif
->type
== NL80211_IFTYPE_ADHOC
)
2820 && (sc
->num_ap_vifs
+ sc
->num_adhoc_vifs
) >= ATH_BCBUF
) {
2825 /* Don't allow other interfaces if one ad-hoc is configured.
2826 * TODO: Fix the problems with ad-hoc and multiple other interfaces.
2827 * We would need to operate the HW in ad-hoc mode to allow TSF updates
2828 * for the IBSS, but this breaks with additional AP or STA interfaces
2830 if (sc
->num_adhoc_vifs
||
2831 (sc
->nvifs
&& vif
->type
== NL80211_IFTYPE_ADHOC
)) {
2832 ATH5K_ERR(sc
, "Only one single ad-hoc interface is allowed.\n");
2837 switch (vif
->type
) {
2838 case NL80211_IFTYPE_AP
:
2839 case NL80211_IFTYPE_STATION
:
2840 case NL80211_IFTYPE_ADHOC
:
2841 case NL80211_IFTYPE_MESH_POINT
:
2842 avf
->opmode
= vif
->type
;
2850 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "add interface mode %d\n", avf
->opmode
);
2852 /* Assign the vap/adhoc to a beacon xmit slot. */
2853 if ((avf
->opmode
== NL80211_IFTYPE_AP
) ||
2854 (avf
->opmode
== NL80211_IFTYPE_ADHOC
)) {
2857 WARN_ON(list_empty(&sc
->bcbuf
));
2858 avf
->bbuf
= list_first_entry(&sc
->bcbuf
, struct ath5k_buf
,
2860 list_del(&avf
->bbuf
->list
);
2863 for (slot
= 0; slot
< ATH_BCBUF
; slot
++) {
2864 if (!sc
->bslot
[slot
]) {
2869 BUG_ON(sc
->bslot
[avf
->bslot
] != NULL
);
2870 sc
->bslot
[avf
->bslot
] = vif
;
2871 if (avf
->opmode
== NL80211_IFTYPE_AP
)
2874 sc
->num_adhoc_vifs
++;
2877 /* Any MAC address is fine, all others are included through the
2880 memcpy(&sc
->lladdr
, vif
->addr
, ETH_ALEN
);
2881 ath5k_hw_set_lladdr(sc
->ah
, vif
->addr
);
2883 memcpy(&avf
->lladdr
, vif
->addr
, ETH_ALEN
);
2885 ath5k_mode_setup(sc
, vif
);
2889 mutex_unlock(&sc
->lock
);
2894 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2895 struct ieee80211_vif
*vif
)
2897 struct ath5k_softc
*sc
= hw
->priv
;
2898 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
2901 mutex_lock(&sc
->lock
);
2905 ath5k_txbuf_free_skb(sc
, avf
->bbuf
);
2906 list_add_tail(&avf
->bbuf
->list
, &sc
->bcbuf
);
2907 for (i
= 0; i
< ATH_BCBUF
; i
++) {
2908 if (sc
->bslot
[i
] == vif
) {
2909 sc
->bslot
[i
] = NULL
;
2915 if (avf
->opmode
== NL80211_IFTYPE_AP
)
2917 else if (avf
->opmode
== NL80211_IFTYPE_ADHOC
)
2918 sc
->num_adhoc_vifs
--;
2920 ath5k_update_bssid_mask_and_opmode(sc
, NULL
);
2921 mutex_unlock(&sc
->lock
);
2925 * TODO: Phy disable/diversity etc
2928 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2930 struct ath5k_softc
*sc
= hw
->priv
;
2931 struct ath5k_hw
*ah
= sc
->ah
;
2932 struct ieee80211_conf
*conf
= &hw
->conf
;
2935 mutex_lock(&sc
->lock
);
2937 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
2938 ret
= ath5k_chan_set(sc
, conf
->channel
);
2943 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
2944 (sc
->power_level
!= conf
->power_level
)) {
2945 sc
->power_level
= conf
->power_level
;
2948 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
2952 * 1) Move this on config_interface and handle each case
2953 * separately eg. when we have only one STA vif, use
2954 * AR5K_ANTMODE_SINGLE_AP
2956 * 2) Allow the user to change antenna mode eg. when only
2957 * one antenna is present
2959 * 3) Allow the user to set default/tx antenna when possible
2961 * 4) Default mode should handle 90% of the cases, together
2962 * with fixed a/b and single AP modes we should be able to
2963 * handle 99%. Sectored modes are extreme cases and i still
2964 * haven't found a usage for them. If we decide to support them,
2965 * then we must allow the user to set how many tx antennas we
2968 ath5k_hw_set_antenna_mode(ah
, ah
->ah_ant_mode
);
2971 mutex_unlock(&sc
->lock
);
2975 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
2976 struct netdev_hw_addr_list
*mc_list
)
2980 struct netdev_hw_addr
*ha
;
2985 netdev_hw_addr_list_for_each(ha
, mc_list
) {
2986 /* calculate XOR of eight 6-bit values */
2987 val
= get_unaligned_le32(ha
->addr
+ 0);
2988 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2989 val
= get_unaligned_le32(ha
->addr
+ 3);
2990 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2992 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2993 /* XXX: we might be able to just do this instead,
2994 * but not sure, needs testing, if we do use this we'd
2995 * neet to inform below to not reset the mcast */
2996 /* ath5k_hw_set_mcast_filterindex(ah,
3000 return ((u64
)(mfilt
[1]) << 32) | mfilt
[0];
3003 static bool ath_any_vif_assoc(struct ath5k_softc
*sc
)
3005 struct ath_vif_iter_data iter_data
;
3006 iter_data
.hw_macaddr
= NULL
;
3007 iter_data
.any_assoc
= false;
3008 iter_data
.need_set_hw_addr
= false;
3009 iter_data
.found_active
= true;
3011 ieee80211_iterate_active_interfaces_atomic(sc
->hw
, ath_vif_iter
,
3013 return iter_data
.any_assoc
;
3016 #define SUPPORTED_FIF_FLAGS \
3017 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3018 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3019 FIF_BCN_PRBRESP_PROMISC
3021 * o always accept unicast, broadcast, and multicast traffic
3022 * o multicast traffic for all BSSIDs will be enabled if mac80211
3024 * o maintain current state of phy ofdm or phy cck error reception.
3025 * If the hardware detects any of these type of errors then
3026 * ath5k_hw_get_rx_filter() will pass to us the respective
3027 * hardware filters to be able to receive these type of frames.
3028 * o probe request frames are accepted only when operating in
3029 * hostap, adhoc, or monitor modes
3030 * o enable promiscuous mode according to the interface state
3032 * - when operating in adhoc mode so the 802.11 layer creates
3033 * node table entries for peers,
3034 * - when operating in station mode for collecting rssi data when
3035 * the station is otherwise quiet, or
3038 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
3039 unsigned int changed_flags
,
3040 unsigned int *new_flags
,
3043 struct ath5k_softc
*sc
= hw
->priv
;
3044 struct ath5k_hw
*ah
= sc
->ah
;
3045 u32 mfilt
[2], rfilt
;
3047 mutex_lock(&sc
->lock
);
3049 mfilt
[0] = multicast
;
3050 mfilt
[1] = multicast
>> 32;
3052 /* Only deal with supported flags */
3053 changed_flags
&= SUPPORTED_FIF_FLAGS
;
3054 *new_flags
&= SUPPORTED_FIF_FLAGS
;
3056 /* If HW detects any phy or radar errors, leave those filters on.
3057 * Also, always enable Unicast, Broadcasts and Multicast
3058 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3059 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
3060 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
3061 AR5K_RX_FILTER_MCAST
);
3063 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
3064 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
3065 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
3067 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
3071 if (test_bit(ATH_STAT_PROMISC
, sc
->status
))
3072 rfilt
|= AR5K_RX_FILTER_PROM
;
3074 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3075 if (*new_flags
& FIF_ALLMULTI
) {
3080 /* This is the best we can do */
3081 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
3082 rfilt
|= AR5K_RX_FILTER_PHYERR
;
3084 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3085 * and probes for any BSSID */
3086 if ((*new_flags
& FIF_BCN_PRBRESP_PROMISC
) || (sc
->nvifs
> 1))
3087 rfilt
|= AR5K_RX_FILTER_BEACON
;
3089 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3090 * set we should only pass on control frames for this
3091 * station. This needs testing. I believe right now this
3092 * enables *all* control frames, which is OK.. but
3093 * but we should see if we can improve on granularity */
3094 if (*new_flags
& FIF_CONTROL
)
3095 rfilt
|= AR5K_RX_FILTER_CONTROL
;
3097 /* Additional settings per mode -- this is per ath5k */
3099 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3101 switch (sc
->opmode
) {
3102 case NL80211_IFTYPE_MESH_POINT
:
3103 rfilt
|= AR5K_RX_FILTER_CONTROL
|
3104 AR5K_RX_FILTER_BEACON
|
3105 AR5K_RX_FILTER_PROBEREQ
|
3106 AR5K_RX_FILTER_PROM
;
3108 case NL80211_IFTYPE_AP
:
3109 case NL80211_IFTYPE_ADHOC
:
3110 rfilt
|= AR5K_RX_FILTER_PROBEREQ
|
3111 AR5K_RX_FILTER_BEACON
;
3113 case NL80211_IFTYPE_STATION
:
3115 rfilt
|= AR5K_RX_FILTER_BEACON
;
3121 ath5k_hw_set_rx_filter(ah
, rfilt
);
3123 /* Set multicast bits */
3124 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
3125 /* Set the cached hw filter flags, this will later actually
3127 sc
->filter_flags
= rfilt
;
3129 mutex_unlock(&sc
->lock
);
3133 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3134 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3135 struct ieee80211_key_conf
*key
)
3137 struct ath5k_softc
*sc
= hw
->priv
;
3138 struct ath5k_hw
*ah
= sc
->ah
;
3139 struct ath_common
*common
= ath5k_hw_common(ah
);
3142 if (modparam_nohwcrypt
)
3145 switch (key
->cipher
) {
3146 case WLAN_CIPHER_SUITE_WEP40
:
3147 case WLAN_CIPHER_SUITE_WEP104
:
3148 case WLAN_CIPHER_SUITE_TKIP
:
3150 case WLAN_CIPHER_SUITE_CCMP
:
3151 if (common
->crypt_caps
& ATH_CRYPT_CAP_CIPHER_AESCCM
)
3159 mutex_lock(&sc
->lock
);
3163 ret
= ath_key_config(common
, vif
, sta
, key
);
3165 key
->hw_key_idx
= ret
;
3166 /* push IV and Michael MIC generation to stack */
3167 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
3168 if (key
->cipher
== WLAN_CIPHER_SUITE_TKIP
)
3169 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
3170 if (key
->cipher
== WLAN_CIPHER_SUITE_CCMP
)
3171 key
->flags
|= IEEE80211_KEY_FLAG_SW_MGMT
;
3176 ath_key_delete(common
, key
);
3183 mutex_unlock(&sc
->lock
);
3188 ath5k_get_stats(struct ieee80211_hw
*hw
,
3189 struct ieee80211_low_level_stats
*stats
)
3191 struct ath5k_softc
*sc
= hw
->priv
;
3194 ath5k_hw_update_mib_counters(sc
->ah
);
3196 stats
->dot11ACKFailureCount
= sc
->stats
.ack_fail
;
3197 stats
->dot11RTSFailureCount
= sc
->stats
.rts_fail
;
3198 stats
->dot11RTSSuccessCount
= sc
->stats
.rts_ok
;
3199 stats
->dot11FCSErrorCount
= sc
->stats
.fcs_error
;
3204 static int ath5k_get_survey(struct ieee80211_hw
*hw
, int idx
,
3205 struct survey_info
*survey
)
3207 struct ath5k_softc
*sc
= hw
->priv
;
3208 struct ieee80211_conf
*conf
= &hw
->conf
;
3213 survey
->channel
= conf
->channel
;
3214 survey
->filled
= SURVEY_INFO_NOISE_DBM
;
3215 survey
->noise
= sc
->ah
->ah_noise_floor
;
3221 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3223 struct ath5k_softc
*sc
= hw
->priv
;
3225 return ath5k_hw_get_tsf64(sc
->ah
);
3229 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3231 struct ath5k_softc
*sc
= hw
->priv
;
3233 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3237 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3239 struct ath5k_softc
*sc
= hw
->priv
;
3242 * in IBSS mode we need to update the beacon timers too.
3243 * this will also reset the TSF if we call it with 0
3245 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3246 ath5k_beacon_update_timers(sc
, 0);
3248 ath5k_hw_reset_tsf(sc
->ah
);
3252 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3254 struct ath5k_softc
*sc
= hw
->priv
;
3255 struct ath5k_hw
*ah
= sc
->ah
;
3257 rfilt
= ath5k_hw_get_rx_filter(ah
);
3259 rfilt
|= AR5K_RX_FILTER_BEACON
;
3261 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3262 ath5k_hw_set_rx_filter(ah
, rfilt
);
3263 sc
->filter_flags
= rfilt
;
3266 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3267 struct ieee80211_vif
*vif
,
3268 struct ieee80211_bss_conf
*bss_conf
,
3271 struct ath5k_vif
*avf
= (void *)vif
->drv_priv
;
3272 struct ath5k_softc
*sc
= hw
->priv
;
3273 struct ath5k_hw
*ah
= sc
->ah
;
3274 struct ath_common
*common
= ath5k_hw_common(ah
);
3275 unsigned long flags
;
3277 mutex_lock(&sc
->lock
);
3279 if (changes
& BSS_CHANGED_BSSID
) {
3280 /* Cache for later use during resets */
3281 memcpy(common
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
3283 ath5k_hw_set_bssid(ah
);
3287 if (changes
& BSS_CHANGED_BEACON_INT
)
3288 sc
->bintval
= bss_conf
->beacon_int
;
3290 if (changes
& BSS_CHANGED_ASSOC
) {
3291 avf
->assoc
= bss_conf
->assoc
;
3292 if (bss_conf
->assoc
)
3293 sc
->assoc
= bss_conf
->assoc
;
3295 sc
->assoc
= ath_any_vif_assoc(sc
);
3297 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3298 set_beacon_filter(hw
, sc
->assoc
);
3299 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3300 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3301 if (bss_conf
->assoc
) {
3302 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3303 "Bss Info ASSOC %d, bssid: %pM\n",
3304 bss_conf
->aid
, common
->curbssid
);
3305 common
->curaid
= bss_conf
->aid
;
3306 ath5k_hw_set_bssid(ah
);
3307 /* Once ANI is available you would start it here */
3311 if (changes
& BSS_CHANGED_BEACON
) {
3312 spin_lock_irqsave(&sc
->block
, flags
);
3313 ath5k_beacon_update(hw
, vif
);
3314 spin_unlock_irqrestore(&sc
->block
, flags
);
3317 if (changes
& BSS_CHANGED_BEACON_ENABLED
)
3318 sc
->enable_beacon
= bss_conf
->enable_beacon
;
3320 if (changes
& (BSS_CHANGED_BEACON
| BSS_CHANGED_BEACON_ENABLED
|
3321 BSS_CHANGED_BEACON_INT
))
3322 ath5k_beacon_config(sc
);
3324 mutex_unlock(&sc
->lock
);
3327 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
)
3329 struct ath5k_softc
*sc
= hw
->priv
;
3331 ath5k_hw_set_ledstate(sc
->ah
, AR5K_LED_SCAN
);
3334 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
)
3336 struct ath5k_softc
*sc
= hw
->priv
;
3337 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3338 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3342 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3344 * @hw: struct ieee80211_hw pointer
3345 * @coverage_class: IEEE 802.11 coverage class number
3347 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3348 * coverage class. The values are persistent, they are restored after device
3351 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
, u8 coverage_class
)
3353 struct ath5k_softc
*sc
= hw
->priv
;
3355 mutex_lock(&sc
->lock
);
3356 ath5k_hw_set_coverage_class(sc
->ah
, coverage_class
);
3357 mutex_unlock(&sc
->lock
);
3360 static int ath5k_conf_tx(struct ieee80211_hw
*hw
, u16 queue
,
3361 const struct ieee80211_tx_queue_params
*params
)
3363 struct ath5k_softc
*sc
= hw
->priv
;
3364 struct ath5k_hw
*ah
= sc
->ah
;
3365 struct ath5k_txq_info qi
;
3368 if (queue
>= ah
->ah_capabilities
.cap_queues
.q_tx_num
)
3371 mutex_lock(&sc
->lock
);
3373 ath5k_hw_get_tx_queueprops(ah
, queue
, &qi
);
3375 qi
.tqi_aifs
= params
->aifs
;
3376 qi
.tqi_cw_min
= params
->cw_min
;
3377 qi
.tqi_cw_max
= params
->cw_max
;
3378 qi
.tqi_burst_time
= params
->txop
;
3380 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3381 "Configure tx [queue %d], "
3382 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3383 queue
, params
->aifs
, params
->cw_min
,
3384 params
->cw_max
, params
->txop
);
3386 if (ath5k_hw_set_tx_queueprops(ah
, queue
, &qi
)) {
3388 "Unable to update hardware queue %u!\n", queue
);
3391 ath5k_hw_reset_tx_queue(ah
, queue
);
3393 mutex_unlock(&sc
->lock
);
3398 static const struct ieee80211_ops ath5k_hw_ops
= {
3400 .start
= ath5k_start
,
3402 .add_interface
= ath5k_add_interface
,
3403 .remove_interface
= ath5k_remove_interface
,
3404 .config
= ath5k_config
,
3405 .prepare_multicast
= ath5k_prepare_multicast
,
3406 .configure_filter
= ath5k_configure_filter
,
3407 .set_key
= ath5k_set_key
,
3408 .get_stats
= ath5k_get_stats
,
3409 .get_survey
= ath5k_get_survey
,
3410 .conf_tx
= ath5k_conf_tx
,
3411 .get_tsf
= ath5k_get_tsf
,
3412 .set_tsf
= ath5k_set_tsf
,
3413 .reset_tsf
= ath5k_reset_tsf
,
3414 .bss_info_changed
= ath5k_bss_info_changed
,
3415 .sw_scan_start
= ath5k_sw_scan_start
,
3416 .sw_scan_complete
= ath5k_sw_scan_complete
,
3417 .set_coverage_class
= ath5k_set_coverage_class
,
3420 /********************\
3421 * PCI Initialization *
3422 \********************/
3424 static int __devinit
3425 ath5k_pci_probe(struct pci_dev
*pdev
,
3426 const struct pci_device_id
*id
)
3429 struct ath5k_softc
*sc
;
3430 struct ath_common
*common
;
3431 struct ieee80211_hw
*hw
;
3436 * L0s needs to be disabled on all ath5k cards.
3438 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3439 * by default in the future in 2.6.36) this will also mean both L1 and
3440 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3441 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3442 * though but cannot currently undue the effect of a blacklist, for
3443 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3444 * the device link capability.
3446 * It may be possible in the future to implement some PCI API to allow
3447 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3448 * best to accept that both L0s and L1 will be disabled completely for
3449 * distributions shipping with CONFIG_PCIEASPM rather than having this
3450 * issue present. Motivation for adding this new API will be to help
3451 * with power consumption for some of these devices.
3453 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
);
3455 ret
= pci_enable_device(pdev
);
3457 dev_err(&pdev
->dev
, "can't enable device\n");
3461 /* XXX 32-bit addressing only */
3462 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3464 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
3469 * Cache line size is used to size and align various
3470 * structures used to communicate with the hardware.
3472 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
3475 * Linux 2.4.18 (at least) writes the cache line size
3476 * register as a 16-bit wide register which is wrong.
3477 * We must have this setup properly for rx buffer
3478 * DMA to work so force a reasonable value here if it
3481 csz
= L1_CACHE_BYTES
>> 2;
3482 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
3485 * The default setting of latency timer yields poor results,
3486 * set it to the value used by other systems. It may be worth
3487 * tweaking this setting more.
3489 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
3491 /* Enable bus mastering */
3492 pci_set_master(pdev
);
3495 * Disable the RETRY_TIMEOUT register (0x41) to keep
3496 * PCI Tx retries from interfering with C3 CPU state.
3498 pci_write_config_byte(pdev
, 0x41, 0);
3500 ret
= pci_request_region(pdev
, 0, "ath5k");
3502 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
3506 mem
= pci_iomap(pdev
, 0, 0);
3508 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
3514 * Allocate hw (mac80211 main struct)
3515 * and hw->priv (driver private data)
3517 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
3519 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
3524 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
3526 /* Initialize driver private data */
3527 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
3528 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
3529 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
3530 IEEE80211_HW_SIGNAL_DBM
;
3532 hw
->wiphy
->interface_modes
=
3533 BIT(NL80211_IFTYPE_AP
) |
3534 BIT(NL80211_IFTYPE_STATION
) |
3535 BIT(NL80211_IFTYPE_ADHOC
) |
3536 BIT(NL80211_IFTYPE_MESH_POINT
);
3538 hw
->extra_tx_headroom
= 2;
3539 hw
->channel_change_time
= 5000;
3545 * Mark the device as detached to avoid processing
3546 * interrupts until setup is complete.
3548 __set_bit(ATH_STAT_INVALID
, sc
->status
);
3550 sc
->iobase
= mem
; /* So we can unmap it on detach */
3551 sc
->opmode
= NL80211_IFTYPE_STATION
;
3553 mutex_init(&sc
->lock
);
3554 spin_lock_init(&sc
->rxbuflock
);
3555 spin_lock_init(&sc
->txbuflock
);
3556 spin_lock_init(&sc
->block
);
3558 /* Set private data */
3559 pci_set_drvdata(pdev
, sc
);
3561 /* Setup interrupt handler */
3562 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
3564 ATH5K_ERR(sc
, "request_irq failed\n");
3568 /* If we passed the test, malloc an ath5k_hw struct */
3569 sc
->ah
= kzalloc(sizeof(struct ath5k_hw
), GFP_KERNEL
);
3572 ATH5K_ERR(sc
, "out of memory\n");
3577 sc
->ah
->ah_iobase
= sc
->iobase
;
3578 common
= ath5k_hw_common(sc
->ah
);
3579 common
->ops
= &ath5k_common_ops
;
3580 common
->ah
= sc
->ah
;
3582 common
->cachelsz
= csz
<< 2; /* convert to bytes */
3584 /* Initialize device */
3585 ret
= ath5k_hw_attach(sc
);
3590 /* set up multi-rate retry capabilities */
3591 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
3593 hw
->max_rate_tries
= 11;
3596 hw
->vif_data_size
= sizeof(struct ath5k_vif
);
3598 /* Finish private driver data initialization */
3599 ret
= ath5k_attach(pdev
, hw
);
3603 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3604 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
3605 sc
->ah
->ah_mac_srev
,
3606 sc
->ah
->ah_phy_revision
);
3608 if (!sc
->ah
->ah_single_chip
) {
3609 /* Single chip radio (!RF5111) */
3610 if (sc
->ah
->ah_radio_5ghz_revision
&&
3611 !sc
->ah
->ah_radio_2ghz_revision
) {
3612 /* No 5GHz support -> report 2GHz radio */
3613 if (!test_bit(AR5K_MODE_11A
,
3614 sc
->ah
->ah_capabilities
.cap_mode
)) {
3615 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
3616 ath5k_chip_name(AR5K_VERSION_RAD
,
3617 sc
->ah
->ah_radio_5ghz_revision
),
3618 sc
->ah
->ah_radio_5ghz_revision
);
3619 /* No 2GHz support (5110 and some
3620 * 5Ghz only cards) -> report 5Ghz radio */
3621 } else if (!test_bit(AR5K_MODE_11B
,
3622 sc
->ah
->ah_capabilities
.cap_mode
)) {
3623 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
3624 ath5k_chip_name(AR5K_VERSION_RAD
,
3625 sc
->ah
->ah_radio_5ghz_revision
),
3626 sc
->ah
->ah_radio_5ghz_revision
);
3627 /* Multiband radio */
3629 ATH5K_INFO(sc
, "RF%s multiband radio found"
3631 ath5k_chip_name(AR5K_VERSION_RAD
,
3632 sc
->ah
->ah_radio_5ghz_revision
),
3633 sc
->ah
->ah_radio_5ghz_revision
);
3636 /* Multi chip radio (RF5111 - RF2111) ->
3637 * report both 2GHz/5GHz radios */
3638 else if (sc
->ah
->ah_radio_5ghz_revision
&&
3639 sc
->ah
->ah_radio_2ghz_revision
){
3640 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
3641 ath5k_chip_name(AR5K_VERSION_RAD
,
3642 sc
->ah
->ah_radio_5ghz_revision
),
3643 sc
->ah
->ah_radio_5ghz_revision
);
3644 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
3645 ath5k_chip_name(AR5K_VERSION_RAD
,
3646 sc
->ah
->ah_radio_2ghz_revision
),
3647 sc
->ah
->ah_radio_2ghz_revision
);
3651 ath5k_debug_init_device(sc
);
3653 /* ready to process interrupts */
3654 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
3658 ath5k_hw_detach(sc
->ah
);
3662 free_irq(pdev
->irq
, sc
);
3664 ieee80211_free_hw(hw
);
3666 pci_iounmap(pdev
, mem
);
3668 pci_release_region(pdev
, 0);
3670 pci_disable_device(pdev
);
3675 static void __devexit
3676 ath5k_pci_remove(struct pci_dev
*pdev
)
3678 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
3680 ath5k_debug_finish_device(sc
);
3681 ath5k_detach(pdev
, sc
->hw
);
3682 ath5k_hw_detach(sc
->ah
);
3684 free_irq(pdev
->irq
, sc
);
3685 pci_iounmap(pdev
, sc
->iobase
);
3686 pci_release_region(pdev
, 0);
3687 pci_disable_device(pdev
);
3688 ieee80211_free_hw(sc
->hw
);
3691 #ifdef CONFIG_PM_SLEEP
3692 static int ath5k_pci_suspend(struct device
*dev
)
3694 struct ath5k_softc
*sc
= pci_get_drvdata(to_pci_dev(dev
));
3700 static int ath5k_pci_resume(struct device
*dev
)
3702 struct pci_dev
*pdev
= to_pci_dev(dev
);
3703 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
3706 * Suspend/Resume resets the PCI configuration space, so we have to
3707 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3708 * PCI Tx retries from interfering with C3 CPU state
3710 pci_write_config_byte(pdev
, 0x41, 0);
3712 ath5k_led_enable(sc
);
3716 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops
, ath5k_pci_suspend
, ath5k_pci_resume
);
3717 #define ATH5K_PM_OPS (&ath5k_pm_ops)
3719 #define ATH5K_PM_OPS NULL
3720 #endif /* CONFIG_PM_SLEEP */
3722 static struct pci_driver ath5k_pci_driver
= {
3723 .name
= KBUILD_MODNAME
,
3724 .id_table
= ath5k_pci_id_table
,
3725 .probe
= ath5k_pci_probe
,
3726 .remove
= __devexit_p(ath5k_pci_remove
),
3727 .driver
.pm
= ATH5K_PM_OPS
,
3731 * Module init/exit functions
3734 init_ath5k_pci(void)
3738 ret
= pci_register_driver(&ath5k_pci_driver
);
3740 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
3748 exit_ath5k_pci(void)
3750 pci_unregister_driver(&ath5k_pci_driver
);
3753 module_init(init_ath5k_pci
);
3754 module_exit(exit_ath5k_pci
);